Consumable chip communication method and device, equipment and storage medium

Abstract

The embodiment of the invention provides a communication method and device for a consumable chip, equipment and a storage medium. First communication verification processing is executed on the consumable chip based on a first clock line and a first data line of a first analog I2C interface; when it is detected that the first communication verification is passed, the first clock line is converted into a second data line, the first data line is converted into a second clock line, and a second analog I2C interface is generated; and executing second communication verification processing on the consumable chip based on a second clock line of the second analog I2C interface and the second data line. And after the first communication verification is passed, the clock line and the data line are regenerated in another simulation mode, and the second communication verification is carried out, so that the cracking difficulty of the communication verification is increased, and the security of the consumable chip is improved.

Description

Technical Field

[0001] The present application relates to the field of image forming technology, and in particular to a communication method, device, equipment and storage medium for a consumable chip. Background Art

[0002] The image forming device is equipped with a detachable consumable device for providing consumables for printing, such as ink required for an inkjet printer or toner required for a laser printer. A consumable chip is generally installed on the housing of the consumable device, and the consumable chip stores consumable information, such as consumable model, consumable capacity, and remaining consumables. After the consumable device is installed in the image forming device, the main control chip of the image forming device can communicate with the consumable chip to verify the security of the current consumable chip.

[0003] Existing main control chips and consumable chips usually communicate and verify through a fixed hardware inter-integrated circuit protocol (I2C), which is easy to crack, resulting in counterfeit consumable chips passing the verification, reducing the security of image forming equipment. Summary of the invention

[0004] In view of this, the present application provides a communication method, device, equipment and storage medium for a consumable chip, so as to solve the problem in the prior art that the communication verification of the consumable chip is easily cracked, resulting in insufficient security.

[0005] In a first aspect, an embodiment of the present application provides a communication method of a consumable chip, which is applied to a main control chip, and the method includes: Performing a first communication verification process on the consumable chip based on a first clock line and a first data line of the first analog I2C interface; When it is detected that the first communication verification passes, the first clock line is converted into a second data line, and the first data line is converted into a second clock line to generate a second simulated I2C interface; A second communication verification process is performed on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.

[0006] In an optional embodiment, the main control chip includes a first pin and a second pin, and the consumable chip includes a third pin and a fourth pin. Before the step of performing a first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface, the method further includes: Based on a first simulation mode, controlling the first pin and the third pin to simulate and generate the first clock line, and controlling the second pin and the fourth pin to simulate and generate the first data line; The first simulated I2C interface is simulated and generated based on the first data line and the first clock line.

[0007] In an optional embodiment, before the step of controlling the first pin and the third pin to simulate generating the first clock line based on the first simulation mode, and controlling the second pin and the fourth pin to simulate generating the first data line, the method further includes: Obtaining the pre-stored first simulation mode; The first simulation mode is sent to the consumable chip. In an optional embodiment, when the first communication verification is detected to be passed, the step of converting the first clock line to a second data line, converting the first data line to a second clock line, and generating a second simulated I2C interface includes: When detecting that the first communication verification passes, determining a second simulation mode based on the first simulation mode; Based on the second simulation mode, the first pin and the third pin are controlled to simulate and generate the second data line, and Control the second pin and the fourth pin to simulate and generate the second clock line; The second simulated I2C interface is simulated and generated based on the second data line and the second clock line.

[0008] In an optional embodiment, the method further includes: When it is detected that the first communication verification fails, determining that the consumable chip is a non-genuine chip; or, When it is detected that the first communication verification passes and the second communication verification fails, it is determined that the consumable chip is a non-genuine chip; or, When it is detected that both the first communication verification and the second communication verification are passed, it is determined that the consumable chip is a genuine chip.

[0009] In an optional embodiment, after the step of performing a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface, the method further includes: If it is determined that the consumable chip is a non-genuine chip, an error prompt message is displayed, and the error prompt message is used to indicate that the current consumable chip cannot communicate normally with the main control chip.

[0010] In a second aspect, an embodiment of the present application provides a communication method for a consumable chip, which is applied to a consumable chip, and the method includes: When the main control chip triggers the first communication verification process, the first communication verification is performed with the main control chip based on the first clock line and the first data line of the first analog I2C interface; When the main control chip triggers the second communication verification process, the first clock line is converted into a second data line, and the first data line is converted into a second clock line to generate a second analog I2C interface; A second communication verification is performed on the main control chip based on the second clock line and the second data line of the second analog I2C interface.

[0011] In an optional embodiment, the main control chip includes a first pin and a second pin, and the consumable chip includes a third pin and a fourth pin. When the main control chip triggers the first communication verification process, before performing the first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface, the method further includes: Receiving first agreed data sent by the main control chip, wherein the first agreed data includes a first simulation mode; Based on the first simulation mode, controlling the third pin and the first pin to simulate generating the first clock line, and controlling the fourth pin and the second pin to simulate generating the first data line; Receive first verification data sent by the main control chip, where the first verification data is used to confirm that the first clock line and the second clock line can communicate normally.

[0012] In an optional embodiment, when the main control chip triggers the second communication verification process, the first clock line is converted into a second data line, and the first data line is converted into a second clock line to generate a second analog I2C interface, including: receiving second agreed data sent by the main control chip, wherein the second agreed data includes a second simulation mode; Based on the second simulation mode, the third pin and the first pin are controlled to simulate and generate a second data line, and the fourth pin and the second pin are controlled to simulate and generate a second clock line.

[0013] In an optional embodiment, the performing a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface includes: After receiving the second verification data sent by the main control chip, a second communication verification is performed on the main control chip based on the second clock line and the second data line.

[0014] In a third aspect, an embodiment of the present application provides a communication device of a consumable chip, which is deployed on a main control chip, and the communication device of the consumable chip includes: A first verification module, configured to perform a first communication verification process on the consumable chip based on a first clock line and a first data line of a first analog I2C interface; A control module, configured to convert the first clock line into a second data line, convert the first data line into a second clock line, and generate a second simulated I2C interface when detecting that the first communication verification is passed; A second verification module is used to perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.

[0015] In a fourth aspect, an embodiment of the present application provides a communication device for a consumable chip, which is deployed on a consumable chip, and the communication device for the consumable chip includes: A first communication verification module, configured to perform a first communication verification with the main control chip based on a first clock line and a first data line of a first analog I2C interface when the main control chip triggers a first communication verification process; an analog module, configured to convert the first clock line into a second data line, convert the first data line into a second clock line, and generate a second analog I2C interface when the main control chip triggers a second communication verification process; The second communication verification module is used to perform a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface.

[0016] In a fifth aspect, an embodiment of the present application provides an electronic device, comprising a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device is triggered to execute any one of the methods described in the first aspect above.

[0017] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored program, wherein when the program is running, the device where the computer-readable storage medium is located is controlled to execute any method described in the first aspect.

[0018] By adopting the scheme provided in the embodiment of the present application, the first communication verification process is performed on the consumable chip based on the first clock line and the first data line of the first analog I2C interface; when it is detected that the first communication verification is passed, the first clock line is converted to the second data line, and the first data line is converted to the second clock line to generate a second analog I2C interface; based on the second clock line and the second data line of the second analog I2C interface, the consumable chip is subjected to a second communication verification process. After the first communication verification is passed, the clock line and the data line are regenerated in another simulation mode and a second communication verification is performed, which increases the difficulty of cracking the communication verification and improves the security of the consumable chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0020] Figure 1 An exemplary schematic diagram of a communication method for a consumable chip provided in an embodiment of the present application; Figure 2 An exemplary schematic diagram of another communication method for a consumable chip provided in an embodiment of the present application; Figure 3 A flow chart of a communication method for a consumable chip provided in an embodiment of the present application; Figure 4a An exemplary schematic diagram of another communication method for a consumable chip provided in an embodiment of the present application; Figure 4b An exemplary schematic diagram of another communication method for a consumable chip provided in an embodiment of the present application; Figure 5 A flow chart of a communication method for a consumable chip provided in an embodiment of the present application; Figure 6 A schematic flow chart of another communication method for a consumable chip provided in an embodiment of the present application; Figure 7 A schematic flow chart of another communication method for a consumable chip provided in an embodiment of the present application; Figure 8 A schematic diagram of the structure of a communication device for a consumable chip provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a communication device for a consumable chip provided in an embodiment of the present application; Fig.10 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0022] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0023] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0024] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0025] Common image forming devices are usually equipped with a detachable consumable device, which contains consumables (such as ink, toner, etc.) and a consumable chip that records consumable data is installed on the housing of the consumable device. Figure 1 The image forming device may include: an image forming device and a consumable device. The image forming device is used to perform operations related to image formation to output a printed image. The consumable device is a replaceable accessory in the image forming device. For example, when the image forming device is an inkjet printer, a laser printer, a 3D printer, a label printer, or a dot matrix printer, the consumable device is an ink cartridge, a toner cartridge, a toner cartridge, a toner cartridge, a ribbon cartridge, etc.

[0026] The consumable chip is an electronic device with a storage function. When the consumable device is installed on the image forming device, the consumable chip is connected to the main control chip of the image forming device. The communication connection can be a communication connection through a contact, an antenna or a coil, which is not limited in the present embodiment. It should be noted that the consumable chip stores information including raw data, and the raw data is information related to the image forming device. For example, the raw data can include at least one of the following categories: (1) imaging control related parameters, such as: printing engine control parameter information, specifically high voltage control parameters, fixing temperature parameters, paper feed speed control parameters, etc. When the image forming device is a color printer, it also includes color calibration parameter information or calibration patterns; (2) consumable related parameters, such as: various proportional factors for calculating toner consumption; or basic attribute information of consumables, wherein the basic attribute information of consumables can specifically be information such as consumable model, consumable serial number, consumable capacity life, etc. It should be noted that those skilled in the art can also design the consumable chip to store other types of raw data according to actual needs, which is not limited in the present embodiment.

[0027] When the consumable is exhausted, the user needs to disassemble the consumable device for update, including replenishing the consumable and replacing the consumable chip (or updating the data in the original consumable chip). After the update of the consumable device is completed, the user can reinstall it to the image forming device. After the main control chip re - establishes a connection with the consumable chip, the main control chip needs to perform communication verification on the consumable chip to confirm that the current consumable chip is a genuine chip and ensure the security of communication.

[0028] The main control chip and the consumable chip simulate the Internal Integrated Circuit (I2C) bus based on General Purpose Input Output (GPIO) pins, and then perform communication verification and subsequent normal communication based on the simulated I2C bus. The I2C bus includes a clock line and a data line. The data line is used to transmit data, and the clock line is used for clock synchronization between both parties. The I2C bus has a simple structure, which can reduce the system cost and improve the reliability of the system.

[0029] Refer to Figure 2 , the main control chip and the consumable chip perform communication verification through fixed hardware IIC interfaces respectively. Interface A of the main control chip and interface C of the consumable chip form the clock line, and interface B of the main control chip and interface D of the consumable chip form the data line. The clock line is connected to the power supply VCC through the resistor R1, and the data line is connected to the power supply VCC through the resistor R2. In the existing communication verification, the main control chip only performs communication verification on the consumable chip through fixed clock lines or / and data lines. This method is easy to be cracked, and it is easy to cause problems such as chip imitation and information leakage.

[0030] In view of the above problems, the embodiment of the present application provides a communication method for a consumable chip. By modifying the simulation method of the clock line and the data line and performing multiple communication verifications, the cracking difficulty of the consumable chip can be effectively improved, and the security is enhanced.

[0031] Figure 3 It is a schematic flow chart of a communication method for a consumable chip provided by the embodiment of the present application. This method can be applied to the main control chip of an image forming device. As Figure 3 shown, this method may include: Step 301, generate a first clock line by simulating based on the first pin and the third pin, generate a first data line by simulating based on the second pin and the fourth pin, and generate a first simulated I2C interface based on the first data line and the first clock line.

[0032] Step 302, perform a first communication verification through the first clock line and the first data line of the first simulated I2C interface.

[0033] Step 303, determine whether the first communication verification is passed, if confirmed to be passed, proceed to step 304, otherwise proceed to step 308.

[0034] Step 304: simulate and generate a second data line based on the first pin and the third pin, simulate and generate a second clock line based on the second pin and the fourth pin, and generate a second simulated I2C interface based on the second clock line and the second data line.

[0035] Step 305: Perform a second communication verification via the second clock line and the second data line of the second analog I2C interface.

[0036] Step 306, determine whether the second communication verification is passed, if confirmed, proceed to step 307, otherwise proceed to step 308.

[0037] Step 307, determine whether the current consumable chip is compatible.

[0038] Step 308, determining that the current consumable chip is incompatible.

[0039] Combination Figure 4a , Figure 4b right Figure 3 The process is described. Figure 4a Pin A, Pin B, Pin C and Pin D in the figure can be regarded as the first pin, the second pin, the third pin and the fourth pin respectively. After the main control chip is connected to the consumable chip, the main control chip simulates and generates the first clock line of the first simulated I2C interface based on its own pin A and Pin C of the consumable chip, and simulates and generates the first data line of the first simulated I2C interface based on its own pin B and Pin D of the consumable chip. The main control chip can perform a first communication verification process on the consumable chip through the first clock line and the first data line of the first simulated I2C interface. The first communication verification process can generate a level signal by manually controlling the high and low levels of the GPIO pins of the main control chip, and the above-mentioned level signal is transmitted to the consumable chip to check whether the simulated clock line and data line can generate start, stop, response and other signals in the manner specified by the I2C protocol, and whether the data transmission is correct.

[0040] If the first communication verification fails, the current consumable chip is directly determined to be incompatible. If the first communication verification passes, the second communication verification process is executed. Figure 4b, the main control chip exchanges the clock line and the data line in an analog manner, and uses its own pin A and the pin C of the consumable chip to simulate the second data line of the second analog I2C interface, and uses its own pin B and the pin D of the consumable chip to simulate the second clock line of the second analog I2C interface. The main control chip can perform the second communication verification through the second clock line and the second data line of the second analog I2C interface. If the second communication fails, the current consumable chip is also determined to be incompatible. If the second communication verification passes, it can be confirmed that the current consumable chip is compatible. The consumable chip determined to be compatible can be regarded as a genuine and safe consumable chip and can be used normally, while the consumable chip determined to be incompatible can be regarded as a counterfeit consumable chip and cannot be used. Among them, the second communication verification process can generate a level signal by manually controlling the high and low levels of the GPIO pins of the main control chip, and the above-mentioned level signal is transmitted to the consumable chip, so as to check whether the simulated clock line and data line can generate start, stop, response and other signals in the manner specified by the I2C protocol, and whether the data transmission is correct.

[0041] Compared with the existing verification method of only executing one communication verification process through a fixed hardware IIC interface, the embodiment of the present application uses a simulation method of exchanging the clock line and the data line after executing one communication verification, and then performs a second communication verification based on the re-simulated clock line and data line. The overall verification process is difficult to crack, which can effectively prevent the counterfeiting of consumable chips and ensure data security.

[0042] In the two communication verifications, the simulation mode of the clock line and the data line can be preset to Figure 3 For example, after the main control chip and the consumable chip are connected, the clock line is simulated by pin A and pin C, and the data line is simulated by pin B and pin D. In the second communication verification, the analog exchange is directly performed, and the data line is simulated by pin A and pin C, and the clock line is simulated by pin B and pin D.

[0043] In an optional embodiment, the simulation method of the clock line and the data line can be determined by negotiation between the two parties. The overall communication verification process can be referred to Figure 5 , which may include: Step 501: Send first agreed data to the consumable chip to determine a first simulation mode.

[0044] Step 502: Generate a first clock line and a first data line based on a first simulation method, and generate a first simulated I2C interface based on the first clock line and the first data line.

[0045] Step 503: Send first verification data to the consumable chip.

[0046] Step 504: Perform a first communication verification through a first clock line and a first data line of the first simulated I2C interface.

[0047] Step 505 , determine whether the first communication verification is passed, if confirmed passed, proceed to step 506 , otherwise proceed to step 512 .

[0048] Step 506: Send second agreed data to the consumable chip to determine the second simulation mode.

[0049] Step 507: Generate a second clock line and a second data line based on a second simulation method, and generate a second simulated I2C interface based on the second clock line and the second data line.

[0050] Step 508: Send second verification data to the consumable chip.

[0051] Step 509: Perform a second communication verification via a second clock line and a second data line of the second analog I2C interface.

[0052] Step 510, determine whether the second communication verification is passed, if confirmed passed, proceed to step 511, otherwise proceed to step 512.

[0053] Step 511, determine whether the current consumable chip is available.

[0054] Step 512, determining that the current consumable chip is unavailable.

[0055] Still taking Figure 4 as an example Figure 5 The process is described below. After the main control chip is connected to the consumable chip, the main control chip can send the first agreed data to the consumable chip through pin A and / or pin C, and the first agreed data includes a first simulation mode. The first simulation mode is used to determine the simulation mode of the clock line and the data line in the first communication verification. For example, the first simulation mode may indicate that pin A and pin C simulate the generation of the clock line, and pin B and pin D simulate the generation of the data line. Optionally, the first simulation mode may also indicate that pin A and pin C simulate the generation of the data line, and pin B and pin D simulate the generation of the clock line, and the specific method is not limited.

[0056] The main control chip controls pin A, pin B, pin C, and pin D to simulate and generate the first data line and the first clock line according to the rules of the first simulation method, and generates a first simulated I2C interface based on the first clock line and the first data line. After the simulation of the first data line and the first clock line is completed, the main control chip can send the first verification data to the consumable chip, and the first verification data can be used to determine whether the first data line and the first clock line can communicate normally or to notify the consumable chip that the first communication verification is about to start.

[0057] The main control chip performs the first communication verification through the first data line and the first clock line of the first analog I2C interface. If the first communication verification fails, it can be directly determined that the current consumable chip is unavailable. If the first communication verification passes, the main control chip sends the second agreed data to the consumable chip to determine the second simulation mode. The main control chip controls pin A, pin B, pin C, and pin D to simulate and generate the second data line and the second clock line according to the rules of the second simulation mode, and generates a second analog I2C interface based on the second clock line and the second data line. After the simulation of the second data line and the second clock line is completed, the main control chip can send the second verification data to the consumable chip, and then perform the second communication verification through the second data line and the second clock line of the second analog I2C interface. If the second verification fails, it can be determined that the current consumable chip is unavailable. If the second communication verification passes, it can be determined that the current consumable chip can be used.

[0058] In an optional embodiment, the above-mentioned first agreed data, second agreed data, first verification data and second verification data can be realized by data levels of specific lengths. For example, the main control chip can send a set of 8-bit data levels (first agreed data) to the consumable chip to notify the consumable chip of the relevant information of the first simulation mode. Afterwards, the main control chip can first send two sets of 8-bit invalid data (first verification data) to the consumable chip, and then perform the first communication verification. After the first communication verification is passed, the main control chip can send another set of 8-bit data levels (second agreed data) to the consumable chip to notify the consumable chip of the relevant information of the second simulation mode. Before the second communication verification begins, the main control chip sends two sets of 8-bit invalid data (second verification data) to the consumable chip, and then performs the second communication verification. If the verification is successful, it can be used normally.

[0059] In the embodiment of the present application, the specific rules of the first simulation mode and the second simulation mode can be flexibly set. For example, the first simulation mode simulates the generation of the clock line with pin A and pin C, and the generation of the data line with pin B and pin D, and the second simulation mode simulates the generation of the data line with pin A and pin C, and the generation of the clock line with pin B and pin D. Alternatively, the first simulation mode simulates the generation of the data line with pin A and pin C, and the generation of the clock line with pin B and pin D, and the second simulation mode simulates the generation of the clock line with pin A and pin C, and the generation of the data line with pin B and pin D. The above two communication verifications are only exemplary descriptions. In other embodiments, the main control chip can also perform three or more communication verifications, and the simulation methods adopted by different communication verifications can also be negotiated and determined. By flexibly setting the simulation methods of the clock line and the data line, the difficulty of cracking the communication verification can be further improved, and the security of the consumable chip can be ensured.

[0060] Figure 6 This is a flow chart of another consumable chip communication method provided in an embodiment of the present application, which method can be applied to the main control chip of an image forming device. Figure 6 As shown, the method may include: Step 601: Perform a first communication verification process on the consumable chip based on a first clock line and a first data line of a first analog I2C interface.

[0061] Step 602: When it is detected that the first communication verification passes, the first clock line is converted into the second data line, and the first data line is converted into the second clock line to generate a second simulated I2C interface.

[0062] Step 603: Perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.

[0063] In an optional embodiment, before performing the first communication verification, the main control chip simulates and generates the first data line and the first clock line based on the first simulation mode, the first pin and the second pin. Specifically, based on the first simulation mode, the first pin and the third pin are controlled to simulate and generate the first clock line, and the second pin and the fourth pin are controlled to simulate and generate the first data line; based on the first data line and the first clock line, a first simulated I2C interface is simulated and generated. The first simulation mode can be a default mode, or it can be determined by negotiation by the main control device sending the first agreed data to the consumable chip.

[0064] After the first communication verification is passed, the main control chip controls the first pin and the third pin to simulate the generation of the second data line, and controls the second pin and the fourth pin to simulate the generation of the second clock line based on the second simulation method; and simulates the generation of the second simulation I2C interface based on the second data line and the second clock line.

[0065] Through the above two communication verifications, the main control chip can accurately determine whether the current consumable chip is a genuine chip. If it is confirmed to be a genuine chip, it can be used normally. If it is confirmed to be a non-genuine chip, the consumable chip cannot be used. At the same time, the main control chip can also generate an error prompt message to prompt the user that there is a problem with the current consumable chip and it cannot be used normally. Optionally, the error prompt message can be displayed through the control panel of the image forming device.

[0066] Figure 7 This is a flow chart of another consumable chip communication method provided in an embodiment of the present application, which can be applied to consumable chips of image forming devices. Figure 7 As shown, the method may include: Step 701: When the main control chip triggers a first communication verification process, a first communication verification is performed with the main control chip based on a first clock line and a first data line of a first analog I2C interface.

[0067] Step 702: When the main control chip triggers the second communication verification process, the first clock line is converted into the second data line, and the first data line is converted into the second clock line to generate a second simulated I2C interface.

[0068] Step 703: Perform a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface.

[0069] Before the first communication verification, the consumable chip can receive the first agreed data sent by the main control chip, and the first agreed data includes the first simulation mode. Based on the first simulation mode, the consumable chip can control the third pin to simulate the generation of the first clock line, and control the fourth pin to simulate the generation of the first data line. After receiving the first verification data sent by the main control chip, the consumable chip can perform the first communication verification.

[0070] After the first verification is passed, the consumable chip receives the second agreed data sent by the main control chip to determine the second simulation mode. Based on the second simulation mode, the consumable chip controls the third pin to simulate the generation of the second data line, and controls the fourth pin to simulate the generation of the second clock line. After receiving the second verification data sent by the main control chip, the consumable chip performs the second communication verification.

[0071] The communication method of the consumable chip provided in the embodiment of the present application can effectively improve the security of the consumable chip and protect the rights and interests of the genuine chip.

[0072] Figure 8 This is a schematic diagram of the structure of a communication device for a consumable chip provided in an embodiment of the present application. The device can be deployed in a main control chip, such as Figure 8 As shown, the device may include: a first verification module 810 , a control module 820 and a second verification module 830 .

[0073] The first verification module 810 is used to perform a first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface.

[0074] The control module 820 is used to convert the first clock line into the second data line and the first data line into the second clock line to generate a second simulated I2C interface when detecting that the first communication verification is passed.

[0075] The second verification module 830 is used to perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.

[0076] Fig. 9 This is a schematic diagram of the structure of a communication device for a consumable chip provided in an embodiment of the present application. The device can be deployed on a consumable chip, such as Fig. 9As shown in the figure, the device may include: a first communication verification module 910, an analog module 920, and a second communication verification module 930.

[0077] The first communication verification module 910 is configured to perform a first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface when the main control chip triggers the first communication verification process.

[0078] The analog module 920 is configured to convert the first clock line into a second data line and convert the first data line into a second clock line to generate a second analog I2C interface when the main control chip triggers the second communication verification process.

[0079] The second communication verification module 930 is configured to perform a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface.

[0080] For the specific process, reference may be made to the description in the above method flowchart.

[0081] Corresponding to the above embodiments, the present application further provides an electronic device. Fig.10 As a schematic structural diagram of an electronic device provided in an embodiment of the present application, the electronic device 1000 may include: a processor 1001, a memory 1002, and a communication unit 1003. These components communicate through one or more buses. Those skilled in the art can understand that the structure of the electronic device shown in the figure does not constitute a limitation on the embodiments of the present application. It can be a bus structure, a star structure, and may also include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0082] Among them, the communication unit 1003 is configured to establish a communication channel so that the electronic device can communicate with other devices. Receive user data sent by other devices or send user data to other devices.

[0083] The processor 1001 is the control center of the electronic device, connecting various parts of the entire electronic device through various interfaces and lines. By running or executing software programs, instructions, and / or modules stored in the memory 1002, and calling data stored in the memory, it executes various functions of the electronic device and / or processes data. The processor may be composed of an integrated circuit (IC). For example, it may be composed of a single packaged IC, or may be composed of connecting multiple packaged ICs with the same or different functions. For example, the processor 1001 may only include a central processing unit (CPU). In the embodiment of the present application, the CPU may be a single operation core or may include multiple operation cores.

[0084] The memory 1002 is used to store the execution instructions of the processor 1001. The memory 1002 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0085] When the execution instructions in the memory 1002 are executed by the processor 1001, the electronic device 1000 can execute Figures 5 to 7 Some or all of the steps in the illustrated embodiments.

[0086] In a specific implementation, the present application also provides a computer storage medium, wherein the computer storage medium may store a program, and when the program is executed, the program may include some or all of the steps in each embodiment of the communication method of the consumable chip provided in the present application. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0087] In a specific implementation, the present application also provides a computer program product, wherein the computer program product includes executable instructions, and when the executable instructions are executed on a computer, the computer executes part or all of the steps in each embodiment of the communication method for the consumable chip provided in the present application.

[0088] The embodiment of the present application also provides a non-temporary computer-readable storage medium, which stores computer instructions, and the computer instructions enable the computer to execute the communication method of the consumable chip provided in the embodiment of the present application.

[0089] The above-mentioned non-temporary computer-readable storage medium may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination thereof. More specific examples (non-exhaustive list) of computer-readable storage media include: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (Read Only Memory; hereinafter referred to as: ROM), an erasable programmable read-only memory (ErasableProgrammable Read Only Memory; hereinafter referred to as: EPROM) or flash memory, optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with an instruction execution system, device or device.

[0090] Computer-readable signal media may include a data signal propagated in baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including, but not limited to, electromagnetic signals, optical signals, or any suitable combination of the above. Computer-readable signal media may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0091] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0092] Those skilled in the art can clearly understand that the technology in the embodiments of the present application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution in the embodiments of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application or some parts of the embodiments.

[0093] In this specification, the same or similar parts between the various embodiments can be referred to each other. In particular, for the device embodiment and the terminal embodiment, since they are basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description in the method embodiment.

Claims

1. A communication method for a consumable chip, characterized in that: Applied to the main control chip, the method includes: Performing a first communication verification process on the consumable chip based on a first clock line and a first data line of the first analog I2C interface; When it is detected that the first communication verification passes, the first clock line is converted into a second data line, and the first data line is converted into a second clock line to generate a second simulated I2C interface; A second communication verification process is performed on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.

2. The method according to claim 1, characterized in that The main control chip includes a first pin and a second pin, and the consumable chip includes a third pin and a fourth pin. Before the step of performing a first communication verification process on the consumable chip based on the first clock line and the first data line of the first analog I2C interface, the method further includes: Based on a first simulation mode, controlling the first pin and the third pin to simulate generating the first clock line, and controlling the second pin and the fourth pin to simulate generating the first data line; The first simulated I2C interface is simulated and generated based on the first data line and the first clock line.

3. The method according to claim 2, characterized in that Before the step of controlling the first pin and the third pin to simulate and generate the first clock line based on the first simulation mode, and controlling the second pin and the fourth pin to simulate and generate the first data line, the method further includes: Obtaining the pre-stored first simulation mode; The first simulation mode is sent to the consumable chip.

4. The method according to claim 2, characterized in that: The step of converting the first clock line into a second data line and converting the first data line into a second clock line to generate a second simulated I2C interface when the first communication verification is detected to be passed includes: When detecting that the first communication verification passes, determining a second simulation mode based on the first simulation mode; Based on the second simulation mode, the first pin and the third pin are controlled to simulate and generate the second data line, and Control the second pin and the fourth pin to simulate and generate the second clock line; The second simulated I2C interface is simulated and generated based on the second data line and the second clock line.

5. The method according to claim 1, characterized in that The method further comprises: When it is detected that the first communication verification fails, determining that the consumable chip is a non-genuine chip; or, When it is detected that the first communication verification passes and the second communication verification fails, it is determined that the consumable chip is a non-genuine chip; or, When it is detected that both the first communication verification and the second communication verification are passed, it is determined that the consumable chip is a genuine chip.

6. The method according to claim 1, characterized in that After the step of performing a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface, the method further includes: If it is determined that the consumable chip is a non-genuine chip, an error prompt message is displayed, and the error prompt message is used to indicate that the current consumable chip cannot communicate normally with the main control chip.

7. A communication method for a consumable chip, characterized in that: Applied to consumable chips, the method comprises: When the main control chip triggers the first communication verification process, the first communication verification is performed with the main control chip based on the first clock line and the first data line of the first analog I2C interface; When the main control chip triggers the second communication verification process, the first clock line is converted into a second data line, and the first data line is converted into a second clock line to generate a second analog I2C interface; A second communication verification is performed on the main control chip based on the second clock line and the second data line of the second analog I2C interface.

8. The method according to claim 7, characterized in that The main control chip includes a first pin and a second pin, the consumable chip includes a third pin and a fourth pin, and when the main control chip triggers the first communication verification process, before performing the first communication verification with the main control chip based on the first clock line and the first data line of the first analog I2C interface, the method further includes: Receiving first agreed data sent by the main control chip, wherein the first agreed data includes a first simulation mode; Based on the first simulation mode, controlling the third pin and the first pin to simulate generating the first clock line, and controlling the fourth pin and the second pin to simulate generating the first data line; Receive first verification data sent by the main control chip, where the first verification data is used to confirm that the first clock line and the second clock line can communicate normally.

9. The method according to claim 8, characterized in that When the main control chip triggers the second communication verification process, converting the first clock line into a second data line, converting the first data line into a second clock line, and generating a second analog I2C interface, includes: receiving second agreed data sent by the main control chip, wherein the second agreed data includes a second simulation mode; Based on the second simulation mode, the third pin and the first pin are controlled to simulate the generation of the second data line, and the fourth pin and the second pin are controlled to simulate the generation of the second clock line.

10. The method according to claim 7, characterized in that The performing a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface includes: After receiving the second verification data sent by the main control chip, the second communication verification is performed on the main control chip based on the second clock line and the second data line.

11. A communication device for a consumable chip, characterized in that: Deployed on the main control chip, the communication device of the consumable chip includes: A first verification module, configured to perform a first communication verification process on the consumable chip based on a first clock line and a first data line of a first analog I2C interface; A control module, configured to convert the first clock line into a second data line, convert the first data line into a second clock line, and generate a second simulated I2C interface when detecting that the first communication verification is passed; A second verification module is used to perform a second communication verification process on the consumable chip based on the second clock line and the second data line of the second analog I2C interface.

12. A communication device for a consumable chip, characterized in that: Deployed on a consumable chip, the communication device of the consumable chip includes: A first communication verification module, configured to perform a first communication verification with the main control chip based on a first clock line and a first data line of a first analog I2C interface when the main control chip triggers a first communication verification process; an analog module, configured to convert the first clock line into a second data line, convert the first data line into a second clock line, and generate a second analog I2C interface when the main control chip triggers a second communication verification process; The second communication verification module is used to perform a second communication verification on the main control chip based on the second clock line and the second data line of the second analog I2C interface.

13. An electronic device, characterized in that: The electronic device comprises a memory for storing computer program instructions and a processor for executing the program instructions, wherein when the computer program instructions are executed by the processor, the electronic device executes the method described in any one of claims 1 to 6 or any one of claims 7 to 10.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes a stored program, wherein when the program is executed, the device where the computer-readable storage medium is located is controlled to execute the method of any one of claims 1 to 6 or any one of claims 7 to 10.

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