Electronic device

Abstract

An electronic device is provided. The electronic device comprises a display panel, a first time schedule controller and a second time schedule controller. The first timing controller generates a first error flag signal, the second timing controller generates a second error flag signal, and the first timing controller and the second timing controller exchange the first error flag signal and the second error flag signal with each other. The first timing controller controls the first completion signal and the second timing controller controls the second completion signal. The first timing controller and the second timing controller drive a first display area and a second display area of the display panel when the first completion signal is activated and the second completion signal is activated.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0163274 filed in the Korean Intellectual Property Office on November 22, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices with improved display quality. Background Art

[0004] Typically, an electronic device capable of displaying an image may include a display panel and a timing controller. The timing controller controls the overall operation of the display panel. For example, the timing controller may control the display panel to display an image. As the size of the display panel increases, the calculations required to control the operation of the display panel may increase. Summary of the invention

[0005] Embodiments of the present disclosure may provide an electronic device having improved display quality.

[0006] According to an embodiment, an electronic device may include a display panel including a first display area and a second display area adjacent to the first display area, a first timing controller configured to drive the first display area, and a second timing controller configured to drive the second display area. The first timing controller may determine a first error state of the first display area and generate a first error flag signal indicating the first error state, the second timing controller may determine a second error state of the second display area and generate a second error flag signal indicating the second error state, the first timing controller and the second timing controller may exchange the first error flag signal and the second error flag signal with each other, when at least one of the first error flag signal and the second error flag signal received from the second timing controller is activated, the first timing controller may deactivate the first completion signal, when at least one of the second error flag signal and the first error flag signal received from the first timing controller is activated, the second timing controller may deactivate the second completion signal, and when the first completion signal is activated and the second completion signal is activated, the first timing controller and the second timing controller may drive the first display area and the second display area of ​​the display panel, respectively.

[0007] The first timing controller may include: a first correction unit such as a register configured to store a first error flag signal; a first memory unit such as a flash memory configured to store a second error flag signal; a logic gate receiving the first error flag signal and the second error flag signal; and a controller receiving the first signal or the second signal from the logic gate to activate or deactivate the first completion signal based on the first signal or the second signal.

[0008] The logic gate may output the first signal when at least one of the first error flag signal and the second error flag signal is activated.

[0009] The logic gate may output a second signal different from the first signal when the first error flag signal is disabled and the second error flag signal is disabled.

[0010] When receiving the second signal, the controller may activate the first completion signal.

[0011] When the first completion signal is deactivated, the first timing controller may operate in an output port mode to output the first completion signal having a low level.

[0012] When the first completion signal is activated, the first timing controller may operate in the input port mode, and when the second completion signal is deactivated, the second timing controller may operate in the output port mode to output the second completion signal having a low level, and the first timing controller may receive the second completion signal having a low level.

[0013] The electronic device may further include a pull-up resistor circuit applying a driving signal having a high level to the first timing controller and the second timing controller.

[0014] When the first completion signal is activated and the second completion signal is activated, the first timing controller may operate in the input port mode to receive the driving signal, and the second timing controller may operate in the input port mode to receive the driving signal, and the first timing controller and the second timing controller may synchronously drive the first display area and the second display area of ​​the display panel when receiving the driving signal.

[0015] The first timing controller may perform a compensation operation on the first display area, and when the compensation operation is not performed, the first error state may be activated.

[0016] The first timing controller may perform a compensation operation through a checksum, and may generate a first error flag signal.

[0017] According to an embodiment, an electronic device may include a display panel including a display area configured to include a first display area and a second display area adjacent to the first display area, a first timing controller driving the first display area, a second timing controller driving the second display area, and a processor driving the first timing controller and the second timing controller, the first timing controller may determine a first error state of the first display area to generate a first error flag signal, the second timing controller may determine a second error state of the second display area to generate a second error flag signal, the first timing controller and the second timing controller may provide the first error flag signal and the second error flag signal to the processor, when at least one of the first error flag signal and the second error flag signal is activated, the processor may deactivate a completion signal, and when the completion signal is activated, the processor may drive the first display area and the second display area of ​​the display panel, respectively.

[0018] The processor may include a logic gate that receives the first error flag signal and the second error flag signal, and a controller that receives the first signal or the second signal from the logic gate and activates or deactivates the completion signal based on the first signal or the second signal.

[0019] The logic gate may be a logical AND gate.

[0020] The logic gate may output the first signal when at least one of the first error flag signal and the second error flag signal is activated.

[0021] The logic gate may output a second signal different from the first signal when the first error flag signal is disabled and the second error flag signal is disabled.

[0022] When the second signal is received, the controller may activate a completion signal.

[0023] The processor may output a completion signal activated by the first timing controller and the second timing controller, and when receiving the completion signal, the first timing controller and the second timing controller may synchronously drive the first display area and the second display area of ​​the display panel.

[0024] The first timing controller may perform a compensation operation on the first display area, and when the compensation operation is not performed, the first error state may be activated.

[0025] The first timing controller may perform a compensation operation through a checksum, and may generate a first error flag signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0027] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure.

[0028] Figure 2 is an exploded perspective view of an electronic device according to an embodiment of the present disclosure.

[0029] Figure 3 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0030] Figure 4 A display panel and a timing controller according to an embodiment of the present disclosure are shown.

[0031] Figure 5A is a block diagram illustrating a first timing controller and a second timing controller according to an embodiment of the present disclosure.

[0032] Figure 5B is a block diagram showing a first timing controller according to an embodiment of the present disclosure.

[0033] Figure 6 is a timing diagram illustrating a first error flag signal and a first completion signal according to an embodiment of the present disclosure.

[0034] Figure 7 is a timing diagram illustrating a first completion signal and a second completion signal according to an embodiment of the present disclosure.

[0035] Figure 8 is a block diagram illustrating a first timing controller, a second timing controller, and a pull-up resistor circuit according to an embodiment of the present disclosure.

[0036] Fig. 9 and Fig.10 A display panel, a timing controller, and a processor according to an embodiment of the present disclosure are shown. DETAILED DESCRIPTION

[0037] In the present specification, a first component (or region, layer, portion, part, etc.) being “on,” “connected to” or “coupled to” a second component means that the first component is directly on, directly connected to or directly coupled to the second component, or that a third component is interposed therebetween.

[0038] The same reference numerals may be assigned to the same components shown in different drawings. In addition, in the drawings, the thickness, proportion and size of components may be exaggerated or otherwise changed to effectively illustrate technical features.

[0039] Although the terms "first," "second," etc., may be used to describe various components, the components should not be construed as being limited by these terms. The terms are used only to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope and spirit of the present disclosure.

[0040] Terms such as "under", "a lower portion", "above", and "an upper portion" are used herein to describe the relationship between components shown in the drawings. Such terms are relative and are described with reference to the directions indicated in the drawings.

[0041] The terms "comprises", "comprising", "includes" or "including" or "having" specify the presence of stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts and / or combinations thereof. The term "and / or" includes any and all combinations of one or more of the associated components. As used herein, the singular forms are intended to include the plural forms unless the context clearly indicates otherwise.

[0042] Unless otherwise defined, all terms (including technical terms and scientific terms) used in the specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, unless explicitly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with the meaning in the context of the relevant technology and should not be interpreted in an idealized or overly formal manner.

[0043] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0044] Figure 1 is a perspective view of an electronic device according to an embodiment of the present disclosure, and Figure 2 yes Figure 1 An exploded perspective view of an embodiment of an electronic device shown in FIG.

[0045] Reference Figure 1 and Figure 2, the electronic device 1000 is a device that can be activated in response to an electrical signal. According to the present disclosure, the electronic device 1000 may be a large electronic device such as a television or a monitor, or a small or medium-sized electronic device such as a cellular phone, a tablet computer, a vehicle navigation system, or a game console. The electronic device 1000 is shown for illustrative purposes only. Without departing from the scope of the present disclosure, devices other than the electronic device 1000 may be implemented in other forms. In the example shown, the electronic device 1000 has a rectangular shape with a longer side extending in a first direction DR1 and a shorter side extending in a second direction DR2 that is angled with the first direction DR1. However, the electronic device 1000 is not limited to a rectangle, but various electronic devices 1000 having various shapes may be provided. The display surface IS of the electronic device 1000 is parallel to the first direction DR1 and the second direction DR2, and may display an image IM observable from a third direction DR3. The display surface IS may correspond to the front surface of the electronic device 1000.

[0046] According to an embodiment, the front surface (or top surface) and the rear surface (or bottom surface) of the member are defined based on the surface displaying the image IM. The front surface and the rear surface are opposite to each other in the third direction DR3, and the normal direction of the front surface and the rear surface may be parallel to the third direction DR3.

[0047] The distance between the front surface and the rear surface in the third direction DR3 may correspond to the thickness of the electronic device 1000 in the third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 may be defined with respect to the electronic device 1000 and may be changed.

[0048] The electronic device 1000 may be capable of sensing external input applied to the electronic device 1000 from the outside. The external input may include various inputs applied from the outside of the electronic device 1000. According to an embodiment of the present disclosure, the electronic device 1000 may sense the external input applied by the user. The external input of the user may include any of various external inputs, such as touch or proximity of a part of the user's body, light, heat or pressure, or a combination thereof. In addition to sensing the external input at the front surface of the electronic device 1000, the electronic device 1000 may also sense the external input that may be applied to the side surface or rear surface of the electronic device 1000. The sensing capability may be based on the structure of the electronic device 1000, and the present disclosure is not limited to any one embodiment. According to an embodiment of the present disclosure, the external input may include, for example, input from a stylus, an active pen, a stylus, an electronic pen, or an electronic whiteboard pen.

[0049] The display surface IS of the electronic device 1000 may be divided into an active area AA and a non-active area NAA. The active area AA may be an area in which an image IM is displayed. A user may observe the image IM through the active area AA. According to an embodiment, the active area AA is shown as a rectangular shape with rounded vertices. However, this shape is provided for illustrative purposes. For example, the active area AA may have various shapes and is not limited to any one embodiment.

[0050] The non-active area NAA may be adjacent to the active area AA. The non-active area NAA may have a specific color. The non-active area NAA may surround the active area AA. Therefore, the shape of the active area AA may be substantially defined by the non-active area NAA. However, Figure 1 The shapes and configurations shown in are provided for illustrative purposes only, and the non-active area AA may be adjacent to only one side of the active area AA, or may be omitted. Figure 1 The electronic device 1000 is illustrated as an exemplary embodiment of the present disclosure, and the present disclosure is not limited to the exemplary embodiment.

[0051] like Figure 2 As shown in FIG. 1 , the electronic device 1000 may include a display module DM and a window WM disposed on the display module DM. The display module DM may include a display panel DP and an input sensing layer ISP.

[0052] According to an embodiment of the present disclosure, the display panel DP may be an emissive display panel. For example, the display panel DP may be an organic light emitting display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. The organic light emitting display panel may include a light emitting layer including an organic light emitting material. The inorganic light emitting display panel may include a light emitting layer including an inorganic light emitting material. The light emitting layer of the quantum dot light emitting display panel may include quantum dots and quantum rods.

[0053] The display panel DP may output an image IM, and the image IM may be displayed on the display surface IS.

[0054] The input sensing layer ISP may be arranged on the display panel DP to sense external input. The input sensing layer ISP may be directly on the display panel DP. According to an embodiment of the present disclosure, the input sensing layer ISP may be formed on the display panel DP by a subsequent process. In other words, when the input sensing layer ISP is arranged directly on the display panel DP, an internal adhesive film (not shown) is not interposed between the input sensing layer ISP and the display panel DP. However, in some embodiments, an internal adhesive film may be interposed between the input sensing layer ISP and the display panel DP. In these cases, the input sensing layer ISP and the display panel DP may be manufactured separately and may be attached to each other by a subsequent process. In other words, after the input sensing layer ISP is manufactured by a process separate from the process of the display panel DP, the input sensing layer ISP may be fixed to the top surface of the display panel DP, for example, using an internal adhesive film.

[0055] The window WM may include a transparent material through which the image IM on the display panel DP is visible. For example, the window WM may include glass, sapphire, or plastic. Figure 2 An example in which the window WM is a single layer is shown, but the present disclosure is not limited thereto. For example, the window WM may include multiple layers.

[0056] The non-active area NAA of the electronic device 1000 described above may correspond to an area defined by printing a material including a specific color on the window WM. According to an embodiment of the present disclosure, the window WM may include a light-blocking pattern to define the non-active area NAA. The light-blocking pattern may include an organic layer having a color, and the coating process may form the light-blocking pattern on the window WM.

[0057] The adhesive film may couple the window WM to the display module DM. According to an embodiment of the present disclosure, the adhesive film may include an optically clear adhesive (OCA) film. However, the adhesive film is not limited thereto, but may include typical adhesives and adhesives. For example, the adhesive film may include an optically clear resin (OCR) or a pressure sensitive adhesive (PSA) film.

[0058] The anti-reflection layer may also be between the window WM and the display module DM. The anti-reflection layer may reduce the reflectivity of external light incident on the electronic device 1000 from above the window WM. According to an embodiment of the present disclosure, the anti-reflection layer may include a phase retarder and a polarizer. The polarizer may be a film-type or liquid crystal coating-type polarizer. The film-type polarizer may include a stretched synthetic resin film, and the liquid crystal coating-type polarizer may include liquid crystals arranged in a specific array. The phase retarder and the polarizer may be implemented with one polarizing film.

[0059] According to an embodiment of the present disclosure, the anti-reflection layer may further include a color filter. The arrangement of the color filter may be based on the plurality of pixels PX (see Figure 3) is determined by the color of the light generated. In this case, the anti-reflection layer may further include a light-blocking pattern between the color filters.

[0060] The display module DM may display an image IM in response to an electrical signal or transmit / receive information based on an external input. The display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area where an image IM from the display panel DP is output or displayed. In addition, the display area DA may be an area where the input sensing layer ISP senses an external input applied from outside the electronic device 1000. According to an embodiment, the display area DA of the display module DM may correspond to at least a portion of the active area AA.

[0061] The non-display area NDA may be an area in which the image IM is not displayed. Figure 2 As shown in , the non-display area NDA may surround the display area DA. Figure 2 For illustrative purposes, only exemplary structures are shown. For example, the non-display area NDA may have various structures and is not limited to the illustrated embodiments. According to embodiments, the non-display area NDA of the display module DM may correspond to (eg, overlap) at least a portion of the non-active area NAA.

[0062] The electronic device 1000 may include a plurality of flexible films FF connected to the display panel DP. A data driving circuit DIC may be mounted on each flexible film FF. According to an embodiment of the present disclosure, a plurality of data driving circuits DIC may be provided, and the plurality of data driving circuits DIC may be mounted on the plurality of flexible films FF, respectively.

[0063] The electronic device 1000 may further include at least one printed circuit board PCB coupled to the plurality of flexible films FF. Figure 2 Two printed circuit boards PCB in the electronic device 1000 are shown, but the number of the printed circuit boards PCB is not limited thereto. Two adjacent printed circuit boards PCB of the printed circuit boards PCB may be electrically connected to each other through the connection film CF. In addition, at least one of the printed circuit boards PCB may be electrically connected to the main board.

[0064] A timing controller TCON may be arranged on the printed circuit board PCB. The timing controller TCON may include a first timing controller TCON1 and a second timing controller TCON2. The first timing controller TCON1 may be arranged on one of the plurality of printed circuit boards PCB, and the second timing controller TCON2 may be arranged on another of the plurality of printed circuit boards PCB.

[0065] Figure 2An example is shown in which a plurality of data driving circuits DIC are mounted on a plurality of flexible films FF, but the present disclosure is not limited thereto. For example, a plurality of data driving circuits DIC may be directly mounted on the display panel DP. For example, the data driving circuit DIC may be mounted on a curved portion of the display panel DP, and the data driving circuit DIC may be arranged on the back surface of the display module DM.

[0066] The input sensing layer ISP may be electrically connected to the printed circuit board PCB through a plurality of flexible films FF. However, the present disclosure is not limited thereto. For example, the display module DM may further include an additional flexible film to electrically connect the input sensing layer ISP to the printed circuit board PCB.

[0067] The electronic device 1000 may further include a housing EDC to accommodate the display module DM. The housing EDC may be coupled to the window WM to define the appearance of the electronic device 1000. The housing EDC may absorb impacts applied from the outside and prevent foreign matter or moisture from penetrating into the display module DM, so that the housing EDC generally protects the components contained in the housing EDC. According to an embodiment of the present disclosure, the housing EDC may have a form designed to accommodate and hold internal components of the electronic device 1000.

[0068] According to an embodiment, the electronic device 1000 may also include an electronic module including various functional modules for operating the display module DM, a power module (e.g., a battery) for supplying power required for the overall operation of the electronic device 1000, and / or a bracket connected to the display module DM, which may include a shell EDC that separates the internal space of the electronic device 1000.

[0069] Figure 3 is a block diagram of an electronic device according to an embodiment of the present disclosure.

[0070] Reference Figure 3 , the electronic device 1000 may include a display panel DP, a timing controller TCON, a data driving circuit DIC, and a scan driving circuit SDC.

[0071] The timing controller TCON may receive input data RGB and a control signal D-CS from a processor or an external controller (not shown). The external controller may include a graphics processor. The control signal D-CS may include various signals. For example, the control signal D-CS may include an input vertical synchronization signal, an input horizontal synchronization signal, a master clock, and a data enable signal.

[0072] The timing controller TCON may generate image data DS obtained by converting the data format of the input data RGB to meet the interface specification of the data driving circuit DIC. In this case, the timing controller TCON may perform a compensation operation to generate the image data DS. For example, the image data DS may include first image data DS1 (see Figure 4 ) and the second image data DS2 (see Figure 4 ).

[0073] The timing controller TCON may generate a scan control signal SCS and a data control signal DCS in response to a control signal D-CS.

[0074] The data driving circuit DIC may output a grayscale voltage for driving the plurality of data lines DL1 to DLm using a data control signal DCS and image data DS from a timing controller TCON. The data driving circuit DIC may be implemented in the form of an integrated circuit that may be directly mounted in a specific area of ​​the display panel DP or may be mounted on a separate printed circuit board in a chip-on-film manner so that the data driving circuit DIC is electrically connected to the display panel DP. Alternatively, the data driving circuit DIC may not be a separate integrated circuit but may be formed by the same process of forming a circuit layer in the display panel DP.

[0075] The display panel DP may be divided into a display area DA and a non-display area NDA. A plurality of pixels PX may be arranged in the display area DA, and a scan driving circuit SDC may be arranged in the non-display area NDA.

[0076] The display panel DP may include a plurality of scan lines SL1 to SLn, a plurality of data lines DL1 to DLm, a plurality of pixels PX, and a scan drive circuit SDC. Each of the plurality of pixels PX may be connected to a related data line among the plurality of data lines DL1 to DLm, and may be connected to a related scan line among the plurality of scan lines SL1 to SLn. According to an embodiment of the present disclosure, the display panel DP further includes a light emission control line, and the electronic device 1000 may further include a light emission drive circuit that provides a control signal to the light emission control line. The configuration of the display panel DP is not particularly limited.

[0077] A plurality of scan lines SL1 to SLn may extend in parallel to the first direction DR1. The plurality of scan lines SL1 to SLn may be spaced apart from each other in the second direction DR2. A plurality of data lines DL1 to DLm may extend from the data driving circuit DIC in parallel to the second direction DR2. The plurality of data lines DL1 to DLm may be spaced apart from each other in the first direction DR1.

[0078] The plurality of pixels PX may be electrically connected to the plurality of scan lines SL1 to SLn and the plurality of data lines DL1 to DLm. For example, the pixels in the first row of the pixel array may be connected to the scan line SL1, and the pixels in the first column of the pixel array may be connected to the data line DL1.

[0079] The scan driving circuit SDC may drive the plurality of scan lines SL1 to SLn in response to the scan control signal SCS. According to an embodiment of the present disclosure, the scan driving circuit SDC may be formed in the same process of forming a circuit layer in the display panel DP, but the present disclosure is not limited thereto. For example, the scan driving circuit SDC may be implemented in the form of a separate integrated circuit (IC) that may be directly mounted in a specific area of ​​the display panel DP or mounted on a separate printed circuit board in a chip on film (COF) manner so that the scan driving circuit SDC is electrically connected to the display panel DP.

[0080] Figure 4 is a block diagram illustrating a display panel and a timing controller according to an embodiment of the present disclosure.

[0081] Reference Figure 4 , the timing controller TCON may include multiple timing controllers. Figure 4 In the embodiment of the present invention, the timing controller TCON includes a first timing controller TCON1 and a second timing controller TCON2. In other embodiments, more than two timing controllers may be used.

[0082] like Figure 4 As shown in the embodiment of FIG. 1 , the display area DA of the display panel DP may include a first display area DA1 and a second display area DA2 adjacent to the first display area DA1. The first timing controller TCON1 may control the first display area DA1, and the second timing controller TCON2 may control the second display area DA2.

[0083] The first timing controller TCON1 may determine a first error state and generate a plurality of first error flag signals ERRFG11 to ERRFG1n. Determining the first error state may include determining whether compensation data for performing a compensation operation is loaded in the first display area DA1. For example, when the compensation operation is not performed, the first timing controller TCON1 may activate the first error state. When the first error state is activated, a plurality of first error flag signals ERRFG11 to ERRFG1n (e.g., one or more of the plurality of first error flag signals ERRFG11 to ERRFG1n) may be activated. The first timing controller TCON1 may be referred to as a master timing controller.

[0084] The second timing controller TCON2 may determine a second error state and generate a plurality of second error flag signals ERRFG21 to ERRFG2n. Determining the second error state may include determining whether compensation data for performing a compensation operation is loaded in the second display area DA2. For example, when the compensation operation is not performed, the second timing controller TCON2 may activate the second error state. When the second error state is activated, a plurality of second error flag signals ERRFG21 to ERRFG2n (e.g., one or more of the plurality of second error flag signals ERRFG21 to ERRFG2n) may be activated. The second timing controller TCON2 may be referred to as a slave timing controller.

[0085] The first timing controller TCON1 and the second timing controller TCON2 may exchange a plurality of first error flag signals ERRFG11 to ERRFG1n and a plurality of second error flag signals ERRFG21 to ERRFG2n with each other.

[0086] The first timing controller TCON1 may be based on the input data RGB (see Figure 3 ) generates the first image data DS1. The first timing controller TCON1 may determine the output timing of the first image data DS1 based on the plurality of first error flag signals ERRFG11 to ERRFG1n and the plurality of second error flag signals ERRFG21 to ERRFG2n. The first timing controller TCON1 may drive the first display area DA1 based on the first image data DS1.

[0087] The second timing controller TCON2 may be based on the input data RGB (see Figure 3 ) generates the second image data DS2. The second timing controller TCON2 may determine the output timing of the second image data DS2 based on the plurality of first error flag signals ERRFG11 to ERRFG1n and the plurality of second error flag signals ERRFG21 to ERRFG2n. As further described below, the second timing controller TCON2 may drive the second display area DA2 based on the second image data DS2.

[0088] Figure 5A is a block diagram showing a first timing controller and a second timing controller according to an embodiment of the present disclosure, Figure 5B is a block diagram showing a first timing controller according to an embodiment of the present disclosure, and Figure 6 is a timing diagram illustrating a first error flag signal and a first completion signal according to an embodiment of the present disclosure.

[0089] Reference Figure 4 , Figure 5A , Figure 5B and Figure 6, the first timing controller TCON1 may include a first memory unit 100-1, a first correction unit 200-1, a first synchronization unit 300-1, and a first image data generation unit 400-1. The second timing controller TCON2 may include a second memory unit 100-2, a second correction unit 200-2, a second synchronization unit 300-2, and a second image data generation unit 400-2.

[0090] The first memory unit 100-1 may include a memory such as a flash memory. The first memory unit 100-1 may store a plurality of first compensation data IP1 that may be used to perform various compensation operations in the first display area DA1. The first memory unit 100-1 may send the plurality of first compensation data IP1 to the first correction unit 200-1. As further described below, the first memory unit 100-1 (e.g., a flash memory) may receive and store the second error flag signals ERRFG21 to ERRFG2n, and may send the second error flag signals ERRFG21 to ERRFG2n to the first synchronization unit 300-1.

[0091] The first correction unit 200-1 may perform a checksum operation while loading each first compensation data IP1. For example, the checksum operation may calculate a checksum value through the loaded first compensation data IP1, and compare the calculated checksum value with the stored checksum value for the first compensation data IP1 to confirm that the first compensation data IP1 has been successfully and correctly loaded into the first correction unit 200-1. During the loading of the plurality of first compensation data IP1 into the first correction unit 200-1, the plurality of first error flag signals ERRFG11 to ERRFG1n may be deactivated. If the loading of the first compensation data IP1 into the first correction unit 200-1 fails, the first error flag signal corresponding to the unloaded first compensation data IP1 among the plurality of first error flag signals ERRFG11 to ERRFG1n may be activated. In other words, each of the first error flag signals ERRFG11 to ERRFG1n may be activated or deactivated according to whether the first compensation data IP1 corresponding to the first error flag signal is successfully loaded.

[0092] The first correction unit 200-1 may include a memory such as a register. The first correction unit 200-1 may store values ​​corresponding to the first error flag signals ERRFG11 to ERRFG1n, respectively. The first correction unit 200-1 may transmit a plurality of first error flag signals ERRFG11 to ERRFG1n to the first synchronization unit 300-1.

[0093] Before the first correction unit 200-1 performs the checksum operation, the plurality of first error flag signals ERRFG11 to ERRFG1n may be activated to have a high level. When the checksum determination is completed and indicates that each of the plurality of first compensation data IP1 is not damaged, the first error flag signals ERRFG11 to ERRFG1n may be switched to a low level, for example, deactivated. The plurality of first compensation data IP1 may be sequentially transmitted to the first correction unit 200-1, and the first correction unit 200-1 may sequentially generate the plurality of first error flag signals ERRFG11 to ERRFG1n by sequentially checking the plurality of first compensation data IP1.

[0094] When the checksum operation of the plurality of first compensation data IP1 is completed, the signal exchange period SGX may begin. During the signal exchange period SGX, the first correction unit 200-1 may send a plurality of first error flag signals ERRFG11 to ERRFG1n to the second memory unit 100-2 of the second timing controller TCON2. In addition, during the signal exchange period SGX, the first memory unit 100-1 (e.g., flash memory) may receive and store a plurality of second error flag signals ERRFG21 to ERRFG2n from the second correction unit 200-2 of the second timing controller TCON2. Various communication interfaces or protocols may be used for communication between the first timing controller TCON1 and the second timing controller TCON2. For example, low voltage differential signaling (LVDS), "Advanced Internal Panel Interface (AiPi)++" or "V by one" communication may be used.

[0095] The first synchronization unit 300-1 may include a logic gate OR and a controller CTR. A plurality of logic gates OR may be provided, and each of the logic gates OR may receive an associated one of the first error flag signals ERRFG11 to ERRFG1n and an associated one of the plurality of second error flag signals ERRFG21 to ERRFG2n. For example, a first logic gate OR among the plurality of logic gates OR may receive a 1-1st error flag signal ERRFG11 and a 2-1st error flag signal ERRFG21, and a second logic gate OR among the plurality of logic gates OR may receive a 1-2nd error flag signal ERRFG12 and a 2-2nd error flag signal ERRFG22.

[0096] When at least one of the 1-1 error flag signal ERRFG11 and the 2-1 error flag signal ERRFG21 is activated, the first logic gate OR may output a first signal. The first signal may be at a high level. In other words, when an error occurs and the first compensation data IP1 and / or the second compensation data IP2 are not successfully loaded from the first timing controller TCON1 and / or the second timing controller TCON2, respectively (or in the first timing controller TCON1 and / or the second timing controller TCON2, respectively), the first signal may be output from the first logic gate OR. While the second compensation data IP2 is loaded, the second error flag signals ERRFG21 to ERRFG2n may be activated or deactivated, and the operation of the second compensation data IP2 is further described below.

[0097] When the 1-1 error flag signal ERRFG11 is disabled and the 2-1 error flag signal ERRFG21 is disabled, the first logic gate OR may output a second signal different from the first signal. The second signal may be at a low level. In other words, when no error occurs and the first compensation data IP1 and the second compensation data IP2 are loaded from the first timing controller TCON1 and the second timing controller TCON2, respectively (or in the first timing controller TCON1 and the second timing controller TCON2, respectively), the second signal may be output from the first logic gate OR. Each of the logic gates OR may be a logic and gate.

[0098] The controller CTR may receive the first signal and / or the second signal from the plurality of logic gates OR. When receiving at least one first signal from the plurality of logic gates OR, the controller CTR may deactivate the first completion signal read_done1 and output the first completion signal read_done1 having a deactivated state to the first correction unit 200-1. Alternatively, when receiving only the second signal from each of the plurality of logic gates OR, the controller CTR may activate the first completion signal read_done1 and output the first completion signal read_done1 having an activated state to the first correction unit 200-1. In other words, the first synchronization unit 300-1 may output the first completion signal read_done1 to the first correction unit 200-1. In other words, when all the first compensation data IP1 are normally loaded from the first timing controller TCON1 (or in the first timing controller TCON1), the first completion signal read_done1 may be activated.

[0099] The first correction unit 200-1 may receive a first completion signal read_done1 from the controller CTR. The first correction unit 200-1 may generate a first correction signal CPS1 based on the first completion signal read_done1 to apply the first compensation data IP1 to the input data RGB. For example, when the first completion signal read_done1 is activated, the first correction unit 200-1 may generate the first correction signal CPS1. The first correction unit 200-1 may output the first correction signal CPS1 to the first image data generation unit 400-1.

[0100] The first image data generating unit 400-1 may receive input data RGB and a first correction signal CPS1. The first image data generating unit 400-1 may generate first image data DS1 by correcting the input data RGB based on the first correction signal CPS1.

[0101] The configuration of the second timing controller TCON2 may be substantially the same as that of the first timing controller TCON1 .

[0102] The second memory unit 100-2 may store a plurality of second compensation data IP2 for performing various compensation operations in the second display area DA2. The second memory unit 100-2 may transmit the plurality of second compensation data IP2 to the second correction unit 200-2. The plurality of second compensation data IP2 may be data for performing a compensation operation of substantially the same type as the compensation operation using the plurality of first compensation data IP1.

[0103] The second correction unit 200-2 may perform a checksum operation while loading a plurality of second compensation data IP2. Therefore, when loading a plurality of second compensation data IP2 into the second correction unit 200-2 has been successfully completed, a plurality of second error flag signals ERRFG21 to ERRFG2n may be deactivated. When loading a plurality of second compensation data IP2 into the second correction unit 200-2 fails, a second error flag signal corresponding to one of the second compensation data IP2 that has not been successfully loaded among the plurality of second error flag signals ERRFG21 to ERRFG2n may be activated. In other words, each of the second error flag signals ERRFG21 to ERRFG2n may be activated or deactivated according to whether the second compensation data IP2 corresponding to the second error flag signal is successfully loaded.

[0104] The second correction unit 200 - 2 may store the plurality of second error flag signals ERRFG21 to ERRFG2n and transmit the plurality of second error flag signals ERRFG21 to ERRFG2n to the second synchronization unit 300 - 2 .

[0105] Before the checksum operation is performed in the second correction unit 200-2, the plurality of second error flag signals ERRFG21 to ERRFG2n may be activated to a high level. When the checksum operation determines that none of the plurality of second compensation data IP2 is damaged, the plurality of second error flag signals ERRFG21 to ERRFG2n may be deactivated, for example, switched to a low level. The plurality of second compensation data IP2 may be sequentially transmitted from the second memory unit 100-2 to the second correction unit 200-2, and the second correction unit 200-2 may sequentially generate the plurality of second error flag signals ERRFG21 to ERRFG2n by sequentially checking the second compensation data IP2.

[0106] When the checksum operation of the plurality of second compensation data IP2 is completed, the signal exchange period SGX may start. During the signal exchange period SGX, the second correction unit 200-2 may transmit the plurality of second error flag signals ERRFG21 to ERRFG2n to the first memory unit 100-1 of the first timing controller TCON1. ​​In addition, during the signal exchange period SGX, the second memory unit 100-2 may receive and store the plurality of first error flag signals ERRFG11 to ERRFG1n from the first correction unit 200-1 of the first timing controller TCON1.

[0107] When an error occurs when loading the plurality of second compensation data IP2, the second synchronization unit 300-2 may deactivate the second completion signal read_done2 ​​and output the second completion signal read_done2 ​​having a deactivated state to the second correction unit 200-2. Alternatively, when the plurality of second compensation data IP2 are loaded without any error, the second synchronization unit 300-2 may activate the second completion signal read_done2 ​​and output the second completion signal read_done2 ​​having an activated state to the second correction unit 200-2. In other words, the second synchronization unit 300-2 may output the second completion signal read_done2 ​​to the second correction unit 200-2, and may activate the second completion signal read_done2 ​​when all the second compensation data IP2 are normally loaded in the second timing controller TCON2.

[0108] The second correction unit 200-2 may receive the second completion signal read_done2. The second correction unit 200-2 may generate a second correction signal CPS2 based on the second completion signal read_done2 ​​to apply the plurality of second compensation data IP2 to the input data RGB. For example, when the second completion signal read_done2 ​​is activated, the second correction unit 200-2 may generate the second correction signal CPS2. The second correction unit 200-2 may output the second correction signal CPS2 to the second image data generation unit 400-2.

[0109] The second image data generating unit 400-2 may receive input data RGB and a second correction signal CPS2. The second image data generating unit 400-2 may generate second image data DS2 by correcting the input data RGB based on the second correction signal CPS2. When a loading error of a corresponding one of a plurality of first compensation data IP1 and a plurality of second compensation data IP2 occurs in one of the first timing controller TCON1 and the second timing controller TCON2, if a timing controller without an error performs a compensation operation to output image data and a timing controller with an error outputs image data without performing a compensation operation, image quality may be deteriorated. In particular, the compensation operation may be performed only in one of the first display area DA1 and the second display area DA2, and a user may recognize a difference in image quality between the first display area DA1 and the second display area DA2. However, according to the present disclosure, the first timing controller TCON1 and the second timing controller TCON2 respectively detect the loading errors of the plurality of first compensation data IP1 and the plurality of second compensation data IP2 to respectively generate the plurality of first error flag signals ERRFG11 to ERRFG1n and the plurality of second error flag signals ERRFG21 to ERRFG2n, and the first timing controller TCON1 and the second timing controller TCON2 exchange the plurality of first error flag signals ERRFG11 to ERRFG1n and the plurality of second error flag signals ERRFG21 to ERRFG2n. When at least one of the first error flag signals ERRFG11 to ERRFG1n and the second error flag signals ERRFG21 to ERRFG2n is activated, the first timing controller TCON1 and the second timing controller TCON2 may not perform the compensation operation in the first display area DA1 and the second display area DA2, respectively. In other words, the compensation operation may be prevented from being performed in only one of the first display area DA1 and the second display area DA2. Therefore, the electronic device 1000 may have improved display quality.

[0110] Figure 7 is a timing diagram illustrating a first completion signal and a second completion signal according to an embodiment of the present disclosure. Figure 8 is a block diagram illustrating a first timing controller, a second timing controller, and a pull-up resistor circuit according to an embodiment of the present disclosure.

[0111] Reference Figure 5A , Figure 7 and Figure 8 , the electronic device 1000 may further include a pull-up resistor circuit PRC.

[0112] The pull-up resistor circuit PRC may be electrically connected between the first timing controller TCON1 and the second timing controller TCON2. The pull-up resistor circuit PRC may apply a driving signal VCC to the first timing controller TCON1 and the second timing controller TCON2, and the driving signal VCC may have the same voltage level as a high level (or activation level) of the first completion signal read_done1 and the second completion signal read_done2.

[0113] The pull-up resistor circuit PRC may include a pull-up resistor PR connected to the ports of the first timing controller TCON1 and the second timing controller TCON2. The pull-up resistor PR may be linked to the drive signal VCC to prevent the ports of the first timing controller TCON1 and the second timing controller TCON2 from floating when the port of the first timing controller TCON1 is in the input port mode and the port of the second timing controller TCON2 is in the input port mode. The input port mode is a mode in which the port can receive an input signal. In other words, when the port of the first timing controller TCON1 is in the input port mode and the port of the second timing controller TCON2 is in the input port mode, the ports of the first timing controller TCON1 and the second timing controller TCON2 can receive the drive signal VCC.

[0114] exist Figure 7 During the first period SS1 shown in , the loading of the plurality of first compensation data IP1 of the first timing controller TCON1 and the loading of the plurality of second compensation data IP2 of the second timing controller TCON2 may not be completed. Therefore, during the first period SS1, the first completion signal read_done1 and the second completion signal read_done2 ​​may be disabled. When the first completion signal read_done1 and the second completion signal read_done2 ​​are disabled, the ports of the first timing controller TCON1 and the second timing controller TCON2 may operate in the output port mode. The output port mode is a mode in which the port can send an output signal. The port of the first timing controller TCON1 may output the first completion signal read_done1 having a disabled state, and the port of the second timing controller TCON2 may output the second completion signal read_done2 ​​having a disabled state.

[0115] The second period SS2 may include a 2-1 period SS2-1 and a 2-2 period SS2-2. During the 2-1 period SS2-1, loading of a plurality of first compensation data IP1 into the first timing controller TCON1 may be completed, and loading of a plurality of second compensation data IP2 into the second timing controller TCON2 may not be completed. During the 2-1 period SS2-1, the first completion signal read_done1 may be activated, and the second completion signal read_done2 ​​may be deactivated. When the first completion signal read_done1 is activated, the port of the first timing controller TCON1 may operate in the input port mode. The second completion signal read_done2 ​​may be deactivated, so that the port of the second timing controller TCON2 may remain in the output port mode. During the 2-2 period SS2-2, the second timing controller TCON2 outputs the second completion signal read_done2 ​​having the deactivated state, and the first timing controller TCON1 may receive the second completion signal read_done2 ​​having the deactivated state through the port operating in the input port mode, and thus the first completion signal read_done1 may remain in a substantially deactivated state.

[0116] During the third period SS3, loading of a plurality of first compensation data IP1 and a plurality of second compensation data IP2 into the first timing controller TCON1 and the second timing controller TCON2 may be completed. In other words, the time point t of the third period SS3 may be a time point at which the loading of a plurality of second compensation data IP2 into the second timing controller TCON2 is completed. The first completion signal read_done1 and the second completion signal read_done2 ​​may be activated. When the second completion signal read_done2 ​​is activated, the port of the second timing controller TCON2 may operate in the input port mode. In other words, during the third period SS3, the port of the first timing controller TCON1 may operate in the input port mode, and the port of the second timing controller TCON2 may operate in the input port mode. The ports of the first timing controller TCON1 and the second timing controller TCON2 may receive the driving signal VCC from the pull-up resistor circuit PRC. During the third period SS3, the first completion signal read_done1 and the second completion signal read_done2 ​​may be simultaneously activated to a high level substantially synchronously at the time point t.

[0117] As mentioned above, refer again Figure 4 and Figure 5A, the first correction unit 200-1 of the first timing controller TCON1 and the second correction unit 200-2 of the second timing controller TCON2 may simultaneously activate the first completion signal read_done1 and the second completion signal read_done2 ​​at the time point t, and output the first completion signal read_done1 having an activated state and the second completion signal read_done2 ​​having an activated state to the first image data generating unit 400-1 and the second image data generating unit 400-2, respectively. Therefore, the time points of outputting the compensated first image data DS1 and the second image data DS2 respectively provided to the first display area DA1 and the second display area DA2 may be simultaneous with each other.

[0118] The electronic device 1000 of the present disclosure is capable of avoiding image degradation that may occur during the second period SS2. In particular, if the port of the first timing controller TCON1 is not operated in the input port mode and the first completion signal read_done1 is activated and the second completion signal read_done2 ​​is deactivated, the first timing controller TCON1 may perform a compensation operation on the first display area DA1. As a result, since the second completion signal read_done2 ​​has not yet been activated, the compensation operation may not be performed in the second display area DA2. In other words, during the second period SS2, the user may recognize the difference in image quality between the first display area DA1 and the second display area DA2. However, according to the present disclosure, during the second period SS2, the first timing controller TCON1 may operate in the input port mode, and the second timing controller TCON2 may operate in the output port mode. Therefore, during the second period SS2, the first timing controller TCON1 may not perform a compensation operation in the first display area DA1. During the third period SS3, the first timing controller TCON1 and the second timing controller TCON2 may simultaneously perform compensation operations on the first display area DA1 and the second display area DA2 at a time point t at which the pull-up resistor circuit PRC activates both the first completion signal read_done1 and the second completion signal read_done2. Therefore, the electronic device 1000 can avoid a difference in image quality between the first display area DA1 and the second display area DA2. Therefore, the electronic device 1000 with improved display quality can be provided.

[0119] Fig. 9 and Fig.10 is a block diagram showing a display panel, a timing controller, and a processor according to an embodiment of the present disclosure. Fig. 9 In the description, the same reference numerals are assigned to the reference Figure 4 The same components as described above will be omitted in detail. Fig.10In the description, the same reference numerals will be assigned to the reference Figure 5B The same components are described herein and their details will be omitted.

[0120] Reference Fig. 9 and Fig.10 , the electronic device 1000-1 may include a display panel DP, a timing controller TCON-1, and a processor AP. The timing controller TCON-1 may include a plurality of timing controllers. For example, the plurality of timing controllers TCON-1 may include a first timing controller TCON1-1 and a second timing controller TCON2-1. In other embodiments, the timing controller TCON-1 may include more than two timing controllers.

[0121] The first timing controller TCON1-1 may determine a first error state and generate a plurality of first error flag signals ERRFG11 to ERRFG1n indicating the first error state. Determining the first error state may include determining whether compensation data for performing a compensation operation is successfully loaded in the first timing controller TCON1-1. In other words, when the first timing controller TCON1-1 does not perform a compensation operation on the first display area DA1, the first error state may be activated. When the first error state is activated, one or more of the first error flag signals ERRFG11 to ERRFG1n may be activated. The first timing controller TCON1-1 may send a plurality of first error flag signals ERRFG11 to ERRFG1n to the processor AP.

[0122] The second timing controller TCON2-1 may determine a second error state and generate a plurality of second error flag signals ERRFG21 to ERRFG2n indicating the second error state. Determining the second error state may include determining whether compensation data for performing a compensation operation is loaded into the second timing controller TCON2-1. In other words, when the second timing controller TCON2-1 does not perform a compensation operation on the second display area DA2, the second error state may be activated. When the second error state is activated, one or more of the second error flag signals ERRFG21 to ERRFG2n may be activated. The second timing controller TCON2-1 may send a plurality of second error flag signals ERRFG21 to ERRFG2n to the processor AP.

[0123] The first timing controller TCON1-1 may be based on the input data RGB (see Figure 3 ) to generate the first image data DS1. The first timing controller TCON1-1 may drive the first display area DA1 based on the first image data DS1.

[0124] The second timing controller TCON2-1 may be based on the input data RGB (see Figure 3) to generate the second image data DS2. The second timing controller TCON2-1 may drive the second display area DA2 based on the second image data DS2.

[0125] The processor AP may receive a plurality of first error flag signals ERRFG11 to ERRFG1n and a plurality of second error flag signals ERRFG21 to ERRFG2n. The processor AP may include a logic gate OR-1 and a controller CTR-1. A plurality of logic gates OR-1 may be provided in the processor AP, and each of the logic gates OR-1 may receive one of the first error flag signals ERRFG11 to ERRFG1n and one of the second error flag signals ERRFG21 to ERRFG2n. For example, the first logic gate OR-1 among the plurality of logic gates OR-1 may receive the 1-1st error flag signal ERRFG11 and the 2-1st error flag signal ERRFG21.

[0126] When at least one of the 1-1st error flag signal ERRFG11 and the 2-1st error flag signal ERRFG21 is activated, the first logic gate OR-1 may output a first signal. The first signal may be at a high level. In other words, when an error occurs when the first timing controller TCON1-1 or the second timing controller TCON2-1 loads compensation data of the display panel DP, the first signal may be output from the first logic gate OR-1.

[0127] When the 1-1 error flag signal ERRFG11 is disabled and the 2-1 error flag signal ERRFG21 is disabled, the first logic gate OR-1 may output a second signal different from the first signal. The second signal may be at a low level. In other words, when no error occurs and the compensation data of the display panel DP is loaded in each of the first timing controller TCON1-1 and the second timing controller TCON2-1, the second signal may be output from the first logic gate OR-1. Each of the remaining logic gates may operate in the same manner. In other words, each of the plurality of logic gates OR-1 may be a logic and gate.

[0128] The controller CTR-1 may receive a first signal and / or a second signal from a plurality of logic gates OR-1. When receiving at least one first signal from a plurality of logic gates OR-1, the controller CTR-1 may deactivate a completion signal read_done, and output a completion signal read_done having a deactivated state to the first timing controller TCON1-1 and the second timing controller TCON2-1. When only a second signal is received from all logic gates OR-1, the controller CTR-1 may activate a completion signal read_done, and output a completion signal read_done having an activated state to the first timing controller TCON1-1 and the second timing controller TCON2-1. The processor AP may therefore output a completion signal read_done to the first timing controller TCON1-1 and the second timing controller TCON2-1, and when compensation data is normally loaded into each of the timing controllers TCON-1, the completion signal read_done may be activated.

[0129] When the first timing controller TCON1-1 and the second timing controller TCON2-1 receive the completion signal read_done, the first timing controller TCON1-1 and the second timing controller TCON2-1 may synchronously drive the first display area DA1 and the second display area DA2 of the display panel DP. The first timing controller TCON1-1 may drive the first display area DA1 based on the first image data DS1 to which the compensation operation is applied. The second timing controller TCON2-1 may drive the second display area DA2 based on the second image data DS2 to which the compensation operation is applied.

[0130] The electronic device 1000-1 is able to avoid image degradation that may otherwise occur when a loading error of compensation data occurs in one of the first timing controller TCON1-1 and the second timing controller TCON2-1. In particular, if a timing controller without an error performs a compensation operation to output image data and a timing controller with an error outputs image data without performing a compensation operation, image degradation may occur. For example, in such a case, a compensation operation may be performed in one of the first display area DA1 and the second display area DA2, but a compensation operation may not be performed in the remaining one of the first display area DA1 and the second display area DA2, and a user may recognize a difference in image quality between the first display area DA1 and the second display area DA2. However, according to the present disclosure, the first timing controller TCON1-1 and the second timing controller TCON2-1 detect a loading error of the compensation data to generate a plurality of first error flag signals ERRFG11 to ERRFG1n and a plurality of second error flag signals ERRFG21 to ERRFG2n, respectively, and transmit the plurality of first error flag signals ERRFG11 to ERRFG1n and a plurality of second error flag signals ERRFG21 to ERRFG2n to the processor AP. When at least one of the first error flag signals ERRFG11 to ERRFG1n and the second error flag signals ERRFG21 to ERRFG2n is activated, the processor AP may deactivate the completion signal read_done so that the compensation operation may not be performed in the first display area DA1 and the second display area DA2. In other words, the compensation operation may be prevented from being performed on only one of the first display area DA1 and the second display area DA2. Therefore, the electronic device 1000-1 may provide improved display quality.

[0131] As described above, the first timing controller and the second timing controller can sense the loading error in the compensation data, can generate a plurality of first error flag signals and a plurality of second error flag signals, respectively, and can exchange the plurality of first error flag signals and a plurality of second error flag signals with each other or with a shared processor. When at least one of the first error flag signal and the second error flag signal is activated, the first timing controller and the second timing controller can be prevented from performing the compensation operation on the first display area and the second display area. In other words, it can be prevented from performing the compensation operation on only one of the first display area and the second display area. Therefore, an electronic device with improved display quality can be provided.

[0132] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be appreciated by those skilled in the art that various modifications and substitutions are possible without departing from the scope and spirit of the present disclosure disclosed in the appended claims. Therefore, the technical scope of the present disclosure is not limited to the detailed description of this specification, but should be defined by the claims.

[0133] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. An electronic device, comprising: A display panel, the display panel comprising a first display area and a second display area adjacent to the first display area; a first timing controller configured to drive the first display area; and a second timing controller, the second timing controller being configured to drive the second display area, wherein the first timing controller determines a first error state of the first display area and generates a first error flag signal indicating the first error state, wherein the second timing controller determines a second error state of the second display area and generates a second error flag signal indicating the second error state, The first timing controller and the second timing controller exchange the first error flag signal and the second error flag signal with each other. wherein, when at least one of the first error flag signal and the second error flag signal is activated, the first timing controller deactivates the first completion signal, wherein when at least one of the second error flag signal and the first error flag signal is activated, the second timing controller deactivates the second completion signal, and Wherein, when the first completion signal is activated and the second completion signal is activated, the first timing controller and the second timing controller drive the first display area and the second display area of ​​the display panel respectively.

2. The electronic device according to claim 1, wherein: The first timing controller comprises: a first correction unit, the first correction unit being configured to store the first error flag signal; a first memory unit, the first memory unit being configured to store the second error flag signal; a logic gate that receives the first error flag signal and the second error flag signal; and A controller is configured to receive a first signal or a second signal from the logic gate and activate or deactivate the first completion signal based on the first signal or the second signal.

3. The electronic device according to claim 2, wherein: The logic gate outputs the first signal when at least one of the first error flag signal and the second error flag signal is activated.

4. The electronic device according to claim 3, wherein: The logic gate outputs the second signal different from the first signal when the first error flag signal is disabled and the second error flag signal is disabled.

5. The electronic device according to claim 4, wherein: The controller activates the first completion signal in response to the second signal.

6. The electronic device according to claim 1, wherein: The first timing controller is configured to operate in an output port mode to output the first completion signal having a low level when the first completion signal is deactivated.

7. The electronic device according to claim 1, wherein: The first timing controller is configured to operate in an input port mode when the first completion signal is activated, wherein the second timing controller is configured to operate in an output port mode to output the second completion signal having a low level when the second completion signal is disabled, and Wherein, the first timing controller is configured to receive the second completion signal having the low level.

8. The electronic device according to claim 1, further comprising: A pull-up resistor circuit applies a driving signal having a high level to the first timing controller and the second timing controller.

9. The electronic device according to claim 8, wherein: When the first completion signal is activated and the second completion signal is activated, the first timing controller is configured to operate in an input port mode to receive the driving signal, and the second timing controller operates in the input port mode to receive the driving signal, and When receiving the driving signal, the first timing controller and the second timing controller synchronously drive the first display area and the second display area of ​​the display panel.

10. The electronic device according to claim 1, wherein: The first timing controller is configured to perform a compensation operation on the first display area, and Wherein, when the compensation operation is not performed, the first error state is activated.

11. The electronic device according to claim 10, wherein: The first timing controller is configured to perform a checksum operation on data required for the compensation operation and generate the first error flag signal based on a result of the checksum operation.

12. An electronic device comprising: A display panel, the display panel comprising a first display area and a second display area adjacent to the first display area; a first timing controller, the first timing controller being configured to drive the first display area; a second timing controller, the second timing controller being configured to drive the second display area; as well as a processor, wherein the processor is configured to drive the first timing controller and the second timing controller, wherein the first timing controller determines a first error state of the first display area and generates a first error flag signal indicating the first error state, wherein the second timing controller determines a second error state of the second display area and generates a second error flag signal indicating the second error state, The first timing controller and the second timing controller provide the first error flag signal and the second error flag signal to the processor, wherein the processor is configured to deactivate the completion signal when at least one of the first error flag signal and the second error flag signal is activated, and Wherein, the processor is configured to respectively drive the first display area and the second display area of ​​the display panel when the completion signal is activated.

13. The electronic device according to claim 12, wherein: The processor comprises: a logic gate that receives the first error flag signal and the second error flag signal; and A controller is configured to receive a first signal or a second signal from the logic gate and activate or deactivate the completion signal based on the first signal or the second signal.

14. The electronic device according to claim 13, wherein: The logic gate is a logic AND gate.

15. The electronic device according to claim 13, wherein: The logic gate outputs the first signal when at least one of the first error flag signal and the second error flag signal is activated.

16. The electronic device according to claim 15, wherein: The logic gate outputs the second signal different from the first signal when the first error flag signal is disabled and the second error flag signal is disabled.

17. The electronic device according to claim 16, wherein: The controller activates the completion signal upon receiving the second signal.

18. The electronic device according to claim 12, wherein: The processor is configured to output the completion signal activated by the first timing controller and the second timing controller, and When receiving the completion signal, the first timing controller and the second timing controller synchronously drive the first display area and the second display area of ​​the display panel.

19. The electronic device according to claim 12, wherein: The first timing controller is configured to perform a compensation operation on the first display area, and Wherein, when the compensation operation is not performed, the first error state is activated.

20. The electronic device according to claim 19, wherein: The first timing controller is configured to perform the compensation operation through a checksum and generate the first error flag signal.

Images