Compression memory module and apparatus

Abstract

The disclosure provides a crimped memory module and equipment, and relates to the technical field of semiconductors. The crimped memory module comprises a crimped memory circuit board, a plurality of memory chips arranged on the crimped memory circuit board, and a power management device arranged on the crimped memory circuit board and electrically connected with the plurality of memory chips. The power management device comprises a preset number of power management chips, and is configured to provide power generated by the preset number of power management chips to the plurality of memory chips as power supply power. The preset number of power management chips in the power management device is preset according to the power demand of the plurality of memory chips. According to the embodiment of the disclosure, the crimped memory module can have a power supply scheme suitable for itself.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a compress attached memory module and a device. BACKGROUND

[0002] With the development of semiconductor technology, a compress attached memory module (CAMM) has become one of the important research directions of semiconductor technology due to its thinner thickness, better heat dissipation effect, lower power consumption and other characteristics.

[0003] However, the compress attached memory module at the present stage lacks a power supply scheme suitable for itself.

[0004] Therefore, how to provide a compress attached memory module with a power supply scheme suitable for itself has become a technical problem to be solved. SUMMARY

[0005] The present disclosure provides a compress attached memory module and a device, which at least partially solves the problem that the compress attached memory module lacks a power supply scheme suitable for its own power supply needs.

[0006] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a compress attached memory module is provided, comprising:

[0008] a compress attached memory circuit board;

[0009] a plurality of memory chips disposed on the compress attached memory circuit board;

[0010] a power management device disposed on the compress attached memory circuit board and electrically connected to the plurality of memory chips, the power management device comprising a preset number of power management chips for providing power generated by the preset number of power management chips to the plurality of memory chips as power supply energy, wherein the preset number of power management chips in the power management device is preset according to the power consumption demand of the plurality of memory chips.

[0011] In one embodiment, the power management device comprises a plurality of power management chips, wherein the power management chip comprises a first power supply pin, and the first power supply pins of the plurality of power management chips are connected to provide power generated by the plurality of power management chips to the plurality of memory chips through the connected first power supply pins.

[0012] In one embodiment, the first power supply pin includes N power supply pins, each of which is configured to output a power supply voltage, wherein an i-th power supply pin of the plurality of power management chips is connected to provide the power supply voltage outputted by the connected i-th power supply pin to the plurality of memory chips, wherein N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

[0013] In one embodiment, the module further includes a configuration serial detection chip configured to store preset power supply quantity information, wherein the preset power supply quantity information is configured to indicate the quantity of power management chips in the power management device.

[0014] In one embodiment, the power management chip further includes a mode register configured to store preset power supply configuration information of the power management chip, wherein the preset power supply configuration information is configured by the chip control device based on the preset power supply quantity information in the configuration serial detection chip.

[0015] In one embodiment, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin, wherein the first communication pin is connected to the second communication pin of each power management chip to realize the communication connection between the configuration serial detection chip and each power management chip.

[0016] In one embodiment, the configuration serial detection chip includes a first power supply pin, and each power management chip further includes a second power supply pin.

[0017] In the case that the power management device includes a plurality of power management chips, the second power supply pin of a target power management chip in the power management device is connected to the first power supply pin, and the second power supply pin of each power management chip other than the target power management chip is left unused, so that the electric energy outputted by the second power supply pin of the target power management chip is provided to the configuration serial detection chip as the power supply electric energy of the configuration serial detection chip.

[0018] In one embodiment, each power management chip includes a state signal pin configured to output a first level indicating normality of each power management chip or a second level indicating failure of each power management chip, wherein, in the case that the power management device includes a plurality of power management chips, the state signal pins of the plurality of power management chips are connected to a state signal transmission line, wherein, when the state signal pin of one or more power management chips outputs the second level, the level on the state signal transmission line is adjusted to the second level, and the second level on the state signal transmission line represents failure of the power management device.

[0019] In one embodiment, each power management chip comprises an enable pin, the enable pin being used to start or stop each power management chip, wherein the enable pin of each power management chip is used to receive a control instruction sent by the chip control device, the control instruction being used to start or stop each power management chip.

[0020] In one embodiment, each power management chip comprises a communication address pin, the communication address pin being used to indicate the communication address of each power management chip, wherein the communication address pins of the plurality of power management chips correspond to different voltages, and the different voltages represent different communication addresses.

[0021] In one embodiment, the first power supply pin of one of the plurality of power management chips is directly connected to the first conductive wire, and the first power supply pins of the other power management chips are connected to the first conductive wire or the first power supply pin of one of the power management chips through a connection.

[0022] In one embodiment, the connection comprises one or more of a resistor with a preset resistance, a connection wire, a switching element, and a fuse device.

[0023] In one embodiment, the connection comprises a fuse device, which is a fuse or an anti-fuse.

[0024] For each other power management chip, when the fuse device corresponding to each other power management chip is in a low resistance state, each other power management chip supplies power to the plurality of memory chips; and when the fuse device is in a high resistance state, each other power management chip does not supply power to the plurality of memory chips.

[0025] In one embodiment, the resistance state of the fuse device is adjusted by a test machine when the actual number of power supply management chips is incorrect.

[0026] In one embodiment, the test machine determines whether the actual number is incorrect based on preset power supply number information, wherein the preset power supply number information is stored in the configuration serial detection chip and is used to indicate the number of power management chips in the power supply management device; when the actual number is incorrect and the actual number is greater than the number indicated by the preset power supply number information, the test machine adjusts the first target fuse device to a high resistance state to disconnect the power management chip corresponding to the first target fuse device from the power supply management device; and when the actual number is incorrect and the actual number is less than the number indicated by the preset power supply number information, the test machine adjusts the fuse device to a low resistance state to connect the power management chip corresponding to the second target fuse device to the power supply management device.

[0027] In one embodiment, each power management chip is used to supply power to part of the plurality of memory chips.

[0028] In one embodiment, the plurality of memory chips can be divided into a plurality of groups, each group of memory chips belonging to one memory channel, each power management chip corresponding to at least one memory channel, and each power management chip being configured to provide power supply energy for the memory chips in the corresponding memory channel.

[0029] According to still another aspect of the present disclosure, an electronic device is provided, comprising the crimped memory module as described above.

[0030] The crimped memory module and the electronic device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power consumption demand of the memory chips, so that the power consumption demand of various crimped memory modules can be flexibly met according to the power generated by the preset number of power management chips, and the occurrence of voltage drop caused by insufficient power supply is avoided. Furthermore, the technical solutions provided by the embodiments of the present disclosure can ensure the stability of power supply while realizing flexible power supply for the crimped memory module, so that the crimped memory module can have a power supply scheme suitable for itself.

[0031] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0032] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0033] Figure 1 A structural schematic diagram of a crimped memory module provided by an embodiment of the present disclosure is shown;

[0034] Figure 2 A structural schematic diagram of a crimped memory module provided by an embodiment of the present disclosure is shown;

[0035] Figure 3 A structural schematic diagram of an exemplary crimped memory module provided by an embodiment of the present disclosure is shown;

[0036] Figure 4 A structural schematic diagram of an exemplary power management chip provided by an embodiment of the present disclosure is shown;

[0037] Figure 5 A structural schematic diagram of another exemplary crimped memory module provided by an embodiment of the present disclosure is shown;

[0038] Figure 6Fig. 6 shows a structural schematic diagram of another exemplary crimped memory module provided by an embodiment of the present disclosure;

[0039] Figure 7 Fig. 7 shows a structural schematic diagram of another exemplary crimped memory module provided by an embodiment of the present disclosure;

[0040] Figure 8 Fig. 8 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0041] Figure 9 Fig. 9 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0042] Figure 10 Fig. 10 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0043] Figure 11 Fig. 11 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0044] Figure 12 Fig. 12 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0045] Figure 13 Fig. 13 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0046] Figure 14 Fig. 14 shows a structural schematic diagram of another exemplary power management chip provided by an embodiment of the present disclosure;

[0047] Figure 15 Fig. 15 shows a structural schematic diagram of an exemplary first power management chip provided by an embodiment of the present disclosure;

[0048] Figure 16 Fig. 16 shows a structural schematic diagram of an exemplary second power management chip provided by an embodiment of the present disclosure;

[0049] Figure 17 Fig. 17 shows a structural schematic diagram of an exemplary configuration serial detection chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] Example implementations will now be described more fully with reference to the accompanying drawings. Example implementations can be implemented in any number of manners, and are not limited to the examples described herein; rather, examples are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example implementations to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more implementations.

[0051] As background, Compress Attached Memory Module (CAMM) has become one of the important research directions of semiconductor technology.

[0052] Figure 1 A structural schematic diagram of a compress attached memory module is shown. As shown, the compress attached memory module 10 and the system main board 20 can be arranged between the top bolster plate 30 and the bottom bolster plate 40, and the compress attached memory module 10 can be fixed on the compression connector 50 of the system main board 20 by using screws. In some embodiments, the external connection end of the compress attached memory module 10 can be a contact. Accordingly, the compress attached memory module 10 can use a combination of contacts and screws to realize circuit connection and fixation with the system main board. Figure 1

[0053] However, the standard of the compress attached memory module has not yet been completed. The inventors have found through research that, in an exemplary scenario, a small outline dual in-line memory module (SoDIMM) has only one memory channel, while the compress attached memory module can have two independent memory channels. Therefore, theoretically, the load of the compress attached memory module is twice that of the small outline dual in-line memory module. Thus, if the power supply design scheme of the small outline dual in-line memory module is borrowed, that is, if one power management integrated circuit (PMIC) is used to supply power to the memory chips in the compress attached memory module, in an extreme case, the power supply demand of the compress attached memory module may not be met, causing voltage drop and the like.

[0054] Therefore, how to provide a compress attached memory module with a power supply scheme suitable for itself has become a technical solution to be solved.

[0055] Based on this, the embodiments of the present disclosure provide a compress attached memory module and equipment, which can be applied in a semiconductor storage scene, such as a module design scene, especially a power supply design scene of a CAMM module. Through the technical scheme provided by the embodiments of the present disclosure, flexible power supply for the compress attached memory module can be realized while ensuring the stability of the power supply, so that the compress attached memory module can have a power supply scheme suitable for itself.

[0056] ​Before starting to explain the technical solutions provided by the embodiments of the present disclosure, the technical terms related to the embodiments of the present disclosure are explained.

[0057] (1) Power Management Integrated Circuit (PMIC), which is an integrated circuit for voltage conversion, voltage stabilization, and battery management. Exemplarily, in the field of semiconductor technology, its important role can be to provide power support for other chips (such as memory chips, etc.) on the memory module.

[0058] (2) Serial Presence Detect (SPD), which is a chip for storing SPD information of the memory module. Exemplarily, the SPD information includes important information of the memory module, such as chip information of the memory mode, module manufacturer information, working frequency, working voltage, speed, capacity, voltage, row-column address bandwidth, etc. Exemplarily, the serial presence detect chip can be an Electrically Erasable Programmable Read-Only Memory (EEPROM). Exemplarily, the chip control device can access the SPD information in the serial presence detect chip through an Inter-Integrated Circuit (I2C) bus or a System Management Bus (SMBus).

[0059] After introducing the above technical terms, the technical solutions provided by the embodiments of the present disclosure are explained next.

[0060] Figure 2 A structure schematic diagram of a crimped memory module provided by an embodiment of the present disclosure is shown. As shown in Figure 2 The crimped memory module 20 can include a crimped memory circuit board 21, a plurality of memory chips 22, and a power management device 23. The crimped memory module can have two independent memory channels. Next, the parts of the crimped memory module will be explained one by one.

[0061] For the crimped memory circuit board 21, it can be a circuit board for realizing electrical connection between devices in the crimped memory module 20, such as a Printed Circuit Board (PCB) or other circuit board, and the specific form of the crimped memory circuit board 21 is not limited.

[0062] For the memory chip 22, it can be disposed on the crimped memory circuit board 10.

[0063] In terms of the arrangement, in some embodiments, the memory chips 22 can be arranged on one side surface of the press-fit memory circuit board 10. In other embodiments, the memory chips 22 can be arranged on both side surfaces of the press-fit memory circuit board 10.

[0064] In terms of the specific form, in some embodiments, the memory chips 22 can be chips for data storage. For example, the memory chips 22 can be Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), or flash memory chips. For example, the memory chips 22 can be Dual Data Rate SDRAM (DDR SDRAM) or Low Power Dual Data Rate SDRAM (LPDDR SDRAM). For example, the semiconductor memory can be DDR5, DDR6, LPDDR4, LPDDR5, LPDDR6, etc. The present disclosure does not limit the specific form of the memory chips 22.

[0065] After the memory chips 22 are introduced, the power management device 23 will be described next.

[0066] The power management device 23 can be arranged on the press-fit memory circuit board 21 and electrically connected to the plurality of memory chips 22. The power management device 23 includes a predetermined number (such as K) of power management chips 2311 to 231K for providing power energy generated by the predetermined number of power management chips 2311 to 231K to the plurality of memory chips 20 as supply power energy. The number (i.e., K) of power management chips in the power management device 23 is set according to the power demand of the plurality of memory chips 20.

[0067] Next, the power management device 23 will be described in terms of the arrangement position, the specific structure, the number of power management chips, the power supply mode, etc.

[0068] In terms of the arrangement position, in some embodiments, the power management chips 2311 to 231K can be arranged on the memory card of the press-fit memory module.

[0069] In terms of the specific structure, in some embodiments, in order to provide supply power energy to the memory chips, in the case where the power management device 23 includes a plurality of power management chips 2311 to 231K, each power management chip includes a first supply pin A1, where the first supply pin A1 can be a pin for providing supply power energy to the memory chips.

[0070] Specifically, the first supply pins A1 of the plurality of power management chips are connected to supply the electric energy generated by the plurality of power management chips 2311 to 231K to the plurality of memory chips through the connected first supply pins A1. For example, the first supply pins of the plurality of power management chips 2311 to 231K can supply the electric energy generated by the plurality of power management chips to the plurality of memory chips 22 through the first conductive line by being connected to the same first conductive line.

[0071] In one example, Figure 3 An exemplary structure diagram of a crimped memory module is shown. As Figure 3 As shown, in the case where the power management device 23 includes two power management chips, i.e., the first power management chip 2311 and the second power management chip 2312, the first supply pins A1 of the first power management chip 2311 and the second power management chip 2312 are connected to supply the electric energy generated by the first power management chip 2311 and the second power management chip 2312 to the memory chips through the connected first supply pins A1. For example, the supply voltage V0 output by the first supply pins A1 of the first power management chip 2311 and the second power management chip 2312 after being connected can be supplied to the memory chips as the power supply voltage of the memory chips.

[0072] According to the embodiments of the present disclosure, the first supply pins can be used to realize the joint power supply of the plurality of power management chips to the plurality of memory chips, meet the power demand of the plurality of memory chips, avoid the occurrence of voltage drop caused by insufficient power supply, and ensure the stability of power supply.

[0073] In one embodiment, in order to provide a plurality of supply voltages to the memory chips, each first supply pin A1 includes N power supply pins, and each power supply pin is used to output one supply voltage. N is an integer greater than or equal to 1. For example, Figure 4 An exemplary structure diagram of a power management chip is shown. As Figure 4As shown, for the first power management chip 2311, it can include multiple power supply pins, such as power supply pins A111, A112 and A113. The second power management chip 2312 can include multiple power supply pins, such as power supply pins A121, A122 and A123. In one specific example, in order to ensure stable output of voltage, each power supply pin can include a switching voltage pin, a boot voltage pin and a feedback voltage pin. For example, taking the power supply pins A111 and A121 as an example, they can include a switching voltage pin SWA, a boot voltage pin SWA_BOOT and a feedback voltage pin SWA_FB_P. Taking the power supply pins A112 and A122 as an example, they can include a switching voltage pin SWB, a boot voltage pin SWB_BOOT and a feedback voltage pin SWB_FB_P. Taking the power supply pins A113 and A123 as an example, they can include a switching voltage pin SWC, a boot voltage pin SWC_BOOT and a feedback voltage pin SWC_FB_P.

[0074] Specifically, the ith power supply pin of the multiple power management chips is connected to provide a power supply voltage output by the connected ith power supply pin to the multiple memory chips. Wherein, i is any integer less than or equal to N. Exemplarily, the ith power supply pin can be connected to the ith first conductive line to provide the power supply voltage output by the ith power supply pin to the multiple memory chips through the ith first conductive line.

[0075] In one example, continuing to refer to Figure 4 , the first power supply pin A111 of the first power management chip 2311 is connected to the first power supply pin A121 of the second power management chip 2312 to output a first power supply voltage VDD; the second power supply pin A112 of the first power management chip 2311 is connected to the second power supply pin A122 of the second power management chip 2312 to output a second power supply voltage VDDQ; and the third power supply pin A113 of the first power management chip 2311 is connected to the third power supply pin A123 of the second power management chip 2312 to output a third power supply voltage VPP.

[0076] Through the embodiments of the present disclosure, N power supply pins of the multiple power management chips are connected respectively, and N power supply voltages are provided to the memory chips through the N power supply pins, so that the power management device can realize stable output of multiple power supply voltages, and the power supply capacity of the power management device is improved.

[0077] In some embodiments, Figure 5 An exemplary structure schematic diagram of a crimped memory module provided by the embodiments of the present disclosure is shown. As shown in Figure 5As shown, the first power supply pin A1 of one of the plurality of power management chips 2311-231K (such as the first power management chip 2311) is directly connected to the first conductive line L1, and the first power supply pin A1 of the other power management chips (such as the second power management chip 2312-231K) is connected to the first conductive line L1 or the first power supply pin A1 of one of the plurality of power management chips (such as the first power management chip 2311) through the connecting element 232.

[0078] Through the embodiment, the plurality of power management chips 2311-231K can be connected to the first conductive line L1 through the connecting element 232, so that the power supply voltage capable of meeting the power demand of the crimped memory module can be output through the first conductive line L1, and the power supply quality of the power management device 23 is ensured.

[0079] In an embodiment, the connecting element 232 can be an electrical element for electrical connection. For example, the connecting element 232 can include one or more of a resistor with a preset resistance, a connecting line, a switching element, and a fuse device.

[0080] For the resistor, it can be an electrical element with ohmic characteristics. For example, continuing to refer to FIG. 2, the connecting element 232 can be a resistor R1 in FIG. 2. Figure 3 For the resistor, it can be an electrical element with ohmic characteristics. For example, continuing to refer to FIG. 2, the connecting element 232 can be a resistor R1 in FIG. 2. Figure 3 For example, in order to improve the power supply quality, the preset resistance of the resistor R1 can be 0 ohm. It should be noted that the preset resistance can also be selected as other resistance values according to actual conditions and specific scenarios, which is not limited specifically. In addition, it should be noted that the 0 ohm resistor in the embodiment of the present disclosure can refer to a resistor with very small resistance.

[0081] For the connecting line, it can be a line that can be electrically connected between devices, such as a wire.

[0082] For the switching element, it can be an electrical device that functions as an on-off switch, such as a semiconductor switch such as a metal-oxide semiconductor field effect transistor (MOS), which is not limited specifically. It should be noted that it can also be an electrical element capable of realizing the switching function, which is not limited specifically.

[0083] For the fuse device, it can be an electrical element that switches between a low resistance state and a high resistance state through a fuse operation. For example, the fuse device can be a fuse or an anti-fuse one-time programmable (OTP) device, which is not limited specifically.

[0084] Through the preset resistance value resistor, connecting line, switch element and fuse device, the electrical connection of multiple power management chips can be realized, and the power supply capability of the power management device 23 is ensured. Optionally, in the case that the connecting element 232 includes a switch element and / or a fuse device, flexible power supply of the power management device 20 can be realized.

[0085] In one example, for each other power management chip, when the fuse device corresponding to the each other power management chip is in a low resistance state, the each other power management chip supplies power to the multiple memory chips. When the fuse device is in a high resistance state, the each other power management chip does not supply power to the multiple memory chips.

[0086] Through the example, flexible power supply of multiple power management chips can be realized by controlling the resistance state of the fuse device.

[0087] In one specific example, the resistance state of the fuse device is adjusted by a test machine when the actual number of power management chips being powered is incorrect. For example, during chip testing, if it is found that the actual number of power management chips does not match the pre-designed number, the actual number of power management chips being powered can be adjusted to match the pre-designed number by adjusting the resistance state of each fuse device.

[0088] For example, continuing to refer to Figure 3 , if the resistor R1 is a fuse device in a low resistance state, the actual number of power management chips being powered is 2, and if the pre-designed number is 1, the fuse device can be adjusted to a high resistance state by a fuse processing, at this time the second power management chip 2312 is disconnected from the power supply line, at this time only the first power management chip 2311 supplies power to the memory, and the actual number of power management chips being powered is adjusted to 1, which matches the pre-designed number.

[0089] For example, the test machine can determine whether the actual number is incorrect based on preset power number information, wherein the preset power number information is stored in the configuration serial detection chip and is used to indicate the number of power management chips in the power management device.

[0090] When the actual number is incorrect and the actual number is greater than the number indicated by the preset power supply number information, the test machine adjusts the first target fuse device to a high resistance state to disconnect the power management chip corresponding to the first target fuse device from the power management device. For example, if the actual number is 5 and the number indicated by the preset power supply number information is 3, two power management chips can be selected from the five power management chips connected to the power management device as the power management chip corresponding to the first target fuse device, and the remaining three power management chips are disconnected from the power management device to supply power to the crimped memory module.

[0091] When the actual number is incorrect and the actual number is less than the number indicated by the preset power supply number information, the test machine adjusts the fuse device to a low resistance state to connect the power management chip corresponding to the second target fuse device to the power management device. For example, if the actual number is 2 and the number indicated by the preset power supply number information is 3, one power management chip can be selected from the power management chips not connected to the power management device as the power management chip corresponding to the second target fuse device to be connected to the power management device, so that the two power management chips originally connected and the newly connected power management chip together supply power to the crimped memory module.

[0092] Through the above examples, when the actual number of power management chips supplied by the power management device is incorrect, the number of power management chips connected to the power management device can be adjusted according to the size relationship between the preset power supply number information and the actual number, so that when the power management device cannot normally supply power to the memory chip, the power management device can meet the power supply demand of the memory chip through the adjustment of the high and low resistance states of the fuse device, thereby improving the yield of the memory module.

[0093] Through the above examples, when the actual number of power management chips supplied by the power management device is incorrect, the number of power management chips connected to the power management device can be adjusted according to the size relationship between the preset power supply number information and the actual number, so that when the power management device cannot normally supply power to the memory chip, the power management device can meet the power supply demand of the memory chip through the adjustment of the high and low resistance states of the fuse device, thereby improving the yield of the memory module.

[0094] After the specific structure of the power management device 23 is introduced through the above embodiments, the number of power management chips is described.

[0095] Regarding the specific quantity, in some embodiments, the preset number (i.e., the quantity N) of power management chips in power management device 23 can be any positive integer greater than or equal to 1, such as 1 or 2. It should be noted that the preset number of power management chips in the embodiments of this disclosure can be the number of power management chips on the power supply line connected to the power management device, that is, the number of power management chips used to supply power to the memory chips.

[0096] In some embodiments, the preset number of power management chips in the power management device 23 can be determined by the module manufacturer. For example, the number of power management chips can be determined based on the power consumption requirements of the memory chips.

[0097] In one embodiment, the module information of the press-fit memory module can be input into a preset chip quantity prediction model, and the prediction result output by the preset chip quantity prediction model can be used to determine the preset number of power management chips. For example, the module information can be configuration information of the module, such as one or more of the following: chip model, module model, memory rank information, current parameters of the press-fit memory module, and module capacity. It should be noted that other information can also be selected as configuration information according to the actual setup and specific scenario; there are no specific limitations on this. For example, the preset chip quantity prediction model can be a neural network model, a mathematical model, etc., and there are no specific limitations on it.

[0098] In another embodiment, the actual value of the module information of the pressed memory module can be obtained. If the actual value of the module information is within a preset value range, the number of chips corresponding to the preset value range is determined as the preset number of power management chips. In one example, the current required to press the memory module can be obtained. If the required current is less than or equal to a preset current threshold, the preset number of power management chips is 1. If the required current is greater than the preset current threshold, the preset number of power management chips is 2. For example, continuing with... Figure 3 For example, when the required current is less than or equal to the preset current threshold, i.e., when the current required to press the memory module is relatively small, only one current management chip is needed for power supply. In this case, there is no need to solder resistor R1, nor is there a need to set up a second power management chip 2312. Conversely, when the required current is greater than the preset current threshold, i.e., when the current required to press the memory module is relatively large, two current management chips are needed for power supply. In this case, the first power management chip 2311 and the second power management chip 2312 can be soldered together using resistor R1.

[0099] This embodiment allows for the accurate setting of the preset number of power management chips, thereby improving the power supply accuracy and flexibility of the power management chips.

[0100] After introducing the number of power management chips in the power management device, the power supply mode of the power management device is specifically described.

[0101] In some embodiments, each power management chip is configured to provide power supply energy for part of the plurality of memory chips. For example, the plurality of memory chips can be divided into M groups, and N power management chips correspond to N groups of memory chips one by one, and each power management chip is configured to provide power supply energy for the group of memory chips corresponding to the power management chip.

[0102] For example, Figure 6 Another example structure of the crimped memory module is shown in the structure diagram provided by the embodiment of the present disclosure. As shown in Figure 6 The first power management chip 2311 can provide power supply energy for the memory chips 22 in the first row, and the second power management chip 2312 can provide power supply energy for the memory chips 22 in the second row.

[0103] In one embodiment, the plurality of memory chips can be divided into groups, and each group of memory chips belongs to a memory channel. Each power management chip corresponds to at least one memory channel, and each power management chip is configured to provide power supply energy for the memory chips in the corresponding memory channel. For example, Figure 6 For example, if the memory chips 22 in the first row belong to a first memory channel and the memory chips 22 in the second row belong to a second memory channel, the first power management chip 2311 can provide power supply energy for the memory chips 22 in the first memory channel, and the second power management chip 2312 can provide power supply energy for the memory chips in the second memory channel.

[0104] Since the crimped memory module often has multiple independent memory channels, such as two independent DDR5 memory channels. Through the embodiment, the memory chips in each memory channel of the crimped memory module can be independently powered by one or more power management chips, ensuring the power supply requirements of the crimped memory module.

[0105] Through the embodiment of the present disclosure, the power supply of the crimped memory module can be accurately realized by the way that each power management chip is configured to provide power supply energy for part of the plurality of memory chips, and the power supply stability and reliability are improved.

[0106] In other embodiments, the output end (such as the first power supply pin A1) of each power management chip of the plurality of power management chips can be connected together to supply power to each memory chip by the power of the plurality of power management chips.

[0107] The crimped memory module provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drop caused by insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can ensure the stability of power supply while realizing flexible power supply for the crimped memory module, so that the crimped memory module can have a power supply scheme suitable for itself.

[0108] In addition, it should be noted that, considering that the crimped memory module has two independent memory channels, its load is theoretically twice that of the small outline dual in-line memory module. The power demand of the crimped memory module can be met by two memory management chips, avoiding the voltage drop risk when the small outline dual in-line memory module power supply scheme is used to supply power to the crimped memory module, and realizing stable power supply for the crimped memory module.

[0109] In addition, it should be noted that, through the embodiments of the present disclosure, different flexible power supply schemes can be selected according to the module information of the crimped memory module (such as the configuration information of the crimped memory module and the capacity of the crimped memory module), such as the optional power supply scheme of selecting one power management chip or two power management chips for power supply. For example, when the memory particles on the crimped memory module are less, one power management chip can be used for power supply to reduce the cost of the crimped memory module while meeting the power demand. In addition, when the memory particles on the crimped memory module are more, two power management chips can be used to reduce voltage drop in extreme cases to improve the stability of the power supply.

[0110] Figure 7 Another structure schematic diagram of a crimped memory module provided by the embodiments of the present disclosure is shown. Figure 7 Different from Figure 2 The crimped memory module can further include a configuration serial detection chip 24.

[0111] For the configuration serial detection chip 24, it is used to store preset power number information X1. The preset power number information X1 is used to indicate the number of power management chips in the power management device 23. It should be noted that the preset power number information X1 can also include other power configuration information of the power management device 23, which is not limited specifically.

[0112] Exemplarily, the configuration serial detection chip 24 can include at least one field for storing the preset power quantity information X1. Each field can include one or more bits. In the embodiment of the present disclosure, the preset power quantity information X1 can be written in the at least one field. For example, the preset power quantity information X1 can be written in 1 bit of the configuration serial detection chip 24.

[0113] For example, taking the case that the preset power quantity information X1 is written in 1 bit as an example, a first value of the bit represents quantity 1 (i.e., the crimped memory module is powered by 1 power management chip), and a second value of the bit represents quantity 2 (i.e., the crimped memory module is powered by 2 power management chips). One of the first value and the second value is 0, and the other is 1.

[0114] Through the embodiment, after the power configuration is performed, the quantity of the power management chips in the power management device 23 can be stored in the preset power quantity information X1 of the configuration serial detection chip 24, so that the quantity information of the power management chips is accurately recorded, and subsequent power management is facilitated.

[0115] In one embodiment, the preset power quantity information X1 can be written by the module manufacturer after the power management chips of the power management device 23 are configured. For example, if the module manufacturer determines that the crimped memory module needs 1 power management chip for power supply, 1 power management chip (or multiple power management chips are set but only 1 power management chip is used for power supply) is set on the crimped memory module, and 0 is written in the bit corresponding to the preset power quantity information X1; for another example, if the module manufacturer determines that the crimped memory module needs 2 power management chips for power supply, 2 power management chips are set on the crimped memory module, the first power supply pins of the 2 power management chips are connected through the connecting piece, and 1 is written in the bit corresponding to the preset power quantity information X1.

[0116] Through the embodiment, after the module manufacturer completes the configuration of the power management chips, the quantity of the power management chips can be written in the preset power quantity information of the configuration serial detection chip, so that the accurate quantity of the power management chips in the crimped memory module can be obtained based on the preset power quantity information in the subsequent process of the crimped memory module, and the crimped memory module can be accurately configured, tested, etc., in subsequent processes, thereby improving the convenience and accuracy of the process of the crimped memory module.

[0117] In some embodiments, the power management chip comprises a mode register for storing preset power configuration information of the power management chip. The preset power configuration information is configured by the chip control device based on preset power quantity information in the serial detection chip. For example, Figure 8 An exemplary structure diagram of another power management chip is shown. As shown in Figure 8 The first power management chip 2311 can comprise a first mode register MR1, and the first mode register MR1 stores preset power configuration information X21 of the first power management chip 2311. The second power management chip 2312 can comprise a second mode register MR2, and the second mode register MR2 stores preset power configuration information X22 of the second power management chip 2312.

[0118] The preset power configuration information can refer to power configuration information of the power management chip. For example, the preset power configuration information can comprise one or more of overvoltage, overcurrent, overtemperature, power-on timing, power-off timing, and the like. It should be noted that the preset power configuration information can also comprise other power information to be configured according to actual chip conditions and specific chip scenarios, which is not limited herein.

[0119] For example, the mode register can comprise at least one field for storing the preset power configuration information. Each field can comprise one or more bits. In the embodiments of the present disclosure, the preset power configuration information can be written in the at least one field.

[0120] The chip control device can refer to a device with chip control function. For example, the chip control device can be a host device, such as a system on a chip (SOC), and the like. It should be noted that the chip control device can also be other host devices such as a central processing unit (CPU), which is not limited herein.

[0121] In one embodiment, the chip control device can configure the preset power configuration information according to the quantity indicated by the preset power quantity information according to the provisions of the preset standard protocol. The preset standard protocol can be a protocol for regulating the power management chip. For example, the preset standard protocol can be a Joint Electron Device Engineering Council (JEDEC) standard protocol.

[0122] It should be noted that in the embodiments of the present disclosure, when the number of power management chips is multiple, the configuration information of the multiple power management chips can be the same or different, and no specific limitation is made thereto.

[0123] In one embodiment, the chip management device can access the power management chips through a communication bus such as I2C, and configure each item of information in the power management chips. Alternatively, the chip management device can realize I2C communication with the power management chips by configuring the serial detection chip, and configure the power management chips by configuring the serial detection chip.

[0124] Through the present embodiment, the chip control device realizes accurate and flexible power configuration of the power management chips according to the number of power management chips by configuring the preset power configuration information of the power management chips based on the preset power number information in the configuration serial detection chip, thereby improving the power supply reliability and flexibility of the crimped memory module.

[0125] In some embodiments, in order to realize the communication connection between the configuration serial detection chip and each power management chip, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin. The first communication pin is connected with the second communication pin of each power management chip, respectively, to realize the communication connection between the serial detection chip and each power management chip. Exemplarily, the communication connection can be an I2C communication connection. It should be noted that other communication technologies capable of realizing communication between the power management chip and the configuration serial detection chip can also be selected according to the actual communication situation and specific communication scene, such as I3C, SMBus, and other serial communication connections, and no specific limitation is made thereto.

[0126] In one embodiment, continuing to take Figure 3 as an example, the first communication pin B1 of the configuration serial detection chip 24 can be connected with the second communication pin B2 of the first power management chip 2311 and the second communication pin B2 of the second power management chip 2312, respectively, to realize the local I2C communication connection between the configuration serial detection chip 24 and the first power management chip 2311 and the second power management chip 2312.

[0127] In one example, Figure 9 An example structure diagram of another example power management chip provided by the embodiments of the present disclosure is shown. As Figure 9As shown, the first communication pin B1 of the configuration serial detection chip 24 can include a first clock line pin LSCL and a first bidirectional data line pin LSDA; the second communication pin B2 of the first power management chip 2311 can include a second clock line pin SCL1 and a second bidirectional data line pin SDA1; and the second power management chip 2312 can include a third clock line pin SCL2 and a third bidirectional data line pin SDA2.

[0128] Specifically, the first clock line pin LSCL of the configuration serial detection chip 24 can be connected to the second clock line pin SCL1 and the third clock line pin SCL2 respectively, and the first bidirectional data line pin LSDA can be connected to the second bidirectional data line pin SDA1 and the third bidirectional data line pin SDA2 respectively.

[0129] Through the embodiment, by connecting the first communication pin of the configuration serial detection chip to the second communication pin of each power management chip, the communication connection between the configuration serial detection chip and the power management chip can be realized, thereby facilitating the management of the power management chip such as power configuration.

[0130] In one embodiment, continuing to refer to Figure 3 The configuration serial detection chip 24 can further include a third communication pin B0 to realize the communication connection with the chip control device through the third communication pin B0. For example, the host I2C communication with the chip control device can be realized.

[0131] For example, continuing to refer to Figure 9 The third communication pin B0 includes a fourth clock line pin HSCL and a fourth bidirectional data line pin HSDA to realize the I2C communication with the chip control device through the fourth clock line pin HSCL and the fourth bidirectional data line pin HSDA.

[0132] Through the embodiment, the communication connection between the chip control device and the configuration serial detection chip 24 can be realized through the third communication pin B0, so that the chip control device can communicate with each power management chip through the configuration serial detection chip 24, and the chip control device and other external devices can perform power management operations such as chip configuration on each power management device.

[0133] After introducing the communication mode of the crimped memory module, the power supply mode of the crimped memory module is introduced.

[0134] In some embodiments, the power management chip can also supply power to the configuration serial detection chip, and accordingly, the configuration serial detection chip 24 includes a first power pin, and each power management chip further includes a second power supply pin.

[0135] In the power management device includes a plurality of power management chips, the second power supply pin of the target power management chip in the power management device is connected with the first power supply pin, the second power supply pin of the power management chip other than the target power management chip in the power management device is vacant, so that the power energy output by the second power supply pin of the target power management chip is provided to the serial detection chip as the power supply energy of the serial detection chip. Exemplarily, the target power management chip can be one or more in the power management device. It should be noted that the target power management device can be selected according to the actual power supply situation and the specific scene, and no specific limitation is made thereto.

[0136] In one example, Figure 10 Another exemplary structure schematic diagram of the power management chip is shown. As shown in the figure, Figure 10 The first power supply pin of the serial detection chip 24 can include the SPD power supply pin VDDSPD and the input and output power supply pin VIO, the second power supply pin of the first power management chip 2311 can include the power supply pin VOUT1 and the power supply pin VOUT2, and the second power supply pin of the second power management chip 2312 can include the power supply pin VOUT1 and the power supply pin VOUT2.

[0137] Exemplarily, in the case that the first power management chip 2311 is the target power management chip and the second power management chip 2312 is the other power management chip, the power supply pin VOUT1 of the first power management chip 2311 is connected with the SPD power supply pin VDDSPD of the serial detection chip 24 to provide the first power voltage Vddspd to the serial detection chip 24, and the power supply pin VOUT2 of the first power management chip 2311 is connected with the input and output power supply pin VIO of the serial detection chip 24 to provide the second power voltage VDDIO to the serial detection chip 24. In addition, the power supply pin VOUT1 and the power supply pin VOUT2 of the second power management chip 2312 remain vacant. In this way, the first power management chip 2311 can supply power to the serial detection chip 24. Wherein, the first power voltage Vddspd and the second power voltage VDDIO can be the power voltage required by the serial detection chip 24. Exemplarily, the first power voltage Vddspd can be 1.8V (volt), and the second power voltage VDDIO can be 1V. It should be noted that the first power voltage Vddspd and the second power voltage VDDIO can also be set to other voltage values according to the specific scene and actual demand, and no specific limitation is made thereto.

[0138] In the embodiment, the target power management chip can supply power for the configuration serial detection chip, so that the configuration serial detection chip can work normally without an additional external power supply, and the normal work of the entire crimping memory module is ensured. In addition, the power waste of other power management chips can be avoided by keeping the other power management chips idle, and the power utilization efficiency of the power management chip is improved.

[0139] In some embodiments, each power management chip includes a status signal pin. The status signal pin can indicate whether the working state of the power management chip is normal. Specifically, the status chip pin is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty. One of the first level and the second level is a high level, and the other of the first level and the second level is a low level. For example, the first level can be a high level, and the second level can be a low level. That is, when the power management chip is normal, its status signal pin is pulled high to a high level; when the power management chip is faulty, its status signal pin is pulled low to a low level. In one example, Figure 11 Another exemplary structure of a power management chip is shown in a structure diagram. As shown in Figure 11 The first power management chip 2311 can include a first status signal pin PWR GOOD1, and the second power management chip 2312 can include a second status signal pin PWR GOOD2. Taking the first power management chip 2311 as an example, when the first power management chip 2311 is normal, the first status signal pin PWR GOOD1 outputs a high level, and when the first power management chip 2311 is faulty, the first status signal pin PWR GOOD1 outputs a low level.

[0140] In the case where the power management device includes a plurality of power management chips, the status signal pins of the plurality of power management chips are connected to the status signal transmission line. When the status signal pins of one or more power management chips output the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line represents that the power management device is faulty. In one example, continuing to refer to Figure 11 The first status signal pin PWR GOOD1 of the first power management chip 2311 and the second status signal pin PWR GOOD2 of the second power management chip 2312 are both connected to the status signal transmission line L2. When the first power management chip 2311 and / or the second power management chip 2312 is faulty, the level on the status signal transmission line L2 is a low level; when the first power management chip 2311 and the second power management chip 2312 are both normal, the level on the status signal transmission line L2 is a high level.

[0141] In the embodiment, the state signal transmission line is adjusted to the first level when the voltage levels of the state signal pins of each power management chip are the first level, and is adjusted to the second level when the voltage level of the state signal pin of any one or more power management chips is the second level. Since the first level represents that the power management chip is normal, and the second level represents that the power management chip is faulty, correspondingly, in the embodiment of the present disclosure, the state signal transmission line can output the first level representing that the power management device is normal when all the power management chips in the power management device are normal, and can output the second level representing that the power management device is faulty when any one or more power management chips in the power management device is faulty. Thus, the working state of the power management device can be accurately represented by the output level of the state signal transmission line, so as to accurately and quickly perceive the fault state of the power management device. Further, the power management device can be managed and maintained when the abnormality of the power management device is perceived in the subsequent use, test and the like.

[0142] In some embodiments, in order to facilitate the control of the power management chip, each power management chip includes an enable pin, and the enable pin is used to turn on or turn off each power management chip. The enable pin of each power management chip is used to receive a control instruction sent by a chip control device. The control instruction is used to turn on or turn off each power management chip. It should be noted that the control instructions received by each power management chip can be the same or different, and no specific limitation is made. It should also be noted that in the embodiment of the present disclosure, the chip control device can send the control instruction to the enable pin directly, or send the control instruction to the enable pin under the forwarding of other devices or equipment, and no specific limitation is made.

[0143] In one example, Figure 12 Another example of the structure of the power management chip provided by the embodiment of the present disclosure is shown. As shown in Figure 12 The first power management chip 2311 can include a first enable pin VR_EN1, and the second power management chip 2312 can include a second enable pin VR_EN2. The first enable pin VR_EN1 and the second enable pin VR_EN2 can receive a control instruction PWR_EN. Exemplarily, the control instruction PWR_EN can be a level signal, such as a high level indicating turning on the power management chip, and a low level indicating turning off the power management chip.

[0144] Through the embodiment, the chip control apparatus can control the start or stop of each power management chip flexibly and accurately through the enable pins of each power management chip, so that the power management apparatus can be accurately controlled in the granularity of the power management chip, and the control accuracy is improved. Further, in the case that the power supply demand of part of the chips on the crimped memory module changes, the number of power management chips for power supply can be changed, such as stopping part of the power management chips and using the remaining power management chips to supply power to the crimped memory module, which takes into account the power supply accuracy, reasonable use of electric energy, and improves the power supply flexibility. Further, in the case of power management chip failure, each power management chip or the failed power management chip can be quickly stopped, and the safety of the power management apparatus is improved.

[0145] In some embodiments, in order to realize correct communication of the power management apparatus, each power management chip includes a communication address pin for indicating the communication address of each power management chip. The communication address pins of the plurality of power management chips correspond to different voltages, and the different voltages represent different communication addresses. For example, different voltages can be applied to the communication address pins of different power management chips to represent different communication addresses of the power management chips.

[0146] In one example, Figure 13 Another exemplary structure of a power management chip is shown. As shown in Figure 13 The first power management chip 2311 can include a first communication address pin PID1, and the second power management chip 2312 can include a second communication address pin PID2. The first communication address pin PID1 is grounded, and a preset power voltage is applied to the second communication address pin PID2. Exemplarily, the preset power voltage can be the second power voltage VDDIO.

[0147] Through the embodiment, by configuring different voltages for the communication address pins of the power management chips, different communication addresses can be configured for different power management chips in the same power management apparatus, so that the communication of each power management chip of the power management apparatus can be realized.

[0148] In some embodiments, in addition to the pins shown in combination with the above embodiments, the power management chip can also include one or more other pins. Figure 14 Another exemplary structure of a power management chip is shown. As shown in Figure 14 The power management chip can also include at least one of the following pins 1-8.

[0149] Pin 1, Power Ground pin PGND, for forming a discharge path of dangerous current of a high-power circuit. Illustratively, continuing to refer to Figure 14 , the Power Ground pin PGND is grounded.

[0150] Pin 2, Analog Ground pin AGND, for forming a discharge path of current of an analog signal. Illustratively, continuing to refer to Figure 14 , the Analog Ground pin AGND is grounded.

[0151] Pin 3, Null pin NC, NC1-3, which is not connected to internal functional circuits of the device. Illustratively, continuing to refer to Figure 14 , the Null pin NC, NC1-3 is grounded.

[0152] Pin 4, General Status Interrupt signal output pin GSI_n, which is used to output a general status interrupt signal. As shown in Figure 14 , the General Status Interrupt signal output pin GSI_n can be not connected to outside of the power management device. For example, the General Status Interrupt signal output pin GSI_n can be connected to a reference position point of a voltage dividing structure. Illustratively, the voltage dividing structure can include a first voltage dividing resistor Ra and a second voltage dividing resistor Rb. Wherein one end of the first voltage dividing resistor Ra is applied with a first power supply voltage Vddspd, the other end of the voltage dividing resistor Ra and one end of the second voltage dividing resistor Rb are both connected to the reference position point, and the other end of the second voltage dividing resistor Rb is grounded.

[0153] Pins 5-8, first voltage input pin VIN_BULK_A, second voltage input pin VIN_BULK_B, third voltage input pin VIN_BULK_C, and fourth voltage input pin VIN, which are respectively used to receive an input voltage VIN_BULK, so that the power management chip can generate a supply voltage such as a first supply voltage VDD, a second supply voltage VDDQ, a third supply voltage VPP, and the like based on the input voltage VIN_BULK.

[0154] In some embodiments, in addition to the pins shown in combination with the above-described embodiments, the serial detection chip can further include one or more other pins. Continuing to refer to Figure 14 , the serial detection chip can further include at least one of pins 9-11.

[0155] Pin 9, Address pin HSA.

[0156] Pin 10, Ground pin Gnd.

[0157] Pin 11, Ground / Thermal Pad pin Gnd / Thermal Pad. Wherein, continuing to refer to Figure 14 , the Ground / Thermal Pad pin Gnd / Thermal Pad is grounded.

[0158] To facilitate the overall understanding of the technical solutions provided by the embodiments of the present disclosure, Figure 15 A structural schematic diagram of an exemplary first power management chip provided by the embodiments of the present disclosure is shown. Figure 16 A structural schematic diagram of an exemplary second power management chip provided by the embodiments of the present disclosure is shown. Figure 17 A structural schematic diagram of an exemplary configuration serial detection chip provided by the embodiments of the present disclosure is shown. Next, the technical solutions provided by the embodiments of the present disclosure are described in combination with Figures 15-17 The technical solutions provided by the embodiments of the present disclosure are described.

[0159] As Figure 15 and Figure 16 To improve the quality of the input voltage VIN_BULK, the first power management chip further includes a first filter unit Q1, and the second power management chip further includes a second filter unit Q2. Exemplarily, the first filter unit Q1 can include a plurality of parallel capacitors, such as capacitors C3-C5 and capacitors C7-C14. For example, the second filter unit Q2 can also include a plurality of parallel capacitors, such as capacitors C41-C51. Among them, for any one of the first filter unit Q1 and the second filter unit Q2, there are at least two capacitors of different capacitances in the any one filter unit to realize filtering of different frequencies such as high frequency and low frequency. It should be noted that the capacitors can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0160] The first enable pin VR_EN1 of the first power management chip and the second enable pin VR_EN2 of the second power management chip can be connected together through a resistor R111 to receive a control instruction PWR_EN_0. Exemplarily, to avoid power loss, the resistor R111 can be 0 ohm. It should be noted that the resistance value of the resistor R111 can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0161] The first status signal pin PWR_GOOD1 of the first power management chip and the second status signal pin PWR_GOOD2 of the second power management chip can be connected together through the resistor R112 to output a status signal PWR_GOOD_0. Illustratively, when the level signal on the first status signal pin PWR_GOOD1 and / or the level signal PWR_GOOD2_01 on the second status signal pin PWR_GOOD2 is low, the output status signal PWR_GOOD_0 is low. Illustratively, in order to avoid power loss, the resistor R112 can be 0 ohm. It should be noted that the resistance of the resistor R112 can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0162] For the first power management chip and the second power management chip, the switching voltage pin SWA and the start voltage pin SWA_BOOT are connected through the capacitor C6 (or the capacitor C36, it should be noted that in order to show simply, the different devices of the second power management chip and the first power management chip in the same position are output in the form of brackets), the switching voltage pin SWA is connected with the inductor L1 (or the inductor L4), and the other end of the inductor L1 (or the inductor L4) is connected with the feedback voltage pin SWA_FB_P. Illustratively, in order to improve the power transmission quality of the first power supply voltage V_MEM_VDD, the other end of the inductor L1 (or the inductor L4) is respectively connected with the capacitor C1, the capacitor C2, the capacitor C27, and the capacitor C28 (or the capacitors C37-C40), and the other end of the capacitor C1, the capacitor C2, the capacitor C27, and the capacitor C28 (or the capacitors C37-C40) is grounded.

[0163] In addition, the switching voltage pin SWB and the start voltage pin SWB_BOOT are connected through the capacitor C15 (or the capacitor C52), the switching voltage pin SWB is connected with the inductor L2 (or the inductor L5), and the other end of the inductor L2 (or the inductor L5) is connected with the feedback voltage pin SWB_FB_P. Illustratively, in order to improve the power transmission quality of the second power supply voltage V_MEM_VDDQ, the other end of the inductor L2 (or the inductor L5) is respectively connected with the capacitor C16, the capacitor C17, the capacitor C29, and the capacitor C30 (or the capacitors C53-C56), and the other end of the capacitor C16, the capacitor C17, the capacitor C29, and the capacitor C30 (or the capacitors C53-C56) is grounded.

[0164] And, the switch voltage pin SWC is connected with the boot voltage pin SWC_BOOT through the capacitor C18 (or the capacitor C57), the switch voltage pin SWC is connected with the inductor L3 (or the inductor L6), and the other end of the inductor L3 (or the inductor L6) is connected with the feedback voltage pin SWC_FB_P. Exemplarily, in order to improve the power transmission quality of the third power supply voltage V_MEM_VPP, the other end of the inductor L3 (or the inductor L6) is respectively connected with the capacitor C19 and the capacitor C20 (or the capacitor C58 and the capacitor C59), and the other end of the capacitor C19 and the capacitor C20 (or the capacitor C58 and the capacitor C59) is grounded. It should be noted that the capacitors and inductors can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0165] And, the general state interrupt signal output pin GSI_n of the first power management chip can be connected with one end of the resistor R105 and one end of the resistor R106 respectively, one end of the resistor R105 is used for receiving the first power voltage Vddspd_1P8V, and the other end of the resistor R106 is grounded. The general state interrupt signal output pin GSI_n of the second power management chip can be connected with one end of the resistor R109 and one end of the resistor R110 respectively, one end of the resistor R109 is used for receiving the first power voltage Vddspd_1P8V, and the other end of the resistor R110 is grounded. In one example, the resistance values of the resistor R105 and the resistor R109 can be 1K (kilo-ohm). In another example, the resistance values of the resistor R106 and the resistor R110 can be 0 ohm. It should be noted that the capacitors and capacitors can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0166] And, for any one of the first power management chip and the second power management chip, the power supply pin VOUT_1.8V (also referred to as the power supply pin VOUT1) can be grounded through the capacitor C22 (the capacitor C62) and the capacitor C25 (the capacitor C63) respectively, and the power supply pin VOUT_1.0V (also referred to as the power supply pin VOUT2) can be grounded through the capacitor C21 (the capacitor C60) and the capacitor C23 (the capacitor C61) respectively. It should be noted that the capacitors can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0167] And, please continue to refer to Figure 17 The SPD power pin VDDSPD of the configuration serial detection chip can be grounded through the capacitor C26, and the input and output power pin VIO can be grounded through the capacitor C24. It should be noted that the capacitors can also be selected as other parameters according to actual scenes and specific requirements, and the device parameters are not specifically limited.

[0168] It should be noted that the first power management chip, the second power management chip and other contents of the configuration serial detection chip can be referred to the related description of the above part of the embodiments of the present disclosure, which will not be repeated here.

[0169] Based on the same inventive concept, the embodiments of the present disclosure also provide a power management device. The power management device is arranged on a press-fit memory circuit board of a press-fit memory module, and the power management device is connected with a plurality of memory chips of the press-fit memory module.

[0170] Specifically, the power management device includes: a plurality of power management chips, configured to provide power generated by the plurality of power management chips as power supply power to the plurality of memory chips.

[0171] Among them, the preset number of power management chips in the power management device is related to the power demand of the plurality of memory chips.

[0172] In one embodiment, the power management device includes a plurality of power management chips.

[0173] Among them, the power management chip includes a first power supply pin, and the first power supply pins of the plurality of power management chips are connected to provide power generated by the plurality of power management chips to the plurality of memory chips through the connected first power supply pins.

[0174] In one embodiment, the first power supply pin includes N power supply pins, and each power supply pin is used to output a power supply voltage.

[0175] Among them, the i-th power supply pin of the plurality of power management chips is connected to provide the power supply voltage output by the connected i-th power supply pin to the plurality of memory chips. Wherein, N is an integer greater than or equal to 1, and i is any integer less than or equal to N.

[0176] In one embodiment, the power management chip further includes a mode register.

[0177] The mode register is used to store the preset power configuration information of the power management chip.

[0178] Among them, the preset power configuration information is configured by the chip control device based on the preset power number information in the configuration serial detection chip.

[0179] In one embodiment, when the configuration serial detection chip includes a first communication pin, each power management chip includes a second communication pin.

[0180] Among them, the first communication pin is connected with the second communication pin of each power management chip respectively to realize the communication connection between the configuration serial detection chip and each power management chip.

[0181] In one embodiment, the configuration serial detection chip includes a first power pin, and each power management chip further includes a second power pin.

[0182] In the case that the power management device includes a plurality of power management chips, the second power pin of a target power management chip in the power management device is connected with the first power pin, and the second power pins of the power management chips other than the target power management chip in the power management device are vacant, so that the electric energy outputted by the second power pin of the target power management chip is provided to the configuration serial detection chip as the power supply electric energy of the configuration serial detection chip.

[0183] In one embodiment, each power management chip includes a state signal pin, which is used to output a first level indicating that each power management chip is normal or a second level indicating that each power management chip is faulty.

[0184] In the case that the power management device includes a plurality of power management chips, the state signal pins of the plurality of power management chips are connected to a state signal transmission line, wherein, when the state signal pins of one or more power management chips output the second level, the level on the state signal transmission line is adjusted to the second level, and the second level on the state signal transmission line represents that the power management device is faulty.

[0185] In one embodiment, each power management chip includes an enable pin, which is used to start or close each power management chip.

[0186] In one embodiment, the enable pin of each power management chip is used to receive a control instruction sent by a chip control device, and the control instruction is used to start or close each power management chip.

[0187] In one embodiment, each power management chip includes a communication address pin, which is used to indicate the communication address of each power management chip, wherein the communication address pins of the plurality of power management chips correspond to different voltages, and the different voltages represent different communication addresses.

[0188] In one embodiment, the first power pin of one of the plurality of power management chips is directly connected to the first conductive line, and the first power pins of the other power management chips are connected to the first conductive line or the first power pin of the one of the plurality of power management chips through a connecting member.

[0189] In one embodiment, the connecting member includes one or more of a resistor with a preset resistance, a connecting line, a switching element and a fuse device.

[0190] In an embodiment, the connecting member comprises a fuse device, which is a fuse or an anti-fuse; wherein for each other power management chip, when the fuse device corresponding to each other power management chip is in a low resistance state, each other power management chip supplies power to the plurality of memory chips; and when the fuse device is in a high resistance state, each other power management chip does not supply power to the plurality of memory chips.

[0191] In an embodiment, the resistance state of the fuse device is adjusted by a test machine when the actual number of power management chips is incorrect.

[0192] In an embodiment, the test machine determines whether the actual number is incorrect based on preset power number information, wherein the preset power number information is stored in the configuration serial detection chip and is used to indicate the number of power management chips in the power management device; when the actual number is incorrect and the actual number is greater than the number indicated by the preset power number information, the test machine adjusts the first target fuse device to a high resistance state to disconnect the power management chip corresponding to the first target fuse device from the power management device; and when the actual number is incorrect and the actual number is less than the number indicated by the preset power number information, the test machine adjusts the fuse device to a low resistance state to connect the power management chip corresponding to the second target fuse device to the power management device.

[0193] In an embodiment, each power management chip is used to provide power supply energy for part of the plurality of memory chips.

[0194] In an embodiment, the plurality of memory chips can be divided into multiple groups, each group of memory chips belongs to one memory channel, each power management chip corresponds to at least one memory channel, and each power management chip is used to provide power supply energy for the memory chips in the corresponding memory channel.

[0195] The power management device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chips, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various compression memory modules, and the occurrence of voltage drop caused by insufficient power supply is avoided. Furthermore, the technical solution provided by the embodiments of the present disclosure can ensure the stability of power supply while realizing flexible power supply for the compression memory module, so that the compression memory module can have a power supply scheme suitable for itself.

[0196] It should be noted that the specific content of the power management device can be referred to the above-mentioned part of the embodiments of the present disclosure in combination with the related description of Figures 2-17 .

[0197] Based on the same inventive concept, the embodiments of the present disclosure also provide a configuration serial detection chip.

[0198] The configuration serial detection chip stores preset power quantity information, and the preset power quantity information is used to indicate the quantity of power management chips in the power management device. The power management device is arranged on a press-fit memory circuit board of a press-fit memory module and connected with a plurality of memory chips of the press-fit memory module. The power management device includes a preset quantity of power management chips, and is used to provide power energy generated by the preset quantity of power management chips to the plurality of memory chips as power supply energy. The preset quantity of power management chips in the power management device is related to the power demand of the plurality of memory chips.

[0199] In one embodiment, the configuration serial detection chip includes a first communication pin, and each power management chip includes a second communication pin. The first communication pin is connected with the second communication pin of each power management chip respectively to realize communication connection between the configuration serial detection chip and each power management chip.

[0200] In one embodiment, the configuration serial detection chip includes a first power pin, and each power management chip further includes a second power supply pin. In the case that the power management device includes a plurality of power management chips, the second power supply pin of a target power management chip in the power management device is connected with the first power pin, and the second power supply pin of each power management chip other than the target power management chip in the power management device is vacant. The power energy output by the second power supply pin of the target power management chip is provided to the configuration serial detection chip as power supply energy of the configuration serial detection chip.

[0201] The configuration serial detection chip provided by the embodiments of the present disclosure can flexibly set the preset quantity of power management chips in the power management device according to the power demand of the memory chips, so that the power energy generated by the preset quantity of power management chips can flexibly meet the power demand of various press-fit memory modules, and the occurrence of voltage drop caused by insufficient power supply is avoided. Furthermore, the technical solution provided by the embodiments of the present disclosure can realize flexible power supply for the press-fit memory module while ensuring the stability of power supply, so that the press-fit memory module can have a power supply scheme suitable for itself. After power supply configuration, the quantity of power management chips in the power management device 23 can be stored in the preset power quantity information X1 of the configuration serial detection chip 24 to accurately record the quantity information of the power management chips, which is convenient for subsequent power management.

[0202] It should be noted that the specific content of the configuration serial detection chip can be referred to the above-mentioned part of the embodiments of the present disclosure in combination with the related description of Figures 2-17 .

[0203] Based on the same inventive concept, the embodiments of the present disclosure further provide an electronic device, which can include the crimped memory module provided by any of the above embodiments of the present disclosure. The specific content of the crimped memory module can be referred to the related description of the embodiments of the present disclosure in combination with Figures 2-17 The above description is not repeated here.

[0204] The electronic device of the embodiments of the present disclosure can be an electronic device loaded with a memory. For example, the electronic device can be a mobile terminal, a computer, a server, a virtual reality device, an Internet of Things device, etc.

[0205] The electronic device provided by the embodiments of the present disclosure can flexibly set the preset number of power management chips in the power management device according to the power demand of the memory chip, so that the power generated by the preset number of power management chips can flexibly meet the power demand of various crimped memory modules, avoiding the occurrence of voltage drop caused by insufficient power supply. Furthermore, the technical solution provided by the embodiments of the present disclosure can ensure the stability of power supply while realizing flexible power supply for the crimped memory module, so that the crimped memory module can have a power supply scheme suitable for itself.

[0206] In the description of the present specification, the description referring to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiments or examples are contained in at least one embodiment or example of the present disclosure. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any appropriate manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the present specification and the features of the different embodiments or examples without contradiction.

[0207] Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present disclosure. The person skilled in the art can make changes, modifications, replacements and variations to the above embodiments within the scope of the present disclosure, and any changes or modifications made in accordance with the claims and specification of the present disclosure shall be within the scope of the present disclosure.

Claims

1. A crimped memory module, comprising: a crimped memory circuit board; a plurality of memory chips disposed on the crimped memory circuit board; a power management device disposed on the crimped memory circuit board and electrically connected to the plurality of memory chips, the power management device comprising a preset number of power management chips configured to provide power generated by the preset number of power management chips as a supply power to the plurality of memory chips, wherein the preset number of power management chips in the power management device is preset according to a power demand of the plurality of memory chips; and a configuration serial detection chip configured to store preset power number information, wherein the preset power number information is configured to indicate the number of power management chips in the power management device. 2.The module of claim 1, wherein the power management device comprises a plurality of power management chips, and wherein the power management chips comprise first supply pins, and the first supply pins of the plurality of power management chips are connected to provide power generated by the plurality of power management chips to the plurality of memory chips through the connected first supply pins. 3.The module of claim 2, wherein the first supply pins comprise N power supply pins, each of which is configured to output a supply voltage, and wherein the i th< power supply pin of the plurality of power management chips is connected to provide a supply voltage output by the connected i th< power supply pin to the plurality of memory chips, wherein N is an integer greater than or equal to 1, and i is any integer less than or equal to N. 4.The module of claim 1, wherein the power management chips further comprise a mode register configured to store preset power configuration information of the power management chip, and wherein the preset power configuration information is configured by a chip control device based on the preset power number information in the configuration serial detection chip. 5.The module of claim 1, wherein the configuration serial detection chip comprises a first communication pin, and each power management chip comprises a second communication pin, and wherein the first communication pin is connected to the second communication pin of each power management chip to realize communication connection between the configuration serial detection chip and each power management chip. 6.The module of claim 1, wherein the configuration serial detection chip comprises a first power pin, and each power management chip further comprises a second supply pin, and wherein, when the power management device comprises a plurality of power management chips, the second supply pin of a target power management chip in the power management device is connected to the first power pin, and the second supply pins of the other power management chips in the power management device except the target power management chip are idle, so that power output by the second supply pin of the target power management chip is provided as a supply power of the configuration serial detection chip to the configuration serial detection chip. 7.The module of claim 1, wherein ​ ​ ​ ​ ​ ​ Each power management chip includes a status signal pin for outputting a first level indicating normality of the each power management chip or a second level indicating failure of each of the power management chips, wherein, in the case that the power management device includes a plurality of power management chips, the status signal pins of the plurality of power management chips are connected to a status signal transmission line, wherein, when the status signal pin of one or more power management chips outputs the second level, the level on the status signal transmission line is adjusted to the second level, and the second level on the status signal transmission line represents failure of the power management device.

8. The module of claim 1, wherein Each power management chip includes an enable pin for starting or stopping the each power management chip, wherein the enable pin of the each power management chip is used to receive a control instruction sent by a chip control device, and the control instruction is used to start or stop the each power management chip.

9. The module of claim 1, wherein Each power management chip includes a communication address pin for indicating a communication address of the each power management chip, wherein the communication address pins of the plurality of power management chips correspond to different voltages, and the different voltages represent different communication addresses.

10. The module of claim 2, wherein The first power supply pin of one of the plurality of power management chips is directly connected to a first conductive line, and the first power supply pins of other power management chips are connected to the first conductive line or the first power supply pin of the one of the plurality of power management chips through a connection.

11. The module of claim 10, wherein The connection includes one or more of a resistor with a preset resistance, a connection line, a switching element, and a fuse device.

12. The module of claim 10, wherein The connection includes a fuse device, and the fuse device is a fuse or an anti-fuse. For each of the other power management chips, when the fuse device corresponding to the each of the other power management chips is in a low resistance state, the each of the other power management chips supplies power to the plurality of memory chips. When the fuse device is in a high resistance state, the each of the other power management chips does not supply power to the plurality of memory chips.

13. The module of claim 12, wherein The resistance state of the fuse device is adjusted by a test machine when an actual number of power management chips supplying power is incorrect.

14. The module of claim 13, wherein The test machine determines whether the actual number is incorrect based on preset power number information, and the preset power number information is stored in a configuration serial detection chip and is used to indicate the number of power management chips in the power management device. Wherein, when the actual number is incorrect and the actual number is greater than the number indicated by the preset power number information, the test machine adjusts a first target fuse device to a high resistance state to disconnect a power management chip corresponding to the first target fuse device from the power management device; When the actual number is incorrect and the actual number is less than the number indicated by the preset power number information, the test machine adjusts the fuse device to a low resistance state to connect a second target fuse device to the power management device.

15. The module of claim 1, wherein: Each of the power management chips is configured to provide power supply energy for a part of the plurality of memory chips.

16. The module of claim 15, wherein: The plurality of memory chips can be divided into groups, each group of memory chips belonging to a memory channel, each of the power management chips corresponding to at least one of the memory channels, and each of the power management chips being configured to provide power supply energy for the memory chips in the corresponding memory channel.

17. An electronic device, comprising: The crimped memory module of any one of claims 1-16. ​

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