Method for monitoring manufacturing process of semiconductor gate structure layer

Abstract

The invention provides a method for monitoring a manufacturing process of a semiconductor gate structure layer, and belongs to the field of semiconductors. The method for monitoring the manufacturing process of the semiconductor gate structure layer comprises the following steps of: providing a control wafer, and testing to obtain a work function WSI of the control wafer; the dark field surface contact potential difference VCPDDARK of the control wafer is tested through a non-contact method; the bright field surface contact potential difference VCPDLIGHT of the control wafer is tested through a non-contact method; and calculating the relative work function of the gate structure layer of the control wafer based on the work function WSI of the control wafer, the dark field surface contact potential difference VCPDDARK and the bright field surface contact potential difference VCPDLIGHT. According to the method, the control wafer runs along with the to-be-monitored graphical wafer, the relative work function of the gate structure layer is obtained, and when the error between the absolute work function and the relative work function exceeds a certain range, it can be determined that the film layer quality does not reach the expectation, and technological parameters need to be adjusted. By adopting the control wafer, short-distance wafers are prevented from being used, wafer scrapping is avoided, the monitoring time can be shortened, and the monitoring cost is also reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for monitoring a semiconductor gate structure layer manufacturing process. Background Art

[0002] The work function is an important parameter for selecting gate materials for semiconductor devices. The work function mainly affects the threshold voltage of semiconductor devices, thereby affecting the performance of semiconductor devices. Therefore, in the field of semiconductor manufacturing, it is particularly important to accurately detect the work function of the gate structure of the manufactured semiconductor device.

[0003] In the prior art, the gate of a semiconductor device is made of a metal layer as an example for explanation. When testing the work function, a wafer with a patterned gate structure needs to be manufactured by masking. After a short high-K metal gate process and metal tungsten coating and corresponding patterning (photolithography and etching) processes, the work function of the gate structure can be measured by the contact capacitance method. When the contact capacitance method is used in the laboratory, the capacitance and voltage values ​​are obtained by inserting one end of the probe into the area where the metal tungsten is located and the other end of the probe contacts the metal chuck. When a forward DC bias is applied, the charge between the metal layer and the semiconductor layer will be attracted to one side of the metal layer to form an accumulation zone, at which time the capacitance reaches the maximum value. As the bias decreases, most carriers are repelled from the gate oxide interface to form a depletion zone, and the capacitance value gradually decreases. When a reverse DC bias is applied, the distance that the charge carrier deviates from the oxide layer is the largest, forming an inversion zone, at which time the capacitance value reaches the minimum value, so that the capacitance value curve under different voltages can be obtained. The capacitance value curves obtained under different voltages are compared with the standard capacitance-voltage curve to obtain the work function of the gate structure. However, the existing testing method requires the entire gate structure process to be completed, which is time-consuming. The wafer that has completed the measurement of the contact capacitance method cannot be used anymore and therefore needs to be scrapped.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a method for monitoring the manufacturing process of a semiconductor gate structure layer, so as to solve the problem that the existing gate structure takes a long time to measure the work function and requires the scrapping of wafers.

[0006] In order to solve the above technical problems, the present invention provides a monitoring method for a semiconductor gate structure layer manufacturing process, wherein the gate structure layer includes a gate layer and a gate dielectric layer, and the gate dielectric layer is located between a semiconductor device channel and the gate layer. The monitoring method includes: Provide a control chip, and test and obtain the work function W of the control chip SI ; The control wafer is placed together with a patterned wafer to be monitored, the gate dielectric layer and the gate layer are sequentially formed on the surface of the control wafer, and the patterning process of the gate dielectric layer and the gate layer involved in the patterned wafer is omitted, wherein the gate layer and the control wafer have different doping types; The non-contact method tests the contact potential difference V on the dark field surface of the control film. CPDDARK ; The non-contact method tests the contact potential difference V on the bright field surface of the control piece. CPDLIGHT ; Based on the work function W of the control film SI , dark field surface contact potential difference V CPDDARK The contact potential difference V with the bright field surface CPDLIGHT The relative work function of the gate structure layer of the control wafer is obtained by calculation.

[0007] Preferably, the calculation method comprises: The relative work function of the gate structure layer = work function W SI - Surface barrier V SB , where q is the charge constant, Surface barrier V SB = Dark field surface contact potential difference V CPDDARK -Bright field surface contact potential difference V CPDLIGHT .

[0008] Preferably, the gate layer is a metal layer, and the gate dielectric layer is a high-K dielectric layer.

[0009] Preferably, the work function W of the control sheet is SI The measurement is performed using a non-contact Kelvin probe.

[0010] Preferably, the dark field surface of the control sheet is in contact with a potential difference V CPDDARK The contact potential difference V with the bright field surface CPDLIGHT Measured using a non-contact Kelvin macroprobe with surface photovoltage technology.

[0011] Preferably, it also includes: Sampling absolute work function data measured by a contact capacitance method corresponding to process parameters of a semiconductor gate structure layer to be monitored; Obtaining non-contact relative work function data corresponding to the process parameters of the semiconductor gate structure layer; Based on the absolute work function data and the relative work function data, two work function relationship equations of process parameters are obtained; Based on the relationship, the process parameters of the semiconductor gate structure layer are monitored by measuring the non-contact relative work function.

[0012] Preferably, the process parameters of the semiconductor gate structure layer include the thickness of the gate layer and / or the gate dielectric layer and the composition ratio of the gate layer or a combination of the above process parameters.

[0013] Compared with the prior art, the monitoring method of the semiconductor gate structure layer manufacturing process of the present invention has the following advantages: The present invention obtains the relative work function of the gate structure layer through the above monitoring method. The process parameters of the gate layer and the gate dielectric layer corresponding to the gate structure layer are monitored to see whether they are within the normal range through the relative work function and the absolute work function and relative work function relationship corresponding to the process parameters of the gate structure layer obtained before. The monitoring method can be used to provide timely feedback and adjust the process parameters of the gate layer and the gate dielectric layer, saving the time of the entire gate structure layer process production and adjustment, and reducing the overall production cost. The control chip used in this monitoring method can be used, and after using this control chip, the control chip can be recycled, which can further reduce the cost of this monitoring method. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic structural diagram of measuring the work function of a wafer using a measuring machine having only a large Kelvin probe in one embodiment of the present invention.

[0015] Figure 2 It is a flow chart of a method for monitoring a semiconductor gate structure layer manufacturing process in one embodiment of the present invention.

[0016] Figure 3 It is a schematic diagram of the structure after an interface layer is deposited on the surface of the control sheet in one embodiment of the present invention.

[0017] Figure 4 It is a schematic diagram of the structure after a high-K gate dielectric layer is deposited on the surface of the interface layer in one embodiment of the present invention.

[0018] Figure 5 It is a schematic diagram of the structure after a metal layer is deposited on the surface of a high-K gate dielectric layer in one embodiment of the present invention.

[0019] Figure 6 Graph showing the functional relationship between the work function and the thickness of the metal layer in one embodiment of the present invention.

[0020] Figure 7 4 is a functional relationship diagram of the work function and the metal layer concentration in one embodiment of the present invention.

[0021] Figure 8 4 is a fitting relationship diagram between the relative work function and the absolute work function in one embodiment of the present invention.

[0022] Fig. 9It is a fitting relationship diagram between the relative work function and the absolute work function in another embodiment of the present invention.

[0023] In the figure, 10-carrying platform; 20-large Kelvin probe; 100-control piece; 200-interface layer; 300-high K dielectric layer; 400-metal layer. DETAILED DESCRIPTION

[0024] In order to make the purpose, advantages and features of the present invention clearer, the monitoring method of the semiconductor gate structure layer manufacturing process proposed by the present invention is further described in detail in combination with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific application and use environment. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or a part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0025] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0026] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0027] The core idea of ​​the present invention is to provide a method for monitoring the manufacturing process of a semiconductor gate structure layer, which can shorten the detection time and avoid scrapping wafers based on existing equipment. At the same time, it can also achieve the purpose of reducing detection costs.

[0028] In order to realize the above idea, the present invention provides a monitoring method for the manufacturing process of a semiconductor gate structure layer (hereinafter referred to as the "monitoring method"), wherein the gate structure layer includes a gate layer and a gate dielectric layer, wherein the gate dielectric layer is located between the semiconductor device channel and the gate layer and may be a multi-layer dielectric layer; similarly, based on different processes and gate structure materials, the gate layer may be a single layer or a combination of multiple layers of materials. Figures 1 to 9 A specific implementation of the disclosed monitoring method. The monitoring method includes the following steps S1 to S5.

[0029] Step S1: providing a control wafer 100 and testing to obtain the work function W of the control wafer 100 SI .

[0030] Specifically, refer to Figure 2 and Figure 3 As shown, a wafer without a pattern on the surface is used as the control chip 100. The control chip 100 is used as a substrate. According to the type of the gate in the gate structure layer to be monitored, the control chip selects a substrate of a different type. The work function W of the control chip 100 is SI The measurement is performed by using a non-contact Kelvin probe. The control chip 100 is placed on a measuring machine to measure the work function W of the control chip 100. SI The measuring machine is a machine with a Kelvin probe 20, and the machine is equipped with a Kelvin probe 20 with a diameter of 2 mm. By moving the Kelvin probe 20 above the control piece 100, the work function W of the control piece 100 is measured and obtained. SI .

[0031] Step S2: The control chip 100 and the patterned wafer to be monitored are used to sequentially form a gate dielectric layer and a gate layer on the surface of the control chip 100, and the patterning process of the gate dielectric layer and the gate layer involved in the patterned wafer is omitted. The specific patterning process includes the photolithography and etching process in the semiconductor manufacturing process, but is certainly not limited thereto, and other processes such as cleaning may also be involved. Among them, the doping type of the manufactured gate layer is different from that of the control chip 100.

[0032] Specifically, refer to Figures 2 to 5As shown, the control chip 100 and the patterned wafer to be monitored are subjected to the following steps together, and a gate dielectric layer and a gate layer are sequentially formed on the surface of the control chip 100. The gate dielectric layer includes an interface layer 200 and a high-K dielectric layer 300, and the gate layer is described by taking a metal layer 400 as an example. That is, an interface layer 200, a high-K dielectric layer 300 and a metal layer 400 are sequentially formed on the surface of the control chip 100. Preferably, before forming the interface layer 200, the control chip 100 is first cleaned to remove impurity particles on the surface of the control chip 100 or an impurity layer on the surface. It should be noted that the control chip 100 and the patterned wafer to be monitored perform the above steps together and omit the patterning process of the gate dielectric layer and the gate layer.

[0033] Before forming the high-K dielectric layer 300, an interface layer 200 may be deposited on the surface of the cleaned control wafer 100. The interface layer 200 provides a good interface foundation for the high-K dielectric layer 300 to be formed later, improves the quality of the formed high-K dielectric layer 300, reduces the interface state density between the high-K dielectric layer 300 and the control wafer 100, and enables the high-K dielectric layer 300 to form a good contact with the control wafer 100. In this embodiment, the material of the interface layer 200 may be silicon oxide, and the material of the high-K dielectric layer 300 may be HfO. 2 In other embodiments, the material of the high-K dielectric layer 300 may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or ZrO2. Correspondingly, the interface layer 200 may be made of other silicide materials, such as silicon oxide, silicon nitride, silicon oxynitride and combinations thereof. In this embodiment, the material of the gate layer may be a stack of one or more of TiN, TaN, TaSiN, TiSiN, TiAl, TiAlC, TaAlN, TiAlN, TaCN and AlN. Figure 5 The metal layer 400 is taken as an example. Figure 3 , Figure 4 and Figure 5 The film layer of the gate structure layer formed on the surface of the control chip 100 is only illustrated for the sake of a simple schematic diagram, and does not represent the thickness of the film layer in the actual gate structure layer or the specific ratio between the film layer thicknesses. If the gate layer / metal layer in the gate structure layer to be monitored is an N-type material, the control chip 100 is selected as a P-type substrate. If the gate layer / metal layer to be monitored is a P-type material, the control chip 100 is an N-type substrate.

[0034] Step S3: Testing the dark field surface contact potential difference V of the control sheet 100 by non-contact method CPDDARK .

[0035] Specifically, refer to Figure 2 As shown, a non-contact Kelvin large probe with surface photovoltage technology is used to measure the dark field surface contact potential difference V under dark field conditions. CPDDARKThe so-called dark field refers to the surface contact potential difference measured in the absence of light.

[0036] Step S4: Testing the contact potential difference V of the surface of the control sheet 100 in the bright field by non-contact method CPDLIGHT .

[0037] Specifically, refer to Figures 1 to 5 The surface contact potential difference V is measured using a non-contact Kelvin probe with surface photovoltage technology. CPDLIGHT . The so-called bright field refers to the surface contact potential difference measured under illumination conditions. The light source can be green light or white light. In order to improve the accuracy of the measurement, the output power of the light source is greater than or equal to 100 watts. The test machine with only a large Kelvin probe 20 is still used as an example for explanation. This test machine is equipped with a large Kelvin probe 20 with a diameter of 2 mm. Take the measurement of the surface potential barrier (Vsb) of the control piece 100 as an example. First, place the control piece 100 on the carrier 10, and measure the control piece 100 by moving the probe above the control piece 100. The measuring machine uses a non-contact large Kelvin probe for measurement. During the specific measurement, the surface photovoltage technology is used to generate carriers by irradiating the wafer with light of a specific wavelength, and by measuring the change in voltage. For example, the bright field surface contact potential difference V of the control piece 100 can be measured by irradiating the wafer with green light with a wavelength of about 500 nm and without irradiation. CPDLIGHT The contact potential difference V between the dark field surface and the control piece 100 CPDDARK .

[0038] Step S5: Based on the work function W of the control sheet 100 SI , dark field surface contact potential difference V CPDDARK The contact potential difference V with the bright field surface CPDLIGHT , calculate and obtain the relative work function of the gate structure layer of the control wafer 100.

[0039] Specifically, refer to Figures 2 to 5 As shown, based on the work function W of the control sheet 100 SI , dark field surface contact potential difference V CPDDARK The contact potential difference V with the bright field surface CPDLIGHT The calculation to obtain the relative work function of the gate structure layer of the control wafer 100 includes: The relative work function of the gate structure layer = work function W SI - Surface potential barrier V SB , where q is the charge constant, and q is preferably 1.6×10 -19 Coulomb. Surface barrier V SB = Dark field surface contact potential difference V CPDDARK -Bright field surface contact potential difference V CPDLIGHT .

[0040] The above-described example can obtain the relative work function of the control wafer gate structure layer. The gate structure layer of the control wafer 100 involved in this measurement method does not need to be patterned, the time for making the test control wafer 100 can be shortened, and the equipment requirements for measuring the work function are also relatively low. The measurement equipment with surface photovoltage technology and Kelvin large probe can meet the requirements.

[0041] In the monitoring method described above, in order to further obtain the process parameters of the specific monitoring layer in the semiconductor gate structure layer to be monitored, it is also necessary to sample the absolute work function data corresponding to the process parameters in advance. The absolute work function measurement method can be obtained according to the contact capacitance method introduced above, or it can be measured by other methods and is not limited to the contact capacitance method mentioned above. Please refer to Figure 6 or Figure 7 , a schematic description is given by taking the case where the gate layer body is made of a metal layer and the process parameters of the gate structure to be monitored are the thickness of the metal layer and the concentration of the metal layer as an example.

[0042] Figure 6 The process parameter of the semiconductor gate structure to be monitored is the film thickness of the metal layer. When using the relative work function measurement method disclosed above, the laboratory capacitance measurement method can be used to measure and collect absolute work function data within a preset process film thickness range. In this embodiment, the metal film thickness is taken as an example, and the relative work function data of the corresponding film thickness collected by the measurement method disclosed in the present invention is used to establish a mathematical relationship between the relative work function and the absolute work function of the film thickness within the preset range of the metal layer. Figure 6 The dotted line in the figure is the curve of the relative work function obtained by the online wafer measurement equipment disclosed in the present invention as a function of the metal layer thickness, and the solid line is the curve of the absolute work function obtained by the traditional laboratory capacitance measurement as a function of the metal layer thickness. Figure 6 As shown in Figure 2, the work function of the metal layer increases with the increase of the metal layer thickness. Figure 6 The data of the relative work function corresponding to the metal layer thickness and the absolute work function corresponding to the metal layer thickness are fitted to obtain the following: Figure 8 The fitted relationship diagram shown in the figure shows that the linear regression coefficient R 2 =0.987. Therefore, in the subsequent monitoring of the thickness of the metal layer in the gate structure manufacturing process, it is only necessary to use the method of measuring the relative work function disclosed by the present invention to compare this relationship to monitor whether the thickness of the metal layer in this process is within the expected process range. This monitoring method of the present invention can effectively shorten the time required for the traditional laboratory capacitance measurement method, avoid traditional destructive testing, and the measured control chip 100 can be recycled and reused, saving costs.

[0043] Taking the gate structure in which the main body of the gate layer is the metal layer 400 as an example, the metal layer 400 is not a metal layer 400 of a single component, and the process parameter of the semiconductor gate structure to be monitored is the concentration of the metal layer 400. Figure 7 The figure is a functional relationship between the work function and the metal layer concentration (i.e., the metal layer composition ratio). The metal layer concentration directly affects the electronic structure of the material. The dotted line is the curve of the relative work function versus the metal layer concentration obtained by the online wafer measurement equipment disclosed in the present invention, and the solid line is the curve of the absolute work function versus the metal layer concentration obtained by the traditional laboratory capacitance measurement. Figure 7 It can be seen that the work function of the metal layer decreases as the concentration of a metal component in the metal layer increases. Figure 7 The relative work function corresponding to the concentration of a certain metal in the metal layer is fitted with the data of the absolute work function corresponding to the metal layer of this metal concentration, and the following is obtained: Fig. 9 The fitted relationship diagram shown in the figure shows that the linear regression coefficient R 2 =0.9988. In the subsequent gate structure manufacturing process, the metal concentration in the metal layer is monitored by comparing this relationship with the method for measuring the relative work function disclosed in the present invention to monitor whether the metal layer concentration in the process is within the expected process range.

[0044] The monitoring of the two process parameters is described in more detail above. Of course, the process parameters of the gate structure monitored by the present invention are not limited to the process parameters in the above gate structure. The monitored process parameters may include the thickness of the gate layer and / or the gate dielectric layer and the composition ratio of the gate layer or a combination of the above process parameters.

[0045] For those skilled in the art, the gate structure layer will have different changes in the materials of the gate dielectric layer and the gate layer as the process of different process nodes changes. The gate dielectric layer can be a single layer or a multi-layer stack and combination, and the gate layer can also be a single layer or a combination of multiple layers, and is not limited to the materials involved in the gate structure listed above. The manufacturing process of the gate structure layer is extremely important for the production of the entire semiconductor chip, and directly determines the yield of the final chip. Monitoring the process links of the gate structure is also particularly important. The traditional contact capacitance measurement method is time-consuming and destructive testing, so it is not suitable for use in mass production of later products.

[0046] The monitoring method disclosed in the present invention can quickly and accurately monitor the parameters of the gate structure layer process link only by measuring the relative work function method, without the need for the traditional time-consuming and costly contact capacitance testing method for monitoring. As described above, the premise for the use of this method is to collect the data of the relative work function and the absolute work function corresponding to the parameters to be monitored within the preset process range, and establish a corresponding mathematical function relationship. The monitoring method can be used to provide timely feedback and adjustment of process parameters for the manufacturing process of the gate layer and the gate dielectric layer, saving the time for the entire gate structure layer process manufacturing and adjustment, and reducing the overall manufacturing cost. The control piece 100 used in this monitoring method can be carried out, and after using this control piece 100, the control piece 100 can be recycled, which can further reduce the cost of this monitoring method.

[0047] In summary, the above embodiments have detailed descriptions of different configurations of the monitoring method for the semiconductor gate structure layer manufacturing process. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not any limitation to the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above implementations. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure are within the scope of protection of the claims.

Claims

1. A method for monitoring a semiconductor gate structure layer manufacturing process, wherein the gate structure layer comprises a gate layer and a gate dielectric layer, wherein the gate dielectric layer is located between a semiconductor device channel and the gate layer, wherein: The monitoring method comprises: Provide a control chip, and test and obtain the work function W of the control chip SI ; The control wafer is combined with a patterned wafer to be monitored, and the gate dielectric layer and the gate layer are sequentially formed on the surface of the control wafer, and the patterning process of the gate dielectric layer and the gate layer involved in the patterned wafer is omitted, wherein the gate layer and the control wafer have different doping types; The non-contact method tests the contact potential difference V on the dark field surface of the control film. CPDDARK ; The non-contact method tests the contact potential difference V on the bright field surface of the control piece. CPDLIGHT ; Based on the work function W of the control film SI , dark field surface contact potential difference V CPDDARK The contact potential difference V with the bright field surface CPDLIGHT The relative work function of the gate structure layer of the control wafer is obtained by calculation.

2. The method for monitoring the semiconductor gate structure layer manufacturing process according to claim 1, characterized in that: The calculation method includes: The relative work function of the gate structure layer = work function W SI - Surface potential barrier V SB , where q is the charge constant, Surface barrier V SB = Dark field surface contact potential difference V CPDDARK -Bright field surface contact potential difference V CPDLIGHT .

3. The method for monitoring the semiconductor gate structure layer manufacturing process according to claim 1, characterized in that: The gate layer is a metal layer, and the gate dielectric layer is a high-K dielectric layer.

4. The method for monitoring the semiconductor gate structure layer manufacturing process according to claim 3, characterized in that: The work function W of the control film SI The measurement is carried out using a non-contact Kelvin probe.

5. The method for monitoring the semiconductor gate structure layer manufacturing process according to claim 4, characterized in that: The dark field surface of the control piece contacts the potential difference V CPDDARK The contact potential difference V with the bright field surface CPDLIGHT Measured using a non-contact Kelvin macroprobe with surface photovoltage technology.

6. The method for monitoring the semiconductor gate structure layer manufacturing process according to claim 1, characterized in that: Also includes: Sampling absolute work function data measured by a contact capacitance method corresponding to process parameters of a semiconductor gate structure layer to be monitored; Obtaining non-contact relative work function data corresponding to the process parameters of the semiconductor gate structure layer; Based on the absolute work function data and the relative work function data, two work function relationship equations of process parameters are obtained; Based on the relationship, the process parameters of the semiconductor gate structure layer are monitored by measuring the non-contact relative work function.

7. The method for monitoring the semiconductor gate structure layer manufacturing process according to claim 6, characterized in that: The process parameters of the semiconductor gate structure layer include the thickness of the gate layer and / or the gate dielectric layer and the composition ratio of the gate layer or a combination of the above process parameters.

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