Optoelectronic unit

Abstract

The invention discloses a photoelectric unit which comprises a base layer, a functional area, a semiconductor element and a coating layer. The base layer has a first side and a second side opposite to the first side. The functional area is arranged on the first side of the base layer. The semiconductor element is arranged on the second side of the base layer, comprises a first electrode and a second electrode, and corresponds to the functional area. The cladding layer is disposed on the second side of the base layer and surrounds the semiconductor element, wherein a portion of the first electrode and a portion of the second electrode are exposed out of the cladding layer.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and in particular to a photovoltaic unit. Background Art

[0002] Vertical Cavity Surface Emitting Laser (VCSEL) is a type of semiconductor laser element. Due to its structural advantage of emitting light from the epitaxial surface, and with the emergence of more application needs and market demand for various IoT products, smart electronic products, and smart sensing products, VCSEL components have gradually expanded from the network communication product market to various smart products (for example, optical communication light source modules, proximity sensors in smart tablet phones and smart headphones, depth, distance, and 3D sensors, lidar sensors for advanced driver assistance systems, micro-projection display light sources or panels, eye trackers in interactive devices, integrated optical circuits, etc.).

[0003] In most of the aforementioned current application products, due to various requirements in product development and product use (for example, low cost, light and easy to carry, miniaturization, high integration and matching with other components, strict environmental reliability in automotive applications, long product life, low power consumption, long usage time, high-frequency electrical drive operation, etc.), more and more VCSEL devices adopt flip-chip packaging technology to meet the aforementioned requirements. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a photovoltaic unit.

[0005] In some embodiments, a photovoltaic unit is provided, comprising a substrate, a functional area, a semiconductor element, and a coating layer. The substrate has a first side and a second side, the second side being opposite to the first side. The functional area is disposed on the first side of the substrate. The semiconductor element is disposed on the second side of the substrate, the semiconductor element comprises a first electrode and a second electrode, and the semiconductor element corresponds to the functional area. The coating layer is disposed on the second side of the substrate and surrounds the semiconductor element, wherein a portion of the first electrode and a portion of the second electrode are exposed outside the coating layer.

[0006] In some embodiments, the semiconductor device is a flip-chip vertical cavity laser chip.

[0007] In some embodiments, the optoelectronic unit further includes a plurality of the functional regions and a plurality of the semiconductor elements, wherein the number of the functional regions is the same as the number of the semiconductor elements.

[0008] In some embodiments, the photovoltaic unit further includes a light-transmitting substrate disposed on the first side of the base layer.

[0009] In some embodiments, the light-transmitting substrate is located between the functional area and the base layer.

[0010] In some embodiments, the functional region has a microstructure with nanometer to micrometer dimensions.

[0011] In some embodiments, the microstructure includes a metainterface structure, a diffractive optical element structure, a microlens array structure, or a combination of at least two of the foregoing.

[0012] In some embodiments, at least one of the first electrode and the second electrode is coplanar with the cladding layer.

[0013] In some embodiments, the functional area is smaller than the optoelectronic unit and larger than the semiconductor device.

[0014] In some embodiments, the width of the first side of the base layer is smaller than the width of the cladding layer.

[0015] In some embodiments, a width of the first side of the base layer is smaller than a width of the semiconductor device.

[0016] According to some embodiments, a semiconductor laser is provided, comprising: a first-type semiconductor layer having a light-emitting hole; a second-type semiconductor layer; an active structure located between the first-type semiconductor layer and the second-type semiconductor layer; and a spacer layer. The active structure and the spacer layer are stacked to form a vertical space as an optical resonant cavity. The spacer layer includes a first spacer layer and a second spacer layer, the first spacer layer is located between the first-type semiconductor layer and the active structure, and the second spacer layer is located between the second-type semiconductor layer and the active structure. The active structure includes at least one first quantum well layer, at least one second quantum well layer, and a barrier layer structure located between the at least one first quantum well layer and the at least one second quantum well layer, the at least one second quantum well layer is farther away from the light-emitting hole than the at least one first quantum well layer, and the emission wavelength of the at least one second quantum well layer is greater than the emission wavelength of the at least one first quantum well layer. In some embodiments, the total thickness of the optical resonant cavity is an integer multiple (nλp) of the peak value (λp) of the resonant wavelength of the semiconductor laser, where n is a positive integer.

[0017] In some embodiments, a semiconductor laser comprises a conductive substrate, a semiconductor stacking layer, a contact electrode layer, a metal bonding layer, a first conductive structure, a plurality of insulating structures, a plurality of anti-reflective structures, and a plurality of second conductive structures. The semiconductor stacking layer is located on the conductive substrate, wherein the semiconductor stacking layer comprises: a first-type semiconductor layer, a second-type semiconductor layer, and an active structure. The active structure is located between the first-type semiconductor layer and the second-type semiconductor layer. The contact electrode layer is located on one side of the conductive substrate relative to the semiconductor stacking layer. The metal bonding layer is located between the conductive substrate and the second-type semiconductor layer of the semiconductor stacking layer. A plurality of first conductive structures are located between the metal bonding layer and the second-type semiconductor layer of the semiconductor stacking layer. A plurality of insulating structures extend from the metal bonding layer through the first conductive structures, the second-type semiconductor layer, and the active structure and at least extend to a portion of the first-type semiconductor layer, and define the second-type semiconductor layer and the active structure as a plurality of columnar structures. A plurality of anti-reflective structures are located on one side of the first-type semiconductor layer of the semiconductor stacking layer relative to the metal bonding layer and correspond to the columnar structures. A plurality of second conductive structures are located on a side of the first type semiconductor layer of the semiconductor stack layer opposite to the metal bonding layer, wherein the second conductive structures are located between the anti-reflection structures and correspond to the insulating structures.

[0018] In some embodiments, a semiconductor laser includes a light-transmitting substrate, a semiconductor stacking layer, a light-transmitting bonding layer, a plurality of insulating structures, a plurality of first conductive structures, a plurality of second conductive structures, a first electrode structure, a second electrode structure, and an insulating layer. The semiconductor stacking layer is located on the light-transmitting substrate. The semiconductor stacking layer includes: a first-type semiconductor layer, a second-type semiconductor layer, and an active structure located between the first-type semiconductor layer and the second-type semiconductor layer. The light-transmitting bonding layer is located between the light-transmitting substrate and the first-type semiconductor layer of the semiconductor stacking layer. A plurality of insulating structures extend from the second-type semiconductor layer of the semiconductor stacking layer through the active structure and at least extend to a portion of the first-type semiconductor layer, and define the second-type semiconductor layer, the active structure, and a portion of the first-type semiconductor layer as a plurality of columnar structures. A plurality of first conductive structures are located between the first-type semiconductor layer of the semiconductor stacking layer and the light-transmitting bonding layer and correspond to the insulating structures. A plurality of second conductive structures are located on one side of the second-type semiconductor layer of the semiconductor stacking layer relative to the light-transmitting bonding layer. The first electrode structure is located on the second type semiconductor layer of the semiconductor stack layer and extends to the side of the semiconductor stack layer to connect at least one of the first conductive structures, wherein the first electrode structure is electrically connected to the first type semiconductor layer through the first conductive structures. In some embodiments, the first electrode structure covers at least one columnar structure. The second electrode structure is located on the second type semiconductor layer of the semiconductor stack layer. The insulating layer is located between the semiconductor stack layer and the first electrode structure, and between the semiconductor stack layer and the second electrode structure, wherein the insulating layer has an opening, and the second electrode structure is further distributed in the opening and contacts the second conductive structures, so that the second electrode structure is electrically connected to the second type semiconductor layer through the second conductive structures.

[0019] In some embodiments, a semiconductor laser comprises a conductive substrate, a semiconductor stacking layer, a contact electrode layer, a metal bonding layer, a plurality of first conductive structures, a plurality of insulating structures, a plurality of anti-reflective structures, and a plurality of second conductive structures. The semiconductor stacking layer is located on the conductive substrate, wherein the semiconductor stacking layer comprises: a first-type semiconductor layer, a second-type semiconductor layer, and an active structure. The active structure is located between the first-type semiconductor layer and the second-type semiconductor layer. The contact electrode layer is located on one side of the conductive substrate relative to the semiconductor stacking layer. The metal bonding layer is located between the conductive substrate and the second-type semiconductor layer of the semiconductor stacking layer. A plurality of second conductive structures are located between the metal bonding layer and the second-type semiconductor layer of the semiconductor stacking layer. A plurality of insulating structures extend from the metal bonding layer through the second conductive structures, the second-type semiconductor layer, and the active structure and extend to at least part of the first-type semiconductor layer, and define the second-type semiconductor layer, the active structure, and part of the first-type semiconductor layer as a plurality of columnar structures. A plurality of anti-reflective structures are located on one side of the first-type semiconductor layer of the semiconductor stacking layer relative to the metal bonding layer and correspond to the columnar structures. A plurality of first conductive structures are located on a side of the first type semiconductor layer of the semiconductor stack layer opposite to the metal bonding layer, wherein the first conductive structures are located between the anti-reflection structures and correspond to the insulating structures.

[0020] In some embodiments, a semiconductor laser comprises a conductive substrate, a semiconductor stacking layer, a contact electrode layer, a metal bonding layer, a plurality of first conductive structures, a plurality of insulating structures, a plurality of anti-reflective structures, and a plurality of second conductive structures. The semiconductor stacking layer is located on the conductive substrate, wherein the semiconductor stacking layer comprises: a first-type semiconductor layer, a second-type semiconductor layer, and an active structure. The active structure is located between the first-type semiconductor layer and the second-type semiconductor layer. The contact electrode layer is located on one side of the conductive substrate relative to the semiconductor stacking layer. The metal bonding layer is located between the conductive substrate and the second-type semiconductor layer of the semiconductor stacking layer. A plurality of second conductive structures are located between the metal bonding layer and the second-type semiconductor layer of the semiconductor stacking layer. A plurality of insulating structures extend from the metal bonding layer through the second conductive structures, the second-type semiconductor layer, and the active structure and at least extend to a portion of the first-type semiconductor layer, and define the second-type semiconductor layer and the active structure as a plurality of columnar structures. A plurality of anti-reflective structures are located on one side of the first-type semiconductor layer of the semiconductor stacking layer relative to the metal bonding layer and correspond to the columnar structures. A plurality of first conductive structures are located on a side of the first type semiconductor layer of the semiconductor stack layer opposite to the metal bonding layer, wherein the first conductive structures are located between the anti-reflection structures and correspond to the insulating structures.

[0021] According to some embodiments, a photoelectric device is provided, comprising: a light-emitting unit, including a substrate and a light-emitting element located on one side of the substrate, wherein the light-emitting element is configured to provide a light; a switch unit, located on a light-emitting path of the light, wherein the switch unit is configured to allow the light to pass through the switch unit or be shielded by the switch unit; a light-receiving element, configured to receive a reflected light after the light is reflected; and a driving chip, including a driving function block, a modulation function block and a signal processing function block, which are signal-connected to each other; wherein the driving function block is electrically connected to the light-emitting element and the light-receiving element, and the modulation function block is electrically connected to the switch unit; wherein the signal processing function block is signal-connected to the light-receiving element and is configured to analyze the reflected light.

[0022] According to some embodiments, a photoelectric device is provided, comprising: a light-emitting unit, including a substrate and a light-emitting element located on one side of the substrate, wherein the light-emitting element is configured to provide a light; a light-receiving element, configured to receive a reflected light after the light is reflected; and a driving chip, including a driving functional block and a signal processing functional block that are signal-connected to each other; wherein the driving functional block is electrically connected to the light-emitting element and the light-receiving element; wherein the signal processing functional block is signal-connected to the light-receiving element and is configured to analyze the reflected light.

[0023] According to some embodiments, a semiconductor laser is provided, comprising: a conductive substrate; a semiconductor stack layer located on the conductive substrate, wherein the semiconductor stack layer comprises: a first-type semiconductor layer; a second-type semiconductor layer; and an active structure located between the first-type semiconductor layer and the second-type semiconductor layer; a contact electrode layer located on a side of the conductive substrate opposite to the semiconductor stack layer and electrically connected to the second-type semiconductor layer through the conductive substrate; wherein the first-type semiconductor layer, the active structure and a portion of the second-type semiconductor layer define a plurality of high-platform structures, and grooves are provided between the high-platform structures; a conductive layer located on the high-platform structures and extending through the grooves to the first-type semiconductor layer, wherein the conductive layer is electrically connected to the first-type semiconductor layer; and an insulating layer located between the conductive layer and the high-platform structures and between the conductive layer and the grooves, wherein the insulating layer further extends through the side of the semiconductor stack layer and extends to the conductive substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic cross-sectional view of a packaging structure of an optoelectronic component;

[0025] Figure 2-1A is a cross-sectional schematic diagram of a packaging structure of a photovoltaic unit according to an embodiment;

[0026] Figure 2-1B is a cross-sectional schematic diagram of a packaging structure of a photovoltaic unit according to an embodiment;

[0027] Figure 2-1C is a schematic cross-sectional view of a packaging structure of a light emitting sensor package according to an embodiment;

[0028] Figure 2-1D is a schematic cross-sectional view of a packaging structure of a light emitting sensor package according to an embodiment;

[0029] Figure 2-2A is a cross-sectional schematic diagram of a packaging structure of a photovoltaic unit according to an embodiment;

[0030] Figure 2-2B is a schematic cross-sectional view of a packaging structure of a light emitting sensor package according to an embodiment;

[0031] Figure 2-3 is a cross-sectional schematic diagram of a packaging structure of a photovoltaic unit according to an embodiment;

[0032] FIG. 3A to FIG. 3D For one or more embodiments of the invention, Figure 3E A schematic diagram of the process flow of the photovoltaic unit shown;

[0033] Figure 3E is a cross-sectional schematic diagram of a photovoltaic unit according to one or more embodiments;

[0034] FIG. 4A to FIG. 4C One or more embodiments are manufactured using a panel chip size package manufacturing process such as Figure 4D A schematic diagram of the process flow of the photovoltaic unit shown;

[0035] Figure 4D is a cross-sectional schematic diagram of a photovoltaic unit according to one or more embodiments;

[0036] FIG. 5A to FIG. 5C One or more embodiments are manufactured using a panel chip size package manufacturing process such as Figure 5D The schematic diagram of the process of the photovoltaic unit shown;

[0037] Figure 5D is a cross-sectional schematic diagram of a photovoltaic unit according to one or more embodiments;

[0038] FIG. 6A to FIG. 6C One or more embodiments are manufactured using a panel chip size package manufacturing process such as Fig.6D The schematic diagram of the process of the photovoltaic unit shown;

[0039] Fig.6D is a cross-sectional schematic diagram of a photovoltaic unit according to one or more embodiments;

[0040] Figure 7 is a cross-sectional schematic diagram of a semiconductor light emitting device according to an embodiment;

[0041] Fig. 8Ais a cross-sectional schematic diagram of a semiconductor light emitting device according to an embodiment;

[0042] Figure 8B For Fig. 8A A bottom view of the semiconductor light emitting element shown;

[0043] Figure 8C For Fig. 8A A top view of the semiconductor light emitting element shown;

[0044] Fig. 9 is a cross-sectional schematic diagram of a semiconductor light emitting device according to an embodiment;

[0045] FIG. 10A to FIG. 10E Schematic diagrams of bottom perspective, top perspective and cross-sectional views of a semiconductor light emitting element of an exemplary embodiment;

[0046] Fig.11 is a cross-sectional schematic diagram of a semiconductor light emitting device according to an embodiment;

[0047] Fig. 12A is a schematic top perspective view of a semiconductor light emitting element according to an embodiment;

[0048] Fig. 12B and Fig. 12C Along the Fig. 12A 12B-12B' and 12C-12C' are cross-sectional schematic diagrams of the cross-sections shown in the line segment;

[0049] Fig.13 is a cross-sectional schematic diagram of a semiconductor light emitting device according to an embodiment;

[0050] Fig.13A and Fig. 13B A schematic cross-sectional view and a schematic top view of a chip packaging structure according to an embodiment of the present invention;

[0051] Fig.14A is a cross-sectional side view of a chip packaging structure according to another embodiment of the present invention;

[0052] Fig. 14B and Fig. 14C A schematic top view and a schematic cross-sectional view of a chip packaging structure according to an embodiment of the present invention;

[0053] Fig.15 is a cross-sectional side view of a chip packaging structure according to another embodiment of the present invention;

[0054] Fig.16 is a cross-sectional side view of a chip packaging structure according to another embodiment of the present invention;

[0055] Fig.17 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention;

[0056] Fig.18 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention;

[0057] Fig.19 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention;

[0058] Fig. 20 A schematic cross-sectional view of a partial structure of a chip packaging structure according to another embodiment of the present invention;

[0059] Fig.21 is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention;

[0060] Fig.22A and Fig. 22B Schematic diagrams for explaining the shape of a first chip in a chip packaging structure according to two embodiments of the present invention;

[0061] Fig.23A and Fig. 23B A schematic top view and a schematic cross-sectional view of a chip packaging structure according to another embodiment of the present invention;

[0062] Fig.23C is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment;

[0063] Fig.24A A top view of a microscopic image of a light receiving portion of a photoelectric converter;

[0064] Fig. 24B For along Fig.24A A schematic cross-sectional view of line segment 24A-24A';

[0065] Fig.25A as well as Fig.25B Schematic diagrams of equivalent circuits of high voltage photoelectric converter and low voltage photoelectric converter respectively;

[0066] Fig.26A is a top perspective schematic diagram of a rectangular unit of a photoelectric converter according to an embodiment;

[0067] Fig.26B as well as Fig.26C They are respectively schematic top perspective views of a hexagonal unit of a photoelectric converter according to an embodiment;

[0068] Fig.27A is a top perspective schematic diagram of a plurality of hexagonal units of a photoelectric converter according to an embodiment;

[0069] Fig.27B Schematic diagram of the layout design for rectangular cells and hexagonal cells with different diameters of light emitting areas or light receiving areas;

[0070] Fig.27C A schematic top perspective view of a plurality of hexagonal units of a photoelectric converter in one embodiment connected in series;

[0071] Fig.27D A schematic top perspective view of a plurality of hexagonal units of a photoelectric converter of an embodiment connected in parallel;

[0072] Fig.28A is the relationship between the top view layout and the cross-sectional layout of the hexagonal unit;

[0073] Fig.28B A schematic diagram of the chip layout of a high voltage photoelectric converter;

[0074] FIG. 29A to FIG. 29C They are respectively the relationship diagrams between the gain spectrum of the active structure of the semiconductor laser known to the inventor and the resonance wavelength of the emitted light of the semiconductor laser at different temperatures;

[0075] FIG. 29D to FIG. 29F The following are relationship diagrams of the gain spectrum of the active structure and the resonance wavelength of the emitted light of the semiconductor laser at different temperatures of the semiconductor laser of some embodiments of the present invention;

[0076] Fig.30 is a cross-sectional schematic diagram of a semiconductor laser according to an embodiment;

[0077] Fig.31 is a schematic cross-sectional view of a semiconductor laser according to an embodiment;

[0078] Fig.32 is a cross-sectional schematic diagram of a semiconductor laser according to an embodiment;

[0079] Fig.33 is a cross-sectional schematic diagram of a semiconductor laser according to an embodiment;

[0080] Fig.34 is a cross-sectional schematic diagram of a semiconductor laser according to an embodiment;

[0081] Fig.35 is a cross-sectional schematic diagram of a semiconductor laser according to an embodiment;

[0082] Fig.36 Schematic diagram of the cross-sectional structure of semiconductor lasers according to some embodiments of the present invention;

[0083] FIG. 37A to FIG. 37F Schematic diagram of the cross-sectional structure of multiple steps of the manufacturing process of the semiconductor laser in some embodiments of the present invention;

[0084] FIG. 38A to FIG. 38F Schematic diagram of the cross-sectional structure of multiple steps of the manufacturing process of the semiconductor laser in some embodiments of the present invention;

[0085] Fig.39 Schematic diagram of the cross-sectional structure of semiconductor lasers according to some embodiments of the present invention;

[0086] FIG. 40A to FIG. 40F Schematic diagram of the cross-sectional structure of multiple steps of the manufacturing process of the semiconductor laser in some embodiments of the present invention;

[0087] Fig.41 Schematic diagram of the cross-sectional structure of semiconductor lasers according to some embodiments of the present invention;

[0088] Fig.42 Schematic diagram of the cross-sectional structure of semiconductor lasers according to some embodiments of the present invention;

[0089] Fig.43 Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0090] Fig.44A Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0091] Fig.44B Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0092] Fig.45A Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0093] Fig.45B Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0094] Fig.46A Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0095] Fig.46B Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0096] Fig.47A Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0097] Fig.47B Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0098] Fig.47C Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0099] Fig.47D Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0100] Fig.47E Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0101] Fig.48 Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0102] Fig.49 Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0103] Fig.50A Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0104] Fig.50B Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0105] Fig.51 Schematic cross-sectional view of a photovoltaic device according to some embodiments of the present invention;

[0106] FIG. 52A to FIG. 52C They are schematic diagrams of switch units of some embodiments;

[0107] Fig.53 is a schematic diagram of a switch unit of some embodiments;

[0108] Fig.54 is a schematic diagram of a switch unit of some embodiments;

[0109] Fig.55 A schematic cross-sectional view of a semiconductor laser known to the inventor;

[0110] Fig.56 Schematic cross-sectional view of semiconductor lasers in some embodiments;

[0111] Fig.57 Schematic cross-sectional view of semiconductor lasers in some embodiments;

[0112] Fig.58 Schematic cross-sectional view of semiconductor lasers in some embodiments;

[0113] Fig.59 Schematic cross-sectional view of semiconductor lasers in some embodiments;

[0114] FIG. 60A to FIG. 60G For Fig.55 The illustrated schematic cross-sectional structure diagram of multiple steps of the manufacturing process of a semiconductor laser known to the inventor;

[0115] Figures 61A to 61H For Fig.57 Schematic cross-sectional views of multiple steps of a semiconductor laser manufacturing process of some embodiments;

[0116] Figures 62A to 62G Schematic diagram of cross-sectional structures of multiple steps of a semiconductor laser manufacturing process in some embodiments;

[0117] FIG. 63A to FIG. 63I For Fig.58 Schematic cross-sectional views of multiple steps of a semiconductor laser manufacturing process of some embodiments;

[0118] Fig.64A A schematic top view of a noise test of a semiconductor laser using an optical receiver;

[0119] Fig.64B A schematic diagram of a cross-sectional structure for performing noise testing on a semiconductor laser using an optical receiver;

[0120] Fig.64C A comparison diagram of noise tests performed on semiconductor lasers known to the inventor and semiconductor lasers according to some embodiments.

[0121] Explanation of symbols

[0122] 1: Optoelectronic components

[0123] 1c: Coupling Fiber

[0124] 1d: Optical components

[0125] 2, 2', 2-1, 2-2, 2-1', 2-2', 3A: Photoelectric unit

[0126] 2C, 2D, 2D': Luminous sensor package

[0127] 1100: Transparent base

[0128] 1101, 1401: Integrated optical components

[0129] 1101A, 1101B: microlens

[0130] 1200, 2500: Adhesion layer

[0131] 1300:Carrier board

[0132] 1310: First corresponding pad

[0133] 1320: Second corresponding pad

[0134] 1330: Third corresponding pad

[0135] 1400: Shell

[0136] 1401A, 1401B, 34: Optical components

[0137] 2000: Stacked Structure

[0138] 2000T, 2100T, 2100UT, 2100LT: Top surface

[0139] 2000B, 2200B: bottom surface

[0140] 2100, 2100': Luminescent epitaxial structure

[0141] 2100U, 2100U': Distributed Bragg Reflector

[0142] 2100L, 2100L': Distributed Bragg Reflector

[0143] 2100L1, 2100L2, 2210': Distributed Bragg reflector structure

[0144] 2100A, 2100A': Active structure

[0145] 2100P, 2100P1, 2100P2, 2200N, 2200N1, 2200N2, 2200N3, 2400, 2401, 2402: Conductive structure

[0146] 2000V, 2100V: Through-hole structure

[0147] 2000VI, 2100VI: Insulation structure

[0148] 2125: Current limiting layer

[0149] 2125A: Current conduction area

[0150] 2125B: Current Limit Area

[0151] 2200, 2200': Light receiving structure

[0152] 2100e, 2200e, 2200e1, 2200e2, 2200e3, 2400e: electrode pads

[0153] Lo, Lo', Lo1, Lo2: Coherent light

[0154] Lr, Lr1, Lr2: reflected light

[0155] 3, 4, 5, 6: Photoelectric unit

[0156] 31: Grassroots

[0157] 300: Optoelectronics wafer

[0158] 309: Cutting Machine

[0159] 311, 342: Functional area

[0160] 312: Alignment mark

[0161] 32: Semiconductor components

[0162] 32a: first semiconductor element

[0163] 32b: Second semiconductor element

[0164] 33: Coating layer

[0165] 34: Optical components

[0166] 34a: first optical element

[0167] 34b: Second optical element

[0168] 341, 341a, 341b: light-transmitting substrate

[0169] 342, 342a, 342b: Functional area

[0170] 35:Jointing material

[0171] 7000:Semiconductor light emitting element

[0172] 7001: Transparent base

[0173] 7002: Adhesion layer

[0174] 7003:Laser unit

[0175] 7003S: light output side

[0176] 7010: Conductive layer

[0177] 7030: Positive conductive structure

[0178] 7031:First type semiconductor layer

[0179] 7032: Back conductive structure

[0180] 7032A, 7032B: Detection electrodes

[0181] 7032C, 7032D: Conductive electrode

[0182] 7033: Active layer

[0183] 7034: First channel

[0184] 7035: Second type semiconductor layer

[0185] 7036, 7340: Insulation layer

[0186] 7320: Second channel

[0187] L7: Laser beam

[0188] 8000:Semiconductor light emitting element

[0189] 8010: Transparent base

[0190] 8020: epitaxial structure

[0191] 8032: First insulation layer

[0192] 8034: First metal connection layer

[0193] 8040: Adhesion layer

[0194] 8050: Second metal connection layer

[0195] 8060: Second insulation layer

[0196] 8080: The third insulating layer

[0197] 8101: Anti-reflective structure

[0198] 8202: First semiconductor structure

[0199] 8204:Active structure

[0200] 8205: Current limiting layer

[0201] 8205A: Current conduction area

[0202] 8205B: Current Limit Area

[0203] 8206: Second semiconductor structure

[0204] 8206A: End face

[0205] 8206B: Bottom surface

[0206] 8322: First opening

[0207] 8341a: first protrusion

[0208] 8341b: second protrusion

[0209] 8342: Second opening

[0210] 8344A, 8344B, 8344C, 8344D: Marking structure

[0211] 8601: Side

[0212] 8602a: first opening

[0213] 8602b: Second opening

[0214] 8602c: Third opening

[0215] 8602d: Fourth opening

[0216] 8603: Fifth opening

[0217] 8702: first electrode

[0218] 8704: Second electrode

[0219] 8802: First hole

[0220] 8804: Second hole

[0221] 8902: First pad structure

[0222] 8904: Second pad structure

[0223] 8902A, 8904A, 9123: Middle layer

[0224] 8902B, 8904B: Binding layer

[0225] C81: First Boundary

[0226] C82: Second Boundary

[0227] D81: First Distance

[0228] D82: Second distance

[0229] G8: Spacing

[0230] G81: First spacing

[0231] G82: Second spacing

[0232] G83: Third spacing

[0233] G84: Fourth spacing

[0234] L81, L82: Connection

[0235] O8: Central location

[0236] P8: Columnar structure

[0237] P81: Upper surface

[0238] P82: Side surface

[0239] S81: First side

[0240] S82: Second side

[0241] 9000:Semiconductor light emitting element

[0242] 9110: Base

[0243] 9110A: First surface

[0244] 9110B: Second surface

[0245] 9120:Epitaxial stacking

[0246] 9121: First semiconductor structure

[0247] 9122: Second semiconductor structure

[0248] 9123: Middle layer

[0249] 9124: The third semiconductor structure

[0250] 9125: Current limiting layer

[0251] 9125A: Current conduction area

[0252] 9125B: Current Limit Area

[0253] 9126:Active structure

[0254] 9127: Fourth semiconductor structure

[0255] 9132: First electrode structure

[0256] 9132A: Part 1

[0257] 9132B: Part 2

[0258] 9134: Second electrode structure

[0259] 9140: Recessed structure

[0260] 9150: Protective layer

[0261] 9160:Optical Components

[0262] 10-000:Semiconductor light emitting element

[0263] 10-000A, 10-000B, 10-000C, 10-000D: Luminous area

[0264] 10-010: Grassroots

[0265] 10-040:Metal connection layer

[0266] 10-050A, 10-050B, 10-060A, 10-060B, 10-070A, 10-070B, 10-080A, 10-080B: Electrode structure

[0267] 10-082, 10-084, 10-090: Insulation layer

[0268] 10-226, 10-326: Platform structure

[0269] 10-040a, 10-040b: Part

[0270] 10-040B: Interval

[0271] 10-420, 10-520: Electrode connection layer

[0272] 10-421: Conductive layer

[0273] 10-502A, 10-702A: Middle layer

[0274] 10-504A, 10-704A: Bonding layer

[0275] 10-901: Adhesion layer

[0276] O10: Luminous hole

[0277] P10, P1011, P1012, P1013, P1014, P1015, P1016, P1021, P1022, P1023, P1024, P1031, P1032: epitaxial columnar structure

[0278] TP10: Thermally conductive structure

[0279] 11-000:Semiconductor light emitting components

[0280] 11-010: Grassroots

[0281] 11-010A, 11-010B: Side

[0282] 11-040:Metallic connection layer

[0283] 11-084, 11-090, 11-782: Insulation layer

[0284] 11-242, 11-342: Electrode connection layer

[0285] 11-720, 11-730: epitaxial structure

[0286] 11-720B: Surface

[0287] 11-726, 11-736: Platform structure

[0288] 11-750, 11-760, 11-770, 11-780: Electrode structure

[0289] 11-901: Adhesion layer

[0290] P111, P112: epitaxial columnar structure

[0291] W111, W112: Width

[0292] 12-000:Semiconductor light emitting components

[0293] 12-010: Grassroots

[0294] 12-040:Metallic connection layer

[0295] 12-326, 12-826: Platform structure

[0296] 12-825A: Luminous hole

[0297] 12-825A1, 12-825A2, 12-825A3, 12-825A4: Open

[0298] 12-840, 12-850A, 12-850B, 12-850C, 12-850D: Concave structure

[0299] 12-825, 12-8251, 12-8252, 12-8253, 12-8254: Current limiting layer

[0300] 12-090: Insulation layer

[0301] 12-901: Adhesion layer

[0302] 13-000:Semiconductor light emitting components

[0303] 13-100:Substrate

[0304] 13-105, 13-106: Electrode structure

[0305] 13-040:Metallic connection layer

[0306] 13-040A: Connection layer opening

[0307] 13-082, 13-090: Insulation layer

[0308] 13-082A, 13-082B: Open

[0309] 13-090A: Insulation layer opening

[0310] 13-104: Concave structure

[0311] 13-200: Semiconductor stacking layer

[0312] 13-202, 13-206: Semiconductor layer

[0313] 13-220: Contact structure

[0314] 13-225: Current limiting layer

[0315] 13-225A: Current conduction area

[0316] 13-225B: Current Limit Area

[0317] 13-204: Active layer

[0318] 13-420: Electrode connection layer

[0319] 13-900: Growth substrate

[0320] 13-901: Adhesion layer

[0321] P13: Epitaxial columnar structure

[0322] PB13: Side surface

[0323] U13:Through hole

[0324] 13'-000, 14-000, 15-000: Packaging structure

[0325] 13'-110: Base material

[0326] 13'-110A: First surface

[0327] 13'-110B: Second surface

[0328] 13'-111, 13'-112, 13'-113, 13'-114: Electrically conductive columns

[0329] 13'-120, 13'-320: Bracket

[0330] 13'-120A: Chip area

[0331] 13'-121: first electrical conduction structure

[0332] 13'-122: Second electrical conduction structure

[0333] 13'-130: First Chip

[0334] 13'-131, 13'-231: first conductive structure

[0335] 13'-132, 13'-232: second conductive structure

[0336] 13'-14: Connection layer

[0337] 13'-141: First alignment connection structure

[0338] 13'-142: Second alignment connection structure

[0339] 13'-143, 13'-343: first conductive connection structure

[0340] 13'-144, 13'-344: second conductive connection structure

[0341] 13'-140: Second chip

[0342] 13'-130A, 13'-140A: Active surface

[0343] 13'-140B: Surface

[0344] 13'-211, 13'-212: first electrical conductive column

[0345] 13'-232A, 13'-232B: second conductive structure

[0346] 13'-234, 13'-345, 13'-346: Wire

[0347] D13-1, D13-2, DP13: Distance

[0348] H13: Height

[0349] T13:Thickness

[0350] WC13: Width

[0351] 16-000: Packaging structure

[0352] 16-110: Base material

[0353] 16-411, 16-412: first electrical conduction column

[0354] 16-430: The first chip

[0355] 16-430A: Transmitter surface

[0356] 16-431: First conductive structure

[0357] 16-432: Second conductive structure

[0358] 16-434: Wire

[0359] 17-000, 18-000, 19-000: Packaging structure

[0360] 17-10: Base material

[0361] 17-10A: First surface

[0362] 17-10B: Second surface

[0363] 17-11, 17-12, 17-12': first electrical conductive column

[0364] 17-13, 17-14: Second electrical conductive column

[0365] 17-30: First Chip

[0366] 17-30A: Third surface

[0367] 17-30B: Fourth surface

[0368] 17-31: First conductive structure

[0369] 17-32, 17-32': second conductive structure

[0370] 17-34, 17-34': Connecting wire

[0371] 17-40: Second chip

[0372] 17-40A: Fifth surface

[0373] 17-40B: Sixth surface

[0374] 17-43: First conductive connection structure

[0375] 17-44: Second conductive connection structure

[0376] 17-45: First connecting wire

[0377] 17-46: Second connecting wire

[0378] 17-71: First bonding layer

[0379] 17-72: Second bonding layer

[0380] 17-80: light-transmitting middle layer

[0381] 17-90: Spacer layer

[0382] 20-000: Packaging structure

[0383] 20-206: Second semiconductor structure

[0384] 20-30: First Chip

[0385] 20-321A: Groove

[0386] 20-40: Second chip

[0387] 20-421, 20-422: Second high platform structure

[0388] 20-470A: Sixth opening

[0389] A20-1, A20-2: Block

[0390] d203, d204: distance

[0391] P2012, P2013, P2014, P2022, P2023, P2024: Columnar structure

[0392] W203, W204: Width

[0393] 21-000: Packaging structure

[0394] 21-10: Base material

[0395] 21-21, 21-41: First semiconductor structure

[0396] 21-22, 21-43: Second semiconductor structure

[0397] 21-23, 21-42: Active structures

[0398] 21-24: First contact layer

[0399] 21-25: Second contact layer

[0400] 21-30, 21-30A, 21-30B: First chip

[0401] 21-31, 21-31': first conductive structure

[0402] 21-32, 21-32': second conductive structure

[0403] 21-40: Second chip

[0404] 21-44, 21-45, 21-46: Contact

[0405] 21-50: Connection layer

[0406] 21-60: First connection structure

[0407] 21-90: Spacer layer

[0408] 23-000: Packaging structure

[0409] 23-10: Base material

[0410] 23-30: First Chip

[0411] 23-31: First conductive structure

[0412] 23-32: Second conductive structure

[0413] 23-35, 23-36, 23-45, 23-46: Conductive structure

[0414] 23-37, 23-38: Bonding pads

[0415] 23-40: Second chip

[0416] 23-43: First conductive connection structure

[0417] 23-44: Second conductive connection structure

[0418] 23-50, 23-60: Joint structure

[0419] 23-95: Bottom filling glue

[0420] CW: Connecting wire

[0421] 24-000: Photoelectric converter

[0422] 24-100: Light receiving unit

[0423] 24-110: Photoelectric epitaxial layer

[0424] 24-120: Transparent base

[0425] 24-130: Mirror layer

[0426] 24-141, 24-142, 24-221: Conductive layer

[0427] 24-200: Light emitting unit

[0428] 24-210: Epitaxial layer

[0429] 24-220: Metal layer

[0430] 24-300: Metal Core Printed Circuit Board

[0431] 24-410, 24-410(E), 24-410(D), 24-420, 24-420(E), 24-420(R): Joint structure

[0432] 24-610, 24-620: Conductive structure

[0433] 24-500: Bottom filling glue

[0434] 26-000A: Rectangular unit

[0435] 26-001A: First rectangular area

[0436] 26-002A: Second rectangular area

[0437] 26-003A, 26-003B, 26-003C: Circular area

[0438] 26-004A, 26-005A, 26-004B, 26-005B, 26-004C, 26-005C: Long strip area

[0439] L261A, L262A, L261B, L262B, L263B: side length

[0440] 26-000B, 26-000C: Hexagonal unit

[0441] 26-000B1, 26-000C1: Unit boundary

[0442] 26-001B, 26-001C: First hexagonal area

[0443] 26-002B: Second hexagonal area

[0444] 26-002C: Polygonal area

[0445] 26-A: Active Layer

[0446] 26-N: N-type semiconductor layer

[0447] 26-NP:N conductive connection pad

[0448] 26-P: P-type semiconductor layer

[0449] 26-PA: Passivation layer

[0450] 26-PA2: Protective layer

[0451] 26-PP:P conductive connection pad

[0452] 26-S: Grassroots

[0453] 26-U: Adhesive layer

[0454] L: Length

[0455] W: Width

[0456] D: Diameter

[0457] S: side length

[0458] 28-000: Chip Layout

[0459] 28-100(E), 28-100(R), 28-100(D): First connection structure

[0460] 28-200(E), 28-200(R), 28-200(D): Second connection structure

[0461] 28-110, 28-210: First platform structure

[0462] 28-120, 28-220: Second platform structure

[0463] A261, A262, A263: inside angle

[0464] Cs: Conductive connection structure

[0465] Gi: Spacing

[0466] Wpl: Line width

[0467] 30-000, 31-000, 32-000, 33-000, 34-000, 35-000: semiconductor laser

[0468] 30-100: Type I semiconductor layer

[0469] 30-110: Light-emitting hole

[0470] 30-200: Type II semiconductor layer

[0471] 30-300: Active structure

[0472] 30-400: Optical Resonance Cavity

[0473] 30-310: First quantum well layer

[0474] 30-310G: The first group of quantum well layers

[0475] 30-320: Second quantum well layer

[0476] 30-320G: The second group of quantum well layers

[0477] 30-330: The third quantum well layer

[0478] 30-330G: The third group of quantum well layers

[0479] 30-380: Spacer layer

[0480] 30-381: First spacer layer

[0481] 30-382: Second spacer layer

[0482] 30-390, 30-391, 30-392: Barrier layer structure

[0483] TJ: Tunnel Junction

[0484] 36-000: Semiconductor Laser

[0485] 36-090: Grassroots

[0486] 36-091: Protective layer

[0487] 36-100: Conductive substrate

[0488] 36-200: Semiconductor stacking layer

[0489] 36-210: Type I semiconductor layer

[0490] 36-220: Second type semiconductor layer

[0491] 36-230: Active Structure

[0492] 36-240: Columnar structure

[0493] 36-300: Contact electrode layer

[0494] 36-400: Metal bonding layer

[0495] 36-500: First conductive structure

[0496] 36-600: Insulation structure

[0497] 36-700: Anti-reflective structure

[0498] 36-800: Second conductive structure

[0499] 39-000: Semiconductor Laser

[0500] 39-090: Grassroots

[0501] 39-091: Protective layer

[0502] 39-092: Adhesive layer

[0503] 39-093: Temporary substrate

[0504] 39-100: Translucent substrate

[0505] 39-200: Semiconductor stacking layer

[0506] 39-201: Side

[0507] 39-210: Type I semiconductor layer

[0508] 39-220: Type II semiconductor layer

[0509] 39-230: Active Structure

[0510] 39-240: Columnar structure

[0511] 39-310: First electrode structure

[0512] 39-320: Second electrode structure

[0513] 39-330: Insulation layer

[0514] 39-331: Opening

[0515] 39-400: light-transmitting bonding layer

[0516] 39-500: first conductive structure

[0517] 39-600: Insulation structure

[0518] 39-800: Second conductive structure

[0519] 41-000:Semiconductor Laser

[0520] 41-100: Conductive substrate

[0521] 41-200: Semiconductor stacking layer

[0522] 41-210: Type I semiconductor layer

[0523] 41-220: Type II semiconductor layer

[0524] 41-230: Active Structure

[0525] 41-240: Columnar structure

[0526] 41-250: Protective layer

[0527] 41-300: Contact electrode layer

[0528] 41-400: Metal bonding layer

[0529] 41-500: first conductive structure

[0530] 41-600: Insulation structure

[0531] 41-700: Anti-reflective structure

[0532] 41-800: Second conductive structure

[0533] 42-000:Semiconductor Laser

[0534] 42-100: Conductive substrate

[0535] 42-200: Semiconductor stacking layer

[0536] 42-210: Type I semiconductor layer

[0537] 42-220: Type II semiconductor layer

[0538] 42-221: Aluminum oxide layer

[0539] 42-230: Active Structure

[0540] 42-240: Columnar structure

[0541] 42-250: Protective layer

[0542] 42-300: Contact electrode layer

[0543] 42-400: Metal bonding layer

[0544] 42-500: first conductive structure

[0545] 42-600: Insulation structure

[0546] 42-700: Anti-reflective structure

[0547] 42-800: Second conductive structure

[0548] 43-000, 44-000A, 44-000B, 45-000A, 45-000B, 46-000A, 46-000B, 47-000A, 47-000B, 47-000C, 47-000D, 47-000E, 48-000: Photoelectric device

[0549] 43-100: Light emitting unit

[0550] 43-110:Substrate

[0551] 43-120: Light-emitting components

[0552] 43-121: First conductive structure

[0553] 43-122: Second conductive structure

[0554] 43-123: Shared Conductive Structure

[0555] 43-124: Through-hole structure

[0556] 43-125: The third conductive structure

[0557] 43-130: Part

[0558] 43-140: Passivation layer

[0559] 43-200: Switch unit

[0560] 43-210: Hollow Area

[0561] 43-300: Light receiving element

[0562] 43-400: Driver chip

[0563] 43-410: Drive function block

[0564] 43-420: Modulation function block

[0565] 43-430: Signal processing functional block

[0566] 43-440: Light receiving functional block

[0567] 43-500: Optical layer

[0568] 43-600: Waveguide unit

[0569] L431: Light

[0570] L432: Reflected light

[0571] 49-000, 50-000A, 50-000B, 51-000: Photoelectric devices

[0572] 49-100: Light emitting unit

[0573] 49-110:Substrate

[0574] 49-120: Light-emitting components

[0575] 49-121: First conductive structure

[0576] 49-122: Second conductive structure

[0577] 49-123: Shared Conductive Structure

[0578] 49-300: Light receiving element

[0579] 49-400: Driver chip

[0580] 49-410: Drive function block

[0581] 49-420: Modulation function block

[0582] 49-430: Signal processing functional block

[0583] 49-440: Light receiving functional block

[0584] 49-500: Optical layer

[0585] 49-600: Waveguide unit

[0586] L491: Light

[0587] L492: Reflected light

[0588] 43-200A, 43-200B, 43-200C, 43-200D, 43-200E: Switching unit

[0589] 43-201: Waveguide structure

[0590] 43-202: Gate

[0591] 43-203: Reflector

[0592] 43-204:Liquid crystal molecules

[0593] 43-205: Sound wave generator

[0594] 43-206: Acoustic Deflector

[0595] 55-000: Semiconductor Laser

[0596] 55-100: Conductive substrate

[0597] 55-200: Semiconductor stacking layer

[0598] 55-201: Platform structure

[0599] 55-202: Groove

[0600] 55-203: Side

[0601] 55-210: Type I semiconductor layer

[0602] 55-210R: Ring electrode structure

[0603] 55-211: Current limiting layer

[0604] 55-220: Second type semiconductor layer

[0605] 55-230: Active Structure

[0606] 55-300: contact electrode layer

[0607] 55-400: Conductive layer

[0608] 55-500: Insulation layer

[0609] 55-900: Hard mask

[0610] 56-000, 57-000, 58-000, 59-000, 62-000: semiconductor laser

[0611] 56-100: Conductive substrate

[0612] 56-101: Platform surface

[0613] 56-102: Platform side

[0614] 56-103:Substrate surface

[0615] 56-200: Semiconductor stacking layer

[0616] 56-201: Platform structure

[0617] 56-202: Groove

[0618] 56-203: Side

[0619] 56-204: Platform structure

[0620] 56-210: Type I semiconductor layer

[0621] 56-210R: Ring electrode structure

[0622] 56-211: Current limiting layer

[0623] 56-220: Type II semiconductor layer

[0624] 56-230: Active Structure

[0625] 56-300: Contact electrode layer

[0626] 56-400: Conductive layer

[0627] 56-500: Insulation layer

[0628] 56-600: High reflective layer

[0629] 56-900: Hard mask

[0630] PD64: Optical Receiver

[0631] B64: Sunshade

[0632] S64: Test substrate

[0633] W64: Wire DETAILED DESCRIPTION

[0634] The following is a description of the concept of the present invention with reference to the accompanying drawings and exemplary embodiments. In the drawings or descriptions, similar or identical parts are represented by the same reference numerals. Furthermore, the drawings are drawn for ease of understanding, and the thickness and shape of each layer in the drawings are not the actual size or proportional relationship of the elements. It should be noted that the elements not shown in the drawings or described in the specification may be in a form known to a person of ordinary skill in the art to which the present invention belongs.

[0635] The following description of various embodiments of the present invention is made in conjunction with the accompanying drawings for the purpose of helping to clearly understand, so they should be regarded as exemplary descriptions. The phrases such as "in one embodiment" in this specification are not limited to specific or identical embodiments. Ordinary technicians in the technical field to which the invention belongs should recognize that various changes, combinations or adjustments can be made to the various embodiments of the present invention without departing from the scope and spirit of the present invention.

[0636] The terms "first", "second", "third", etc. used in this specification are intended to indicate and describe the features of each corresponding embodiment, and do not necessarily have any order, hierarchy, or before and after meaning (for example, spatial position, time sequence, step sequence, etc.).

[0637] The terms "upper", "lower", "left", "right", "front", "back", "lower", "higher", "top" or "bottom" used in this specification are used to describe the spatial distribution relative relationship of one element to another element (or one structure to another structure) in each figure. It is understood that if the structure shown in the figure is turned upside down, the element described on the "lower", "below", "lower" side will become the element on the "upper", "above", "higher" side.

[0638] Figure 1 is a schematic cross-sectional view of a packaging structure of an optoelectronic component 1. According to one embodiment, the optoelectronic component 1 includes an integrated self-mixing interferometry (SMI) sensing unit (eg Figure 2-1A and Figure 2-1B The optoelectronic unit 2 shown), the carrier 1300 and the waveguide element (eg Figure 1 The SMI sensing unit includes a transmitter structure and a receiver structure. In one or more embodiments, the SMI sensing unit may also include an optical element 1d to focus or collimate the light from the transmitter structure to a waveguide element (such as but not limited to a coupling optical fiber or a light-guiding element). In one or more embodiments, the optoelectronic component 1 may function similarly to a silicon photonic element to transmit and receive optical signals.

[0639] Figure 2-1A FIG. 2 is a schematic cross-sectional view of a packaging structure of a photoelectric unit 2 according to an embodiment. The photoelectric unit 2 can be used as a self-mixing interferometry (SMI) sensing unit and can be applied to Figure 1 The optoelectronic component 1 is shown.

[0640] Figure 2-1B FIG. 2 is a cross-sectional schematic diagram showing a packaging structure of a photovoltaic unit 2 according to an embodiment. Figure 2-1AThe photovoltaic unit 2 is shown to be adhered to a transparent substrate 1100 .

[0641] Figure 2-1C FIG. 1 is a cross-sectional view of a packaging structure of a light emitting sensor package 2C according to an embodiment, which includes a plurality of components such as Figure 2-1A The photoelectric unit 2 shown; and the light-emitting sensing package 2C can be used as a self-mixing interference sensing unit and can be applied to Figure 1 The optoelectronic component 1 is shown.

[0642] Figure 2-1D FIG. 2 is a schematic cross-sectional view of a packaging structure of a light emitting sensor package 2D according to an embodiment, which includes a plurality of components such as Figure 2-1A The photoelectric unit 2 shown; and the light-emitting sensing package 2D can be used as a self-mixing interference sensing unit and can be applied to Figure 1 The optoelectronic component 1 is shown.

[0643] according to Figure 2-1A In the embodiment shown, the optoelectronic unit 2 includes a light emitting structure and a light receiving structure, and the optoelectronic unit 2 is a stacked structure 2000 including a semiconductor epitaxial structure, a conductive structure, and an insulating structure. The stacked structure 2000 has an upper surface 2000T and a lower surface 2000B opposite to the upper surface 2000T. Figure 2-1A In the illustrated embodiment, the stacked structure 2000 of the photovoltaic unit 2 may be formed by epitaxial growth.

[0644] exist Figure 2-1A In the illustrated embodiment, the stacked structure 2000 includes a light-emitting epitaxial structure 2100, which corresponds to the light-emitting structure of the optoelectronic unit 2. In this embodiment, the light-emitting epitaxial structure 2100 may be a vertical-cavity surface-emitting laser (VCSEL), which may be a stacked epitaxial structure including an upper distributed Bragg reflector (hereinafter referred to as DBR) 2100U, a lower DBR 2100L, and an active structure 2100A located between the upper DBR 2100U and the lower DBR 2100L.

[0645] exist Figure 2-1AIn the illustrated embodiment, the conductive structure 2100P contacts the upper DBR 2100U at the upper surface 2100T / 2100UT of the upper DBR 2100U, and then the conductive structure 2100P continues to extend and covers a portion of the lower surface 2000B through the through-hole structure 2100V formed inside the stacked structure 2000. In some embodiments, a ring-shaped contact metal (not shown) is further included between the conductive structure 2100P and the upper surface 2100UT of the upper DBR 2100U, wherein the ring-shaped contact metal forms an ohmic contact with the upper DBR 2100U at the upper surface 2100UT of the upper DBR 2100U. In this embodiment, the insulating structure 2100VI is formed between the conductive structure 2100P and the stacked structure 2000, and the insulating structure 2100VI is used to electrically insulate the conductive structure 2100P from the upper DBR 2100U, and the active structure 2100A from the lower DBR 2100L.

[0646] exist Figure 2-1A In the embodiment shown, the upper DBR 2100U includes a P-type semiconductor structure, and the lower DBR 2100L includes an N-type semiconductor layer structure. In this embodiment, the conductive structure 2100P serves as a P-electrode of the light-emitting epitaxial structure 2100.

[0647] exist Figure 2-1A In the illustrated embodiment, the light receiving structure 2200 is a part of the lower DBR 2100L integrally formed as the light emitting epitaxial structure 2100 (eg, VCSEL). In other words, in this embodiment, the lower DBR 2100L includes the DBR structure 2100L1, the light receiving structure 2200, and the DBR structure 2100L2 stacked in sequence.

[0648] exist Figure 2-1A In the illustrated embodiment, the conductive structure 2200N contacts the light receiving structure 2200 at the lower surface 2200B of the light receiving structure 2200. In one embodiment, the light receiving structure 2200 may be a photodiode, such as an avalanche photodiode (APD) or a PIN photodiode. Figure 2-1A In the illustrated embodiment, the conductive structure 2200N serves as an N-electrode of the light receiving structure 2200 .

[0649] exist Figure 2-1AIn the illustrated embodiment, the conductive structure 2400 contacts the DBR structure 2100L1 at the upper surface 2100LT of the lower DBR 2100L, and then the conductive structure 2400 continues to extend to cover a portion of the lower surface 2000B through the through-hole structure 2000V formed inside the stacked structure 2000. In some embodiments, a contact layer (not shown) is further included between the conductive structure 2400 and the upper surface 2100LT of the lower DBR 2100L, wherein the contact layer forms an ohmic contact with the lower DBR 2100L at the upper surface 2100LT of the lower DBR 2100L. Figure 2-1A In the illustrated embodiment, the insulating structure 2000VI is located within the through-hole structure 2000V and extends to cover a portion of the lower surface 2000B, and the insulating structure 2000VI is used to electrically insulate the conductive structure 2400 from the lower DBR 2100L. Figure 2-1A In the illustrated embodiment, the conductive structure 2400 contacts the DBR structure 2100L1 of the N-type semiconductor, and the lower DBR 2100L of the N-type semiconductor is connected to the upper portion of the light receiving structure 2200. Therefore, the conductive structure 2400 is a common electrode of the light emitting epitaxial structure 2100 and the light receiving structure 2200. In this embodiment, the conductive structure 2400 is both an N-electrode of the light emitting epitaxial structure 2100 and a P-electrode of the light receiving structure 2200.

[0650] In one embodiment, see Figure 2-1A The light-emitting epitaxial structure 2100 may further include a current limiting layer 2125 located between the upper DBR 2100U and the active structure 2100A, and the current limiting layer 2125 includes a current limiting region 2125B and a current conduction region 2125A, and the current conduction region 2125A is surrounded and defined by the current limiting region 2125B. The active structure 2100A may be a single-layer or multi-layer structure, for example, the active structure 2100A includes at least one quantum well layer. In addition, the active structure 2100A may include at least one current limiting layer and / or at least one tunnel junction structure.

[0651] In one embodiment, see Figure 2-1A and Figure 2-1B , the transparent base layer 1100 can be adhered to the upper surface 2000T through the adhesive layer 1200, wherein the transparent base layer 1100 and the adhesive layer 1200 are transparent to the light emitted from the active structure 2100A of the light-emitting epitaxial structure 2100. In this embodiment, the electrode pads 2400e, 2200e, and 2100e are respectively formed on the lower surface 2000B, and the electrode pad 2400e contacts the conductive structure 2400 to be bonded to the second corresponding pad 1320 (such as Figure 2-1BAs shown in FIG. 1 , the electrode pad 2200e contacts the conductive structure 2200N to be bonded to the first corresponding pad 1310 of the carrier 1300, and the electrode pad 2100e contacts the conductive structure 2100P to be bonded to the third corresponding pad 1330 of the carrier 1300. Figure 2-1A In the illustrated embodiment, the optoelectronic unit 2 is driven to emit the coherent light Lo to the first object, and then the reflected light Lr from the first object can be detected by the light receiving structure 2200 of the optoelectronic unit 2 .

[0652] In one or more embodiments, see Figure 2-1B As an example, the photoelectric unit 2 can be coupled to the controller via the carrier 1300. Then, the light emitting structure of the photoelectric unit 2 and the light receiving structure of the photoelectric unit 2 can be enabled to operate separately by the controller through the conductive structure 2100P or the conductive structure 2200N corresponding to the individual structure (light emitting structure or light receiving structure) in combination with the common electrode (conductive structure 2400) of the emitting device and the light receiving structure. Alternatively, the light emitting structure of the photoelectric unit 2 and the light receiving structure of the photoelectric unit 2 can also be enabled to operate together by the controller through the common electrode (conductive structure 2400) of the emitting device and the light receiving structure in combination with the conductive structure 2100P of the light emitting structure and the conductive structure 2200N of the light receiving structure.

[0653] Figure 2-1C FIG. 1 is a cross-sectional view of a packaging structure of a light emitting sensor package 2C according to an embodiment, which includes a plurality of components such as Figure 2-1A The photoelectric units 2 (photoelectric unit 2-1 and photoelectric unit 2-2) shown in the figure and the light-emitting sensing package 2C can be used as a self-mixing interference sensing device. In one or more embodiments, the plurality of photoelectric units 2 of the light-emitting sensing package 2C can be arranged in an array.

[0654] exist Figure 2-1C In the illustrated embodiment, each stacking structure of the photovoltaic unit 2-1 and the photovoltaic unit 2-2 has the same or similar structure as the photovoltaic unit 2. Figure 2-1C In the embodiment shown, the conductive structure 2100P1 of the optoelectronic unit 2-1 can be connected through an interconnection structure (not shown in FIG. Figure 2-1C ) is connected to the conductive structure 2100P2 of the photovoltaic unit 2-2. In other words, in this embodiment, the conductive structures 2100P1 and 2100P2 can be connected to form a common electrode (conductive structure 2100P) and serve as a common electrode of the photovoltaic units 2-1 and 2-2. Figure 2-1C In the illustrated embodiment, the common electrode (conductive structure 2100P) is a common P electrode of the optoelectronic unit of the light emitting sensing package 2C.

[0655] exist Figure 2-1CIn the illustrated embodiment, the electrode pad 2200e1 of the conductive structure 2200N1 may be provided via a carrier 1300 (not shown). Figure 2-1C ) is connected to the electrode pad 2200e2 of the conductive structure 2200N2; in other words, in this embodiment, the common pad (first corresponding pad 1310) of the carrier 1300 can be used as a common N electrode electrically connected to the light receiving structure of the light emitting sensing package 2C. Figure 2-1C In the illustrated embodiment, in addition, the electrode pad 2200e3 of the conductive structure 2200N3 can be connected to the electrode pads 2200e1 and 2200e2 via the common pad (the first corresponding pad 1310 ) of the carrier 1300 .

[0656] exist Figure 2-1C In the illustrated embodiment, the conductive structure 2401 of the photovoltaic unit 2-1 is separated from the conductive structure 2402 of the photovoltaic unit 2-2; in other words, in this embodiment, the conductive structure 2401 and the conductive structure 2402 are substantially electrically separated from each other. Therefore, each of the photovoltaic units 2-1 and 2-2 can be driven / controlled individually. Figure 2-1C In the illustrated embodiment, the photoelectric unit 2-1 is driven to emit the coherent light Lo1 to the first object, and then the reflected light Lr1 from the first object can be detected by the light receiving structure of the photoelectric unit 2-1; the photoelectric unit 2-2 is driven to emit the coherent light Lo2 to the second object, and then the reflected light Lr2 from the second object can be detected by the light receiving structure of the photoelectric unit 2-2.

[0657] Specifically, in some embodiments, since the laser light is reflected from an object, it contains information about the state of the object (such as the distance relative to the photoelectric unit, rotation speed, movement speed, acceleration, etc.). Therefore, the aforementioned information can be obtained by comparing the phase changes between different laser lights and performing conversion calculations.

[0658] Figure 2-1D FIG. 2 is a schematic cross-sectional view of a packaging structure of a light emitting sensor package 2D according to an embodiment, which includes a plurality of components such as Figure 2-1A The photovoltaic unit 2 shown (for example, photovoltaic units 2-1 and 2-2, as shown in FIG. Figure 2-1C and the light-emitting sensing package 2D can be used as a self-mixing interference sensing device. Figure 2-1D Each stacked structure of the photovoltaic unit 2 of the embodiment shown has the same Figure 1 The stacking structure of the photovoltaic units 2 of the embodiment shown in A is the same or similar structure.

[0659] See also Figure 2-1D and Figure 2-1CThe structure of the light-emitting sensing package 2D is similar to that of the light-emitting sensing package 2C. The conductive structures 2100P1 and 2100P2 can be connected to form a common electrode (conductive structure 2100P) and serve as a common electrode (e.g., a common P electrode) of the photoelectric unit 2; and the conductive structures 2401 and 2402 are substantially electrically separated from each other. Therefore, Figure 2-1D Each of the photovoltaic units 2 shown can be driven / controlled individually.

[0660] Specifically, in Figure 2-1D In the illustrated embodiment, the conductive structure 2200N1 and the conductive structure 2200N2 are respectively covered by an insulating structure, and the conductive structure 2200N1 and the conductive structure 2200N2 are connected to each other via an interconnection structure (not shown in FIG. Figure 2-1D ) is connected to the conductive structure 2200N3. Therefore, the conductive structure 2200N3 can be used as a common conductive structure, which is connected to the electrode pad 2200e3 that is electrically connected to each of the light receiving structures 2200 as a common electrode. In other words, Figure 2-1D In the illustrated embodiment, the electrode pad 2200e3 may serve as a common N-electrode electrically connected to the light receiving structure 2200 of the light emitting sensing package 2D.

[0661] See also Figure 2-1D For example, in one or more embodiments, the transparent base layer 1100 may have an integrated optical element 1101. In one or more embodiments, the integrated optical element 1101 may include a plurality of optical elements (e.g., microlenses 1101A and 1101B), and the microlens 1101A corresponds to a photoelectric unit 2-1 under the microlens 1101A, and the microlens 1101B corresponds to the photoelectric unit 2-2 under the microlens 1101B. In one or more embodiments, the center position (or optical axis) of the microlens 1101A is misaligned with the center position of the current conduction region in the photoelectric unit 2-1 thereunder, or / and the center position (or optical axis) of the microlens 1101B is misaligned with the center position of the current conduction region in the photoelectric unit 2-2 thereunder, but the present invention is not limited thereto.

[0662] In some embodiments, the light emitted by the semiconductor laser can be offset by displacing the optical element with the current conduction area of ​​each semiconductor laser (i.e., the light outlet corresponding to the semiconductor laser), thereby changing the field of illumination (FOI) of the photoelectric unit. In some embodiments, the directions and displacements of the displacing configurations of the optical element and the current conduction area of ​​each semiconductor laser can be different, so that when the illumination field of the photoelectric unit is changed, the uniformity in the illumination field can be maintained. In some embodiments, the directions and displacements of the displacing configurations of the optical element and the current conduction area of ​​each semiconductor laser can be different, and the directions and displacements of the displacing configurations are symmetrically distributed as a whole.

[0663] Figure 2-2A FIG. 2 is a schematic cross-sectional view of a packaging structure of a photoelectric unit 2' according to an embodiment. The photoelectric unit 2' can be used as a self-mixing interference (SMI) sensing unit and can be applied to Figure 1 The optoelectronic component 1 is shown.

[0664] See also Figure 2-2A and Figure 2-1A , the photovoltaic unit 2' has a similar structure to the photovoltaic unit 2. Figure 2-2A In the illustrated embodiment, the optoelectronic unit 2 ′ includes a light-emitting epitaxial structure 2100 ′ and a light-receiving structure 2200 ′, wherein the light-receiving structure 2200 ′ is located below the light-emitting epitaxial structure 2100 ′.

[0665] Specifically, Figure 2-1A The embodiments shown are different ( Figure 2-1A In the embodiment, the light receiving structure 2200 is integrally formed as a part of the lower DBR 2100L of the light emitting epitaxial structure 2100. Figure 2-2A In the illustrated embodiment, the photoelectric unit 2' further includes a bonding layer 2500 located between the light-emitting epitaxial structure 2100' and the light-receiving structure 2200', and the upper surface of the light-receiving structure 2200' is mostly adhered to the lower surface of the light-emitting epitaxial structure 2100' through the bonding layer 2500, wherein the bonding layer 2500 is transparent to the coherent light Lo' emitted by the active structure 2100A' of the self-luminous epitaxial structure 2100'.

[0666] exist Figure 2-2A In the illustrated embodiment, the light emitting epitaxial structure 2100' may be a VCSEL, which may be a stacked epitaxial structure including an upper DBR 2100U', a lower DBR 2100L', and an active structure 2100A' located between the upper DBR 2100U' and the lower DBR 2100L'. Figure 2-2AIn the embodiment shown, the upper DBR 2100U' comprises a P-type semiconductor structure, and the lower DBR 2100L' comprises an N-type semiconductor layer structure. Then, the conductive structure 2100P (eg Figure 2-2A ) is a P electrode serving as the light-emitting epitaxial structure 2100'.

[0667] exist Figure 2-2A In the embodiment shown, the next layer 2500 is conductive so that the conductive structures (such as Figure 2-2A The conductive structure 2400 is electrically connected to the lower DBR 2100L' of the light-emitting epitaxial structure 2100' and the light-receiving structure 2200'. Therefore, the conductive structure 2400 is a common electrode of the light-emitting epitaxial structure 2100' and the light-receiving structure 2200'. Figure 2-2A In the illustrated embodiment, the conductive structure 2400 is simultaneously an N-electrode of the light-emitting epitaxial structure 2100 ′ and a P-electrode of the light-receiving structure 2200 ′.

[0668] exist Figure 2-2A In the illustrated embodiment, the light receiving structure 2200' further includes a DBR structure 2210' and a conductive structure 2200N, wherein the conductive structure 2200N contacts the light receiving structure 2200' on the lower surface of the light receiving structure 2200'. In some embodiments, a contact layer (not shown) is further included between the conductive structure 2200N and the lower surface of the light receiving structure 2200', wherein the conductive structure 2200N forms an ohmic contact with the light receiving structure 2200' through the contact layer. In one embodiment, the light receiving structure 2200' may be a photodiode, such as an avalanche photodiode (APD) or a PIN photodiode. Figure 2-2A In the illustrated embodiment, the conductive structure 2200N serves as an N-electrode of the light receiving structure 2200'. Figure 2-2A In the illustrated embodiment, the light receiving structure 2200 ′ may be formed by a wafer fusion process.

[0669] Figure 2-2B FIG. 2 is a schematic cross-sectional view of a packaging structure of a light emitting sensing package 2D′ according to an embodiment, which includes a plurality of components such as Figure 2-2A The photoelectric unit 2' (photoelectric unit 2-1' and photoelectric unit 2-2') shown in FIG. 2 ; and the light-emitting sensing package 2D' can be used as a self-mixing interference sensing unit and can be applied to Figure 1 The optoelectronic component 1 is shown. In one or more embodiments, the plurality of optoelectronic units 2' of the light emitting sensing package 2D' may be arranged in an array.

[0670] exist Figure 2-2BIn the illustrated embodiment, the conductive structure 2100P1 of the optoelectronic unit 2-1' can be connected to the conductive structure 2100P2 of the optoelectronic unit 2-2' through an interconnect structure (not shown in Figure 2-2B ). In other words, in this embodiment, the conductive structures 2100P1 and 2100P2 can be connected to form a common electrode (conductive structure 2100P) (as shown in Figure 2-2B ) to serve as the common electrode of the optoelectronic units 2-1' and 2-2'. For example, in the embodiment shown in Figure 2-2B , the common electrode is the common P electrode of the optoelectronic units of the light-emitting and sensing package 2D'.

[0671] In Figure 2-2B the illustrated embodiment, the conductive structure 2401 of the optoelectronic unit 2-1' and the conductive structure 2402 of the optoelectronic unit 2-2' are separated; in other words, in this embodiment, the conductive structure 2401 and the conductive structure 2402 are substantially electrically separated from each other. Therefore, each of the optoelectronic units 2-1' and 2-2' can be individually driven / controlled.

[0672] In Figure 2-2B the illustrated embodiment, the conductive structure 2200N1 and the conductive structure 2200N2 can be connected to the conductive structure 2200N3 through an internal interconnect structure (not shown in Figure 2-2B ). Therefore, the conductive structure 2200N3 can serve as a common conductive structure, which is connected as a common electrode to the electrode pads 2200e3 of each of the light-receiving structures 2200'. In other words, in the embodiment shown in Figure 2-2B , the electrode pads 2200e3 can serve as the common N electrode for electrically connecting the light-receiving structures 2200' of the light-emitting and sensing package 2D'.

[0673] Figure 2-3 is a schematic cross-sectional view showing the packaging structure of an optoelectronic unit 3A according to an embodiment. Please refer to Figure 2-3 As an example, in one or more embodiments, the optoelectronic unit 3A further includes a housing 1400 covering the light-emitting and sensing package 2D'. It should be noted that the light-emitting and sensing package 2D' can be replaced by any one of the foregoing light-emitting and sensing packages, but the present invention is not limited thereto.

[0674] In one or more embodiments, taking the embodiment shown in Figure 2-3 as an example, the housing 1400 can have an integrated optical element 1401.

[0675] In one or more embodiments, taking the embodiment shown in Figure 2-3 as an example, the housing 1400 can have a plurality of optical elements 1401A and 1401B. In one or more embodiments, taking the embodiment shown in Figure 2-3Taking the embodiment shown as an example, the optical elements 1401A and 1401B may have the same or different optical functions. In one embodiment, the optical elements 1401A and 1401B may be used to project light. In another embodiment, the optical elements 1401A and 1401B may be used to focus light. In other embodiments, the optical element 1401A may be used to project light, while the optical element 1401B may be used to focus light. In one embodiment, the optical elements 1401A and 1401B may be used to project light or focus light in different directions, or the optical elements 1401A and 1401B may be used to project light at different angles, thereby expanding the field of view of the optoelectronic unit 3A.

[0676] In one or more embodiments, Figure 2-3 Taking the illustrated embodiment as an example, the carrier 1300 may be a ceramic substrate, a printed circuit board, etc.

[0677] In some embodiments, since there may be a containing space between the housing 1400 and the transparent substrate 1100, it may be filled with normal air, or may be filled with an inert gas, nitrogen, or maintained in a vacuum, to provide a medium environment with different refractive indices. In other embodiments, an optical element with a concave lens structure may also be formed on the transparent substrate 1100 and then covered with the housing 1400, which may also provide focusing and / or collimation functions of the optical element.

[0678] In some embodiments, Figure 1 , Figure 2-1D or Figure 2-3 Taking the embodiment shown as an example, the aforementioned optical element may include a diffraction optical element (DOE) structure, a micro lens array (Micro Lens Array) structure, a metasurface structure or a metalens structure or a combination of the aforementioned various optical element structures. Among them, the metasurface structure is a nanostructure with multiple periodic arrangements.

[0679] In one embodiment, Figure 3ETaking the embodiment shown as an example, the optoelectronic unit 3 includes a base layer 31, a functional area 311 disposed on a first side of the base layer 31, a semiconductor element 32 disposed on a second side of the base layer 31 (the second side is relative to the first side) and corresponding to the functional area 311, and a cladding layer 33 surrounding the semiconductor element 32. The semiconductor element 32 has a first electrode and a second electrode. Part of the first electrode and part of the second electrode are exposed outside the cladding layer 33. In some embodiments, the electrode of the semiconductor element 32 is coplanar with the surrounding cladding layer 33; in some embodiments, at least one of the first electrode and the second electrode of the semiconductor element 32 is coplanar with the cladding layer 33. The functional area 311 may include, but is not limited to, an optical structure of nanometer or micrometer dimensions, such as a metasurface structure, a diffraction optical element (DOE) structure, or a micro lens array structure. The semiconductor element 32 may be, but is not limited to, a flip-chip vertical resonant cavity laser chip. In one or more embodiments, the photoelectric unit 3 may further include an adhesive layer at the interface between the base layer 31 and the light-emitting surface of the semiconductor element 32. In some embodiments, the cladding layer 33 may be opaque, so as to prevent the lateral light emission of the semiconductor element 32 from causing noise. In some embodiments, the range of the functional area 311 is smaller than the photoelectric unit 3 and larger than the semiconductor element 32. In some embodiments, the width of the first side of the base layer 31 is smaller than the width of the cladding layer 33. In some embodiments, the width of the first side of the base layer 31 is smaller than the width of the semiconductor element 32.

[0680] FIG. 3A to FIG. 3D The invention is a diagram showing a method of manufacturing a Figure 3E The schematic diagram of the process of the photovoltaic unit 3 is shown. Figure 3E FIG. 4 is a cross-sectional schematic diagram of a photovoltaic unit 3 according to one or more embodiments. Figure 3A The process steps of manufacturing an optoelectronic wafer 300 are shown. The optoelectronic wafer 300 includes a substrate 31 and a plurality of functional areas 311 located on a first side of the substrate 31. In one or more embodiments, the optoelectronic wafer 300 further includes a plurality of alignment marks 312. The substrate 31 may be a light-transmitting substrate, such as a glass or sapphire substrate. Figure 3B The manufacturing process steps of mounting a plurality of semiconductor devices 32 on the second side of the base layer 31 by bonding materials are shown. The second side is opposite to the first side of the base layer 31 . Figure 3CThe process steps of forming a coating layer 33 around the plurality of semiconductor elements 32 on the second side of the base layer 31 (the same side as the plurality of semiconductor elements 32) are shown. The coating layer 33 can be formed on the base layer 31 by, but not limited to, molding, spraying, or spin coating processes; for example, the coating layer 33 can be a resin material, but is not limited thereto. In the present embodiment, the number of functional areas 311 is the same as the number of semiconductor elements 32. In one or more embodiments, the electrodes of the semiconductor elements 32 can be buried in the coating layer 33 during the molding, spraying, or spin coating process. Then, an additional grinding or polishing process is required to remove part of the coating layer 33 until all electrodes of the semiconductor elements 32 are exposed. Specifically, in some embodiments, the coating layer 33 can be formed on the base layer 31 and be at the same height as the electrodes of the semiconductor element 32 to expose all the electrodes of the semiconductor element 32; in other embodiments, the coating layer 33 can be formed on the base layer 31 and be higher than the electrodes of the semiconductor element 32, and then a portion of the coating layer 33 is removed by a physical or chemical polishing process until all the electrodes of the semiconductor element 32 are exposed. In one or more embodiments, the exposed electrode surface and the polished coating layer 33 can be coplanar. Figure 3D The cutting process of cutting the optoelectronic wafer 300 into a plurality of single dies as the optoelectronic units 3 is shown. In one or more embodiments, the cutting process may include but is not limited to laser cutting, wheel cutting or a combination thereof. Figure 3D As shown, in this embodiment, a cutting machine 309 is used to perform the aforementioned cutting process.

[0681] In some embodiments, the thickness of the base layer 31 is between 200 μm and 1 mm, and the refractive index is between 1.4 and 1.6; the thickness of the semiconductor element 32 is between 50 μm and 200 μm, and the refractive index is 3.5; and the thickness of the nano- or micro-dimensional optical structure of the functional area 311 on the base layer 31 is between 10 nm and 1000 nm, and the refractive index is between 2.0 and 3.5.

[0682] FIG. 4A to FIG. 4C As another embodiment, a production process of a panel-type chip scale package (CSP) is shown for manufacturing a Figure 4D The schematic diagram of the process of the photovoltaic unit 4 is shown. Figure 4AThe process steps of mounting a plurality of semiconductor elements 32 on a first side of a base layer 31 by a bonding material are shown, and then forming a coating layer 33 around the semiconductor elements 32 on the same side of the base layer 31. In one or more embodiments, a plurality of alignment marks 312 may be formed on a second side of the base layer 31. In one or more embodiments, the electrodes of the semiconductor elements 32 may be embedded in the coating layer 33 during a molding, spraying, or spin coating process. Then, an additional grinding or polishing process is required to remove a portion of the coating layer 33 until all electrodes of the semiconductor elements 32 are exposed. In one or more embodiments, the exposed electrode surface and the polished coating layer 33 may be coplanar.

[0683] Figure 4B The process steps of arranging and bonding a plurality of optical elements 34 (which are properly aligned with the plurality of semiconductor elements 32 in a one-to-one manner) to the second side of the substrate 31 by bonding material are shown. The second side is opposite to the first side of the substrate 31. The optical element 34 includes a light-transmitting substrate 341 and a functional area 342. In this embodiment, the functional area 342 of the optical element 34 is as shown in FIG. Figure 4B In one or more embodiments, the functional area 342 is located between the base layer 31 and the light-transmitting substrate 341. The functional area 342 may include, but is not limited to, a nano- or micro-dimensional optical structure, such as a metasurface structure, a diffraction optical element (DOE) structure, or a micro lens array structure. Figure 4C The dicing process of dicing an optical wafer into a plurality of single dies serving as optoelectronic units 4 is illustrated. Figure 4D A schematic diagram of the photovoltaic unit 4 is shown.

[0684] In one or more embodiments, FIG. 5A to FIG. 5C FIG. 1 is a diagram illustrating a manufacturing process of a panel type chip size package according to one or more embodiments. Figure 5D The schematic diagram of the process of the photovoltaic unit 5 is shown. Figure 5A The process steps of mounting a plurality of semiconductor elements 32 on a first side of a base layer 31 by bonding materials are shown, and then a covering layer 33 surrounding the semiconductor elements 32 is formed on the same side of the base layer 31. In one or more embodiments, the plurality of semiconductor elements 32 may include two or more types of semiconductor elements 32 (for example, FIG. 5A to FIG. 5DIn one or more embodiments, a plurality of alignment marks 312 may be formed on the second side of the base layer 31. In one or more embodiments, the electrodes of the semiconductor element 32 may be buried in the coating layer 33 during a molding, spraying, or spin coating process. Then, an additional grinding or polishing process is required to remove a portion of the coating layer 33 until all electrodes of the semiconductor element 32 are exposed. In one or more embodiments, the exposed electrode surface and the polished coating layer 33 may be coplanar.

[0685] Figure 5B The process steps of arranging and bonding a plurality of optical elements 34 (which are properly aligned with the plurality of semiconductor elements 32 in a one-to-one manner) to the second side of the substrate 31 by a bonding material are shown. The second side is opposite to the first side of the substrate 31. In one or more embodiments, the plurality of optical elements 34 may include two or more optical elements (for example, FIG. 5B to FIG. 5D The first optical element 34a and the second optical element 34b may be different types of optical elements), but the present invention is not limited thereto. In this embodiment, the light-transmitting substrate 341 is located between the base layer 31 and the functional area 342, but the present invention is not limited thereto. Figure 5B In one or more embodiments, the functional area 342 (342a / 342b) is located between the base layer 31 and the light-transmitting substrate 341 (341a / 341b). Figure 5C The dicing process of dicing the optical wafer into a plurality of single dies as the optoelectronic units 5 is shown. Each optoelectronic unit 5 may include two or more optical elements 34 and two or more semiconductor elements 32, but is not limited thereto. Figure 5D A schematic diagram of a photovoltaic unit 5 including two optical elements 34 and two semiconductor elements 32 is shown.

[0686] FIG. 6A to FIG. 6C As another embodiment, a manufacturing process of a panel type chip size package is shown according to one or more embodiments. Fig.6D The schematic diagram of the process of the photovoltaic unit 6 is shown. Fig. 6A The process steps of mounting a plurality of semiconductor elements 32 on a first side of a base layer 31 by bonding materials are shown, and then a covering layer 33 surrounding the semiconductor elements 32 is formed on the same side of the base layer 31. In one or more embodiments, the plurality of semiconductor elements 32 may include two or more types of semiconductor elements 32 (for example, FIG. 6A to FIG. 6DIn one or more embodiments, a plurality of alignment marks 312 may be formed on the second side of the base layer 31. In one or more embodiments, the electrodes of the semiconductor element 32 may be buried in the coating layer 33 during a molding, spraying, or spin coating process. Then, an additional grinding or polishing process is required to remove a portion of the coating layer 33 until all electrodes of the semiconductor element 32 are exposed. In one or more embodiments, the exposed electrode surface and the polished coating layer 33 may be coplanar. Figure 6B The step of setting the optical elements is shown, and the plurality of optical elements 34 are set and bonded to the second side of the base layer 31 by the bonding material 35. In one or more embodiments, the plurality of optical elements 34 may include two or more optical elements (for example, FIG. 6B to FIG. 6D The first optical element 34a and the second optical element 34b may be different types of optical elements), but are not limited thereto. In this embodiment, the functional area 342 of the optical element 34 faces the base layer 31. The second side is the opposite side of the first side of the base layer 31. The optical element 34 includes a light-transmitting substrate 341 and a functional area 342. The functional area 342 may include, but is not limited to, an optical structure of nanometer or micrometer dimensions, such as a metasurface structure, a diffraction optical element (DOE) structure, or a microlens array structure. In some embodiments, the optical element 34 may first be provided with a functional area 342 on a light-transmitting substrate 341, and then the optical element 34 may be provided on the base layer 31 using a bonding material 35; in other embodiments, the functional area 342 may be provided on the base layer 31 first, and then the light-transmitting substrate 341 may be provided on the base layer 31 using a bonding material 35. Figure 6C The dicing process of dicing the optical wafer into a plurality of individual dies serving as the optoelectronic units 6 is illustrated. Fig.6D A schematic diagram of a photovoltaic unit 6 is shown. In some embodiments, Fig.6D The two or more photovoltaic units 6 shown can be connected together to form a single photovoltaic unit (with Figure 5D Similar to the optoelectronic unit 5 shown, a single optoelectronic unit has two or more optical elements 34 and two or more semiconductor elements 32, wherein the two or more optical elements 34 can be the same type or different types of optical elements, and the two or more semiconductor elements 32 can be the same or different semiconductor elements).

[0687] In some embodiments, the foregoing FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D, FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be Figure 2-1A to Figure 2-3 The luminescent sensing package or Figures 7 to 13 A combination of one or more semiconductor light emitting elements.

[0688] Figure 7 FIG. 2 is a cross-sectional view of a semiconductor light emitting device 7000 according to an embodiment. FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 7000, such as Figure 7 Referring to this embodiment, Figure 7 As shown, the semiconductor light emitting element 7000 includes a transparent base layer 7001, a bonding layer 7002, a laser unit 7003 and a plurality of first channels 7034. The transparent base layer 7001 includes a conductive layer 7010. For example, the transparent base layer 7001 includes sapphire, glass or silicon carbide (SiC). In some embodiments, the transparent base layer 7001 is an optical element, and can also produce a specific optical effect after patterning; for example, the optical element can enable the light emitting device to produce a patterned light source, and the light source is a point light source, a surface light source or a multiple pattern light source with a predetermined illumination area (FOI). The conductive layer 7010 includes a transparent conductive film (Transparent Conductive Oxide) or a metal. The transparent conductive film can be indium tin oxide (ITO) or indium zinc oxide (IZO). In this embodiment, the conductive layer 7010 is disposed between the transparent base layer 7001 and the bonding layer 7002.

[0689] One side of the bonding layer 7002 is connected to the conductive layer 7010 of the transparent base layer 7001, and the other side thereof is connected to the light-emitting side 7003S of the laser unit 7003. For example, the bonding layer 7002 may be benzocyclobutene (BCB), silicon dioxide or a transparent conductive film.

[0690] The laser unit 7003 includes a forward conductive structure 7030, a first-type semiconductor layer 7031, an active layer 7033, a second-type semiconductor layer 7035, an insulating layer 7036, and a back conductive structure 7032. The back conductive structure 7032 includes conductive electrodes 7032C and 7032D separated from each other. Here, the first type and the second type refer to semiconductor structures of different electrical properties. If the semiconductor structure has holes as the majority carriers, it is a p-type semiconductor, and if the semiconductor structure has electrons as the majority carriers, it is an n-type semiconductor. For example, the first-type semiconductor layer 7031 is an N-type semiconductor, and the second-type semiconductor layer 7035 is a P-type semiconductor, and vice versa. The active layer 7033 is located between the first-type semiconductor layer 7031 and the second-type semiconductor layer 7035, and includes a pn interface (p-n junction) to generate a depletion region for electron holes to recombine and emit light. In some embodiments, the active layer 7033 is composed of a multiple quantum well (MQW), so as to have better light-emitting efficiency than the pn interface, but the invention is not limited thereto. In one embodiment, the materials of the first-type semiconductor layer 7031, the second-type semiconductor layer 7035 and the active layer 7033 include group III and V compound semiconductors, such as GaAs, InGaAs, AlGaAs, AlInGaAs, GaP, InGaP, AlInP, AlGaInP, GaN, InGaN, AlGaN, AlInGaN, AlAsSb, InGaAsP, InGaAsN, AlGaAsP, etc. In the embodiments of the present invention, unless otherwise specified, the chemical formula includes "stoichiometric compounds" and "non-stoichiometric compounds", wherein "stoichiometric compounds" are, for example, the total element content of group III elements is the same as the total element content of group V elements, whereas "non-stoichiometric compounds" are, for example, the total element content of group III elements is different from the total element content of group V elements. For example, the chemical formula AlGaAs means that it contains Group III elements aluminum (Al) and / or gallium (Ga), and Group V elements arsenic (As), wherein the total element content of Group III elements (aluminum and / or gallium) may be the same as or different from the total element content of Group V elements (arsenic). In addition, if the compounds represented by the chemical formula are stoichiometric compounds, AlGaAs means Al x1 Ga (1-x1) As, where 0≤x1≤1; AlInP represents Al x2 In (1-x2) P, where 0≤x2≤1; AlGaInP represents (Al y1 Ga (1-y1) ) 1-x3 In x3 P, where 0≤x3≤1, 0≤y1≤1; AlGaN represents Al x4 Ga(1-x4) N, where 0≤x4≤1; AlAsSb represents AlAs x5 Sb (1-x5) , where 0≤x5≤1; InGaP represents In x6 Ga 1-x6 P, where 0≤x6≤1; InGaAsP represents In x Ga 1-x6 As 1-y2 P y2 , where 0≤x6≤1, 0≤y2≤1; InGaAsN represents In x8 Ga 1- x8 As 1-y3 N y3 , where 0≤x8≤1, 0≤y3≤1; AlGaAsP represents Al x9 Ga 1-x9 As 1-y4 P y4 , where 0≤x9≤1, 0≤y4≤1; InGaAs represents In x10 Ga 1-x10 As, where 0≤x10≤1. According to the material of the active layer 7033, when the materials of the first-type semiconductor layer 7031 and the second-type semiconductor layer 7035 are AlGaAs series, the active layer 7033 can emit infrared light with a peak wavelength between 700nm and 1700nm. When the materials of the first-type semiconductor layer 7031 and the second-type semiconductor layer 7035 are AlGaInP series, the active layer 7033 can emit orange-red light with a peak wavelength between 610nm and 700nm, or green-yellow light with a peak wavelength between 570nm and 610nm, or green light with a peak wavelength between 530nm and 570nm. When the materials of the first-type semiconductor layer 7031 and the second-type semiconductor layer 7035 are InGaN series, the active layer 7033 can emit blue light, deep blue light with a peak wavelength between 400nm and 490nm, or green light with a peak wavelength between 490nm and 550nm. When the materials of the first-type semiconductor layer 7031 and the second-type semiconductor layer 7035 are AlGaN series, the active layer 7033 can emit ultraviolet light with a peak wavelength between 250nm and 400nm.

[0691] In this embodiment, the first-type semiconductor layer 7031 and the second-type semiconductor layer 7035 include a DBR structure, so that the light emitted by the active layer 7033 can be reflected back and forth between the two DBR structures to form coherent light, and then the coherent light is emitted from the direction of the first-type semiconductor layer 7031 to form laser light L7.

[0692] In this embodiment, if Figure 7 As shown, the insulating layer 7036 is located between the back conductive structure 7032 and the second-type semiconductor layer 7035. In one embodiment, the material of the insulating layer 7036 includes silicon oxide.

[0693] In this embodiment, the contact resistance between the back conductive structure 7032 and the second-type semiconductor layer 7035 is less than 10 -4 Ωcm 2 , and an ohmic contact is formed between the back conductive structure 7032 and the second semiconductor layer 7035. The formation mechanism of the ohmic contact is that the metal work function must be smaller than the semiconductor work function, so that electrons from the semiconductor to the metal and from the metal to the semiconductor can easily jump over this energy level, and the current can be conducted in both directions. For example, the metal component of the conductive electrode 7032D of the back conductive structure 7032 is mainly titanium aluminum alloy, because titanium can form titanium nitride with the III-V compound (such as aluminum gallium nitride) of the second semiconductor layer 7035, so that nitrogen atoms on the surface become an n-type doped surface, and a good ohmic contact is formed after high temperature annealing, but it is not limited to this.

[0694] In this embodiment, if Figure 7 As shown, the first-type semiconductor layer 7031 is connected to the positive conductive structure 7030, the positive conductive structure 7030 is connected to the conductive electrode 7032C through the second channel 7320, the conductive electrode 7032D is separated from the conductive electrode 7032C to avoid short circuit, and the second-type semiconductor layer 7035 is connected to the conductive electrode 7032D. In order to prevent the conductive medium filled in the second channel 7320 from contacting with the second-type semiconductor layer 7035 of the laser unit 7003 to form a short circuit, the laser unit 7003 also includes an insulating layer 7340 located on the inner wall of the second channel 7320. Through the above conductive structure, the laser unit 7003 receives external driving voltage / current and generates laser light L7. The positive conductive structure 7030 is located on the light-emitting side 7003S of the laser unit 7003 and is connected to the bonding layer 7002. Therefore, the laser light L7 emitted by the laser unit 7003 will be output to the outside through the bonding layer 7002 and the transparent base layer 7001. It should be noted that the transparent base layer 7001 is transparent to the laser light L7 of the laser unit 7003. Therefore, the objects under the transparent base layer 7001 do not need to be clearly seen by the naked eye, and the light can be UV light, visible light or infrared light, but the present invention is not limited to this.

[0695] In one or more embodiments, when the time-of-flight ranging module with the semiconductor light-emitting element 7000 is applied to a living object (such as a human face or human eye), since the coherent light emitted by the semiconductor light-emitting element 7000 has a higher energy, a corresponding optical element (such as a transparent substrate) is required to process the coherent light and output a laser light L7 of appropriate intensity. In order to effectively monitor whether the semiconductor light-emitting element 7000 is damaged and prevent the laser light L7 that has not been optically processed by the transparent substrate 7001 from leaking and directly hitting the human eye, the semiconductor light-emitting element 7000 of this embodiment has an eye safety monitoring circuit that can monitor abnormal damage of the light-emitting side 7003S of the laser unit 7003 in real time. The following examples illustrate the working principles of the semiconductor light-emitting element 7000 of some embodiments.

[0696] Please continue to refer to this example. Figure 7 As shown, in addition to the semiconductor structures required for emitting laser light, the laser unit 7003 further includes a back conductive structure 7032. The back conductive structure 7032 includes a plurality of detection electrodes 7032A and 7032B, and the back conductive structure 7032 and the front conductive structure 7030 are arranged on both sides of the laser unit 7003 opposite to each other. A plurality of first channels 7034 extend from the back conductive structure 7032 and penetrate the front conductive structure 7030 and the adhesive layer 7002, and connect to the conductive layer 7010. In other words, in this embodiment, the two ends of the first channel 7034 are respectively connected to the plurality of detection electrodes 7032A, 7032B and the conductive layer 7010. In some embodiments, the plurality of detection electrodes 7032A and 7032B separated from each other are connected to the two ends of the conductive layer 7010 through the first channel 7034. Therefore, the plurality of detection electrodes 7032A and 7032B are connected to a control circuit externally, and the resistance value change of the conductive layer 7010 can be monitored in real time. When the semiconductor light-emitting element 7000 is damaged by external impact, especially when the light-emitting side 7003S is damaged, the conductive layer 7010 will also be damaged, thereby increasing the resistance value, or even causing a circuit breakage due to damage. Therefore, the control circuit decides whether to cut off the power supply of the laser unit 7003 through the monitoring circuit according to the change in the resistance value of the conductive layer 7010, so as to prevent the laser light L7 emitted by the laser unit 7003 from leaking through the damaged gap of the transparent base layer 7001 and directly irradiating the human eye, thereby achieving the effect of real-time monitoring of abnormal conditions.

[0697] In this embodiment, if Figure 7 As shown, in order to prevent the conductive medium filled in the first channel 7034 from contacting the positive conductive structure 7030, the first type semiconductor layer 7031 or the second type semiconductor layer 7035 of the laser unit 7003 and forming a short circuit, the laser unit 7003 further includes an insulating layer 7340 located between the inner wall of the laser unit 7003 and the first channel 7034.

[0698] In some embodiments, the back conductive structure 7032 includes a plurality of detection electrodes 7032A and 7032B and a plurality of conductive electrodes 7032C and 7032D that are separated from each other and coplanar. Figure 7 As shown. Thus, the semiconductor light emitting device 7000 is suitable for flip chip connection to a carrier without wire bonding process, thereby saving packaging volume. In one or more embodiments, the back conductive structure 7032 includes a plurality of detection electrodes 7032A, 7032B, and the plurality of detection electrodes 7032A, 7032B extend from the back conductive structure 7032 and penetrate the front conductive structure 7030 and the adhesive layer 7002, and connect the conductive layer 7010.

[0699] In one or more embodiments, FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 8000, such as FIG. 8A to FIG. 8C shown. Figure 8B It is shown as Fig. 8A The bottom view of the semiconductor light emitting element 8000 shown in FIG. Fig. 8A , i.e., viewed from the direction of arrow C, i.e., viewed from the direction of the first pad structure 8902 and the second pad structure 8904), and Fig. 8A It is drawn along Figure 8B A schematic cross-sectional view of the cross-section shown by line segment 8A-8A'. Figure 8C It is shown as Fig. 8A The top view of the semiconductor light emitting element 8000 is shown, that is, from the direction of the transparent substrate 8010 (eg Fig. 8A A view of observing the semiconductor light emitting element 8000 in the direction indicated by the arrow D in FIG. 1 , and Fig. 8A It is drawn along Figure 8C A schematic cross-sectional view of the cross-section shown by line segment 8B-8B'.

[0700] Fig. 8A 1 is a cross-sectional schematic diagram of a semiconductor light emitting device 8000 according to an embodiment. In this embodiment, the semiconductor light emitting device 8000 includes a transparent base layer 8010 and an epitaxial structure 8020 located on one side of the transparent base layer 8010, and the epitaxial structure 8020 includes at least one columnar structure P8; in this embodiment, the epitaxial structure 8020 includes a plurality of columnar structures P8. Each columnar structure P8 includes a first semiconductor structure 8202, a current limiting layer 8205, and an active structure 8204 sequentially located on the transparent base layer 8010.

[0701] A plurality of columnar structures P8 may be arranged regularly (regular arrangement) or irregularly (random arrangement) on the second semiconductor structure 8206. The so-called regular arrangement means that the plurality of columnar structures P8 have a specific spatial relationship and are arranged in a fixed and repetitive manner. For example, in some regularly arranged columnar structures P8, the spacing between adjacent columnar structures P8 is approximately the same; in other regularly arranged columnar structures P8, the plurality of columnar structures P8 are arranged along a specific direction. Each columnar structure P8 includes an upper surface P81 facing the transparent base layer 8010 and a side surface P82 connecting the upper surface P81 and the second semiconductor structure 8206. In addition, the epitaxial structure 8020 further includes a lower surface 8206B away from the transparent base layer 8010, and the lower surface 8206B is the surface of the second semiconductor structure 8206. In the present embodiment, the conductivity type of the first semiconductor structure 8202 is P-type, and the conductivity type of the second semiconductor structure 8206 is N-type. For the sake of simplicity in the illustration, Fig. 8A Only five columnar structures P8 are used as an example. However, in actual VCSEL products, the number of columnar structures P8 can be adjusted according to the current and power requirements of the application, for example, 100 to 1000, but not limited thereto.

[0702] In this embodiment, if FIG. 8A to FIG. 8C As shown, the current limiting layer 8205 can be selectively located between the active structure 8204 and the first semiconductor structure 8202, or between the active structure 8204 and the second semiconductor structure 8206. The current limiting layer 8205 includes a current limiting region 8205B and a current conducting region 8205A surrounded by the current limiting region 8205B. The conductivity of the current conducting region 8205A is higher than that of the current limiting region 8205B, so that the current is concentrated and conducted in the current conducting region 8205A.

[0703] In this embodiment, if FIG. 8A to FIG. 8CAs shown, the first semiconductor structure 8202 and the active structure 8204 are partially covered on the second semiconductor structure 8206, and an end surface 8206A of the second semiconductor structure 8206 is exposed. The semiconductor light emitting element 8000 also includes a first insulating layer 8032 and a first metal connection layer 8034. The first insulating layer 8032 covers the side surface P82 of the columnar structure P8, the end surface 8206A of the second semiconductor structure 8206, and a portion of the upper surface P81 of the columnar structure P8. The first insulating layer 8032 has a plurality of first openings 8322, exposing a portion of the upper surface P81 from the first insulating layer 8032. The first metal connection layer 8034 is located on the first insulating layer 8032, and is electrically connected to the first semiconductor structure 8202 through the first openings 8322. The first metal connection layer 8034 has a plurality of second openings 8342, so that the light emitted by the active structure 8204 can be emitted from the second openings 8342 to the direction of the transparent base layer 8010 and out of the semiconductor light emitting element 8000. In addition, the second semiconductor structure 8206 has a first side S81 and a second side S82 relative to the first side S81. The first metal connection layer 8034 has a first protrusion 8341a extending beyond the first side S81 and a second protrusion 8341b extending beyond the second side S82. The first protrusion 8341a and the second protrusion 8341b can be used for subsequent electrical connection, and the detailed structure and electrical connection method will be described in detail below.

[0704] In this embodiment, if FIG. 8A to FIG. 8CAs shown, the semiconductor light emitting device 8000 further includes a bonding layer 8040, and the epitaxial structure 8020 is connected to the transparent base layer 8010 through the bonding layer 8040. A second metal connection layer 8050 is provided on the second semiconductor structure 8206 away from the transparent base layer 8010, and the second metal connection layer 8050 is electrically connected to the second semiconductor structure 8206. The semiconductor light emitting device 8000 of the present invention includes a second insulating layer 8060, and the second insulating layer 8060 covers the second metal connection layer 8050. The second insulating layer 8060 has two side portions 8601, and four opening portions (a first opening portion 8602a, a second opening portion 8602b, a third opening portion 8602c, and a fourth opening portion 8602d) further pass through the second insulating layer 8060. The side portion 8601 covers the first side edge S81 and the second side edge S82 of the second semiconductor structure 8206. The first opening 8602a further penetrates the first insulating layer 8032 to expose the first protrusion 8341a of the first metal connection layer 8034, and the second opening 8602b further penetrates the first insulating layer 8032 to expose the second protrusion 8341b of the first metal connection layer 8034. The second insulating layer 8060 also has a fifth opening 8603 to expose the second metal connection layer 8050. The semiconductor light emitting element 8000 of the present invention includes a first electrode 8702 and a second electrode 8704, which are located on the same side of the transparent base layer 8010 and are physically separated from each other.

[0705] In this embodiment, if FIG. 8A to FIG. 8C As shown, the semiconductor light emitting element 8000 is a flip-chip laser element. The semiconductor light emitting element 8000 can be subsequently bonded to an external carrier (such as a printed circuit board or a driver chip) by a flip-chip bonding process using solder. The first electrode 8702 is connected to the first metal connection layer 8034 through the first opening 8602a to the fourth opening 8602d, respectively, and is electrically connected to the first semiconductor structure 8202 through the first protrusion 8341a and the second protrusion 8341b of the first metal connection layer 8034. In addition, the first electrode 8702 covers the side of the second insulating layer 8060 and extends to cover the second metal connection layer 8050. The second insulating layer 8060 is located between the first electrode 8702 and the second metal connection layer 8050 to avoid forming a short circuit path. The second electrode 8704 is connected to the second metal connection layer 8050 through the fifth opening 8603, thereby making the second electrode 8704 electrically connected to the second semiconductor structure 8206.

[0706] In this embodiment, if FIG. 8A to FIG. 8CAs shown, the semiconductor light emitting device 8000 of the present invention may further include a first pad structure 8902 and a second pad structure 8904, which are respectively located on the first electrode 8702 and the second electrode 8704. The semiconductor light emitting device 8000 of the present invention further includes a third insulating layer 8080 covering the first electrode 8702 and the second electrode 8704. The third insulating layer 8080 has a first hole 8802 to expose the first electrode 8702 and a second hole 8804 to expose the second electrode 8704; the first pad structure 8902 is electrically connected to the first electrode 8702 through the first hole 8802, and the second pad structure 8904 is electrically connected to the second electrode 8704 through the second hole 8804. In addition, there is a spacing G8 between the first pad structure 8902 and the second pad structure 8904 ranging from 10 μm to 200 μm. In this embodiment, from the bottom view of the semiconductor light emitting device 8000, the shape of the first pad structure 8902 is different from the shape of the second pad structure 8904 for electrical identification.

[0707] In this embodiment, if FIG. 8A to FIG. 8C As shown, the semiconductor light emitting device 8000 of the present invention may selectively include an anti-reflection structure 8101 located on the transparent substrate 8010 and away from the first electrode 8702 and the second electrode 8704. The anti-reflection structure 8101 can be used to reduce the reflection of the light emitted by the semiconductor light emitting device 8000 at the interface between the transparent substrate 8010 and the air, so as to avoid the reduction of the light emitting efficiency of the semiconductor light emitting device 8000 or the generation of unexpected light shapes.

[0708] In this embodiment, if FIG. 8A to FIG. 8CAs shown, the first semiconductor structure 8202 and the second semiconductor structure 8206 include a plurality of layers with different refractive indices that are stacked alternately and periodically (for example, AlGaAs layers with high aluminum content and AlGaAs layers with low aluminum content are stacked alternately and periodically) to form a DBR structure, so that the light emitted by the active structure 8204 can be reflected back and forth between the two DBR structures to form coherent light. The reflectivity of the first semiconductor structure 8202 is lower than the reflectivity of the second semiconductor structure 8206, thereby causing the coherent light to be emitted in the direction of the transparent base layer 8010. The materials of the first semiconductor structure 8202, the second semiconductor structure 8206 and the active structure 8204 include III-V compound semiconductors, such as AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series and AlGaAsP series, such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN or AlGaN compounds. In the embodiments of the present invention, unless otherwise specified, the chemical formula includes "stoichiometric compounds" and "non-stoichiometric compounds", wherein "stoichiometric compounds" are, for example, compounds in which the total element content of group III elements is the same as the total element content of group V elements, whereas "non-stoichiometric compounds" are, for example, compounds in which the total element content of group III elements is different from the total element content of group V elements. For example, a chemical formula of the AlGaInAs series means that it contains group III elements aluminum (Al) and / or gallium (Ga) and / or indium (In), and group V elements arsenic (As), wherein the total element content of group III elements (aluminum and / or gallium and / or indium) may be the same as or different from the total element content of group V elements (arsenic). In addition, if the compounds represented by the chemical formula are stoichiometric compounds, the AlGaInAs series means (Al y1 Ga (1-y1) ) 1-x1 In x1 As, where 0≤x1≤1, 0≤y1≤1; AlGaInP series represents (Al y2 Ga (1-y2) ) 1- x2 In x2 P, where 0≤x2≤1, 0≤y2≤1; AlInGaN series represents (Al y3 Ga (1-y3) ) 1-x3 In x3 N, where 0≤x3≤1, 0≤y3≤1; AlAsSb series represents AlAs x4 Sb (1-x4), where 0≤x4≤1; InGaAsP series represents In x5 Ga 1-x5 As 1-y4 P y4 , where 0≤x5≤1, 0≤y4≤1; InGaAsN series represents In x6 Ga 1-x6 As 1-y5 N y5 , where 0≤x6≤1, 0≤y5≤1; AlGaAsP series represents Al x7 Ga 1-x7 As 1-y6 P y6 , where 0≤x7≤1, 0≤y6≤1.

[0709] Depending on the material, the active structure 8204 can emit infrared light with a peak wavelength between 700nm and 1700nm, red light with a peak wavelength between 610nm and 700nm, yellow light with a peak wavelength between 530nm and 570nm, green light with a peak wavelength between 490nm and 550nm, blue light or deep blue light with a peak wavelength between 400nm and 490nm, or ultraviolet light with a peak wavelength between 250nm and 400nm. In this embodiment, the peak wavelength of the active structure 8204 is infrared light between 750nm and 1200nm.

[0710] The material of the current limiting layer 8205 can be the above-mentioned III-V semiconductor material. In this embodiment, FIG. 8A to FIG. 8C As shown, the material of the current limiting layer 8205 is AlGaAs, and the active structure 8204, the first semiconductor structure 8202 and the second semiconductor structure 8206 are made of a material containing aluminum. The aluminum content of the current limiting layer 8205 is greater than the aluminum content of the active structure 8204, the first semiconductor structure 8202 and the second semiconductor structure 8206. For example, the aluminum content of the current limiting layer 8205 is greater than 97%. In this embodiment, the oxygen content of the current limiting region 8205B of the current limiting layer 8205 is greater than the oxygen content of the current conducting region 8205A, so that the current limiting region 8205B has a lower conductivity than the current conducting region 8205A. The subsequent layer 8040 is a material having a high transmittance to the light emitted by the active structure 8204, such as a transmittance greater than 80%. The material of the subsequent layer 8040 is an insulating material, such as benzocyclobutene resin (BCB), epoxy resin, polyimide, spin-on glass (SOG), silicone or octafluorocyclobutane (PFCB).

[0711] In this embodiment, if FIG. 8A to FIG. 8C As shown, the first insulating layer 8032, the second insulating layer 8060 and the third insulating layer 8080 are made of non-conductive materials. The non-conductive materials include organic materials or inorganic materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin (Acrylic Resin), cyclic olefin copolymer (cyclic olefin copolymer, COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide (Polyetherimide) or fluorocarbon polymer (FluorocarbonPolymer). Inorganic materials include silicone or glass, aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x In one embodiment, the first insulating layer 8032, the second insulating layer 8060 and / or the third insulating layer 8080 include one or more layers (e.g., a Bragg reflector (DBR) structure formed by alternately stacking two sub-layers, such as SiO x Sublayer and TiO x sub-layer).

[0712] In this embodiment, if FIG. 8A to FIG. 8CAs shown, the materials of the first metal connection layer 8034 and the second metal connection layer 8050 may include metals, such as aluminum (Al), silver (Ag), chromium (Cr), platinum (Pt), nickel (Ni), germanium (Ge), beryllium (Be), gold (Au), titanium (Ti), tungsten (W) or zinc (Zn). The materials of the first electrode 8702 and the second electrode 8704 may be metal materials, such as gold (Au), tin (Sn), titanium (Ti) or their alloys. In this embodiment, the first electrode 8702 may be a multi-layer electrode structure, for example, it may include a titanium (Ti) layer and a gold (Au) layer in the direction away from the transparent base layer 8010. The second electrode 8704 has the same material and structural composition as the first electrode 8702. The materials of the first pad structure 8902 and the second pad structure 8904 are metal materials, such as gold (Au), tin (Sn), titanium (Ti), copper (Cu), nickel (Ni), platinum (Pt) or their alloys. The material of the first electrode 8702 is different from that of the first pad structure 8902, and the material of the second electrode 8704 is different from that of the second pad structure 8904. For example, the first pad structure 8902 and the second pad structure 8904 contain an element, while the first electrode 8702 and the second electrode 8704 do not contain the element, so as to prevent the external (tin-containing) solder from damaging the first electrode 8702 and the second electrode 8704 and causing electrical failure during die bonding or high current operation, thereby further improving the reliability of the semiconductor light emitting device 8000 of the present invention. The above-mentioned element can be used to prevent the solder from diffusing into the first electrode 8702 and the second electrode 8704, and the element is, for example, nickel (Ni) and / or platinum (Pt). In detail, the first pad structure 8902 and the second pad structure 8904 may be multi-layered, respectively, and include an intermediate layer 8902A, an intermediate layer 8904A, and a bonding layer 8902B, and a bonding layer 8904B in order away from the transparent base layer 8010. The materials of the intermediate layers 8902A and 8904A are different from the first electrode 8702 and the second electrode 8704, thereby preventing solder (e.g., tin or gold-tin alloy (AuSn)) from diffusing into the first electrode 8702 and the second electrode 8704. Therefore, the materials of the intermediate layers 8902A and 8904A preferably include metal elements other than gold (Au), tin (Sn) and copper (Cu), such as nickel (Ni) and / or platinum (Pt). The materials of the bonding layers 8902B and 8904B include metal materials with high ductility, such as gold (Au). In this embodiment, the materials of the intermediate layers 8902A and 8904A are platinum (Pt) and nickel (Ni) stacked in sequence in the direction away from the transparent base layer 8010, and the materials of the bonding layers 8902B and 8904B are gold (Au). In other words, in the direction away from the transparent base layer 8010, the first pad structure 8902 and the second pad structure 8904 include a nickel layer, a platinum layer and a gold layer.

[0713] See also Fig. 8A and Figure 8B , the transparent base layer 8010 has a middle area and a peripheral area surrounding the middle area. The second insulating layer 8060 has a plurality of openings (e.g., a first opening 8602a, a second opening 8602b, a third opening 8602c, and a fourth opening 8602d) dispersedly arranged in the peripheral area of ​​the transparent base layer 8010. In addition, there are four spacings between the four openings. More specifically, in this embodiment, the first opening 8602a and the fourth opening 8602d are separated by a first spacing G81, the first opening 8602a and the second opening 8602b are separated by a second spacing G82, the second opening 8602b and the third opening 8602c are separated by a third spacing G83, and the third opening 8602c and the fourth opening 8602d are separated by a fourth spacing G84.

[0714] In addition, if Figure 8C As shown, in this embodiment, the first metal connection layer 8034 is formed with a plurality of marking structures 8344A-8344D, which are convenient for machine identification to facilitate the subsequent packaging manufacturing process. The marking structures 8344B and 8344D are relatively connected and define the connection line L81, and the marking structures 8344A and 8344C are relatively connected and define the connection line L82. The connection line L81 and the connection line L82 are interlaced at the center position O8. Figure 8B and Figure 8C , the marking structure 8344A corresponds to the first spacing G81, the marking structure 8344B corresponds to the second spacing G82, the marking structure 8344C corresponds to the third spacing G83, and the marking structure 8344D corresponds to the fourth spacing G84. Special instructions are required, Figure 8B and Figure 8C The dotted lines indicate that the structure cannot be directly observed from the bottom view / top view and only the outline of the dotted lines can be seen.

[0715] In this embodiment, the second semiconductor structure 8206 may be located on the middle area of ​​the transparent base layer 8010. In one embodiment, the distance from any side of the second semiconductor structure 8206 to a border of the adjacent transparent base layer 8010 is substantially equal, so that the first pad structure 8902 and the second pad structure 8904 (or the first electrode 8702 and the second electrode 8704) can be symmetrical to the connection line L81, which is beneficial to the structural design of the subsequent packaging process and increases the effective area for connecting to the external circuit. Figure 8BAs shown, from the direction of the second semiconductor structure 8206 of the semiconductor light emitting device 8000 toward the active structure 8204, the transparent base layer 8010 has a first boundary C81 adjacent to the first side S81 and a second boundary C82 opposite to the first boundary C81 and adjacent to the second side S82, the first boundary C81 and the second boundary C82 corresponding to each other and each disposed at the side of the transparent base layer 8010. The difference between the first distance D81 between the first side S81 and the first boundary C81 and the second distance D82 between the second side S82 and the second boundary C82 is less than 30% of the first distance D81; that is, the difference between the first distance D81 and the second distance D82 is 0≤(D81-D82) / D81<30%, in another embodiment, 0≤(D81-D82) / D81<20%; preferably, 0≤(D81-D82) / D81<15%. In another embodiment, 1%<(D81-D82) / D81<10%. In this embodiment, the first distance D81 is equal to the second distance D82.

[0716] In one or more embodiments, FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 9000, such as Fig. 9 shown.

[0717] See also Fig. 9 , is a cross-sectional schematic diagram of a semiconductor light emitting device 9000 according to an embodiment. The semiconductor light emitting device 9000 of this embodiment is a laser diode, and includes a substrate 9110, an epitaxial stack 9120 formed on the substrate 9110, and a first electrode structure 9132 and a second electrode structure 9134 located on the epitaxial stack 9120. The substrate 9110 is a gallium arsenide (GaAs) substrate with high transmittance, and has a first surface 9110A and a second surface 9110B. The light emitting surface (e.g. Fig. 9 The epitaxial stack 9120 is located on the second surface 9110B of the substrate 9110 and includes a first semiconductor structure 9121, a second semiconductor structure 9122, an intermediate layer 9123, a third semiconductor structure 9124, an active structure 9126 and a fourth semiconductor structure 9127 in sequence.

[0718] In this embodiment, if Fig. 9As shown, the substrate 9110 includes a dopant to have a p-type or n-type conductivity type. Alternatively, in another embodiment, the substrate 9110 does not include a dopant or the substrate 9110 is an undoped substrate layer. The first semiconductor structure 9121 is a semiconductor material that does not include a dopant, which is used to reduce the problem of light absorption by the dopant. The second semiconductor structure 9122, the intermediate layer 9123, the third semiconductor structure 9124 and the fourth semiconductor structure 9127 are semiconductor materials that include a dopant. The second semiconductor structure 9122, the intermediate layer 9123 and the third semiconductor structure 9124 have the same conductivity type, and the third semiconductor structure 9124 (or the second semiconductor structure 9122 or the intermediate layer 9123) and the fourth semiconductor structure 9127 have different conductivity types. In this embodiment, the conductivity type of the second semiconductor structure 9122, the intermediate layer 9123 and the third semiconductor structure 9124 is p-type, and the conductivity type of the fourth semiconductor structure 9127 is n-type. In another embodiment, the conductivity type of the second semiconductor structure 9122, the intermediate layer 9123 and the third semiconductor structure 9124 is n-type, and the conductivity type of the fourth semiconductor structure 9127 is p-type. The first electrode structure 9132 and the second electrode structure 9134 are located on the fourth semiconductor structure 9127. The dopant may include beryllium, magnesium, zinc, carbon, silicon or antimony, or a combination of the above elements.

[0719] See again Fig. 9 In the embodiment shown, the third semiconductor structure 9124 or the fourth semiconductor structure 9127 optionally includes a current limiting layer 9125. Alternatively, in the present embodiment, the current limiting layer 9125 is formed in the third semiconductor structure 9124 or the fourth semiconductor structure 9127. The current limiting layer 9125 includes a current limiting region 9125B and a current conduction region 9125A defined by the current limiting region 9125B.

[0720] In this embodiment, if Fig. 9As shown, the semiconductor light emitting device 9000 further includes a recessed structure 9140 and a protective layer 9150. The recessed structure 9140 is formed in the epitaxial stack 9120. In detail, in the present embodiment, the recessed structure 9140 is formed in the fourth semiconductor structure 9127, the active structure 9126 and the third semiconductor structure 9124. In other words, in the present embodiment, the recessed structure 9140 penetrates the fourth semiconductor structure 9127, the active structure 9126 and the third semiconductor structure 9124 to expose the intermediate layer 9123. The protective layer 9150 fills the recessed structure 9140 and is located between the first electrode structure 9132 and the fourth semiconductor structure 9127. The first electrode structure 9132 has a first portion 9132A and a second portion 9132B. The first portion 9132A fills the recessed structure 9140 and contacts the intermediate layer 9123, and is electrically connected to the intermediate layer 9123. The second portion 9132B is extended from the first portion 9132A and is located on the protection layer 9150. The second electrode structure 9134 is disposed on the fourth semiconductor structure 9127 and is electrically connected to the fourth semiconductor structure 9127.

[0721] In this embodiment, if Fig. 9 As shown, the semiconductor light emitting element 9000 optionally further includes an optical element 9160, covering the first surface 9110A of the substrate 9110. For example, the optical element 9160 may be an anti-reflection element, which is used to further reduce the reflection of the light emitted by the semiconductor light emitting element 9000 at the interface between the substrate 9110 and the air, so as to avoid the reduction of the light emitting efficiency of the semiconductor light emitting element 9000 or to prevent the interference between the interface reflected light and the light emitted from the semiconductor light emitting element 9000.

[0722] In this embodiment, if Fig. 9As shown, the first semiconductor structure 9121, the second semiconductor structure 9122, the third semiconductor structure 9124 and the fourth semiconductor structure 9127 may respectively include a plurality of film layers with different refractive indices that are periodically stacked alternately (for example, AlGaAs layers with high aluminum content and AlGaAs layers with low aluminum content that are periodically stacked alternately) to form a distributed Bragg reflector (DBR), so that the light emitted from the active structure 9126 can be reflected between the Bragg reflectors to form coherent light. The reflectivity of the first semiconductor structure 9121, the second semiconductor structure 9122 and the third semiconductor structure 9124 is lower than the reflectivity of the fourth semiconductor structure 9127, thereby allowing the coherent light to be emitted toward the substrate 9110. The materials of the first semiconductor structure 9121, the second semiconductor structure 9122, the third semiconductor structure 9124, the fourth semiconductor structure 9127 and the active structure 9126 include group III and V compound semiconductors, such as AlGaInAs series, AlGaInP series, AlInGaN series, AlAsSb series, InGaAsP series, InGaAsN series, AlGaAsP series, etc., such as AlGaInP, GaAs, InGaAs, AlGaAs, GaAsP, GaP, InGaP, AlInP, GaN, InGaN, AlGaN, etc. In the embodiments of the present invention, unless otherwise specified, the chemical formula includes "compounds that meet stoichiometric requirements" and "compounds that do not meet stoichiometric requirements", wherein "compounds that meet stoichiometric requirements" are, for example, the total element content of group III elements is the same as the total element content of group V elements, whereas "compounds that do not meet stoichiometric requirements" are, for example, the total element content of group III elements is different from the total element content of group V elements. For example, the chemical formula AlGaInAs series means that it contains the group III elements aluminum (Al) and / or gallium (Ga) and / or indium (In), and the group V element arsenic (As), wherein the total element content of the group III elements (aluminum and / or gallium and / or indium) can be the same as or different from the total element content of the group V element (arsenic). In addition, if the compounds represented by the chemical formula are stoichiometric compounds, the AlGaInAs series means (Al y1 Ga (1-y1) ) 1-x1 In x1 As, where 0≤x1≤1, 0≤y1≤1; AlGaInP series represents (Al y2 Ga (1-y2) ) 1-x2 In x2 P, where 0≤x2≤1, 0≤y2≤1; AlInGaN series represents (Al y3 Ga (1-y3) ) 1-x3 In x3N, where 0≤x3≤1, 0≤y3≤1; AlAsSb series represents AlAs x4 Sb (1-x4) , where 0≤x4≤1; InGaAsP series represents In x5 Ga 1-x5 As 1-y4 P y4 , where 0≤x5≤1, 0≤y4≤1; InGaAsN series represents In x6 Ga 1-x6 As 1-y5 N y5 , where 0≤x6≤1, 0≤y5≤1; AlGaAsP series represents Al x7 Ga 1-x7 As 1-y6 P y6 , where 0≤x7≤1, 0≤y6≤1.

[0723] Depending on the material, the active structure 9126 can emit infrared light with a peak wavelength between 700nm and 1700nm, red light with a peak wavelength between 610nm and 700nm, yellow light with a peak wavelength between 530nm and 570nm, green light with a peak wavelength between 490nm and 550nm, blue light or deep blue light with a peak wavelength between 400nm and 490nm, or ultraviolet light with a peak wavelength between 250nm and 400nm. In this embodiment, the peak wavelength of the active structure 9126 is infrared light between 750nm and 2000nm.

[0724] The current limiting layer 9125 can be formed by an oxidation process or an ion implantation process. In the present embodiment, when the first semiconductor structure 9121, the second semiconductor structure 9122, the third semiconductor structure 9124, the active structure 9126 and the fourth semiconductor structure 9127 include multiple film layers and all include aluminum, the aluminum content of one or more layers in the third semiconductor structure 9124 can be designed to be greater than 97% (defined as the current limiting layer 9125) and greater than the aluminum content of the active structure 9126, other film layers of the third semiconductor structure 9124, the second semiconductor structure 9122, the first semiconductor structure 9121 and the fourth semiconductor structure 9127. Thus, after the oxidation process, the layer or portions of the layers with an aluminum content greater than 97% will be oxidized to form a current limiting region 9125B (e.g., aluminum oxide), and the unoxidized portion will be the current conduction region 9125A. In the oxidation process, oxygen undergoes an oxidation reaction with the epitaxial stack 9120 through the recessed structure 9140.

[0725] The materials of the first electrode structure 9132 and the second electrode structure 9134 include metal materials, such as gold (Au), tin (Sn), titanium (Ti), copper (Cu), silver (Ag), germanium (Ge), platinum (Pt), palladium (Pd), nickel (Ni) or their alloys.

[0726] In this embodiment, if Fig. 9 As shown, the material of the intermediate layer 9123 is different from the first semiconductor structure 9121, the second semiconductor structure 9122 and the third semiconductor structure 9124. The intermediate layer 9123 can be a single layer or a multi-layer and serves as an etching stop layer to control the depth of the recessed structure 9140. The intermediate layer 9123 includes a semiconductor material, such as GaAs or InGaP, and has a thickness that is an odd multiple of 1 / 4n of the peak wavelength of the light emitted by the active structure 9126, where n is the refractive index. In one embodiment, since the material of the intermediate layer 9123 is different from the first semiconductor structure 9121, the second semiconductor structure 9122 and the third semiconductor structure 9124, the optical properties of the semiconductor light emitting element 9000 (e.g., reflectivity, threshold current (I th )), therefore, the thickness of the intermediate layer 9123 is designed to be between 0.05 μm and 0.5 μm. In one embodiment, the intermediate layer 9123 may reduce lateral current diffusion, therefore, the second semiconductor structure 9122 is provided as a current diffusion layer in addition to the consideration of optical properties. When the intermediate layer 9123 is multi-layered (for example, comprising two layers, and the first layer is InGaP and the second layer is GaAs), the total thickness of the multi-layers is between 0.05 μm and 0.5 μm.

[0727] In one embodiment, if Fig. 9 As shown, when the first semiconductor structure 9121, the second semiconductor structure 9122, and the third semiconductor structure 9124 are all distributed Bragg reflectors (DBRs), the number of pairs of film layers periodically stacked alternately in the first semiconductor structure 9121 may be greater than, equal to, or less than that of the second semiconductor structure 9122, and / or the number of pairs of film layers periodically stacked alternately in the first semiconductor structure 9121 may be greater than, equal to, or less than that of the third semiconductor structure 9124. In one embodiment, the number of pairs of film layers of the second semiconductor structure 9122 is less than that of the third semiconductor structure 9124. In one embodiment, the number of pairs of film layers of the first semiconductor structure 9121 may be 5 to 15 pairs, the number of pairs of film layers of the second semiconductor structure 9122 may be 2 to 5 pairs, and the number of pairs of film layers of the third semiconductor structure 9124 may be 5 to 15 pairs.

[0728] In one embodiment, if Fig. 9As shown, according to the requirements of optical properties, the sum of the number of film layer pairs of the first semiconductor structure 9121, the second semiconductor structure 9122 and the third semiconductor structure 9124 is less than the number of film layer pairs of the fourth semiconductor structure 9127. For example, the sum of the number of film layer pairs of the first semiconductor structure 9121, the second semiconductor structure 9122 and the third semiconductor structure 9124 is 15 to 25 pairs, and the number of film layer pairs of the fourth semiconductor structure 9127 is 30 to 60 pairs.

[0729] In one embodiment, if Fig. 9 As shown, due to the manufacturing process, the P-type semiconductor layer has a lower doping concentration than the N-type semiconductor layer, and in design, the sum of the film layer logarithms of the second semiconductor structure 9122 and the third semiconductor structure 9124 is less than the film layer logarithm of the fourth semiconductor structure 9127. Therefore, the conductive type of the first semiconductor structure 9121 and the third semiconductor structure 9124 can be designed to be P-type, and the conductive type of the fourth semiconductor structure 9127 is n-type, thereby reducing the series resistance of the overall semiconductor light-emitting element 9000 and improving the luminous efficiency.

[0730] In one or more embodiments, FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 10-000, such as FIG. 10A to FIG. 10E See FIG. 10C to FIG. 10E , are cross-sectional schematic diagrams showing different cross-sections of the semiconductor light emitting element 10-000 of the present invention; wherein, Fig. 10C The schematic diagram shows the Fig. 10A The cross-sectional structure shown by the line segment 10C-10C', Fig. 10D Schematic diagram along the Fig. 10A The cross-sectional structure shown by line segment 10D-10D', and Fig. 10E Schematic diagram along the Fig. 10A The cross-sectional structure is shown by the line segment 10E-10E'.

[0731] It should be noted that, to avoid confusion, Fig. 10A The component symbols below are presented in the form of XX (drawing number)-XXX (random code), for example, semiconductor light emitting component 10-000.

[0732] See also FIG. 10A to FIG. 10E , which respectively illustrate a bottom perspective schematic diagram, a top perspective schematic diagram, and a cross-sectional schematic diagram of different cross sections of a semiconductor light emitting device 10-000 according to an exemplary embodiment. In this embodiment, as Fig. 10CAs shown, the semiconductor light emitting element 10-000 includes a base layer 10-010, a bonding layer 10-901, a plurality of epitaxial columnar structures P10 (P1011 to P1014) and a platform structure 10-226, wherein the epitaxial columnar structure P10 is formed on the platform structure 10-226 and bonded to the base layer 10-010 through the bonding layer 10-901. The semiconductor light emitting element 10-000 also includes a metal connection layer 10-040, which is located between the epitaxial columnar structure P10 and the base layer 10-010, and the metal connection layer 10-040 electrically connects the first semiconductor structure of each epitaxial columnar structure P10 (P1011 to P1014), and the insulating layer 10-090 is located between the metal connection layer 10-040 and the epitaxial columnar structure P10. In this embodiment, the semiconductor light emitting element 10-000 further includes an insulating layer 10-082, and the insulating layer 10-090 covers the metal connection layer 10-420, covers the side and partial surface of the metal connection layer 10-520, and covers the side and partial surface of the platform structure 10-226 and the platform structure 10-326.

[0733] In this embodiment, if FIG. 10B to FIG. 10E As shown, the semiconductor light emitting element 10-000 further includes electrode structures 10-050A, 10-050B, 10-060A, 10-060B, 10-070A, 10-070B, 10-080A, 10-080B. In this embodiment, Fig. 10B As shown, the electrode structures 10-050A, 10-050B, 10-060A, 10-060B, 10-070A, 10-070B, 10-080A, 10-080B of the semiconductor light emitting element 10-000 are located outside the light emitting regions 10-000A, 10-000B, 10-000C, 10-000D, and the electrode structures and the light emitting regions do not overlap with each other. Specifically, in this embodiment, the structure of the semiconductor light emitting element is composed of the structure of the light emitting region and the structure of the non-light emitting region. The structure of the light-emitting region of the semiconductor light-emitting element 10-000 includes four light-emitting regions 10-000A, 10-000B, 10-000C, and 10-000D, and the structure of the non-light-emitting region of the semiconductor light-emitting element 10-000 includes electrode structures 10-050A, 10-050B, 10-060A, 10-060B, 10-070A, 10-070B, 10-080A, and 10-080B, but the number of light-emitting regions and the number of electrode structures of the present invention are not limited thereto. In this embodiment, as Fig. 10BAs shown, the electrode structure 10-050A and the electrode structure 10-060A located in the outer area of ​​the light-emitting area 10-000A are used to control the light-emitting area 10-000A; the electrode structure 10-070A and the electrode structure 10-080A located in the outer area of ​​the light-emitting area 10-000B are used to control the light-emitting area 10-000B; the electrode structure 10-070B and the electrode structure 10-080B located in the outer area of ​​the light-emitting area 10-000C are used to control the light-emitting area 10-000C; the electrode structure 10-050B and the electrode structure 10-060B located in the outer area of ​​the light-emitting area 10-000D are used to control the light-emitting area 10-000D. In this embodiment, as Fig. 10B As shown, multiple electrode structures 10-050A, 10-060A, 10-070A, 10-080A, 10-050B, 10-060B, 10-070B, and 10-080B are separated from each other.

[0734] In the present embodiment, the semiconductor light emitting element 10-000 may selectively further include a heat conductive structure TP10 located on the back of the plurality of light emitting regions 10-000A, 10-000B, 10-000C, and 10-000D, for conducting the heat energy generated by each light emitting region to the outside, so as to increase the heat dissipation effect of the semiconductor light emitting element 10-000. The material of the heat conductive structure TP10 may be, for example, a metal heat conductive structure, and the distribution area of ​​the heat conductive structure TP10 covers the corresponding area range where all the epitaxial columnar structures P10 are located for each light emitting region to conduct heat, but the present invention is not limited thereto. In one embodiment, for example, the electrode structure 10-060A and the electrode structure 10-080A may have an internal connection structure that is electrically conductive to each other, so that the electrode structure 10-060A and the electrode structure 10-080A form a common electrode structure architecture. In another embodiment, for example, the diagonally located electrode structure 10-060A and the electrode structure 10-080B, or the diagonally located electrode structure 10-060B and the electrode structure 10-080A may have an internal connection structure that is electrically conductive to each other to form two electrode structures with different electrical properties, which can further improve the current distribution, but the present invention is not limited to this.

[0735] like Fig. 10CAs shown, the four epitaxial columnar structures (i.e. corresponding to the light-emitting hole O10) P1011, P1012, P1013, and P1014 of the light-emitting area 10-000A are located above the same platform structure 10-226, and the electrical control signal passes through the electrode structure 10-050A and the electrode structure 10-060A located outside the platform structure 10-226 to control the light-emitting state of the light-emitting area 10-000A. In this embodiment, the electrode structure 10-050A is electrically connected to the semiconductor structure (i.e. corresponding to the platform structure 10-226) via the electrode connection layer 10-420, and the electrode structure 10-060A is connected to the conductive layer 10-421, thereby electrically connecting the metal connection layer 10-040 of the semiconductor light-emitting element 10-000. In this embodiment, the semiconductor light-emitting element 10-000 also includes a thermal conductive structure TP10, which is covered on the insulating layer 10-084 for conduction and heat dissipation.

[0736] Fig. 10D The epitaxial columnar structures P1015, P1016, P1021, and P1022 located in different light-emitting regions 10-000A and 10-000B are shown, wherein the epitaxial columnar structures P1015 and P1016 are located on the platform structure 10-226, and the epitaxial columnar structures P1021 and P1022 are located on the platform structure 10-326. Fig. 10D As shown, the electrode structure 10-050A and the electrode structure 10-070A are electrically connected to the platform structure 10-226 and the platform structure 10-326, respectively, and the electrode structure 10-050A and the electrode structure 10-070A are not electrically connected to each other (i.e., the electrode structure 10-050A and the electrode structure 10-070A are isolated by the insulating layer 10-084), so that the electrical control signal can pass through the electrode structure 10-050A and the electrode structure 10-070A outside the light-emitting area 10-000A and the light-emitting area 10-000B to control the light-emitting state of the light-emitting area 10-000A and the light-emitting area 10-000B. Similarly, the heat-conducting structure TP10 is covered on the insulating layer 10-084 and the area range covers the range where all the epitaxial columnar structures P10 are located for the purpose of heat conduction and heat dissipation of each light-emitting area.

[0737] exist Fig. 10EIn the cross-sectional structure shown, the epitaxial columnar structures P1023 and P1024 of the light-emitting area 10-000B and the epitaxial columnar structures P1031 and P1032 of the light-emitting area 10-000C are located on the same platform structure 10-326. As shown in the figure, the electrode structure 10-080A and the electrode structure 10-080B located outside the light-emitting area 10-000B and the light-emitting area 10-000C are not electrically connected to each other, so that the light-emitting states of the light-emitting area 10-000B and the light-emitting area 10-000C can be controlled independently. Similarly, the heat-conducting structure TP10 is covered on the insulating layer 10-084 for the light-emitting area to conduct heat dissipation. Fig. 10E As shown, a spacer 10-040B is also formed in the metal connection layer 10-040 on the platform structure 10-226 to separate the metal connection layer 10-040 into mutually separated parts 10-040a and 10-040b, that is, a groove structure is formed between the parts 10-040a and 10-040b and a part of the surface of the insulating layer 10-090 is exposed.

[0738] Please see again FIG. 10A to FIG. 10E In the present embodiment, the electrode structures 10-050A, 10-060A, 10-070A, 10-080A, 10-080B may respectively include an intermediate layer (eg, intermediate layer 10-502A, 10-702A) and a bonding layer (eg, bonding layer 10-504A, 10-704A).

[0739] In this embodiment, if FIG. 10A to FIG. 10E As shown, the semiconductor light emitting element 10-000 is a flip-chip laser element. Solder can be used to subsequently bond the semiconductor light emitting element 10-000 to an external carrier (such as a printed circuit board or a driver chip) using a flip-chip bonding process.

[0740] In one or more embodiments, FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 11-000, such as Fig.11 shown.

[0741] According to the present invention, the selection and configuration design of the insulating layer material can be further utilized to reduce the overall capacitance of the semiconductor light emitting device, thereby improving the operating performance of the semiconductor light emitting device. Fig.11 , which is a cross-sectional schematic diagram of a semiconductor light emitting element 11-000 according to one embodiment.

[0742] like Fig.11As shown, the semiconductor light emitting element 11-000 of this embodiment further includes a metal connection layer 11-040 located between the epitaxial structure 11-720 and the base layer 11-010, and between the epitaxial structure 11-730 and the base layer 11-010. Fig.11 As shown, the semiconductor light emitting element 11-000 of this embodiment further includes a bonding layer 11-901, and the epitaxial structure 11-720 and the epitaxial structure 11-730 are connected to the base layer 11-010 via the bonding layer 11-901. Fig.11 As shown, the semiconductor light emitting element 11-000 of this embodiment further includes an insulating layer 11-090, which covers the side and part of the upper surface of each epitaxial columnar structure P111, P112, and the insulating layer 11-090 is transparent to the light emitted from each epitaxial columnar structure P111, P112. Fig.11 As shown, the semiconductor light emitting element 11-000 of this embodiment further includes an insulating layer 11-084, and the insulating layer 11-084 covers the sides and a portion of the surface of the electrode structure 11-770 and the electrode structure 11-780, and covers the sides and a portion of the surface of the platform structure 11-726 and the platform structure 11-736. Fig.11 As shown, the semiconductor light emitting element 11-000 of this embodiment has an electrode connection layer 11-242 and an electrode connection layer 11-342 respectively located on the side of the platform structure 11-726 and the platform structure 11-736 away from the base layer 11-010, and the electrode connection layer 11-242 and the electrode connection layer 11-342 are respectively electrically connected to the epitaxial structure 11-720 and the epitaxial structure 11-730.

[0743] like Fig.11 In the embodiment shown, the electrode structure 11-770 and the electrode structure 11-780 in the semiconductor light emitting element 11-000 are located outside the epitaxial structure 11-720 and the epitaxial structure 11-730; that is, in this embodiment, the electrode structure 11-770 is located on the side of the epitaxial structure 11-720 close to the side 11-010A of the base layer 11-010, and the electrode structure 11-780 is located on the side of the epitaxial structure 11-730 close to the side 11-010B of the base layer 11-010. In this embodiment, the electrode structure 11-770 and the electrode structure 11-780 are located on the outside of the electrode structure 11-750 and the electrode structure 11-760, respectively, as shown in FIG. Fig.11 In addition, each electrode structure 11-750, 11-760 includes an intermediate layer and an adhesive layer. In this embodiment, as shown in FIG. Fig.11 As shown, the semiconductor light emitting element 11-000 is a flip-chip laser element. Solder can be used to subsequently bond the semiconductor light emitting element 11-000 to an external carrier (such as a printed circuit board or a driver chip) using a flip-chip bonding process.

[0744] In such Fig.11 In the illustrated embodiment, the epitaxial columnar structures P111 and P112 have a width W111, and the platform structures 11-726 and the platform structures 11-736 have a width W112. In some embodiments, the width W111 is smaller than the width W112; in other words, in some embodiments, the platform structures 11-726 and the platform structures 11-736 are formed as high platforms with their outer sides protruding outside the epitaxial columnar structures P111 and P112, and form a two-stage high platform structure with the epitaxial columnar structures P111 and P112.

[0745] Or, if Fig.11 In the present embodiment shown, the width W112 of the platform structure 11-726 and the platform structure 11-736 of the semiconductor light-emitting element 11-000 is equal to or close to the width W111 of the epitaxial columnar structures P111 and P112, that is, the width W112 is equal to the width W111; in other words, in this embodiment, the platform structure 11-726 and the platform structure 11-736 and the epitaxial columnar structures P111 and P112 are formed as high platforms of the same section, so the epitaxial structures 11-720 and the epitaxial structures 11-730 do not have a two-section high platform structure.

[0746] exist Fig.11 In the illustrated embodiment, since the epitaxial structure 11-720 and the epitaxial structure 11-730 respectively form a high platform structure and the electrode structure 11-770 and the electrode structure 11-780 are respectively arranged on the outer sides of the epitaxial structure 11-720 and the epitaxial structure 11-730, the aspect ratio at the interval between the epitaxial structure 11-720 and the epitaxial structure 11-730 is higher than that of a general semiconductor light emitting element. Based on this, the present invention uses a low dielectric value (low-k) glue (for example, spin-on glass (SOG) glue) as the insulating material of the insulating layer 11-782 in the semiconductor light emitting element 11-000.

[0747] Therefore, the glue layer can not only easily fill the spacing area between the epitaxial structure 11-720 and the epitaxial structure 11-730, but also form a co-planarized surface 11-720B between the epitaxial structures 11-720, 11-730 and the insulating layer 11-782 therebetween, thereby flattening the entire device surface to facilitate the distribution of the metal layer and reduce the resistance. Moreover, the glue layer can also serve as a buffer layer to protect the chip in the subsequent die attach manufacturing process. In addition, due to the application of the glue layer, the thickness of the semiconductor light-emitting element 11-000 can be increased, and the overall capacitance value of the semiconductor light-emitting element 11-000 can be further reduced.

[0748] In one or more embodiments, FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 12-000, such as FIG. 12A to FIG. 12C shown. Fig. 12A FIG. 1 is a schematic top perspective view of a semiconductor light emitting device 12 - 000 according to an embodiment of the present invention. Fig. 12B and Fig. 12C are drawn along Fig. 12A 12B-12B' and 12C-12C' are cross-sectional schematic diagrams of the cross-section shown in the line segment; in this embodiment, as Fig. 12B and Fig. 12C As shown, the semiconductor light emitting element 12-000 is a flip-chip laser element. Solder can be used to subsequently bond the semiconductor light emitting element 12-000 to an external carrier (such as a printed circuit board or a driver chip) using a flip-chip bonding process.

[0749] See also FIG. 12A to FIG. 12C The embodiment shown is a top view and a cross-sectional view of a semiconductor light emitting element 12-000 of another embodiment, wherein Fig. 12A is a top perspective schematic diagram of a semiconductor light emitting element 12-000, Fig. 12B and Fig. 12C are drawn along Fig. 12A Schematic cross-sectional view of the cross-section shown by line segment 12B-12B' and line segment 12C-12C'.

[0750] According to one or more embodiments of the present invention, when forming the light-emitting holes of the semiconductor light-emitting element, the structural design of the light-emitting area can be adjusted to change the positions and number of the light-emitting holes, so as to further increase the light-emitting hole density in the light-emitting area and the flexibility of addressing control, wherein the light-emitting holes are formed by, for example, utilizing a wet oxidation manufacturing process.

[0751] like Fig. 12A In the illustrated embodiment, the semiconductor light emitting element 12-000 includes a plurality of light emitting holes 12-825A, for example, Fig. 12B and Fig. 12C The openings 12-825A1, 12-825A2, 12-825A3, and 12-825A4 shown in the figure are arranged in an array. Fig. 12AIn the top view shown, the multiple openings (light-emitting holes) 12-825A in the semiconductor light-emitting element 12-000 are arranged in a closest packing manner. For example, the multiple light-emitting holes 12-825A are arranged in a hexagonal closest packing manner, that is, six adjacent light-emitting holes 12-825A are formed around each light-emitting hole 12-825A, and each light-emitting hole 12-825A is surrounded by six recessed structures 12-840, wherein the recessed structures 12-840 are used for an oxidation manufacturing process to form a current limiting region in the current limiting layer 12-825 (wherein the current limiting layer 12-825 includes a current limiting layer 12-8251, a current limiting layer 12-8252, a current limiting layer 12-8253, and a current limiting layer 12-8254) in the semiconductor light-emitting element 12-000, but the present invention is not limited to this. In this way, six recess structures 12-840 are evenly distributed (i.e., arranged 60 degrees apart around) in the epitaxial structure of each light-emitting hole. Therefore, by implementing a wet oxidation process through the six recess structures 12-840, a roughly circular opening (i.e., the light-emitting hole of the semiconductor light-emitting element) can be formed in the epitaxial structure of the semiconductor light-emitting element. According to one or more embodiments of the present invention, each recess structure is shared by its adjacent light-emitting holes, so that the multiple light-emitting holes in the semiconductor light-emitting element of the present invention can be arranged in the densest packing manner, thereby increasing the layout space of the light-emitting hole structure in the semiconductor light-emitting element.

[0752] Fig. 12B As shown, in Fig. 12A In the cross section shown by the line segment 12B-12B', there is no concave structure between the openings (i.e., light-emitting holes) 12-825A1 and 12-825A2, that is, the current limiting regions in the current limiting layers 12-8252 and 12-8251 are respectively formed by the outer wall surfaces of the concave structures 12-850A and 12-850B on both sides of the same platform structure 12-826 through a wet oxidation process, so that the openings (i.e., light-emitting holes) 12-825A1 and 12-825A2 are located on the same platform structure 12-826. For example Fig. 12C As shown, in Fig. 12AIn the cross-section shown by the line segment 12C-12C', in addition to the recessed structures 12-850C and 12-850D on the outside, two recessed structures 12-840 are formed between the opening 12-825A3 and the adjacent opening 12-825A4, that is, the outer wall surface of the recessed structure 12-850C and the side wall surface of the recessed structure 12-840 are processed by a wet oxidation process to form a current limiting region in the current limiting layer 12-8253 to define the opening 12-825A3; the side wall surface of the recessed structure 12-840 and the outer wall surface of the recessed structure 12-850D are processed by a wet oxidation process to form a current limiting layer 12-8254 to define the opening 12-825A4. In one embodiment, two adjacent openings may share a concave structure therebetween, or there may be only one concave structure between two adjacent openings, so as to further reduce the distance between the adjacent openings and make the light-emitting holes of the semiconductor light-emitting element more closely arranged.

[0753] like Fig. 12B and Fig. 12C As shown, the semiconductor light emitting element 12-000 of this embodiment further includes a metal connection layer 12-040 located between the platform structure 12-326 and the base layer 12-010. Fig. 12B and Fig. 12C As shown, the semiconductor light emitting element 12-000 of this embodiment further includes a bonding layer 12-901, and the above-mentioned platform structure 12-326 is connected to the base layer 12-010 through the bonding layer 12-901. Fig. 12B and Fig. 12C As shown, the semiconductor light emitting element 12-000 of this embodiment also includes an insulating layer 12-090, which covers the side and upper surface of the epitaxial structure, and the insulating layer 12-090 is transparent to the light emitted from each epitaxial structure.

[0754] In one or more embodiments, FIG. 3A to FIG. 3E , FIG. 4A to FIG. 4D , FIG. 5A to FIG. 5D as well as FIG. 6A to FIG. 6D The semiconductor device 32 shown may be a semiconductor light emitting device 13-000, such as Fig.13 shown. Fig.13It is a cross-sectional schematic diagram of a semiconductor light-emitting element according to one embodiment. In this embodiment, a semiconductor light-emitting element 13-000 is provided. The semiconductor light-emitting element 13-000 includes a semiconductor stacking layer 13-200 formed on a growth substrate 13-900, and the semiconductor stacking layer 13-200 includes a semiconductor layer 13-206, an active layer 13-204 and a semiconductor layer 13-202 in sequence located on the growth substrate 13-900. Then, a portion of the epitaxial columnar structure P13 to be subsequently formed on the semiconductor light-emitting element 13-000 is formed to form a corresponding contact structure 13-220. Then, an insulating layer 13-090 is formed on the contact structure 13-220 and the semiconductor stacking layer 13-200 as a protective layer. Then, an etching process is performed to form a through hole U13, thereby exposing the end face of the growth substrate 13-900, wherein the shape of the through hole is not limited; in other words, the shape of the through hole can be a circular arc columnar hole, a polygonal columnar hole or a columnar hole of any shape. Next, an etching process is performed to form an epitaxial columnar structure P13 and a recessed structure 13-104 to expose a portion of the end surface of the semiconductor layer 13-206. The epitaxial columnar structure P13 has a side surface PB13.

[0755] Next, a current limiting layer is formed in the epitaxial columnar structure P13 using a wet oxidation process. In this embodiment, a current limiting layer 13-225 is formed between the semiconductor layer 13-202 and the active layer 13-204, and the current limiting layer 13-225 includes a current limiting region 13-225B and a current conduction region 13-225A surrounded by the current limiting region 13-225B. The insulating layer 13-090 is formed in the through hole U13 and the recessed structure 13-104, and covers the side surface PB13 of the epitaxial columnar structure P13, the end face of the semiconductor layer 13-206, and the end face of the growth substrate 13-900. Next, an insulating layer opening 13-090A is formed in the insulating layer 13-090 to expose a portion of the surface of the contact structure 13-220, wherein the top view shape of the insulating layer opening 13-090A may be, for example, an annular shape, a circular shape, an elliptical shape, a square shape, an irregular shape, etc. In this embodiment, when viewed from above, the shape of the insulating layer opening 13-090A is annular, but not limited to this.

[0756] Next, a metal connection layer 13-040 is formed on the insulating layer 13-090, and the metal connection layer 13-040 covers the insulating layer 13-090 and fills the insulating layer opening 13-090A to connect with the contact structure 13-220, thereby further electrically connecting with the semiconductor layer 13-202. The metal connection layer 13-040 has a connection layer opening 13-040A above the epitaxial columnar structure P13, and the position of the connection layer opening 13-040A corresponds to the position of the current conduction area 13-225A, and exposes the insulating layer 13-090 below. Next, the epitaxial columnar structure P13 and the semiconductor layer 13-206 are bonded to the substrate 13-100 through the bonding layer 13-901. In the present embodiment, the substrate 13-100 is a permanent substrate.

[0757] Next, a portion of the growth substrate 13-900 is removed to expose a portion of the surface of the metal connection layer 13-040 and the insulating layer 13-090. In the present embodiment, the growth substrate 13-900 is, for example, a GaAs substrate. Next, an electrode connection layer 13-420 is formed on the growth substrate 13-900. Next, an insulating layer 13-082 is formed to cover a portion of the electrode connection layer 13-420. A plurality of openings 13-082A and 13-082B are provided in the insulating layer 13-082 to respectively expose at least a portion of the electrode connection layer 13-420 and the metal connection layer 13-040.

[0758] Finally, the openings 13-082A and 13-082B are filled with conductive materials to form the electrode structures 13-105 and 13-106 of the semiconductor light emitting element, respectively. Fig.13 shown.

[0759] See also Fig.13A and Fig. 13B , which is a cross-sectional schematic diagram and a top schematic diagram of a chip packaging structure according to an embodiment of the present invention, wherein Fig.13A It is along Fig. 13B The schematic structure shown in line 13A-13A'. Fig.13AAs shown, the package structure 13'-000 includes a substrate 13'-110 and a bracket 13'-120 located on the first surface 13'-110A of the substrate 13'-110; the substrate 13'-110 is used to support the package structure 13'-000, and includes electrical conductive pillars 13'-111, 13'-112, 13'-113, and 13'-114 that extend through the substrate 13'-110 and extend to the second surface 13'-110B of the substrate 13'-110, so as to provide electrical conduction between the package structure 13'-000 and the outside. The bracket 13'-120 is disposed on the first surface 13'-110A of the substrate 13'-110, and a chip area 13'-120A is enclosed on the first surface 13'-110A of the substrate 13'-110. The packaging structure 13'-000 includes a chipset disposed in the chip area 13'-120A and electrically connected to the substrate 13'-110, wherein the chipset includes a first chip 13'-130 and a second chip 13'-140 arranged opposite to each other, wherein the active surface 13'-140A of the second chip 13'-140 is opposite to the active surface 13'-130A of the first chip 13'-130.

[0760] In this embodiment, the bracket 13'-120 is a conductive bracket, which includes a first electrically conductive structure 13'-121 and a second electrically conductive structure 13'-122 running through it, and surrounds a first chip 13'-130 located on the first surface 13'-110A; wherein the height H13 of the bracket 13'-120 is greater than the thickness T13 of the first chip 13'-130, and the second chip 13'-140 is disposed on the bracket 13'-120 and is electrically connected to the substrate 13'-110 through the first electrically conductive structure 13'-121 and the second electrically conductive structure 13'-122. In detail, as described above, the substrate 13'-110 includes electrical conductive pillars 13'-111, 13'-112, 13'-113, 13'-114 extending therethrough to the second surface 13'-110B of the substrate 13'-110, wherein the electrical conductive pillars 13'-111, 13'-112 are respectively connected to the first conductive structure 13'-131 and the second conductive structure 13'-132 of the first chip 13'-130, so that the first chip 13'-130 is electrically connected to the package structure 13'-00 0's external circuit (not shown in the figure), and the electrically conductive columns 13'-113 and 13'-114 are respectively connected to the first electrically conductive structure 13'-121 and the second electrically conductive structure 13'-122 in the bracket 13'-120, so that the second chip 13'-140 located on the bracket 13'-120 is electrically connected to the external circuit of the packaging structure 13'-000 via the first electrically conductive structure 13'-121 and the second electrically conductive structure 13'-122, and the electrically conductive columns 13'-113 and 13'-114.

[0761] And participate Fig. 13B The second chip 13'-140 also includes a connection layer 13'-14, and the connection layer 13'-14 includes a plurality of first alignment connection structures 13'-141, a plurality of second alignment connection structures 13'-142, and a first conductive connection structure 13'-143 and a second conductive connection structure 13'-144, wherein the second chip 13'-140 is connected to the first and second electrical conduction structures 13'-121 and 13'-122 of the bracket 13'-120 with its first and second conductive connection structures 13'-143 and 13'-144, respectively, and the first and second electrical conduction structures 13'-121 and 13'-122 are further connected to the second electrical conduction columns 13'-113 and 13'-114 of the substrate 13'-110, respectively, thereby forming an electrical connection between the second chip 13'-140 and the external circuit of the package structure 13'-000; the connection layer 13' -14, the first and second alignment connection structures 13'-141, 13'-142 do not form electrical conduction, and are aligned with the first conductive connection structure 13'-143 and the second conductive connection structure 13'-144, respectively, for positioning the second chip 13'-140 in the packaging structure 13'-000. The first and second alignment connection structures 13'-141, 13'-142 are asymmetrically designed, so that the gripping forces formed on the chip by the alignment connection structures on both sides are different, thereby preventing the chip from shifting during the alignment process. The asymmetrical design includes the first alignment connection structure 13'-141 and the second alignment connection structure 13'-142 having different structural quantities and / or different relative positions (for example, the spacing between two adjacent first alignment connection structures 13'-141 is different from the spacing between two adjacent second alignment connection structures 13'-142), but is not limited to these.

[0762] In this embodiment, the first chip 13'-130 is a light emitting chip, such as a light emitting diode or a laser diode, and the active surface of the light emitting chip is the light emitting surface; the second chip 13'-140 is a light receiving chip, such as a photovoltaic (PV) chip or a photodiode (Photodiode) chip, and the active surface of the light receiving chip is the light receiving surface or the photosensitive surface. In this embodiment, the first chip 13'-130 can be a vertical cavity surface emitting laser (Vertical Cavity Surface Emitting Laser, VCSEL) chip or a flip chip laser chip (Flip Chip Laserdiode). However, the present invention is not limited to this. In other embodiments, the first chip is a light receiving chip, and the second chip is a light emitting chip.

[0763] In the present embodiment, the active surface 13'-130A (emitting surface) of the first chip 13'-130 is opposite to the active surface 13'-140A (receiving surface) of the second chip 13'-140, and the active surface 13'-140A (receiving surface) of the second chip 13'-140 receives the light from the first chip 13'-130, and its area is larger than the area of ​​the active surface 13'-130A (emitting surface) of the first chip 13'-130. In the present embodiment, the active surface 13'-130A (emitting surface) of the first chip 13'-130 and the active surface 13'-140A (receiving surface) of the second chip 13'-140 are separated by a distance D13-1, and the size of this distance D13-1 depends on the application of the packaging structure and / or the optoelectronic characteristics of the first chip and the second chip. In this embodiment, the distance D13-1 between the active surface 13'-130A (transmitting surface) of the first chip 13'-130 and the active surface 13'-140A (receiving surface) of the second chip 13'-140 is between 1 micrometer (μm) and 30 micrometers.

[0764] See also Fig.14A , which is a cross-sectional side view of a chip packaging structure according to another embodiment of the present invention. Fig.14A As shown, the package structure 14-000 has Fig.13A The composition and structure of the packaging structure 13'-000 are similar; however, the difference is that in the packaging structure 14-000, the first chip 13'-130 is a vertical chip, that is, the first conductive structure 13'-231 and the second conductive structure 13'-232 are respectively located on the opposite surfaces of the first chip 13'-130; wherein the first conductive structure 13'-231 is connected to the first electrical conductive column 13'-211, and the second conductive structure 13'-232 located on the active surface 13'-130A (emitting surface) of the first chip 13'-130 is connected to the first electrical conductive column 13'-212 via a connecting wire 13'-234. In this embodiment, the first chip 13'-130 is electrically connected to the substrate 13'-110 through the connection between the first conductive structure 13'-231 and the first electrical conductive column 13'-211, and the second conductive structure 13'-232 is electrically connected to the first electrical conductive column 13'-212 through the connecting wire 13'-234, thereby electrically conducting the outside of the packaging structure 14-000.

[0765] See also Fig. 14B and Fig. 14C 1 is a top view and a cross-sectional view of a chip packaging structure according to an embodiment of the present invention. Fig. 14C It is along Fig. 14B The cross-sectional schematic structure shown in line 14A-14A'; Fig. 14CAs shown, the first chip 13'-130 is a vertical chip, that is, the first conductive structure 13'-231 and the second conductive structure 13'-232A, 13'-232B are respectively located on opposite surfaces of the first chip 13'-130, wherein the second conductive structures 13'-232A, 13'-232B are respectively located on the two side areas of the active surface 13'-130A of the first chip 13'-130. In this embodiment, the second conductive structures 13'-232A, 13'-232B on the first chip 13'-130 and the first conductive connection structure 13'-143 and the second conductive connection structure 13'-144 on the second chip 13'-140 are arranged in different orientations, thereby avoiding the height of the metal bonding wire (i.e., the connecting wire 13'-234) required for the first chip 13'-130 from limiting the distance D13-2 between the first chip 13'-130 and the second chip 13'-140.

[0766] Preferably, see Fig. 14C , the distance DP13 between the second conductive structure 13'-232A and the second conductive structure 13'-232B on both side areas of the first chip 13'-130, and the width WC13 of the second chip 13'-140, the distance DP13 is greater than the width WC13, thereby avoiding the height formed by the metal bonding wire (i.e., the connecting wire 13'-234) required for the first chip 13'-130 to limit the distance D13-2 between the first chip 13'-130 and the second chip 13'-140, and avoiding the connecting wire 13'-234 from accidentally touching the second chip 13'-140, but the present invention is not limited to this.

[0767] See also Fig.15 , which is a cross-sectional side view of a chip packaging structure according to another embodiment of the present invention. Fig.15 As shown, the package structure 15-000 has Fig.13A The package structure 13'-000 of FIG. 15-000 is similar in composition and structure; however, the difference is that in the package structure 15-000, the bracket 13'-320 is not a conductive bracket (that is, no electrical conductive structure is formed in the bracket to penetrate therethrough), but is simply used to support the entire component. In this embodiment, the second chip 13'-140 is a horizontal chip, that is, its conductive connection structure is located on the same side of the chip; Fig.15As shown, the first conductive connection structure 13'-343 and the second conductive connection structure 13'-344 are also located on the opposite surface 13'-140B of the active surface 13'-140A (receiving surface) of the second chip 13'-140, and are electrically connected to the electrical conductive pillars 13'-113 and 13'-114 of the substrate 13'-110 via the conductive wires 13'-345 and 13'-346, respectively. In other words, in this embodiment, the conductive wires 13'-345 and 13'-346 are respectively connected between the first conductive connection structure 13'-343 and the electrical conductive pillar 13'-113, and between the second conductive connection structure 13'-344 and the electrical conductive pillar 13'-114, so that the second chip 13'-140 is electrically connected to the substrate 13'-110, thereby electrically conducting the outside of the package structure 15-000.

[0768] See also Fig.16 , which is a cross-sectional side view of a chip packaging structure according to another embodiment of the present invention. Fig.16 As shown, the package structure 16-000 has Fig.15 The package structure 15-000 is similar in composition and structure; however, the difference is that in the package structure 16-000, the first conductive structure 16-431 and the second conductive structure 16-432 are located on opposite surfaces of the first chip 16-430, wherein the first conductive structure 16-431 is connected to the first electrical conductive column 16-411, and the second conductive structure 16-432 located on the emission surface 16-430A of the first chip 16-430 is connected to the first electrical conductive column 16-412 via a wire 16-434; Fig.14A Similar to the embodiment, the first chip 16-430 of the package structure 16-000 is a vertical chip, which is electrically connected to the substrate 16-110 through the connection between the first conductive structure 16-431 and the first electrical conductive column 16-411, and the second conductive structure 16-432 is connected to the first electrical conductive column 16-412 through the connecting wire 16-434, thereby electrically conducting the outside of the package structure 16-000.

[0769] See also Fig.17, which is a cross-sectional schematic diagram of a chip packaging structure of another embodiment of the present invention. In this embodiment, the packaging structure 17-000 is a photoelectric conversion element of wafer-level packaging; that is, the first chip 17-30 and the second chip 17-40 in the packaging structure 17-000 are combined by a wafer-to-wafer bonding process. In some embodiments, the photoelectric conversion element includes an optical transformer, wherein the photoelectric conversion element can utilize the principle of photoelectric conversion to convert the input voltage magnitude into a different voltage magnitude output. For example, after first converting the electrical signal into an optical signal through the first chip, the optical signal is converted back into an electrical signal of a different voltage magnitude or a different current magnitude through the second chip.

[0770] like Fig.17 As shown, in this embodiment, the package structure 17-000 includes a substrate 17-10, the substrate 17-10 has a first surface 17-10A and a second surface 17-10B opposite to each other, and at least two first electrical conductive pillars 17-11, 17-12 and at least two second electrical conductive pillars 17-13, 17-14 running therethrough. The package structure 17-000 includes a chip set disposed on the first surface 17-10A of the substrate 17-10 and consisting of a first chip 17-30 and a second chip 17-40 disposed opposite to each other; in this embodiment, the first chip 17-30 and the second chip 17-40 are bonded to the light-transmitting intermediate layer 17-80 therebetween through a first bonding layer 17-71 and a second bonding layer 17-72, respectively, wherein the receiving surface of the second chip 17-40 is opposite to the emitting surface of the first chip 17-30 to receive the light emitted by the first chip 17-30. In this embodiment, the first electrically conductive columns 17-11 and 17-12 of the substrate 17-10 electrically connect the first chip 17-30 to the outside of the photoelectric conversion element (i.e., the packaging structure 17-000), and the second electrically conductive columns 17-13 and 17-14 electrically connect the second chip 17-40 to the outside of the photoelectric conversion element (i.e., the packaging structure 17-000).

[0771] In detail, in this embodiment, the first chip 17-30 includes a third surface 17-30A facing the first surface 17-10A, and a fourth surface 17-30B facing the first surface 17-10A and opposite to the third surface 17-30A; the second chip 17-40 includes a fifth surface 17-40A facing the fourth surface 17-30B, and a sixth surface 17-40B facing the fourth surface 17-30B and opposite to the fifth surface 17-40A, wherein the fourth surface 17-30B is the emitting surface of the first chip 17-30, and the fifth surface 17-40A is the receiving surface of the second chip 17-40. The package structure 17-000 of this embodiment further includes a first conductive structure 17-31 and a second conductive structure 17-32, which are located on the third surface 17-30A of the first chip 17-30 and connected to the first electrically conductive pillars 17-11 and 17-12, so that the first chip 17-30 is electrically connected to the first electrically conductive pillars 17-11 and 17-12 of the substrate 17-10, and the first chip 17-30 is thus electrically conductive to the outside of the photoelectric conversion element (i.e., the package structure 17-000); the package structure 17-0 00 also includes a first conductive connection structure 17-43 and a second conductive connection structure 17-44, which are located on the sixth surface 17-40B and are connected to the second electrically conductive columns 17-13 and 17-14 via a first connecting wire 17-45 and a second connecting wire 17-46, respectively, so that the second chip 17-40 is electrically connected to the second electrically conductive columns 17-13 and 17-14 of the substrate 17-10, and the second chip 17-40 is thereby electrically conductive to the outside of the photoelectric conversion element (i.e., the packaging structure 17-000).

[0772] In this embodiment, the first bonding layer 17-71 and the second bonding layer 17-72, and / or the light-transmitting intermediate layer 17-80 in the packaging structure 17-000 may be made of an electrically insulating material. Fig.13A The packaging structure 13'-000 is packaged using a wafer-to-wafer bonding process, which can further reduce the distance between the first chip 17-30 and the second chip 17-40 to reduce the overall volume of the packaging structure 17-000, which is beneficial to the application of small-size devices.

[0773] See also Fig.18 , which is a cross-sectional schematic diagram of a chip packaging structure according to another embodiment of the present invention. Fig.18 As shown, the package structure 18-000 has Fig.17The packaging structure 17-000 has a similar composition and structure, and is also a wafer-level packaged photoelectric conversion element; but the difference is that in the packaging structure 18-000, the first chip 17-30 is a vertical chip rather than a flip-chip in the packaging structure 17-000, and the width of the first chip 17-30 is greater than the width of the second chip 17-40.

[0774] In detail, in the present embodiment, the packaging structure 18-000 includes a first conductive structure 17-31 and a second conductive structure 17-32, 17-32' respectively located on the third surface 17-30A and the fourth surface 17-30B of the first chip 17-30, wherein the first conductive structure 17-31 is connected to the first electrically conductive column 17-11, and the second conductive structures 17-32, 17-32' are connected to the first electrically conductive columns 17-12, 17-12' through corresponding connecting wires 17-34, 17-34', thereby making the first chip 17-30 electrically connected to the substrate 17-10 to generate electrical conduction of the first chip 17-30 to the outside of the photoelectric conversion element (i.e., the packaging structure 18-000); as for the method of establishing electrical conduction of the second chip 17-40 to the outside of the photoelectric conversion element (i.e., the packaging structure 18-000), it is the same as Fig.17 The embodiments shown are identical.

[0775] In this embodiment, when manufacturing the package structure, a plurality of second chips are bonded to the cut light emitting layer to form a first wafer (not shown) having a plurality of first chips, and then the first wafer is cut. Thereafter, a first conductive structure and a second conductive structure are formed on the obtained structure, and the first chip is mounted on a substrate. In one embodiment, the first chip and the second chip are electrically connected to the substrate via connecting wires, thereby completing the package structure of this embodiment.

[0776] As described above, the second chip is connected to the first chip by chip to wafer bonding. Similarly, the first chip can also be connected to the second chip by chip to wafer bonding; that is, multiple first chips are bonded to a second wafer having multiple second chips, and the second wafer is cut. After forming a first conductive connection structure and a second conductive connection structure on the resulting structure, and mounting and electrically connecting them to the substrate, the chip packaging structure of the present invention is formed, wherein the width of the second chip is greater than the width of the first chip. In one embodiment, after the packaging is completed, the chip made from an epitaxial wafer (first wafer or second wafer) with a higher yield is located close to the substrate.

[0777] See also Fig.19, which is a cross-sectional schematic diagram of a chip packaging structure of another embodiment of the present invention. In the present embodiment, the first chip 17-30 and the second chip 17-40 in the packaging structure 19-000 are both horizontal chips; the difference between the present embodiment and the aforementioned embodiment is that in the packaging structure 19-000 of the present embodiment, the first chip 17-30 and the second chip 17-40 are connected to each other through a spacer layer 17-90, and are electrically isolated from each other by the spacer layer 17-90. Among them, the spacer layer 17-90 can be a light-transmitting layer, such as a light-transmitting intermediate layer, and the spacer layer can be a single-layer structure or a multi-layer structure, but the present invention is not limited thereto. In the present embodiment, the electrical connection method of the first chip 17-30 and the second chip 17-40 to the substrate 17-10 is the same as Fig.17 The embodiment shown is the same; that is, in the package structure 19-000 of the present embodiment, the first conductive structure 17-31 and the second conductive structure 17-32 are located on the third surface 17-30A of the first chip 17-30 and are connected to the first electrically conductive pillars 17-11 and 17-12, so that the first chip 17-30 is electrically connected to the first electrically conductive pillars 17-11 and 17-12 of the substrate 17-10, and the first chip 17-30 is thus electrically connected to the external electrical connection of the photoelectric conversion element (i.e., the package structure 19-000). The first conductive connection structure 17-43 and the second conductive connection structure 17-44 are located on the sixth surface 17-40B, and are connected to the second electrically conductive columns 17-13 and 17-14 via the first connecting wire 17-45 and the second connecting wire 17-46 respectively, so that the second chip 17-40 is electrically connected to the second electrically conductive columns 17-13 and 17-14 of the substrate 17-10, and the second chip 17-40 is thereby electrically conductive to the outside of the photoelectric conversion element (i.e., the packaging structure 19-000).

[0778] In this embodiment, the spacer layer and the first chip can be sequentially epitaxially grown on the second chip. The material of the spacer layer can be a semiconductor with a low doping concentration (for example, a doping concentration between 1×10 15 cm -3 Up to 5×10 16 cm -3 ), and has a high resistance value. In one embodiment, the material of the spacer layer can be AlGaAs produced by oxidation. 2 O 3 .

[0779] See also Fig. 20 , which is a cross-sectional schematic diagram showing a partial structure of a chip packaging structure according to another embodiment of the present invention. Fig. 20 As shown, Fig. 20 The package structure 20-000 shown is oriented in the same direction as Fig.13AThe package structure 13'-000 is shown upside down. In this embodiment, the first chip may be a VCSEL chip, and the second chip may be a PV chip. For the purpose of clarity, Fig. 20 Most of the structures or layers of the first chip 20-30 are not shown, and only the second semiconductor structure 20-206 and a plurality of columnar structures (eg, Fig. 20 As shown, the columnar structures P2012, P2013, P2014 located in block A20-1, and the columnar structures P2022, P2023, P2024 located in block A20-2).

[0780] like Fig. 20 As shown, multiple columnar structures P2012, P2013, P2014, P2022, P2023, and P2024 of the first chip 20-30 are arranged on the second high platform structures 20-421 and 20-422 of the second chip 20-40; specifically, in this embodiment, the columnar structures P2012, P2013, and P2014 of the first chip 20-30 are aligned with the second high platform structure 20-421 in the second chip 20-40, and the columnar structures P2022, P2023, and P2024 of the first chip 20-30 are aligned with the second high platform structure 20-422 of the second chip 20-40. In other words, in this embodiment, the first chip 20-30 and the second chip 20-40 can be bonded together, and the light-emitting area of ​​the first chip 20-30 (the area where the columnar structures P2012, P2013, P2014 are located and the area where the columnar structures P2022, P2023, P2024 are located) and the light-collecting area of ​​the second chip 20-40 (the second high platform structure 20-421 and the second high platform structure 20-422) are in a one-to-one correspondence; however, considering the electrodes and wiring space of the second chip 20-40, the size of the light-collecting area of ​​the packaging structure may be slightly smaller than the light-emitting area.

[0781] In this embodiment, if Fig. 20 As shown, the distance d203 between the columnar structure P2014 in the block A20-1 and the columnar structure P2022 in the block A20-2 is greater than the width W203 of the groove portion 20-321A, and the distance d204 between the leftmost columnar structure P2012, P2022 and the rightmost columnar structure P2014, P2024 in each block A20-1, A20-2 is equal to or less than the width W204 of the sixth opening 20-470A of the electrode layer. In other words, the light emitted by all the columnar structures P2012, P2013, P2014, P2022, P2023, P2024 in the blocks A20-1, A20-2 of the first chip 20-30 can be completely received by the second high platform structures 20-421, 20-422.

[0782] See also Fig.21 , which is a cross-sectional schematic diagram of a chip packaging structure of another embodiment of the present invention. As shown in the figure, the packaging structure 21-000 includes a first chip 21-30 and a second chip 21-40 located on a substrate 21-10, wherein the first chip 21-30 and the second chip 21-40 are both horizontal chips. The first chip 21-30 and the second chip 21-40 are connected to each other and electrically isolated via a spacer layer 21-90 located therebetween. The spacer layer 21-90 and the first chip 21-30 can be sequentially formed on the second chip 21-40 by epitaxial growth. As described above, the material of the spacer layer 21-90 is a semiconductor material with low doping concentration and high resistance value.

[0783] In this embodiment, the first chips 21-30 may be laser chips. Fig.21 As shown, the first chip 21-30 includes a first semiconductor structure 21-21, a second semiconductor structure 21-22, and an active structure 21-23 located between the first semiconductor structure 21-21 and the second semiconductor structure 21-22. The first chip 21-30 includes a first contact layer 21-24 covering the second semiconductor structure 21-22, and the first contact layer 21-24 is connected to the first conductive structure 21-31 to form an electrical connection. The first chip 21-30 also includes a second contact layer 21-25, which connects the first semiconductor structure 21-21 and the second conductive structure 21-32 to form an electrical connection.

[0784] The second chip 21-40 may be a photovoltaic chip. Fig.21 As shown, the high platform structure of the second chip 21-40 includes a first semiconductor structure 21-41, an active structure 21-42, a second semiconductor structure 21-43, and contacts 21-44 and 21-45 for forming electrical connections; the contacts 21-45 and 21-46 of two adjacent high platform structures are connected by a connecting layer 21-50, and the two high platform structures of the second chip 21-40 are connected in series. In addition, the first conductive structures 21-31 and 21-31' of two adjacent first chips 21-30 are connected by a first connecting structure 21-60, and the two adjacent first chips 21-30 are connected in parallel. In other words, in this embodiment, the first conductive structures 21-31 and 21-31' of two adjacent first chips 21-30 are electrically connected to each other via the first connecting structure 21-60; similarly, the second conductive structures 21-32 and 21-32' of two adjacent first chips 21-30 are electrically connected to each other via a second connecting structure (not shown).

[0785] Fig.22A and Fig. 22BSchematic diagram of the shape of the first chip in the chip packaging structure of the two embodiments of the present invention. As shown in the figure, the first chip in the packaging structure of the present invention can be formed into a cylindrical shape, such as Fig.22A The first chip 21-30A shown in the figure may be, for example, a VCSEL chip; or may be formed in a cubic shape, such as Fig. 22B The first chip 21-30B shown in the figure may be, for example, an LED chip. Fig.22A The first chip 21-30A shown is Fig. 22B The first chips 21-30B shown may have exactly the same composition, but Fig. 22B The effective light emitting area of ​​the first chip 21-30B is larger than Fig.22A The first chip 21-30A shown can make the package structure of the present invention have a higher energy conversion efficiency. The light emitting element material of the present invention can be GaAs or GaN.

[0786] Fig.23A and Fig. 23B 1 is a top view and a cross-sectional view of a chip packaging structure according to another embodiment of the present invention, wherein Fig. 23B For along Fig.23A In this embodiment, as shown in the figure, the first chip is a vertical chip, and the second chip is a horizontal chip, and the size of the second chip is smaller than the first chip. Fig.17The package structure 17-000 shown in FIG. 1 is similar in configuration to the package structure 17-000; however, the difference is that, in the present embodiment, the first conductive connection structure 23-43 and the second conductive connection structure 23-44 of the package structure 23-000 are located on the side of the second chip 23-40 facing the first chip 23-30. In addition, there are conductive structures 23-35 and 23-36 on the first chip 23-30, which are electrically connected to the first conductive connection structure 23-43 and the second conductive connection structure 23-44 of the second chip 23-40 through the bonding structure 23-50, respectively. The conductive structures 23-35 and 23-36 are electrically isolated from the first conductive structure 23-31 and the second conductive structure 23-32 of the first chip 23-30, and can provide a positioning function to align the first chip 23-30 and the second chip 23-40 in the package. The packaging structure 23-000 of this embodiment also includes bonding pads 23-37 and 23-38 electrically connected to the first conductive connection structure 23-43 and the second conductive connection structure 23-44, and the second chip 23-40, wherein the bonding pads 23-37 and 23-38 and the first conductive structure 23-31 are electrically connected to the electrical conductive column (not shown) of the packaging substrate through the corresponding connecting wire CW. In this embodiment, the packaging structure 23-000 also includes a bottom filler (Underfill) 23-95, which is located between the first chip 23-30 and the second chip 23-40 to further fix the first chip 23-30 and the second chip 23-40. In this embodiment, the bottom filler 23-95 can be a dielectric material and / or a light-transmitting material, such as BCB (Bisbenzocyclobutene).

[0787] In this embodiment, the first chip 23-30 and the second chip 23-40 are bonded via chip to wafer bonding. During the packaging process, the plurality of second chips 23-40 are bonded to a first wafer (not shown) of the plurality of first chips 23-30 via the bonding structure 23-50. Then, an underfill 23-95 is applied between the first chip 23-30 and the second chip 23-40, and then the chips are cut and the resulting chip set (including the first chip 23-30 and the second chip 23-40) is mounted on a substrate (e.g. Fig.13A The substrate 13'-110, Fig.17 On the substrate 17-10), the packaging structure 23-000 of the present invention is obtained.

[0788] In another embodiment, the size of the first chip is smaller than that of the second chip, and the chipset is mounted on the substrate 23-10 by flip chip method. Fig.23CIt is a cross-sectional schematic diagram of a chip packaging structure of another embodiment. As shown in the figure, the first chip is a vertical chip, and the second chip is a horizontal chip, and the size of the first chip is smaller than that of the second chip. There are conductive structures 23-35 and 23-36 on the first chip 23-30, which are electrically connected to the first conductive connection structure 23-43 and the second conductive connection structure 23-44 of the second chip 23-40 through the bonding structure 23-50 respectively. There are conductive structures 23-45 and 23-46 on the second chip 23-40, which are electrically connected to the substrate 23-10 through the bonding structure 23-60. In this embodiment, it also includes an underfill 23-95, which is located between the first chip 23-30 and the second chip 23-40 to further fix the first chip 23-30 and the second chip 23-40. In this embodiment, the underfill can be a dielectric material and / or a light-transmitting material, such as BCB (Bisbenzocyclobutene).

[0789] See also Fig.24A and Fig. 24B . Fig.24A The photoelectric converter 24-000 includes a plurality of units, each of which is substantially rectangular, but the present invention is not limited thereto. In this exemplary embodiment, each unit is connected in series to serve as a high-voltage photoelectric converter. Fig. 24B Draw along Fig.24A The photoelectric converter 24-000 includes a light emitting portion 24-200 having an electrode sheet and a light receiving portion 24-100 having an electrode sheet, wherein at least a portion of the light emitting portion 24-200 faces at least a portion of the light receiving portion 24-100. In one embodiment, as Fig. 24BAs shown, the photoelectric converter 24-000 may further include a metal core printed circuit board (MCPCB) 24-300 electrically connected to the electrode sheet of the light emitting part 24-200 and / or the electrode sheet of the light receiving part 24-100 through a conductive structure 24-610. In one or more embodiments, the photoelectric converter 24-000 may further include an underfill 24-500, which is located between the light emitting part 24-200 and the light receiving part 24-100 to further fix the light emitting part 24-200 and the light receiving part 24-100. In this embodiment, the underfill 24-500 may be a dielectric material and / or a light-transmitting material, such as BCB (Bisbenzocyclobutene) adhesive. The light emitting part 24-200 includes an epitaxial layer 24-210. In one or more embodiments, the epitaxial layer 24-210 may be the aforementioned VCSEL chip. In one or more embodiments, the light emitting portion 24-200 may further include a heat dissipation layer, such as a metal layer 24-220 located between the epitaxial layer 24-210 and the metal core printed circuit board 24-300. In one or more embodiments, if the emission wavelength of the light emitting portion 24-200 is 840nm (but not limited to this), the light receiving portion 24-100 will be designed to receive incident light of the same wavelength. The light receiving portion 24-100 includes an optoelectronic epitaxial layer 24-110, a transparent base layer 24-120, a mirror layer 24-130, and a plurality of conductive layers 24-141, 24-142 (wherein each conductive layer 24-141, 24-142 may be one or more layers). The transparent base layer 24-120 may be sapphire or glass, but is not limited to this. The photoepitaxial layer 24-110 and the plurality of conductive layers 24-141 and 24-142 are formed on the same side of the transparent base layer 24-120, while the mirror layer 24-130 is formed on the opposite side of the transparent base layer 24-120. The plurality of conductive layers 24-142 are electrically connected to the conductive structure 24-620 of the metal core printed circuit board 24-300 through the bonding structure 24-420, wherein a portion of the plurality of conductive layers 24-142 respectively serve as the positive electrode and the negative electrode of the light receiving part 24-100, and another portion of the plurality of conductive layers 24-142 are connected to the conductive layer 24-141 and connected to the conductive layer 24-221 of the light emitting part 24-200 through the bonding structure 24-410, serving as one of the electrodes (e.g., the negative electrode) of the light emitting part 24-200. In some embodiments, the conductive structure 24-620 of a portion of the metal core printed circuit board 24-300 can also be one of the electrodes (e.g., the negative electrode) of the epitaxial layer 24-210, and the conductive structure 24-610 can be used as another electrode (e.g., the positive electrode) of the epitaxial layer 24-210.

[0790] In one or more embodiments, the photoelectric converter includes a light emitting part and a light receiving part, each part has multiple units and is electrically connected through different circuit designs to convert input voltage and input current into different output voltages and output currents, such as Fig.25A as well as Fig.25B shown. Fig.25A as well as Fig.25B 1 and 1 are schematic diagrams of equivalent circuits of a high voltage photoelectric converter and a low voltage photoelectric converter. For a specific output voltage and output current, both the output voltage and the output current can be optimized by the circuit design of the light emitting unit and the light receiving unit. In one or more embodiments, the light receiving unit includes a plurality of VCSEL units and the light receiving unit includes a plurality of photoelectric units, but this is not limiting. Fig.25A as well as Fig.25B In one or more embodiments, the number of light emitting units may be equal to the number of light receiving units, but this is not a limitation. Fig.25A In the embodiment shown, the plurality of VCSEL units of the light emitting part are electrically connected in parallel, and the plurality of photoelectric units of the light receiving part are electrically connected in series to serve as a high voltage optical transformer (HVOT). Fig.25A In the embodiment shown, the input terminal ( Fig.25A The VCSEL units (represented by the circuit symbol of a diode) of the light emitting part of the lower side) are connected in parallel with each other to have a smaller voltage and a larger current, and the VCSEL units at the output end ( Fig.25A The photoelectric units (represented by the circuit symbol of a diode) of the light receiving part of the upper side) are connected in series with each other to have a larger voltage and a smaller current, so that a small voltage can be converted into a large voltage to serve as a high-voltage photoelectric converter. Fig.25B In another embodiment shown in FIG. 1 , the plurality of VCSEL units of the light emitting part are electrically connected in series, and the plurality of photoelectric units of the light receiving part are electrically connected in parallel to each other, so as to serve as a low voltage optical transformer (LVOT). Fig.25B In the embodiment shown, the input terminal ( Fig.25B The VCSEL units (represented by the circuit symbol of a diode) of the light emitting part of the lower side) are connected in series with each other to have a larger voltage and a smaller current, and the VCSEL units (represented by the circuit symbol of a diode) at the output end ( Fig.25B The photoelectric units (represented by the circuit symbol of a diode) of the light receiving part of the upper side) are connected in parallel with each other to have a smaller voltage and a larger current, so that the large voltage can be converted into a small voltage to serve as a low-voltage photoelectric converter.

[0791] In such Fig.24AIn one embodiment shown, the unit of the photoelectric converter is substantially rectangular. The detailed layout design can be referred to Fig.26A . See Fig.26A , is a top perspective schematic diagram illustrating a rectangular unit 26 - 000A of a photoelectric converter according to an embodiment. Fig.26A The unit layout may be an emitting unit, a VCSEL unit, a receiving unit or a photoelectric unit, and the light emitting area or the light receiving area may be located at the center of each unit, but it is not limited thereto. Specifically, according to some embodiments, in the rectangular unit 26-000A, the first rectangular area 26-001A is a P-type semiconductor layer defining the unit (emitting unit or receiving unit), the second rectangular area 26-002A is a high platform structure (composed of an active layer and an N-type semiconductor layer) of the epitaxial layer defining the unit (emitting unit or receiving unit), the circular area 26-003A is a light emitting area defining the emitting unit or a light receiving area defining the receiving unit, and the long strip areas 26-004A and 26-005A respectively define the P conductive connection pad and the N conductive connection pad of the unit (emitting unit or receiving unit). As Fig.26A As shown, in one embodiment, the light emitting area of ​​the transmitting unit or the light receiving area of ​​the receiving unit is closer to the N conductive connection pad of the unit (transmitting unit or receiving unit) and farther away from the P conductive connection pad of the unit (transmitting unit or receiving unit). In addition, in one embodiment, the lengths of the side lengths L261A and L262A of the rectangular unit 26-000A are 0.082 mm and 0.064 mm respectively. Fig.26B as well as Fig.26C , are top perspective schematic diagrams of hexagonal units 26-000B and 26-000C of a photoelectric converter according to an embodiment. The units of the photoelectric converter are defined by unit boundaries 26-000B1 and 26-000C1 of the hexagonal units 26-000B and 26-000C, such as Fig.26B as well as Fig.26C As shown. Fig.26BAs shown, in the hexagonal unit 26-000B, the first hexagonal region 26-001B is an insulating structure (composed of a P-type semiconductor layer) defining the unit (transmitting unit or receiving unit), the second hexagonal region 26-002B is a high platform structure (composed of an active layer and an N-type semiconductor layer) of the epitaxial layer defining the unit (transmitting unit or receiving unit), the circular region 26-003B is a light-emitting region defining the transmitting unit or a light-receiving region defining the receiving unit, and the long strip regions 26-004B and 26-005B respectively define the P conductive connection pad and the N conductive connection pad of the unit (transmitting unit or receiving unit). In addition, in one embodiment, the side length L261B, side length L262B and side length L263B of the hexagonal unit 26-000B are 0.0443 mm, 0.0393 mm and 0.0443 mm, respectively, and the inner angle A261, inner angle A262 and inner angle A263 of the hexagonal unit 26-000B are 136 degrees, 112 degrees and 112 degrees, respectively. In some embodiments, two relatively short side lengths of the six side lengths in the hexagonal unit 26-000B are located in opposite positions, and the two relatively short side lengths are approximately equal to each other, and the other four relatively long side lengths are also approximately equal. In some embodiments, two relatively large internal angles of the six internal angles in the hexagonal unit are located in opposite positions, and the two relatively large internal angles are approximately equal to each other, and the angles of the other four relatively small internal angles are also approximately equal. In the hexagonal unit 26-000C, similarly, the first hexagonal region 26-001C is an insulating structure (composed of a P-type semiconductor layer) defining the unit (transmitting unit or receiving unit), the polygonal region 26-002C is a high platform structure (composed of an active layer and an N-type semiconductor layer) defining the epitaxial layer of the unit (transmitting unit or receiving unit), the circular region 26-003C is a light-emitting region defining the transmitting unit or a light-receiving region defining the receiving unit, and the long strip regions 26-004C and 26-005C respectively define the P conductive connection pad and the N conductive connection pad of the unit (transmitting unit or receiving unit). It should be noted that, if Fig.26CAs shown, in the present embodiment, a portion of the boundaries of the polygonal region 26-002C of the high platform structure of the epitaxial layer defining the unit (transmitting unit or receiving unit) corresponds to the light-emitting region / light-collecting region and has a rounded structure. In addition, in the present embodiment, the first hexagonal region 26-001C of the P-type semiconductor layer defining the unit (transmitting unit or receiving unit) may also have a rounded structure (that is, the shape of the first hexagonal region 26-001C is substantially hexagonal). In one or more embodiments, the multiple units are arranged in a rectangular grid configuration, wherein the shape of the unit boundary is substantially rectangular. In one or more embodiments, the multiple units are arranged in a hexagonal grid configuration, wherein the shape of the unit boundary is substantially hexagonal. In one or more embodiments, the multiple units are arranged in a polygonal grid configuration, wherein the shape of the unit boundary is substantially polygonal. In such as Fig.26B as well as Fig.26C In the embodiment shown, the shape of the hexagonal unit boundary is a hexagon that is symmetrical on the X-axis and the Y-axis. The hexagonal unit boundary, the light receiving area, and the light emitting area are design lines that will not appear on the final product, so these lines are dashed lines in the following figures. Fig.26B In the illustrated embodiment, the hexagonal unit may further include a hexagonal platform structure (i.e., the second hexagonal region 26-002B) and a hexagonal insulating structure (i.e., the first hexagonal region 26-001B), but is not limited thereto. The shapes of the platform structure and the insulating structure may be substantially hexagonal or substantially polygonal. The polygonal platform structure may be biased toward the direction of one of the conductive connection pads (for example, toward the N conductive connection pad of the unit (transmitting unit or receiving unit)). The hexagonal insulating structure maintains a fixed distance from the platform structure and the P electrode to ensure voltage insulation. In one or more embodiments, the hexagonal platform structure may not be designed as Fig.26C The hexagon shown.

[0792] See also Fig.27A , is a top perspective view of a plurality of hexagonal units 26-000B of a photoelectric converter according to an embodiment. Fig.27AIn one or more embodiments shown, the side lengths (L261B, L262B, L263B) and the inner angles (A261, A262, A263) of the hexagonal unit 26-000B can be adjusted based on: (1) the diameter of the light emitting area or the light receiving area, (2) the line width Wpl of the conductive connection pad, and (3) the spacing Gi between the insulating structures. The symmetrical hexagonal units 26-000B can be closely arranged in a hexagon. For light emitting areas or light receiving areas with the same diameter, the overall chip size can be reduced by 10-20% compared to the rectangular unit design through the design of the hexagonal unit 26-000B. In some embodiments, among the multiple hexagonal units of the photoelectric converter, the multiple hexagonal units in odd rows have the same arrangement direction, and the multiple hexagonal units in even rows have the same arrangement direction, wherein the arrangement direction of the multiple hexagonal units in odd rows is opposite to the arrangement direction of the multiple hexagonal units in even rows, for example, in Fig.27A In the embodiment shown, the electrodes of the first row of hexagonal cells 26-000B are arranged in the order of PNPN... from the left to the right of the figure, and the electrodes of the second row of hexagonal cells 26-000B are arranged in the order of NPNP... from the left to the right of the figure, and the electrodes of the third row of hexagonal cells 26-000B are arranged in the order of PNPN... from the left to the right of the figure, so that the hexagonal cells 26-000B are arranged in an S shape to be designed into different series or parallel situations. For example, in some embodiments, the hexagonal cells 26-000B in the first row and the hexagonal cells 26-000B in the second row can form a unit group, and the hexagonal cells 26-000B in the third row and the hexagonal cells 26-000B in the fourth row can form another unit group, so that the photoelectric converter has different sections and achieves different voltage conversion combinations. Furthermore, in some embodiments, the aforementioned unit group may correspond to the transmitting unit as the input end and be connected in parallel with each other, and cooperate with the receiving units connected in series with each other as the output end to achieve voltage change (converting a small voltage into a large voltage to serve as a high voltage transformation section), and the aforementioned other unit group may also correspond to the transmitting unit as the input end and be connected in series with each other, and cooperate with the receiving units connected in parallel with each other as the output end to achieve voltage change (for example, converting a large voltage into a small voltage to serve as a low voltage transformation section). In one or more embodiments, Fig.27B is a schematic diagram showing the layout design of rectangular units and hexagonal units with different diameters of light emitting areas or light receiving areas. Specifically, in some embodiments, Fig.27B As shown in (a), the side lengths of the rectangular unit 26-000A are 0.067 mm and 0.049 mm, respectively, and the diameter of the light emitting area or the light receiving area of ​​the rectangular unit 26-000A is 0.025 mm; Fig.27BAs shown in (b), the side lengths of the rectangular unit 26-000A are 0.082 mm and 0.064 mm respectively, and the diameter of the light emitting area or the light receiving area of ​​the rectangular unit 26-000A is 0.04 mm; Fig.27B As shown in (c), the side lengths of the rectangular unit 26-000A are 0.142 mm and 0.124 mm respectively, and the diameter of the light emitting area or the light receiving area of ​​the unit rectangle 26-000A is 0.1 mm. In some embodiments, when the vertical direction of the drawing is defined as the length direction of the hexagonal unit 26-000B and the horizontal direction of the drawing is defined as the width direction of the hexagonal unit 26-000B, as shown in FIG. Fig.27B As shown in (d), the length (L) of the hexagonal unit 26-000B is 0.0542 mm, the width (W) is 0.067 mm, the diameter (D) of the light-emitting area or the light-receiving area of ​​the hexagonal unit 26-000B is 0.025 mm, and the side length (S) corresponding to the length direction of the hexagonal unit 26-000B is 0.0317 mm; Fig.27B As shown in (e), the length (L) of the hexagonal unit 26-000B is 0.0725 mm, the width (W) is 0.082 mm, the diameter (D) of the light-emitting area or the light-receiving area of ​​the hexagonal unit 26-000B is 0.04 mm, and the side length (S) corresponding to the length direction of the hexagonal unit 26-000B is 0.0393 mm; Fig.27B As shown in (f), the length (L) of the hexagonal unit 26-000B is 0.1422 mm, the width (W) is 0.142 mm, the diameter (D) of the light-emitting area or the light-receiving area of ​​the hexagonal unit 26-000B is 0.1 mm, and the side length (S) corresponding to the length direction of the hexagonal unit 26-000B is 0.0727 mm.

[0793] Next, the plurality of hexagonal units 26-000B may be electrically connected in series or in parallel, such as Fig.27C or Fig.27D See Fig.27C , is a top perspective view of a plurality of hexagonal units 26-000B of a photoelectric converter according to an embodiment connected in series. Fig.27D , is a top perspective view of a plurality of hexagonal units 26-000B of a photoelectric converter according to an embodiment connected in parallel. Fig.27C When the series circuit is connected in series through the conductive connection structure Cs as shown, the series circuit is designed to operate at high voltage and low current. Fig.27D In another embodiment shown, the plurality of hexagonal units 26-000B are connected in parallel to each other via a conductive connection structure Cs, and the parallel circuit is designed to operate at low voltage and high current.

[0794] See also Fig.28A . Fig.28A The relationship between the top view and the cross-sectional layout of the hexagonal unit 26-000B is shown. Fig.28A (a) is a top perspective schematic diagram of a hexagonal unit 26-000B electrically connected via a conductive connection structure Cs, Fig.28A (b) is along Fig.28A Schematic cross-sectional view of the hexagonal unit 26-000B along the section line AA' of (a). In this embodiment, the hexagonal unit 26-000B can be designed for an optoelectronic chip or a VCSEL chip. Fig.28A (a) and Fig.28A As shown in (b), two hexagonal units 26-000B are connected in series through a conductive connection structure Cs. The first hexagonal region 26-001B is an insulating structure (composed of a P-type semiconductor layer 26-P) that defines the unit (transmitting unit or receiving unit), the second hexagonal region 26-002B is a high platform structure (composed of an active layer 26-A and an N-type semiconductor layer 26-N) that defines the epitaxial layer of the unit (transmitting unit or receiving unit), the circular region 26-003B defines the light-emitting area of ​​the transmitting unit or the light-receiving area of ​​the receiving unit, and the long strip regions 26-004B and 26-005B respectively define the P conductive connection pad 26-PP and the N conductive connection pad 26-NP of the unit (transmitting unit or receiving unit). The conductive connection structure Cs can be a metal layer or other conductive materials. As Fig.28A (b) shows that the adhesive layer 26-U is located between the base layer 26-S and the epitaxial layer (from bottom to top, the P-type semiconductor layer 26-P, the active layer 26-A and the N-type semiconductor layer 26-N), and the passivation layer 26-PA is located between the epitaxial layers of adjacent hexagonal units 26-000B, and the passivation layer 26-PA has an opening, so that the P conductive connection pad 26-PP and the N conductive connection pad 26-NP of the adjacent hexagonal unit 26-000B can be electrically connected through the opening through the conductive connection structure Cs. In some embodiments, the material of the adhesive layer 26-U can be BCB. In some embodiments, a protective layer 26-PA2 (such as BCB or other passivation materials) can be further provided on the P conductive connection pad 26-PP and the N conductive connection pad 26-NP to prevent the hexagonal unit 26-000B (such as a light-emitting unit) from interfering with its corresponding unit (such as a light-receiving unit). In one or more embodiments, the P conductive connection pad (first electrode), the N conductive connection pad (second electrode) and the conductive connection structure Cs can be manufactured by three different manufacturing processes, but it is not limited thereto. In another embodiment, the N conductive connection pad (second electrode) and the conductive connection structure Cs can be manufactured by the same manufacturing process.

[0795] In such Fig.28B In one embodiment shown, a schematic diagram of a chip layout 28-000 of a high voltage optical-to-electrical converter (HVOT) is shown, wherein the light receiving portion is a plurality of hexagonal units connected in series (for example, the aforementioned Fig.28A The hexagonal units 26-000B shown in FIG. 26-000B) can be closely arranged in a hexagonal shape. Fig.28B As shown, in addition to the light receiving portion composed of hexagonal units, the chip layout 28-000 also includes a plurality of first connection structures and a plurality of second connection structures. In this embodiment, the chip layout 28-000 includes four first connection structures and four second connection structures. In this embodiment, the chip layout 28-000 includes four first connection structures and four second connection structures. Fig.28B The four first connection structures at the upper left, lower left, upper right and lower right of the 28-100 are respectively the first connection structure 28-100(R), the first connection structure 28-100(E), the first connection structure 28-100(E), and the first connection structure 28-100(R); Fig.28B The four second connection structures at the upper left, lower left, upper right and lower right of the 28-200 are respectively the second connection structure 28-200(D), the second connection structure 28-200(E), the second connection structure 28-200(E), and the second connection structure 28-200(D); located at Fig.28B The four joint structures 24-410 at the upper left, lower left, upper right and lower right of the device are respectively a joint structure 24-410(D), a joint structure 24-410(E), a joint structure 24-410(E) and a joint structure 24-410(D); Fig.28B The four joint structures 24-420 at the upper left, lower left, upper right and lower right of the EM are respectively a joint structure 24-420(R), a joint structure 24-420(E), a joint structure 24-420(E) and a joint structure 24-420(R). Fig.28B As shown, in this embodiment, the first connection structure (i.e., located at Fig.28B The first connection structures 28-100(R), the first connection structures 28-100(E), the first connection structures 28-100(E), the first connection structures 28-100(R)) on the upper left, lower left, upper right and lower right respectively include a first platform structure 28-110, a second platform structure 28-120, a conductive connection structure Cs and a bonding structure 24-420 (see Fig. 24B ), the hexagonal units 26-000B of the light receiving portion can be connected to an external circuit board (e.g. Fig. 24B The second connection structure (i.e., located at Fig.28BThe upper left, lower left, upper right and lower right second connection structures 28-200(D), second connection structures 28-200(E), second connection structures 28-200(E), second connection structures 28-200(D)) respectively include a first platform structure 28-210, a second platform structure 28-220, a conductive connection structure Cs and a bonding structure 24-410 (see Fig. 24B ), the hexagonal units 26-000B of the light receiving part can be connected to the light emitting part through the bonding structure 24-410 (E). Fig.28B As shown, the first connection structure 28-100 (E) located at the upper right corner and the second connection structure 28-200 (E) located at the lower left corner are connected together to have a common first platform structure 28-110 / 28-210 and a common second platform structure 28-120 / 28-220. The conductive connection structure Cs is formed on the common second platform structure 28-120 / 28-220 and connects the bonding structure 24-410 (E) and the bonding structure 24-420 (E). The complete high-voltage photoelectric converter may further include a light emitting portion having the same hexagonal unit arrangement, and the light emitting portion is electrically connected to the light receiving portion through a conductive connection pad. Fig.28B The dotted box corresponds to the location of the light emitting unit. In some embodiments, the chip layout 28-000 further includes a protective layer 26-PA2 to prevent the hexagonal unit 26-000B (e.g., a light emitting unit) and its corresponding unit (e.g., a light receiving unit) from interfering with each other, and also to prevent the separated first connection structure and the second connection structure from being electrically connected to each other and short-circuiting. The material of the protective layer 26-PA2 can be an insulating material, including but not limited to silicon oxide and silicon nitride.

[0796] In some embodiments, a semiconductor laser is provided. The gain spectrum of the active structure of the semiconductor laser is expanded by adjusting the element composition ratio, material thickness, and material type of the quantum well layer of the active structure. Accordingly, even when the ambient temperature is lowered (e.g., lowered to -40°C) or raised (e.g., raised to 80°C), the peak position of the resonance wavelength of the emitted light of the semiconductor laser can still correspond to the relative peak of the gain spectrum of its active structure.

[0797] FIG. 29A to FIG. 29C as well as FIG. 29D to FIG. 29F are diagrams respectively showing the relationship between the gain spectrum of the active structure and the resonance wavelength of the emitted light of the semiconductor laser at different temperatures for semiconductor lasers known to the inventor and semiconductor lasers according to some embodiments of the present invention; FIG. 29A to FIG. 29C The semiconductor laser known to the inventors is respectively Fig.29A )、T2( Fig.29B ) and T3( Fig.29C) is a graph showing the relationship between the gain spectrum of the active structure and the resonance wavelength of the emitted light of the semiconductor laser at three different temperatures; and FIG. 29D to FIG. 29F are respectively the semiconductor lasers according to some embodiments of the present invention at T1( Fig.29D )、T2( Fig.29E ) and T3( Fig.29F ) is a graph showing the relationship between the gain spectrum of the active structure and the resonant wavelength of the emitted light of the semiconductor laser at three different temperatures.

[0798] Depend on FIG. 29A to FIG. 29C It can be known that, for the semiconductor laser known to the inventor, when operating at T2, the peak position of the resonant wavelength of the emitted light of the semiconductor laser basically corresponds to the relative peak of the gain spectrum of its active structure; however, since temperature changes will cause changes in the energy level of the active structure and cause the distributed Bragg reflector (DBR) and the optical cavity (Cavity) or the active structure of the semiconductor laser to change their optical thickness due to thermal expansion and contraction, and the degree of influence of temperature changes on the energy level change of the active structure and the change in the optical thickness of the DBR and the optical cavity (Cavity) or the active structure is different, when the temperature changes (for example, decreases to T1 or increases to T3), the peak position of the resonant wavelength of the emitted light of the semiconductor laser will no longer correspond to the relative peak of the gain spectrum of its active structure, thereby causing the maximum light extraction efficiency of the semiconductor laser to deteriorate.

[0799] See also FIG. 29D to FIG. 29F On the other hand, for the semiconductor laser according to some embodiments of the present invention, when operating at T2, the peak position of the resonant wavelength of the emission light of the semiconductor laser also basically corresponds to the relative peak of the gain spectrum of its active structure; and when the temperature changes (for example, decreases to T1 or increases to T3), the gain spectrum of the active structure of the semiconductor laser is expanded by adjusting the material composition ratio, material thickness and material type of the quantum well layer of the active structure, so that the peak position of the resonant wavelength of the emission light of the semiconductor laser can still correspond to the relative peak of the gain spectrum of its active structure.

[0800] Fig.30 FIG. 2 is a cross-sectional view of a semiconductor laser 30-000 according to an embodiment. Fig.30As shown, in some embodiments, the semiconductor laser 30-000 includes a first-type semiconductor layer 30-100, a second-type semiconductor layer 30-200, an active structure 30-300 and a spacer layer 30-380. The active structure 30-300 and the spacer layer 30-380 are stacked to form a vertical space as an optical resonance cavity 30-400. The first-type semiconductor layer 30-100 has a light-emitting hole 30-110. The active structure 30-300 is located between the first-type semiconductor layer 30-100 and the second-type semiconductor layer 30-200. The spacer layer 30-380 includes a first spacer layer 30-381 and a second spacer layer 30-382, the first spacer layer 30-381 is located between the first-type semiconductor layer 30-100 and the active structure 30-300, and the second spacer layer 30-382 is located between the second-type semiconductor layer 30-200 and the active structure 30-300. The active structure 30-300 includes a first quantum well layer 30-310, a second quantum well layer 30-320, and a barrier layer structure (barrier layer) 30-390 located between the first quantum well layer 30-310 and the second quantum well layer 30-320, the second quantum well layer 30-320 is farther away from the light-emitting hole 30-110 than the first quantum well layer 30-310, and the emission wavelength of the second quantum well layer 30-320 is different from the emission wavelength of the first quantum well layer 30-310. In some embodiments, the total thickness of the optical resonant cavity 30-400 is an integer multiple (nλp) of the peak value (λp) of the resonant wavelength of the semiconductor laser 30-000, where n is a positive integer.

[0801] In some embodiments, the active structure 30-300 of the semiconductor laser 30-000 has at least two or more quantum well layers that can emit light of different wavelengths (for example, but not limited to Fig.30 The first quantum well layer 30-310 and the second quantum well layer 30-320 are shown, wherein the emission spectrum emitted by the semiconductor laser 30-000 includes at least two or more peaks, wherein the peak intensities of different wavelengths are not necessarily the same.

[0802] In some embodiments, the first type semiconductor layer 30-100 and the second type semiconductor layer 30-200 may include a distributed Bragg reflector (DBR) structure. In some embodiments, the Bragg reflector structure may be formed by alternately stacking two or more film layers with different refractive indices, such as AlAs / GaAs, AlGaAs / GaAs, AlGaAs / AlGaAs or InGaP / GaAs.

[0803] In some embodiments, there is also a barrier layer structure 30-390 (not shown) between the first type semiconductor layer 30-100 and the first quantum well layer 30-310 and between the second type semiconductor layer 30-200 and the second quantum well layer 30-320. In some embodiments, there may also be a barrier layer structure 30-390 between the first spacer layer 30-381 and the first quantum well layer 30-310 or between the second spacer layer 30-382 and the second quantum well layer 30-320.

[0804] In some embodiments, the difference between the emission wavelength of the second quantum well layer 30 - 320 and the emission wavelength of the first quantum well layer 30 - 310 ranges from 2 nanometers to 20 nanometers.

[0805] In some embodiments, the materials of the first quantum well layer 30-310 and the second quantum well layer 30-320 include III-V compound semiconductors. For example, the III-V compound semiconductors may be binary compositions, such as InP, GaAs, InSb, GaN, GaSb, etc.; ternary compositions, such as InGaAs, InGaP, AlGaAs, InGaN, etc.; quaternary compositions, such as AlGaInP, InGaAsP, InGaAsN, etc.; quinary compositions, such as InGaAsSbN, AlInGaAsN, etc.

[0806] Furthermore, for the semiconductor laser 30-000 emitting red light, the materials of the first quantum well layer 30-310 and the second quantum well layer 30-320 are selected from the group consisting of: Al S Ga T As W P X (where 0≤S≤1, 0≤T≤1, 0≤W≤1, 0≤X≤1) and Al S Ga T In V As W P X (where 0≤S≤1, 0≤T≤1, 0≤V≤1, 0≤W≤1, 0≤X≤1); For the semiconductor laser 30-000 emitting infrared light, the materials of the first quantum well layer 30-310 and the second quantum well layer 30-320 are selected from the group consisting of: Al S Ga T As W P X (where 0≤S≤1, 0≤T≤1, 0≤W≤1, 0≤X≤1) and Ga T In V As W P X(where 0≤T≤1, 0≤V≤1, 0≤W≤1, 0≤X≤1); For the semiconductor laser 30-000 emitting near-infrared light, the materials of the first quantum well layer 30-310 and the second quantum well layer 30-320 are selected from the group consisting of: Al S Ga T In V As W P X Sb Y N Z (where 0≤S≤1, 0≤T≤1, 0≤W≤1, 0≤X≤1, 0≤Y≤1, 0≤Z≤1).

[0807] In the embodiments of the present invention, if not otherwise specified, the chemical formula includes "compounds that meet stoichiometric standards" and "compounds that do not meet stoichiometric standards", wherein "compounds that meet stoichiometric standards" are, for example, compounds whose total element content of group III elements is the same as that of group V elements, whereas "compounds that do not meet stoichiometric standards" are, for example, compounds whose total element content of group III elements is different from that of group V elements. For example, a chemical formula of AlGaAs means that it includes group III elements aluminum (Al) and / or gallium (Ga), and group V elements arsenic (As), wherein the total element content of group III elements (aluminum and / or gallium) may be the same as or different from the total element content of group V elements (arsenic).

[0808] In some embodiments, the material types of the first quantum well layer 30-310 and the second quantum well layer 30-320 may be different; in other words, the materials of the first quantum well layer 30-310 and the second quantum well layer 30-320 may include different III-V compound semiconductors. For example, the first quantum well layer 30-310 includes InGaAs, and the second quantum well layer 30-320 includes InGaN.

[0809] In some embodiments, the material type of the first quantum well layer 30-310 and the second quantum well layer 30-320 may be the same but the element composition ratio is different; in other words, the material of the first quantum well layer 30-310 and the second quantum well layer 30-320 may include the same III-V compound semiconductor, but the element ratio of the III-V compound semiconductor of the first quantum well layer 30-310 and the second quantum well layer 30-320 is different. For example, the first quantum well layer 30-310 includes In 0.3 Ga 0.7 As, and the second quantum well layer 30-320 contains In 0.4 Ga 0.6 As.

[0810] Therefore, according to some embodiments, by changing the material type or element composition ratio of the first quantum well layer 30-310 and the second quantum well layer 30-320, the emission wavelengths of the first quantum well layer 30-310 and the second quantum well layer 30-320 can be different.

[0811] In some embodiments, the barrier layer structure 30-390 is made of GaAs, AlGaAs, GaAsP, AlInGaAs, and has a thickness ranging from 3 nm to 20 nm. In some embodiments, the spacer layer 30-380 and the barrier layer structure 30-390 may be made of the same material or different materials.

[0812] In some embodiments, by changing the thickness of the quantum well layer, the first quantum well layer 30 - 310 and the second quantum well layer 30 - 320 can also have different light emission wavelengths.

[0813] Specifically, in some embodiments, the thickness of the second quantum well layer 30-320 is ±5% of the thickness of the first quantum well layer 30-310. Taking the first quantum well layer 30-310 as an example, its thickness ranges from 60 angstroms to 80 angstroms. Further, assuming that the thickness of the first quantum well layer 30-310 is 60 angstroms, the thickness of the second quantum well layer 30-320 is 57 angstroms (60×(1-5%)) or 63 angstroms (60×(1+5%)), so that the emission wavelengths of the first quantum well layer 30-310 and the second quantum well layer 30-320 are different (for example, the peak spacing between the emission wavelength of the first quantum well layer 30-310 and the emission wavelength of the second quantum well layer 30-320 can be 5-10 nanometers apart due to the thickness difference), thereby expanding the gain spectrum of the active structure 30-300 of the semiconductor laser 30-000.

[0814] See also Fig.30 In some embodiments, the active structure 30 - 300 has a single-layer first quantum well layer 30 - 310 and a single-layer second quantum well layer 30 - 320 .

[0815] See also Fig.31 , is a cross-sectional schematic diagram of a semiconductor laser 31-000 according to an embodiment. In some embodiments, the active structure 30-300 of the semiconductor laser 31-000 may include a plurality of first quantum well layers 30-310 and a plurality of second quantum well layers 30-320; in addition, the number of the first quantum well layers 30-310 and the number of the second quantum well layers 30-320 may be the same or different. Fig.31 In the embodiment, the first quantum well layer 30-310 is two layers and the second quantum well layer 30-320 is three layers, but it is not limited thereto.

[0816] Fig.32 FIG. 2 is a cross-sectional schematic diagram of a semiconductor laser 32-000 according to an embodiment of the present invention. Fig.33 FIG. 3 is a cross-sectional view of a semiconductor laser 33-000 according to an embodiment. Fig.32 and Fig.33 In some embodiments, the active structure 30-300 of the semiconductor laser 32-000 / 33-000 may further include a third quantum well layer 30-330, located between the second quantum well layer 30-320 and the second type semiconductor layer 30-200, and a barrier layer structure 30-390 is provided between the third quantum well layer 30-330 and the second quantum well layer 30-320. The emission wavelength of the third quantum well layer 30-330 is greater than the emission wavelength of the second quantum well layer 30-320.

[0817] In some embodiments, the materials of the barrier layer structures 30-390 may be the same. Fig.32 As shown in the semiconductor laser 32-000, in some embodiments, the materials of the barrier layer structure 30-390 between the third quantum well layer 30-330 and the second quantum well layer 30-320, the barrier layer structure 30-390 between the first quantum well layer 30-310 and the second quantum well layer 30-320, the barrier layer structure 30-390 between the first-type semiconductor layer 30-100 and the first quantum well layer 30-310, and the barrier layer structure 30-390 between the second-type semiconductor layer 30-200 and the second quantum well layer 30-320 are all the same.

[0818] Alternatively, in some embodiments, the materials of the barrier layer structures may not be completely the same. Fig.33 As shown in the semiconductor laser 33-000, the barrier layer structure 30-391 between the first-type semiconductor layer 30-100 and the first quantum well layer 30-310 and the barrier layer structure 30-391 between the second-type semiconductor layer 30-200 and the third quantum well layer 30-330 may be the same, but different from the barrier layer structure 30-392 between the third quantum well layer 30-330 and the second quantum well layer 30-320 and the barrier layer structure 30-392 between the first quantum well layer 30-310 and the second quantum well layer 30-320.

[0819] In some embodiments, the active structure 30-300 may include multiple first quantum well layers 30-310, multiple second quantum well layers 30-320 and multiple third quantum well layers 30-330; in addition, the number of first quantum well layers 30-310, second quantum well layers 30-320 and third quantum well layers 30-330 may be the same or different.

[0820] Specifically, in some embodiments, the active structure 30-300 can be a multiple quantum well layer, wherein multiple first quantum well layers 30-310 together constitute a first group of quantum well layers, multiple second quantum well layers 30-320 together constitute a second group of quantum well layers, and multiple third quantum well layers 30-330 together constitute a third group of quantum well layers.

[0821] Among them, a barrier layer structure 30-390 is provided between multiple first quantum well layers 30-310 of the first group of quantum well layers, a barrier layer structure 30-390 is provided between multiple second quantum well layers 30-320 of the second group of quantum well layers, and a barrier layer structure 30-390 is also provided between multiple third quantum well layers 30-330 of the third group of quantum well layers. The materials of the barrier layer structures 30-390 of different groups of quantum well layers may be the same or different, and the thicknesses of the barrier layer structures 30-390 of different groups of quantum well layers may also be the same or different.

[0822] Fig.34 FIG. 3 is a cross-sectional view of a semiconductor laser 34-000 according to an embodiment. Fig.34 In the semiconductor laser 34-000 of this embodiment, the first group of quantum well layers 30-310G has three first quantum well layers 30-310, the second group of quantum well layers 30-320G has two second quantum well layers 30-320, and the third group of quantum well layers 30-330G has three third quantum well layers 30-330.

[0823] In some embodiments, there may also be a tunnel junction (TJ) between quantum well layers of different groups, and the tunnel junction is composed of a highly doped semiconductor layer (which may be highly doped with a group III compound or a group V compound). When current passes through the active structure 30-300, carriers (electrons or holes) move between quantum well layers of different groups, and the tunnel junction provides a channel so that carriers can cross the energy band barriers between quantum well layers of different groups, making it easier for carriers to diffuse throughout the structure, achieving more efficient carrier injection and radiation recombination. Thereby improving the efficiency and performance of the light-emitting element. In addition, the tunnel junction can also affect the operating voltage characteristics. By adjusting the doping concentration and material combination of the tunnel junction, the energy band gap between the quantum well layers can be changed, thereby affecting the light-emitting wavelength and spectral characteristics of the active structure 30-300.

[0824] Fig.35 FIG. 3 is a cross-sectional view of a semiconductor laser 35-000 according to an embodiment. Fig.35 In the semiconductor laser 35-000 of this embodiment, a tunnel junction TJ ( Figure 7The second group of quantum well layers 30-320G and the third group of quantum well layers 30-330G also have a tunnel junction TJ of a highly doped semiconductor layer.

[0825] In some embodiments, the thickness of the highly doped semiconductor layer is in a range from 5 nanometers to 20 nanometers.

[0826] In some embodiments, a semiconductor laser is provided. In the manufacturing process, a columnar structure of a specific size is first made to define the light-emitting hole, so that it is not necessary to use a relatively difficult-to-control wet oxygen manufacturing process to make an oxide layer, thereby reducing the spacing between the light-emitting holes of the semiconductor laser, thereby reducing the size of the entire semiconductor laser. Furthermore, because the wet oxygen manufacturing process is not required, the surface of the semiconductor laser can be flattened, so that the aperture of the light-emitting hole is uniform.

[0827] Fig.36 Schematic diagram of the cross-sectional structure of a semiconductor laser 36-000 according to some embodiments of the present invention.

[0828] In some embodiments, Fig.36As shown, the semiconductor laser 36-000 includes a conductive substrate 36-100, a semiconductor stack layer 36-200, a contact electrode layer 36-300, a metal bonding layer 36-400, a plurality of first conductive structures 36-500, a plurality of insulating structures 36-600, a plurality of anti-reflective structures 36-700, and a plurality of second conductive structures 36-800. The semiconductor stack layer 36-200 is located on the conductive substrate 36-100, wherein the semiconductor stack layer 36-200 includes: a first type semiconductor layer 36-210, a second type semiconductor layer 36-220, and an active structure 36-230. The active structure 36-230 is located between the first type semiconductor layer 36-210 and the second type semiconductor layer 36-220. The contact electrode layer 36-300 is located on the conductive substrate 36-100 on one side relative to the semiconductor stack layer 36-200. The metal bonding layer 36-400 is located between the conductive substrate 36-100 and the second type semiconductor layer 36-220 of the semiconductor stack layer 36-200. A plurality of first conductive structures 36-500 are located between the metal bonding layer 36-400 and the second type semiconductor layer 36-220 of the semiconductor stack layer 36-200. A plurality of insulating structures 36-600 extend from the metal bonding layer 36-400 through the second conductive structures 36-800, the second type semiconductor layer 36-220 and the active structure 36-230 and extend to at least a portion of the first type semiconductor layer 36-210, and define the second type semiconductor layer 36-220 and the active structure 36-230 as a plurality of columnar structures 36-240. A plurality of anti-reflective structures 36-700 are located on a side of the first type semiconductor layer 36-210 of the semiconductor stack layer 36-200 relative to the metal bonding layer 36-400 and correspond to the columnar structures 36-240. A plurality of first conductive structures 36-500 are located on a side of the first type semiconductor layer 36-210 of the semiconductor stack layer 36-200 relative to the metal bonding layer 36-400, wherein the first conductive structures 36-500 are located between the anti-reflective structures 36-700 and correspond to the insulating structures 36-600.

[0829] In some embodiments, the first type semiconductor layer 36-210 and the second type semiconductor layer 36-220 may include a distributed Bragg reflector (DBR) structure. In some embodiments, the Bragg reflector structure may be formed by alternately stacking two or more film layers with different refractive indices, such as AlAs / GaAs, AlGaAs / GaAs, InGaP / GaAs, AlInP / AlGaInP, AlGaInP / AlGaInP, InGaP / AlGaAs.

[0830] In some embodiments, the width of the columnar structures 36 - 240 is between 3 microns and 25 microns.

[0831] FIG. 37A to FIG. 37F FIG. 1 is a diagram of a semiconductor laser according to some embodiments of the present invention (for example, but not limited to Fig.36 The cross-sectional structure schematic diagram of multiple steps of the production process of the semiconductor laser 36-000) shown.

[0832] First, see Fig.37A , providing an epitaxial chip. The epitaxial chip includes a semiconductor stack layer 36-200 formed on a base layer 36-090, wherein the semiconductor stack layer 36-200 includes a first-type semiconductor layer 36-210, an active structure 36-230 and a second-type semiconductor layer 36-220 from bottom to top, which are located on the base layer 36-090, wherein the first-type semiconductor layer 36-210 and / or the second-type semiconductor layer 36-220 may be a multi-layer structure, in this embodiment, the first-type semiconductor layer 36-210 is an N-type semiconductor layer, and the second-type semiconductor layer 36-220 is a P-type semiconductor layer. The semiconductor stack layer 36-200 may be epitaxially grown on the base layer 36-090, and the epitaxial method includes but is not limited to metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy, liquid phase epitaxy, etc. The base layer 36-090 includes but is not limited to a III-V material, whose lattice constant matches that of the semiconductor stack layer 36-200. In this embodiment, the material of the base layer 36-090 is gallium arsenide (GaAs). In other embodiments, the material of the base layer 36-090 can be indium phosphide (InP), sapphire, gallium nitride (GaN) or silicon carbide (SiC), etc.

[0833] Next, please continue reading Fig.37A , forming a patterned conductive layer on the base layer 36-090. Then, an etching process is performed on the aforementioned epitaxial chip, and a mask with a specific pattern is used to etch away part of the first-type semiconductor layer 36-210, part of the active structure 36-230 and part of the second-type semiconductor layer 36-220 and expose part of the first-type semiconductor layer 36-210, wherein the etching removal area of ​​the specific pattern does not overlap with the pattern of the conductive layer, thereby forming a plurality of columnar structures 36-240 and a plurality of first conductive structures 36-500 located on the columnar structures 36-240 on the side of the second-type semiconductor layer 36-220 of the epitaxial chip.

[0834] Next, see Fig.37B, forming a protective layer 36-091 covering the surface and side of the columnar structure 36-240. The material of the protective layer 36-091 can be an insulating material, including but not limited to silicon oxide and silicon nitride. In some embodiments, the protective layer 36-091 above the plurality of second conductive structures 36-800 has an opening, exposing at least a portion of the plurality of second conductive structures 36-800.

[0835] Next, see Fig.37C , a non-conductive material is filled into the grooves between the columnar structures 36-240 to form an insulating structure 36-600 to perform a planarization process on the epitaxial chip, so that the insulating structure 36-600 can be substantially flush with the second conductive structure 36-800. For example, the non-conductive material can be B-staged bisbenzocyclobutene (BCB), but is not limited thereto. In addition, in some embodiments, after the non-conductive material is filled into the grooves of the epitaxial chip, a chemical mechanical polishing or etching process can be performed to make the surface of the epitaxial chip flatter.

[0836] Next, see Fig.37D The epitaxial chip formed with the columnar structure 36-240 and the insulating structure 36-600 is bonded to the conductive substrate 36-100 through the metal bonding layer 36-400. In this embodiment, the conductive substrate 36-100 may be a silicon substrate, but is not limited thereto and may also be made of other conductive materials.

[0837] Then, see Fig.37E , remove the base layer 36-090 to expose the first type semiconductor layer 36-210. In this embodiment, the base layer 36-090 is removed by an etching process. In some embodiments, there is an etching stop layer (Etching Stop layer) between the first type semiconductor layer 36-210 and the base layer 36-090, and the etching stop layer is not drawn in the figure. After removing the base layer 36-090, the etching stop layer is then removed to expose the first type semiconductor layer 36-210.

[0838] Then, see Fig.37F , a plurality of anti-reflective structures 36-700 and a plurality of first conductive structures 36-500 are formed on the first type semiconductor layer 36-210.

[0839] Specifically, in some embodiments, an anti-reflective layer is first formed on the first-type semiconductor layer 36-210, and then an etching process is performed on the anti-reflective layer, and a mask with a specific pattern is used to etch away part of the anti-reflective layer to form a plurality of anti-reflective structures 36-700, and then a mask with a specific pattern is used to form a plurality of first conductive structures 36-500 between the anti-reflective structures 36-700 and corresponding to the insulating structure 36-600.

[0840] Alternatively, in other embodiments, a plurality of first conductive structures 36-500 corresponding to the insulating structure 36-600 are first formed on the first semiconductor layer 36-210 using a mask with a specific pattern, and then an anti-reflective layer is formed on the first semiconductor layer 36-210 and the first conductive structure 36-500. Then, an etching process is performed on the anti-reflective layer, and a mask with a specific pattern is used to etch and remove part of the anti-reflective layer to form a plurality of anti-reflective structures 36-700 to expose the plurality of first conductive structures 36-500.

[0841] Finally, please continue reading Fig.37F A contact electrode layer 36 - 300 is formed on a side of the conductive substrate 36 - 100 opposite to the semiconductor stack layer 36 - 200 .

[0842] FIG. 38A to FIG. 38F FIG. 1 is a diagram of a semiconductor laser according to some embodiments of the present invention (for example, but not limited to Fig.36 The cross-sectional structure schematic diagram of multiple steps of the production process of the semiconductor laser 36-000) shown.

[0843] First, see Fig.38A , providing an epitaxial chip. The epitaxial chip includes a semiconductor stacking layer 36-200 formed on a base layer 36-090, and the semiconductor stacking layer 36-200 includes a first type semiconductor layer 36-210, an active structure 36-230 and a second type semiconductor layer 36-220 located on the base layer 36-090 in order from bottom to top.

[0844] Next, please continue reading Fig.38A An etching process is performed on the aforementioned epitaxial chip, and a mask with a specific pattern is used to etch away part of the first-type semiconductor layer 36-210, part of the active structure 36-230 and part of the second-type semiconductor layer 36-220 and expose part of the first-type semiconductor layer 36-210, thereby forming a plurality of columnar structures 36-240 on the second-type semiconductor layer 36-220 side of the epitaxial chip.

[0845] Next, please continue reading Fig.38A , forming a protective layer 36-091 covering the surface and side of the columnar structure 36-240.

[0846] Next, see Fig.38B , non-conductive material is filled into the grooves between the columnar structures 36-240 to form an insulating structure 36-600 to perform a planarization process on the epitaxial chip, so that the surface of the epitaxial chip is substantially flat. In addition, in some embodiments, after the non-conductive material is filled into the grooves of the epitaxial chip, a chemical mechanical polishing or etching process can be performed to make the surface of the epitaxial chip more flat.

[0847] Next, see Fig.38C , and then an etching process is performed on the insulating structure 36-600, and a mask with a specific pattern is used to etch away part of the insulating structure 36-600 and part of the protective layer 36-091 located on the surface of the epitaxial chip, and a plurality of second conductive structures 36-800 are formed, so that the insulating structure 36-600 can be basically flush with the second conductive structure 36-800.

[0848] Next, see Fig.38D , the epitaxial chip formed with the columnar structure 36-240 and the insulating structure 36-600 is bonded to the conductive substrate 36-100 through the metal bonding layer 36-400.

[0849] Then, see Fig.38E , remove the base layer 36-090 to expose the first type semiconductor layer 36-210. In this embodiment, the base layer 36-090 is removed by an etching process. In some embodiments, there is an etching stop layer (Etching Stop layer) between the first type semiconductor layer 36-210 and the base layer 36-090, and the etching stop layer is not drawn in the figure. After removing the base layer 36-090, the etching stop layer is then removed to expose the first type semiconductor layer 36-210.

[0850] Then, see Fig.38F , a plurality of anti-reflective structures 36-700 and a plurality of first conductive structures 36-500 are formed on the first type semiconductor layer 36-210.

[0851] Specifically, in some embodiments, an anti-reflective layer is first formed on the first-type semiconductor layer 36-210, and then an etching process is performed on the anti-reflective layer, and a mask with a specific pattern is used to etch and remove part of the anti-reflective layer to form a plurality of anti-reflective structures 36-700, and then a mask with a specific pattern is used to form a plurality of first conductive structures 36-500 between the anti-reflective structures 36-700 and corresponding to the insulating structure 36-600.

[0852] Alternatively, in other embodiments, a plurality of first conductive structures 36-500 corresponding to the insulating structure 36-600 are first formed on the first semiconductor layer 36-210 using a mask with a specific pattern, and then an anti-reflective layer is formed on the first semiconductor layer 36-210 and the first conductive structure 36-500. Then, an etching process is performed on the anti-reflective layer, and a mask with a specific pattern is used to etch and remove part of the anti-reflective layer to form a plurality of anti-reflective structures 36-700 to expose the plurality of first conductive structures 36-500.

[0853] Finally, please continue reading Fig.38F , forming a contact electrode layer 36 - 300 on a side of the conductive substrate 36 - 100 opposite to the semiconductor stack layer 36 - 200.

[0854] Fig.39 It is a schematic diagram of the cross-sectional structure of a semiconductor laser 39-000 according to some embodiments of the present invention.

[0855] In some embodiments, Fig.39As shown, the semiconductor laser 39-000 includes a light-transmitting substrate 39-100, a semiconductor stacking layer 39-200, a light-transmitting bonding layer 39-400, a plurality of insulating structures 39-600, a plurality of first conductive structures 39-500, a plurality of second conductive structures 39-800, a first electrode structure 39-310, a second electrode structure 39-320 and an insulating layer 39-330. The semiconductor stacking layer 39-200 is located on the light-transmitting substrate 39-100. The semiconductor stacking layer 39-200 includes: a first-type semiconductor layer 39-210, a second-type semiconductor layer 39-220 and an active structure 39-230 located between the first-type semiconductor layer 39-210 and the second-type semiconductor layer 39-220. The light-transmitting bonding layer 39-400 is located between the light-transmitting substrate 39-100 and the first-type semiconductor layer 39-210 of the semiconductor stacking layer 39-200. A plurality of insulating structures 39-600 extend from the second-type semiconductor layer 39-220 of the semiconductor stack layer 39-200 through the active structure 39-230 and at least to a portion of the first-type semiconductor layer 39-210, and define the second-type semiconductor layer 39-220, the active structure 39-230 and a portion of the first-type semiconductor layer 39-210 as a plurality of columnar structures 39-240. A plurality of first conductive structures 39-500 are located between the first-type semiconductor layer 39-210 of the semiconductor stack layer 39-200 and the light-transmitting bonding layer 39-400 and correspond to the insulating structures 39-600. A plurality of second conductive structures 39-800 are located on a side of the second-type semiconductor layer 39-220 of the semiconductor stack layer 39-200 relative to the light-transmitting bonding layer 39-400. The first electrode structure 39-310 is located on the second type semiconductor layer 39-220 of the semiconductor stack layer 39-200 and extends to the side surface 39-201 of the semiconductor stack layer 39-200 to connect at least one of the first conductive structures 39-500, wherein the first electrode structure 39-310 and the first type semiconductor layer 39-210 are electrically connected through the first conductive structures 39-500. In some embodiments, the first electrode structure 39-310 covers at least one columnar structure 39-240. The second electrode structure 39-320 is located on the second type semiconductor layer 39-220 of the semiconductor stack layer 39-200. The insulating layer 39-330 is located between the semiconductor stack layer 39-200 and the first electrode structure 39-310, and between the semiconductor stack layer 39-200 and the second electrode structure 39-320, wherein the insulating layer 39-330 has an opening 39-331, and the second electrode structure 39-320 is further distributed in the opening 39-331 and contacts the second conductive structures 39-800, so that the second electrode structure 39-320 is electrically connected to the second type semiconductor layer 39-220 through the second conductive structures 39-800.

[0856] In some embodiments, the plurality of first conductive structures 39 - 500 and the plurality of columnar structures 39 - 240 do not overlap with each other in vertical projection.

[0857] FIG. 40A to FIG. 40F FIG. 1 is a diagram of a semiconductor laser (for example but not limited to) according to some embodiments of the present invention. Fig.39 The cross-sectional structure schematic diagram of multiple steps in the production process of the semiconductor laser 39-000) shown.

[0858] First, see Fig.40A , providing an epitaxial chip. The epitaxial chip includes a semiconductor stack layer 39-200 formed on a base layer 39-090, and the semiconductor stack layer 39-200 sequentially includes a first-type semiconductor layer 39-210, an active structure 39-230 and a second-type semiconductor layer 39-220 located on the base layer 39-090.

[0859] Next, please continue reading Fig.40A An etching process is performed on the aforementioned epitaxial chip, and a mask with a specific pattern is used to etch away part of the first-type semiconductor layer 39-210, part of the active structure 39-230 and part of the second-type semiconductor layer 39-220 and expose part of the first-type semiconductor layer 39-210, thereby forming a plurality of columnar structures 39-240 on the second-type semiconductor layer 39-220 side of the epitaxial chip.

[0860] Next, please continue reading Fig.40A , forming a protective layer 39-091 covering the surface and side of the columnar structure 39-240, and removing part of the protective layer 39-091 on the surface of the columnar structure 39-240 to expose the second-type semiconductor layer 39-220, wherein the material of the protective layer 39-091 may be an insulating material, including but not limited to silicon oxide and silicon nitride.

[0861] Then, continue to Fig.40A , non-conductive material is filled into the grooves between the columnar structures 39-240 to form an insulating structure 39-600 to perform a planarization process on the epitaxial chip, so that the surface of the insulating structure 39-600 can be substantially flush with the surface of the columnar structure 39-240. For example, the non-conductive material can be benzocyclobutene resin (B-stagedbisbenzocyclobutene, BCB) or photoresist, but is not limited to this. In addition, in some embodiments, after the non-conductive material is filled into the grooves of the epitaxial chip, a chemical mechanical polishing or etching process can be performed to make the surface of the epitaxial chip flatter.

[0862] Then, continue to Fig.40A, a mask with a specific pattern is used to form at least one second conductive structure 39-800 on the insulating structure 39-600 and the columnar structure 39-240. In some embodiments, the second conductive structure 39-800 is electrically connected to the second-type semiconductor layer 39-220 of the plurality of columnar structures 39-240.

[0863] Then, see Fig.40B , the epitaxial chip formed with the columnar structure 39-240 and the insulating structure 39-600 is bonded to the temporary substrate 39-093 through the bonding layer 39-092, and the base layer 39-090 is removed to expose the first type semiconductor layer 39-210. In some embodiments, there is an etching stop layer (EtchingStop layer) between the first type semiconductor layer 39-210 and the base layer 39-090, and the etching stop layer is not drawn in the figure. After removing the base layer 39-090, the etching stop layer is then removed to expose the first type semiconductor layer 39-210.

[0864] Then, see Fig.40C , a mask with a specific pattern is used on the first type semiconductor layer 39-210 to form multiple first conductive structures 39-500 corresponding to the insulating structure 39-600.

[0865] Next, see Fig.40D , a light-transmitting bonding layer 39-400 is formed on the first-type semiconductor layer 39-210, and the epitaxial chip formed with a plurality of first conductive structures 39-500 is bonded to the light-transmitting substrate 39-100 through the light-transmitting bonding layer 39-400. In this embodiment, the light-transmitting substrate 39-100 and the light-transmitting bonding layer 39-400 are materials with high transmittance to the light emitted by the active structure 39-230, wherein the light-transmitting substrate 39-100 may be, for example, sapphire with a transmittance greater than 80%, but this is not limiting. In some embodiments, the light-transmitting bonding layer 39-400 may also be a conductive material layer.

[0866] Then, see Fig.40E , remove the temporary substrate 39-093 and the adhesive layer 39-092. In this embodiment, the temporary substrate 39-093 is removed by etching process, but it is not limited to this.

[0867] Next, see Fig.40F , an etching process is performed on the aforementioned epitaxial chip, and a mask with a specific pattern is used to etch away part of the semiconductor stacking layer 39-200 and expose part of the first conductive structure 39-500, thereby forming a high platform structure of the semiconductor stacking layer 39-200 and defining the side 39-201 of the semiconductor stacking layer 39-200.

[0868] Next, please continue reading Fig.40F , forming an insulating layer 39-330 to cover the mesa structure and the side surface 39-201 of the semiconductor stack layer 39-200. Further forming an opening 39-331 in the insulating layer 39-330 to expose a portion of the second conductive structure 39-800.

[0869] Next, see Fig.40F , forming a second electrode structure 39-320 on the insulating layer 39-330 and covering the opening 39-331, so that the second electrode structure 39-320 is electrically connected to the second type semiconductor layer 39-220 through the second conductive structure 39-800. In addition, forming a first electrode structure 39-310 on the platform structure and extending the first electrode structure 39-310 to form on the surface of the insulating layer 39-330 on the side 39-201 of the semiconductor stack layer 39-200 and the exposed first conductive structure 39-500, so that the first electrode structure 39-310 is electrically connected to the first type semiconductor layer 39-210 through the first conductive structure 39-500, and the first electrode structure 39-310 extends from the second type semiconductor layer 39-220 side to the first type semiconductor layer 39-210 side, and through the side 39-201 of the semiconductor stack layer 39-200 to increase the distribution range of the first electrode structure 39-310.

[0870] Fig.41 Schematic diagram of the cross-sectional structure of a semiconductor laser 41-000 according to some embodiments of the present invention.

[0871] In some embodiments, Fig.41As shown, the semiconductor laser 41-000 includes a conductive substrate 41-100, a semiconductor stacking layer 41-200, a contact electrode layer 41-300, a metal bonding layer 41-400, a plurality of first conductive structures 41-500, a plurality of insulating structures 41-600, a plurality of anti-reflective structures 41-700 and a plurality of second conductive structures 41-800. The semiconductor stacking layer 41-200 is located on the conductive substrate 41-100, wherein the semiconductor stacking layer 41-200 includes: a first type semiconductor layer 41-210, a second type semiconductor layer 41-220 and an active structure 41-230. The active structure 41-230 is located between the first type semiconductor layer 41-210 and the second type semiconductor layer 41-220. The contact electrode layer 41-300 is located on the conductive substrate 41-100 on one side relative to the semiconductor stacking layer 41-200. The metal bonding layer 41-400 is located between the conductive substrate 41-100 and the second type semiconductor layer 41-220 of the semiconductor stack layer 41-200. A plurality of second conductive structures 41-800 are located between the metal bonding layer 41-400 and the second type semiconductor layer 41-220 of the semiconductor stack layer 41-200. A plurality of insulating structures 41-600 extend from the metal bonding layer 41-400 through the second conductive structures 41-800, the second type semiconductor layer 41-220 and the active structure 41-230 and extend to at least a portion of the first type semiconductor layer 41-210, and define the second type semiconductor layer 41-220, the active structure 41-230 and a portion of the first type semiconductor layer 41-210 as a plurality of columnar structures 41-240. A plurality of anti-reflective structures 41-700 are located on a side of the first type semiconductor layer 41-210 of the semiconductor stack layer 41-200 relative to the metal bonding layer 41-400 and correspond to the columnar structures 41-240. A plurality of first conductive structures 41-500 are located on a side of the first type semiconductor layer 41-210 of the semiconductor stack layer 41-200 relative to the metal bonding layer 41-400, wherein the first conductive structures 41-500 are located between the anti-reflective structures 41-700 and correspond to the insulating structures 41-600.

[0872] See also Fig.41 In some embodiments, in order to reduce the possibility of leakage of subsequent semiconductor laser products, after forming the columnar structure 41-240, an atomic layer deposition process can be used to form a protective layer 41-250 to cover the surface and side of the columnar structure 41-240. Compared with the protective layer 41-250 formed by chemical vapor deposition or physical vapor deposition, the protective layer 41-250 formed by the atomic layer deposition process is denser, thereby reducing the possibility of leakage.

[0873] Fig.42Schematic diagram of the cross-sectional structure of a semiconductor laser 42-000 according to some embodiments of the present invention.

[0874] In some embodiments, Fig.42 As shown, the semiconductor laser 42-000 includes a conductive substrate 42-100, a semiconductor stack layer 42-200, a contact electrode layer 42-300, a metal bonding layer 42-400, a plurality of first conductive structures 42-500, a plurality of insulating structures 42-600, a plurality of anti-reflective structures 42-700, and a plurality of second conductive structures 42-800. The semiconductor stack layer 42-200 is located on the conductive substrate 42-100, wherein the semiconductor stack layer 42-200 includes: a first type semiconductor layer 42-210, a second type semiconductor layer 42-220, and an active structure 42-230. The active structure 42-230 is located between the first type semiconductor layer 42-210 and the second type semiconductor layer 42-220. The contact electrode layer 42-300 is located on the conductive substrate 42-100 on one side relative to the semiconductor stack layer 42-200. The metal bonding layer 42-400 is located between the conductive substrate 42-100 and the second type semiconductor layer 42-220 of the semiconductor stack layer 42-200. A plurality of second conductive structures 42-800 are located between the metal bonding layer 42-400 and the second type semiconductor layer 42-220 of the semiconductor stack layer 42-200. A plurality of insulating structures 42-600 extend from the metal bonding layer 42-400 through the second conductive structures 42-800, the second type semiconductor layer 42-220 and the active structure 42-230 and extend to at least a portion of the first type semiconductor layer 42-210, and define the second type semiconductor layer 42-220 and the active structure 42-230 as a plurality of columnar structures 42-240. A plurality of anti-reflective structures 42-700 are located on a side of the first type semiconductor layer 42-210 of the semiconductor stack layer 42-200 relative to the metal bonding layer 42-400 and correspond to the columnar structures 42-240. A plurality of first conductive structures 42-500 are located on a side of the first type semiconductor layer 42-210 of the semiconductor stack layer 42-200 relative to the metal bonding layer 42-400, wherein the first conductive structures 42-500 are located between the anti-reflective structures 42-700 and correspond to the insulating structures 42-600.

[0875] See also Fig.42In other embodiments, after the columnar structure 42-240 is formed, the sidewall of the semiconductor stacked layer 42-200 can also be oxidized by a wet oxygen process, so that the AlGaAs exposed on the sidewall of the semiconductor stacked layer 42-200 is oxidized to become an aluminum oxide layer to reduce leakage. In some embodiments, the second type semiconductor layer 42-220 has an AlGaAs layer with a higher aluminum composition, and after the wet oxygen process, an aluminum oxide layer 42-221 extending longer into the column is formed.

[0876] Furthermore, after the wet oxygen manufacturing process, a protective layer 42-250 may be formed on the surface and side of the columnar structure 42-240, and the protective layer 42-250 may be formed by chemical vapor deposition or physical vapor deposition, or by atomic layer deposition.

[0877] In some embodiments, a photoelectric device is provided, wherein the light emitted by the photoelectric device can correspond to high-frequency applications by turning on the light-emitting element permanently and modulating the switching frequency of the switch unit with a modulation function block.

[0878] In some embodiments, the light emitted by the light emitting element may be further guided to the switch unit through a waveguide unit.

[0879] Therefore, according to some embodiments, since the components of the optoelectronic device are integrated, the overall size of the optoelectronic device can be reduced, thereby improving the application possibility and convenience of the optoelectronic device.

[0880] Fig.43 is a schematic cross-sectional view of an optoelectronic device 43 - 000 according to some embodiments of the present invention.

[0881] According to some embodiments, Fig.43 As shown, the optoelectronic device 43-000 includes a light-emitting unit 43-100, a switch unit 43-200, a light-receiving element, and a driving chip 43-400. The light-emitting unit 43-100 includes a substrate 43-110 and a light-emitting element 43-120 located on one side of the substrate 43-110, wherein the light-emitting element 43-120 is configured to provide a light L431.

[0882] The switch unit 43-200 is located on the light-emitting path of the light L431, wherein the switch unit 43-200 is configured to allow the light L431 to pass through the switch unit 43-200 or be shielded by the switch unit 43-200. The light receiving element is configured to receive a reflected light L432 after the light L431 is irradiated onto an object and reflected by the object. The driver chip 43-400 includes a driver function block 43-410, a modulation function block 43-420, and a signal processing function block 43-430 that are signal-connected to each other.

[0883] The driving functional block 43-410 is electrically connected to the light emitting element 43-120 and the light receiving element, and the modulation functional block 43-420 is electrically connected to the switch unit 43-200 to modulate the switching frequency of the switch unit 43-200. In addition, the signal processing functional block 43-430 is signal-connected to the light receiving element and is configured to analyze the reflected light L432.

[0884] In some embodiments, the light emitting element 43-120 is a vertical cavity surface emitting laser (VCSEL), such as Fig.43 shown.

[0885] like Fig.43 As shown, in some embodiments, the optoelectronic device 43-000 further includes an optical layer 43-500 located on the light exit path. Specifically, in some embodiments, the optical layer 43-500 may have a diffraction optical element (DOE) structure, a micro lens array (Micro Lens Array) structure, a metasurface structure or a metalens structure or a combination of the aforementioned various optical element structures. Among them, the metasurface structure is a nanostructure with multiple periodic arrangements.

[0886] like Fig.43 As shown, in some embodiments, the light receiving element can be integrated into the driver chip 43-400, for example, in the form of a light receiving functional block 43-440. In other words, in some embodiments, the driver chip 43-400 also includes a light receiving functional block 43-440.

[0887] like Fig.43 As shown, in some embodiments, the substrate 43-110 is a transparent substrate, the optical layer 43-500 is located on the transparent substrate, and the switching unit 43-200 is located on the optical layer 43-500.

[0888] Specifically, if Fig.43 As shown, the driver chip 43-400 of the optoelectronic device 43-000 further has a light-emitting area (corresponding to Fig.43 The dotted box on the right) and the light receiving area (corresponding to Fig.43). The switch unit 43-200, the optical layer 43-500, the substrate 43-110, the light-emitting element 43-120, the driving functional block 43-410 and the modulation functional block 43-420 are located on the light-emitting area, and the signal processing functional block 43-430 and the light-collecting functional block 43-440 are located on the light-collecting area.

[0889] Please continue reading Fig.43 In some embodiments, the positive electrode and the negative electrode of the light emitting element 43 - 120 are electrically connected to the driving functional block 43 - 410 through the first conductive structure 43 - 121 and the second conductive structure 43 - 122 respectively.

[0890] In some embodiments, the switch unit 43-200 is electrically connected to the modulation functional block 43-420 through a third conductive structure 43-125. The light emitting element 43-120 and the transparent substrate have a through hole structure 43-124, the inner wall of the through hole structure 43-124 is insulated, and the third conductive structure 43-125 extends through the through hole structure 43-124 to electrically connect the switch unit 43-200 to the modulation functional block 43-420.

[0891] Similarly, in some embodiments, the light-emitting element 43-120 has a through-hole structure (not shown), the inner wall of the through-hole structure is insulated, and the first conductive structure 43-121 and the second conductive structure 43-122 respectively extend through the through-hole structure so that the positive electrode structure and the negative electrode structure of the light-emitting element 43-120 are electrically connected to the driving functional block 43-410.

[0892] It should be noted that in the following embodiments, the optoelectronic device may also have a through-hole structure; however, for the convenience of illustration, the optoelectronic device in the following embodiments does not particularly illustrate its through-hole structure.

[0893] See also Fig.44A , Fig.44A 4 is a cross-sectional schematic diagram illustrating an optoelectronic device 44-000A according to some embodiments of the present invention.

[0894] like Fig.44A As shown in the optoelectronic device 44-000A, in some embodiments, the substrate 43-110 is a transparent substrate, and a portion of the transparent substrate corresponding to the light emitting area of ​​the light emitting element 43-120 has the optical layer 43-500, and the switching unit 43-200 is located on the transparent substrate.

[0895] In other words, in some embodiments, the optical layer 43-500 is a part of the transparent substrate; specifically, the optical layer 43-500 can be manufactured by patterning the portion of the transparent substrate corresponding to the light emitting area of ​​the light emitting element 43-120.

[0896] See also Fig.44B , Fig.44B is a schematic cross-sectional view of an optoelectronic device 44-000B according to some embodiments of the present invention.

[0897] like Fig.44B As shown in the optoelectronic device 44-000B, in some embodiments, the switching unit 43-200 is located on the light-emitting element 43-120, the substrate 43-110 is a transparent substrate, and the optical layer 43-500 is located between the switching unit 43-200 and the transparent substrate.

[0898] See also Fig.45A , Fig.45A 4 is a cross-sectional schematic diagram illustrating an optoelectronic device 45-000A according to some embodiments of the present invention.

[0899] like Fig.45A As shown in the optoelectronic device 45-000A, in some embodiments, the substrate 43-110 is a transparent substrate, the switching unit 43-200 is located on the transparent substrate, and the optical layer 43-500 is located on the switching unit 43-200.

[0900] See also Fig.45B , Fig.45B 45 - 000B is a cross-sectional schematic diagram illustrating some embodiments of the optoelectronic device 45 - 000B of the present invention.

[0901] like Fig.45B As shown in the optoelectronic device 45-000B, in some embodiments, the switch unit 43-200 is located on the light-emitting element 43-120, and the substrate 43-110 is a transparent substrate, which is located between the switch unit 43-200 and the optical layer 43-500.

[0902] It should be noted that, in some embodiments, the relative relationship between the switch unit 43-200, the light emitting element 43-120 and the substrate 43-110 may also be adjusted and is not limited to the embodiments drawn in the accompanying drawings.

[0903] See also Fig.46A , Fig.46A is a schematic cross-sectional view of an optoelectronic device 46-000A according to some embodiments of the present invention.

[0904] like Fig.46AAs shown in the optoelectronic device 46-000A, in some embodiments, the substrate 43-110 is a transparent substrate, the optical layer 43-500 is located on the transparent substrate, the switch unit 43-200 is located on the optical layer 43-500, and the light receiving element 43-300 is located on the side of the light emitting element 43-120 opposite to the transparent substrate. It should be noted that in this embodiment, the light emitting element 43-120 and the light receiving element 43-300 use a conductive structure as a common electrode. Specifically, in this embodiment, the positive electrode and the negative electrode of the light emitting element 43-120 are electrically connected to the driving functional block 43-410 through the first conductive structure 43-121 and the common conductive structure 43-123, respectively, and the positive electrode and the negative electrode of the light receiving element 43-300 are electrically connected to the driving functional block 43-410 through the second conductive structure 43-122 and the common conductive structure 43-123, respectively, so that the light emitting element 43-120 and the light receiving element 43-300 form a common electrode design. Therefore, according to this embodiment, the purpose of addressing and controlling the optoelectronic device 46-000A can be achieved by designing the light emitting element 43-120 and the light receiving element 43-300 to share the electrode.

[0905] like Fig.46A As shown, in some embodiments, the light emitting element 43-120, the light receiving element 43-300, the driving functional block 43-410, and the modulation functional block 43-420 are on the same side of the driving chip 43-400, and the signal processing functional block 43-430 is on the opposite side of the driving chip 43-400. In some embodiments, the aforementioned elements are not necessarily located on the same side of the driving chip 43-400, but can also be on the opposite side of the driving chip 43-400, thereby realizing the architecture of a three-dimensional integrated circuit (3DIC). For example, the aforementioned elements can be manufactured separately through appropriate manufacturing processes and then three-dimensionally stacked. For example, the modulation functional block 43-420 or the driving functional block 43-410 can be arranged on the opposite side of the driving chip 43-400 relative to the light-emitting element 43-120 or the light-receiving element 43-300 (in other words, the modulation functional block 43-420 (or the driving functional block 43-410) and the light-emitting element 43-120 (or the light-receiving element 43-300) are connected to the aforementioned electrode structure through a through hole. In addition, the positions of different functional blocks on the driving chip 43-400 are not particularly limited.

[0906] See also Fig.46B , Fig.46B is a schematic cross-sectional view of an optoelectronic device 46-000B according to some embodiments of the present invention.

[0907] like Fig.46BAs shown in the optoelectronic device 46-000B, in some embodiments, the driver chip 43-400 further includes a light receiving functional block 43-440. The substrate 43-110 is a transparent substrate, the optical layer 43-500 is located on the transparent substrate, the switch unit 43-200 is located on the optical layer 43-500, and the light receiving functional block 43-440 corresponds to the light emitting area of ​​the light emitting element 43-120. In other words, compared to Fig.46A The embodiment shown, Fig.46B The embodiment shown does not include a light receiving element that shares an electrode with the light emitting element 43-120, but further includes a light receiving functional block 43-440 on the driver chip 43-400. Thus, the light receiving functional block 43-440 can also receive the aforementioned reflected light L432 and convert it into an electrical signal and then provide it to the signal processing functional block 43-430 for analysis. In this embodiment, the signal processing functional block 43-430 is located on the opposite side of the driver chip 43-400 compared to the light receiving functional block 43-440.

[0908] See also Fig.47A , Fig.47A 47 - 000A is a cross-sectional schematic diagram illustrating some embodiments of the optoelectronic device of the present invention.

[0909] like Fig.47A As shown in the optoelectronic device 47-000A, in some embodiments, the driver chip 43-400 also includes a light receiving functional block 43-440. The substrate 43-110 is a transparent substrate, the optical layer 43-500 is located on the transparent substrate, the switch unit 43-200 is located on the optical layer 43-500, and the light receiving functional block 43-440 does not completely overlap with the light emitting area of ​​the light emitting element 43-120.

[0910] Specifically, if Fig.47A In the embodiment shown, a portion of the semiconductor stacking layer of the light-emitting element 43-120 can be removed by a semiconductor manufacturing process to improve the transmittance of the portion 43-130, and the portion 43-130 is located between the light-emitting element 43-120 and the transparent substrate 43-110. The reflected light L432 reflected by the object can be received by the light receiving functional block 43-440 via the portion 43-130 of the light-emitting element 43-120, thereby improving the strength of the received signal.

[0911] like Fig.47A As shown, in some embodiments, the portion 43-130 of the semiconductor stack layer of the light-emitting element 43-120 after a portion of it is removed by a semiconductor manufacturing process can be re...

Claims

1. A photovoltaic unit, comprising: A base layer having a first side and a second side, the second side being opposite to the first side; A functional area is disposed on the first side of the base layer; A semiconductor element is disposed on the second side of the base layer, the semiconductor element comprises a first electrode and a second electrode, and the semiconductor element corresponds to the functional area; as well as The cladding layer is disposed on the second side of the base layer and surrounds the semiconductor element, wherein a portion of the first electrode and a portion of the second electrode are exposed outside the cladding layer. 2 . The optoelectronic unit as claimed in claim 1 , wherein the semiconductor element is a flip-chip vertical cavity laser chip. 3 . The optoelectronic unit as claimed in claim 1 , further comprising a plurality of the functional regions and a plurality of the semiconductor elements, wherein the number of the functional regions is the same as the number of the semiconductor elements. 4 . The photovoltaic unit as claimed in claim 1 , further comprising a light-transmitting substrate disposed on the first side of the base layer. The photovoltaic unit as claimed in claim 4 , wherein the light-transmitting substrate is located between the functional area and the base layer. The photovoltaic unit as claimed in claim 1 , wherein the functional region has a microstructure with a nanometer to micrometer dimension. 7 . The optoelectronic unit of claim 6 , wherein the microstructure comprises a metainterface structure, a diffractive optical element structure, a microlens array structure, or a combination of at least two of the foregoing. 8 . The photovoltaic cell of claim 1 , wherein at least one of the first electrode and the second electrode is coplanar with the cladding layer. 9 . The photovoltaic unit as claimed in claim 1 , wherein the functional area is smaller than the photovoltaic unit and larger than the semiconductor device. 10 . The photovoltaic unit of claim 1 , wherein a width of the first side of the base layer is smaller than a width of the cladding layer. 11 . The photovoltaic unit of claim 1 , wherein a width of the first side of the base layer is smaller than a width of the semiconductor element.

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