Dual-motor inverter PWM control method and device, electronic equipment, storage medium and vehicle

Abstract

The invention discloses a dual-motor inverter PWM control method and device, electronic equipment, a storage medium and a vehicle. The method comprises the following steps: controlling a first motor period control signal channel of the inverter to periodically generate a first motor period count value; the synchronous control signal channel generates a synchronous control signal count value and generates a synchronous control signal according to the synchronous control signal count value, and the waveform of the synchronous control signal is controllable; a counter of the second motor cycle control signal channel generates a second motor cycle count value, and controls the reset of the second motor cycle count value based on the waveform of the synchronous control signal; and determining phase shift time according to the working modes of the first motor and the second motor, and adjusting the waveform of the synchronous control signal according to the phase shift time. According to the invention, the starting moment of the output cycle of the three-phase PWM signal of the first motor and the starting moment of the output cycle of the three-phase PWM signal of the second motor can be staggered by any phase, and the phase shift phase can be adjusted in real time, so that the phase shift requirement is met.

Description

Technical Field

[0001] The present invention relates to the technical field of vehicle-related technology, and in particular to a dual-motor inverter PWM control method, device, electronic equipment, storage medium and vehicle. Background Art

[0002] In electric drive systems, the inverter usually works in the same-phase pulse width modulation (PWM) output mode. Taking the dual-motor inverter as an example, the inverter controls the integrated starter and generator (ISG) and the traction motor (TM) respectively. When the dual motors work in the same-phase PWM output mode, such as Figure 1 As shown, the driving signal output of each bridge arm has the following characteristics:

[0003] 1) The starting time of the six bridge arm drive signal cycles of the UVW three-phase of ISG completely coincides, and accordingly, the three-phase PWM output waveforms are in phase. The same is true for TM.

[0004] 2) The starting time of the bridge arm drive signal cycle of each phase (e.g., U phase) of the ISG completely coincides with the starting time of the bridge arm drive signal cycle of the same phase (e.g., U phase) of the TM. Accordingly, the PWM output waveform of each phase (e.g., U phase) of the ISG is in phase with the PWM output waveform of the same phase (e.g., U phase) of the TM.

[0005] Combining the above two features, the same-phase output of 12 bridge arm drive signals of six phases of the dual-motor inverter is achieved.

[0006] The in-phase PWM output mode of the dual-motor inverter has the advantages of simple implementation and less MCU resource occupation, but the phase of the PWM output of the ISG and the PWM output of the TM cannot be adjusted, and the flexibility is poor. It cannot be applied to the dual-motor inverter bus capacitor ripple current suppression solution, multi-phase motor control solution and specific subharmonic voltage / current elimination solution.

[0007] Therefore, the dual-motor inverter in the prior art has a technical problem that the phases between the PWM outputs of different phases of different motors cannot be adjusted. Summary of the invention

[0008] Based on this, it is necessary to provide a dual-motor inverter PWM control method, device, electronic device, storage medium and vehicle to address the technical problem that the phases between the PWM outputs of different motors in the prior art cannot be adjusted.

[0009] The present invention provides a dual-motor inverter PWM control method, comprising:

[0010] Controlling a first motor cycle control signal channel of the inverter to periodically generate a first motor cycle count value, and controlling a PWM signal of each phase output channel of the first motor based on the first motor cycle count value;

[0011] Controlling a synchronous control signal channel of the inverter to generate a synchronous control signal count value, wherein the synchronous control signal count value is consistent with the first motor cycle count value, and generating a synchronous control signal according to the synchronous control signal count value;

[0012] Controlling a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, controlling a reset of the second motor cycle count value based on the waveform of the synchronous control signal, and controlling a PWM signal of each phase output channel of the second motor based on the second motor cycle count value;

[0013] A phase shift time is determined according to the working modes of the first motor and the second motor, and a waveform of the synchronization control signal is adjusted according to the phase shift time.

[0014] Further, the synchronization control signal is a PWM signal, and the generating of the synchronization control signal according to the count value of the synchronization control signal includes:

[0015] Compare the synchronous control signal count value with a first flip value and a second flip value, and if the synchronous control signal count value is equal to the first flip value, control the synchronous control signal output by the synchronous control signal channel to flip from a low level to a high level; if the synchronous control signal count value is equal to the second flip value, control the synchronous control signal output by the synchronous control signal channel to flip from a high level to a low level;

[0016] The step of adjusting the waveform of the synchronization control signal according to the phase shift time includes:

[0017] The first flip value or the second flip value is modified according to the phase shift time.

[0018] Further, the synchronous control signal channel of the control inverter generates a synchronous control signal count value, and the synchronous control signal count value is consistent with the first motor cycle count value, including:

[0019] The first motor periodic control signal is set as a master channel, the synchronous control signal channel is set as a slave channel of the first motor periodic control signal channel, and the synchronous control signal channel is controlled to generate a synchronous control signal count value.

[0020] Further, the resetting of the second motor cycle count value based on the waveform control of the synchronous control signal includes:

[0021] The synchronous control signal is acquired from a synchronous control signal capture channel, and the synchronous control signal capture channel is communicatively connected with an output end of the synchronous control signal channel.

[0022] Further, the synchronous control signal is a PWM signal, and the resetting of the second motor cycle count value based on the waveform control of the synchronous control signal includes:

[0023] The waveform of the synchronous control signal is detected, and when the waveform of the synchronous control signal is a rising edge, the second motor cycle count value is controlled to be reset.

[0024] Further, the controlling the PWM signal of each phase output channel of the first motor based on the first motor cycle count value includes:

[0025] Setting the first motor periodic control signal as a master channel, and setting each phase output channel of the first motor as a slave channel of the first motor periodic control signal channel;

[0026] For each phase of the first motor:

[0027] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the first motor;

[0028] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0029] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0030] Further, the controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value includes:

[0031] Setting the second motor period control signal as a master channel, and setting each phase output channel of the second motor as a slave channel of the second motor period control signal channel;

[0032] For each phase of the second motor:

[0033] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the second motor;

[0034] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0035] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0036] The present invention provides a dual-motor inverter PWM control device, comprising:

[0037] A first motor cycle count value generating module, used for controlling a first motor cycle control signal channel of an inverter to periodically generate a first motor cycle count value, and controlling a PWM signal of each phase output channel of a first motor based on the first motor cycle count value;

[0038] A synchronous control signal generating module, used for controlling a synchronous control signal channel of the inverter to generate a synchronous control signal count value, wherein the synchronous control signal count value is consistent with the first motor cycle count value, and generating a synchronous control signal according to the synchronous control signal count value;

[0039] a second motor cycle count value generating module, configured to control a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, control a reset of the second motor cycle count value based on the waveform of the synchronization control signal, and control a PWM signal of each phase output channel of the second motor based on the second motor cycle count value;

[0040] The phase shift module is used to determine the phase shift time according to the working modes of the first motor and the second motor, and adjust the waveform of the synchronization control signal according to the phase shift time.

[0041] The present invention provides an electronic device, comprising:

[0042] at least one processor; and,

[0043] a memory communicatively connected to at least one of the processors; wherein,

[0044] The memory stores instructions that can be executed by at least one of the processors. The instructions are executed by at least one of the processors to enable the at least one of the processors to perform the dual-motor inverter PWM control method as described above.

[0045] The present invention provides a storage medium, wherein the storage medium stores computer instructions. When a computer executes the computer instructions, the storage medium is used to execute all steps of the dual-motor inverter PWM control method as described above.

[0046] The present invention provides a vehicle, comprising the dual-motor inverter PWM control device as described above, or the electronic device as described above, wherein the dual-motor inverter PWM control device or the electronic device controls the dual-motor inverter of the vehicle.

[0047] The present invention controls the PWM signal of each phase output channel of the first motor based on the first motor cycle count value, and keeps the count value of the synchronous control signal consistent with the first motor cycle count value to generate a synchronous control signal. At the same time, the waveform of the waveform-controllable synchronous control signal is used to control the reset of the second motor cycle count value, thereby adjusting the period of the second motor cycle count value. Since the PWM signal of each phase output channel of the second motor is controlled based on the second motor cycle count value, when the phase shift time is determined according to the working mode of the first motor and the second motor, and the waveform of the synchronous control signal is adjusted according to the phase shift time, the period of the second motor cycle count value will be changed, and the period of the PWM signal of each phase output channel of the second motor will be changed synchronously. The present invention allows the output period start time of the three-phase PWM signal of the first motor to be staggered with the output period start time of the three-phase PWM signal of the second motor at any phase, and the phase shift phase can be adjusted in real time to meet the phase shift requirement. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 It is a control signal waveform diagram of a dual-motor inverter in the prior art;

[0049] Figure 2 This is a working flow chart of a dual-motor inverter PWM control method according to an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of generating a first motor cycle control signal according to a first motor cycle count value;

[0051] Figure 4 It is a schematic diagram of the connection of each channel in the micro control unit;

[0052] Figure 5 This is a working flow chart of a dual-motor inverter PWM control method according to another embodiment of the present invention;

[0053] Figure 6 This is a schematic diagram of generating PWM waveforms of the U-phase upper and lower bridge output channels as an example of the present invention;

[0054] Figure 7 This is a schematic diagram of PWM waveforms of dual-motor phase-shift regulation as an example of the present invention;

[0055] Figure 8 A schematic diagram of a dual-motor inverter PWM control device according to an embodiment of the present invention;

[0056] Fig. 9 The figure is a schematic diagram of the hardware structure of an electronic device of the present invention. DETAILED DESCRIPTION

[0057] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. The same components are represented by the same reference numerals. It should be noted that the words "front", "rear", "left", "right", "upper" and "lower" used in the following description refer to directions in the accompanying drawings, and the words "inner" and "outer" refer to directions toward or away from the geometric center of a specific component, respectively.

[0058] like Figure 2 The figure shows a working flow chart of a dual-motor inverter PWM control method according to an embodiment of the present invention, comprising:

[0059] Step S201, controlling a first motor cycle control signal channel of an inverter to periodically generate a first motor cycle count value, and controlling a PWM signal of each phase output channel of a first motor based on the first motor cycle count value;

[0060] Step S202, controlling a synchronous control signal channel of the inverter to generate a synchronous control signal count value, wherein the synchronous control signal count value is consistent with the first motor cycle count value, and generating a synchronous control signal according to the synchronous control signal count value;

[0061] Step S203, controlling the counter of the second motor cycle control signal channel of the inverter to generate a second motor cycle count value, controlling the reset of the second motor cycle count value based on the waveform of the synchronous control signal, and controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value;

[0062] Step S204: determining a phase shift time according to the working modes of the first motor and the second motor, and adjusting the waveform of the synchronization control signal according to the phase shift time.

[0063] Specifically, the present invention can be applied to electronic devices with processing capabilities, such as an electronic control unit (ECU) or an extended domain control unit (XCU) of a vehicle.

[0064] The dual-motor inverter PWM control method of the present invention realizes the dual-motor inverter phase-shift PWM output, and has the following two technical features:

[0065] 1) Inside the first motor and the second motor, the period of the PWM signal output by the upper and lower bridge drivers of each phase is strictly synchronized with the period of the period control channel.

[0066] 2) Between the first motor and the second motor, the starting time of the three-phase PWM signal output cycle of the first motor and the starting time of the three-phase PWM signal output cycle of the second motor can determine the phase shift time according to the working mode of the first motor and the second motor, and staggered by a certain time (phase). The phase shift time (phase) is arbitrary and can be adjusted in real time.

[0067] To this end, the electronic device executes step S201 to control the first motor cycle control signal channel of the inverter to periodically generate the first motor count value. Wherein, periodically generating the first motor count value means that the first motor count value is incremented in one cycle until the cycle ends, and then the first motor count value is set to zero, and then in the next cycle, the first motor count value is incremented again. Specifically, the maximum value of the count value is calculated based on the expected cycle combined with the chip operating frequency. For example, the chip operating frequency is 200MHz and the expected cycle is 100us. In one cycle, the count value gradually increases to 20000, and then returns to zero and increments again.

[0068] A first motor cycle control signal may be generated based on the first motor cycle count value.

[0069] Each output channel has two count value comparison units. When the count value of the corresponding channel counter is equal to the comparison value preset in the comparison unit, a level flip is generated according to the channel working mode, thereby outputting a preset waveform.

[0070] like Figure 3As shown, for the first motor cycle control signal channel, the channel operates in the counter single-increment mode and periodically generates an increasing first motor cycle count value. The first motor cycle control channel serves as the main channel and is responsible for outputting the desired first motor cycle control signal period. One of the count value comparison units is used to compare the first motor cycle count value with the first motor desired PWM cycle comparison value. When a comparison event occurs, that is, the first motor cycle count value is equal to the first motor desired PWM cycle comparison value, the first motor cycle count value is reset to zero and then continues to count from zero. At the same time, the output level of the first motor cycle control signal is flipped to a high level. Therefore, the period can be changed by changing the first motor cycle count value. Another count value comparison unit is used to compare the first motor cycle count value with the first motor cycle control signal high level duration comparison value. When a comparison event occurs, that is, the first motor cycle count value is equal to the first motor cycle control signal high level duration comparison value, the output level of the first motor cycle control signal is flipped to a low level, thereby adjusting the PWM duty cycle of the first motor cycle control signal, and generating a signal as shown in FIG. Figure 3 The first motor cycle control signal is shown as follows. The first motor cycle control signal is preferably a PWM signal.

[0071] Then, the PWM signal of each phase output channel of the first motor is controlled based on the first motor cycle count value, so that the PWM signals of each phase output channel of the first motor are synchronized.

[0072] The electronic device executes step S202, controls the synchronous control signal channel of the inverter to generate a synchronous control signal count value, the synchronous control signal count value is consistent with the first motor cycle count value, and generates a synchronous control signal according to the synchronous control signal count value. Wherein, periodically generating a synchronous control signal count value means that the synchronous control signal count value is incremented in a cycle until the cycle ends, the synchronous control signal count value is set to zero, and then the synchronous control signal count value is incremented again in the next cycle.

[0073] Among them, two independent channels are selected as the first motor cycle control signal channel and the second motor cycle control signal channel, for example, the cycle control signal channel of ISG is selected as the first motor cycle control signal channel, and the cycle control signal channel of TM is selected as the second motor cycle control signal channel. In addition, a synchronous control signal channel is selected as a relay to keep synchronization with the first motor cycle control signal channel, and the second motor cycle control channel is controlled based on the synchronous control signal of the synchronous control signal channel, so as to establish a connection between the first motor cycle control channel and the second motor cycle control channel.

[0074] like Figure 4As shown, in an electronic device, such as a microcontroller unit (MCU) 40, two independent channels are selected as the first motor cycle control signal channel 41 and the second motor cycle control signal channel 42 respectively, and the synchronous control signal channel 43 is selected as a relay to be synchronized with the first motor cycle control signal channel 41. Through the synchronization mechanism of the microcontroller unit, it is ensured that the synchronous control signal count value is consistent with the first motor cycle count value, and the period of the synchronous control signal generated according to the synchronous control signal count value is synchronized with the period of the first motor cycle control signal. Among them, the waveform of the synchronous control signal is controllable.

[0075] Then, step S203 is executed to control the counter of the second motor cycle control signal channel of the inverter to generate a second motor cycle count value, control the reset of the second motor cycle count value based on the waveform of the synchronous control signal, and control the PWM signals of each phase output channel of the second motor based on the second motor cycle count value. Among them, generating the second motor cycle count value periodically means that within one cycle, the second motor cycle count value is incremented until the end of the cycle, then the second motor cycle count value is set to zero, and then within the next cycle, the second motor cycle count value is incremented again.

[0076] Specifically, as Figure 4 shown, the output port of the synchronous control signal channel 43 is connected to the synchronous control signal capture channel 44 through an external hardware circuit. The synchronous control signal capture channel 44 outputs the captured synchronous control signal to the second motor cycle control signal channel 42 through the connection between internal modules of the microcontroller unit 40, and uses the waveform of the synchronous control signal as the reset source for generating the second motor cycle count value of the second motor cycle control channel 42.

[0077] In some embodiments, the rising edge of the synchronous control signal is used as the reset source for the second motor cycle count value, or the falling edge of the synchronous control signal is used as the reset source for the second motor cycle count value.

[0078] The second motor cycle count value can be used to generate a second motor cycle control signal.

[0079] Specifically, for the second motor cycle control signal channel, the channel operates in a counter single-increment mode, and periodically generates an increasing second motor cycle count value. One of the count value comparison units of the second motor cycle control channel is used to compare the second motor cycle count value with the second motor expected PWM cycle comparison value. When a comparison event occurs, that is, when the second motor cycle count value is equal to the second motor expected PWM cycle comparison value, the output level of the second motor cycle control signal is flipped to a high level. Among them, the second motor expected PWM cycle comparison value is set to 0, so when the second motor cycle count value is reset to zero by the waveform of the synchronous control signal, such as the rising edge trigger, the output level of the second motor cycle control signal is flipped to a high level. Another count value comparison unit is used to compare the second motor cycle count value with the second motor cycle control signal high level duration comparison value. When a comparison event occurs, that is, when the second motor cycle count value is equal to the second motor cycle control signal high level duration comparison value, the output level of the second motor cycle control signal is reversed to a low level, thereby adjusting the PWM duty cycle of the second motor cycle control signal and generating the second motor cycle control signal.

[0080] Then, step S204 is executed to determine a phase shift time according to the working modes of the first motor and the second motor, and to adjust the waveform of the synchronization control signal according to the phase shift time.

[0081] In some embodiments, the operating modes include a power generation mode and a motoring mode.

[0082] The specific correspondence between the working mode and the phase shift time can be set according to the requirements of the first motor and the second motor.

[0083] As an example, when the first motor, such as ISG, and the second motor, such as TM, respectively operate in power generation mode and electric mode, the switching frequencies are equal, the phase shift angle is 0, and the corresponding phase shift time is also 0s; when the first motor and the second motor both operate in power generation mode, the switching frequencies are equal, the second motor should lag behind the first motor by 90 degrees, and the phase shift time is the switching cycle / 4.

[0084] In some embodiments, adjusting the waveform of the synchronization control signal according to the phase shift time is: controlling the waveform of the synchronization control signal to lag behind or advance the phase shift time indicated by the phase shift adjustment instruction.

[0085] By lagging the waveform of the synchronous control signal, the resetting of the second motor cycle count value is delayed, thereby lagging the second motor cycle control signal and lagging the PWM signal of each phase output channel of the second motor.

[0086] By advancing the waveform of the synchronous control signal, the reset of the second motor cycle count value is advanced, thereby advancing the second motor cycle control signal and the PWM signal of each phase output channel of the second motor.

[0087] In some embodiments, the method further includes stopping adjusting the waveform of the synchronization control signal after the phase shift adjustment is completed.

[0088] After the phase shift adjustment is completed, the first motor and the second motor operate in a same-phase output mode.

[0089] The dual-motor inverter PWM control method of the present invention can suppress the ripple current of the dual-motor inverter bus capacitor by phase shifting. For dual motors, if the three-phase PWM signals of the two motors are in phase, the switching ripples of the two motors are superimposed on the bus capacitor, which will significantly increase the capacitor ripple voltage and ripple current, resulting in worsening heat. Therefore, adjusting the phase by the dual-motor inverter PWM control method of the present invention can play a role in offsetting, thereby reducing harmonics.

[0090] The present invention controls the PWM signal of each phase output channel of the first motor based on the first motor cycle count value, and keeps the count value of the synchronous control signal consistent with the first motor cycle count value to generate a synchronous control signal. At the same time, the waveform of the waveform-controllable synchronous control signal is used to control the reset of the second motor cycle count value, thereby adjusting the period of the second motor cycle count value. Since the PWM signal of each phase output channel of the second motor is controlled based on the second motor cycle count value, when the phase shift time is determined according to the working mode of the first motor and the second motor, and the waveform of the synchronous control signal is adjusted according to the phase shift time, the period of the second motor cycle count value will be changed, and the period of the PWM signal of each phase output channel of the second motor will be changed synchronously. The present invention allows the output period start time of the three-phase PWM signal of the first motor to be staggered with the output period start time of the three-phase PWM signal of the second motor at any phase, and the phase shift phase can be adjusted in real time to meet the phase shift requirement.

[0091] like Figure 5 The figure shows a working flow chart of a dual-motor inverter PWM control method in another embodiment of the present invention, including:

[0092] Step S501 , controlling a first motor periodic control signal channel of an inverter to periodically generate a first motor count value.

[0093] Step S502 : controlling the PWM signal of each phase output channel of the first motor based on the first motor cycle count value.

[0094] In one embodiment, the controlling the PWM signal of each phase output channel of the first motor based on the first motor cycle count value comprises:

[0095] Setting the first motor periodic control signal as a master channel, and setting each phase output channel of the first motor as a slave channel of the first motor periodic control signal channel;

[0096] For each phase of the first motor:

[0097] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the first motor;

[0098] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0099] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0100] Step S503, setting the first motor cycle control signal as the master channel, setting the synchronous control signal channel as the slave channel of the first motor cycle control signal channel, controlling the synchronous control signal channel to generate a synchronous control signal count value, and generating a synchronous control signal according to the synchronous control signal count value.

[0101] In one embodiment, the synchronization control signal is a PWM signal, and the step of generating the synchronization control signal according to the count value of the synchronization control signal includes:

[0102] The synchronous control signal count value is compared with a first flip value and a second flip value. If the synchronous control signal count value is equal to the first flip value, the synchronous control signal output by the synchronous control signal channel is controlled to flip from a low level to a high level. If the synchronous control signal count value is equal to the second flip value, the synchronous control signal output by the synchronous control signal channel is controlled to flip from a high level to a low level.

[0103] Step S504 , controlling a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, and controlling the resetting of the second motor cycle count value based on the waveform of the synchronous control signal.

[0104] In one embodiment, the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes:

[0105] The synchronous control signal is acquired from a synchronous control signal capture channel, and the synchronous control signal capture channel is communicatively connected with an output end of the synchronous control signal channel.

[0106] In one embodiment, the synchronous control signal is a PWM signal, and the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes:

[0107] The waveform of the synchronous control signal is detected, and when the waveform of the synchronous control signal is a rising edge, the second motor cycle count value is controlled to be reset.

[0108] Step S505 , generating a second motor cycle control signal according to the second motor cycle count value.

[0109] Step S506 , controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value.

[0110] In one embodiment, the controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value comprises:

[0111] Setting the second motor period control signal as a master channel, and setting each phase output channel of the second motor as a slave channel of the second motor period control signal channel;

[0112] For each phase of the second motor:

[0113] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the second motor;

[0114] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0115] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0116] Step S507, determining a phase shift time according to the working modes of the first motor and the second motor, and adjusting the waveform of the synchronization control signal according to the phase shift time.

[0117] In one embodiment, adjusting the waveform of the synchronization control signal according to the phase shift time includes:

[0118] The first flip value or the second flip value is modified according to the phase shift time.

[0119] Specifically, step S501 is first performed to control a first motor periodic control signal channel of the inverter to periodically generate a first motor count value.

[0120] Then, step S502 is executed to control the PWM signal of each phase output channel of the first motor based on the first motor cycle count value.

[0121] In one embodiment, the controlling the PWM signal of each phase output channel of the first motor based on the first motor cycle count value comprises:

[0122] Setting the first motor periodic control signal as a master channel, and setting each phase output channel of the first motor as a slave channel of the first motor periodic control signal channel;

[0123] For each phase of the first motor:

[0124] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the first motor;

[0125] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0126] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0127] By setting the first motor periodic control signal as the main channel and setting each phase output channel of the first motor as a slave channel of the first motor periodic control signal channel, the cycle of the upper and lower bridge drive outputs of each phase of the first motor is strictly synchronized with the cycle of the first motor periodic control signal channel, and the count values ​​generated by the upper bridge output channel counter and the lower bridge output channel counter of each phase are consistent with the count value of the first motor.

[0128] Each phase upper bridge output channel and lower bridge output channel has two count value comparison units. One count value comparison unit is used to compare the count value of each phase upper bridge output channel and lower bridge output channel with the count value at the expected PWM rising edge jump moment, thereby generating a high-level flip event, that is, the PWM signal level of each phase upper bridge output channel flips from a low level to a high level. The other count value comparison unit is used to compare the count value of each phase upper bridge output channel and lower bridge output channel with the count value at the expected PWM falling edge jump moment, thereby generating a low-level flip event, that is, the PWM signal level of each phase upper bridge output channel flips from a high level to a low level, thereby realizing flexible control of the PWM waveform.

[0129] like Figure 6 As shown, in some embodiments, the turn-on level is a high level and the turn-off level is a low level, then the expected PWM rising edge transition moment count value includes the upper bridge turn-on moment comparison value and the lower bridge turn-on moment comparison value, and the expected PWM falling edge transition moment count value is the upper bridge turn-off moment comparison value and the lower bridge turn-off moment comparison value.

[0130] In other embodiments, the turn-on level is a low level and the turn-off level is a high level, then the expected PWM falling edge transition moment count value includes the upper bridge turn-on moment comparison value and the lower bridge turn-on moment comparison value, and the expected PWM rising edge transition moment count value is the upper bridge turn-off moment comparison value and the lower bridge turn-off moment comparison value.

[0131] In this embodiment, the first motor periodic control signal is set as the main channel, and each phase output channel of the first motor is set as a slave channel of the first motor periodic control signal channel, so that the cycle of the upper and lower bridge drive outputs of each phase of the first motor is strictly synchronized with the cycle of the first motor periodic control signal channel, and the count values ​​generated by the upper bridge output channel counter and the lower bridge output channel counter of each phase are consistent with the count value of the first motor.

[0132] Then, step S503 is executed to set the first motor cycle control signal as a master channel and set the synchronization control signal channel as a slave channel of the first motor cycle control signal channel.

[0133] In this embodiment, the synchronous control signal count value generated by the synchronous control signal channel is kept consistent with the first motor cycle count value, and the period of the synchronous control signal generated according to the synchronous control signal count value is kept synchronized with the period of the first motor cycle control signal.

[0134] In one embodiment, the synchronization control signal is a PWM signal, and the step of generating the synchronization control signal according to the count value of the synchronization control signal includes:

[0135] The synchronous control signal count value is compared with a first flip value and a second flip value. If the synchronous control signal count value is equal to the first flip value, the synchronous control signal output by the synchronous control signal channel is controlled to flip from a low level to a high level. If the synchronous control signal count value is equal to the second flip value, the synchronous control signal output by the synchronous control signal channel is controlled to flip from a high level to a low level.

[0136] Specifically, the synchronous control signal channel operates in the counter single-increment mode, and periodically generates an increasing synchronous control signal count value. One of the count value comparison units of the synchronous control signal channel is used to compare the synchronous control signal count value with the first flip value, thereby generating a high-level flip event, that is, the synchronous control signal level flips from a low level to a high level. The other count value comparison unit is used to compare the synchronous control signal count value with the second flip value, thereby generating a low-level flip event, that is, the synchronous control signal level flips from a high level to a low level. By adjusting the first flip value or the second flip value, the waveform of the synchronous control signal is adjusted.

[0137] The first flip value is equivalent to the first motor expected PWM period comparison value of the first motor cycle control signal channel, and the second flip value is equivalent to the first motor cycle control signal high level duration comparison value. The specific first flip value and the second flip value are changed and set by the synchronous control signal channel.

[0138] In this embodiment, the first flip value or the second flip value is used to adjust the waveform of the synchronous control signal.

[0139] The electronic device executes step S504 to control a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, and controls the resetting of the second motor cycle count value based on the waveform of the synchronous control signal.

[0140] In one embodiment, the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes:

[0141] The synchronous control signal is acquired from a synchronous control signal capture channel, and the synchronous control signal capture channel is communicatively connected with an output end of the synchronous control signal channel.

[0142] Specifically, Figure 4 As shown, two independent channels are selected as the first motor cycle control signal channel 41 and the second motor cycle control signal channel 42, and the synchronous control signal channel 43 is selected as a relay to establish the first motor cycle control signal channel 41 and the second motor cycle control signal channel 42. The first motor cycle control signal channel 41 is used as the main channel, and the synchronous control signal channel 43 is used as the slave channel to realize that the synchronous control signal follows the first motor cycle control signal cycle. At the same time, the output port of the synchronous control signal channel 43 is connected to the synchronous control signal capture channel 44 through an external hardware circuit, and the captured synchronous control signal is connected between the internal modules of the microcontroller 40 as the reset source of the count value of the second motor cycle control signal channel 42, thereby changing its cycle.

[0143] This embodiment captures the synchronous control signal through the synchronous control signal capture channel.

[0144] In one embodiment, the synchronous control signal is a PWM signal, and the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes:

[0145] The waveform of the synchronous control signal is detected, and when the waveform of the synchronous control signal is a rising edge, the second motor cycle count value is controlled to be reset.

[0146] This embodiment uses the rising edge of the synchronous control signal to accurately control the resetting of the second motor cycle count value.

[0147] The electronic device executes step S505 to generate a second motor cycle control signal according to the second motor cycle count value, and then executes step S506 to control the PWM signal of each phase output channel of the second motor based on the second motor cycle count value.

[0148] In one embodiment, the controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value comprises:

[0149] Setting the second motor period control signal as a master channel, and setting each phase output channel of the second motor as a slave channel of the second motor period control signal channel;

[0150] For each phase of the second motor:

[0151] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the second motor;

[0152] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0153] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0154] By setting the second motor period control signal as the main channel and setting each phase output channel of the second motor as a slave channel of the second motor period control signal channel, the cycle of the upper and lower bridge drive outputs of each phase of the second motor is strictly synchronized with the cycle of the second motor period control signal channel, and the count values ​​generated by the upper bridge output channel counter and the lower bridge output channel counter of each phase are consistent with the count value of the second motor.

[0155] Each phase upper bridge output channel and lower bridge output channel has two count value comparison units. One count value comparison unit is used to compare the count value of each phase upper bridge output channel and lower bridge output channel with the count value at the expected PWM rising edge jump moment, thereby generating a high-level flip event, that is, the PWM signal level of each phase upper bridge output channel flips from a low level to a high level. The other count value comparison unit is used to compare the count value of each phase upper bridge output channel and lower bridge output channel with the count value at the expected PWM falling edge jump moment, thereby generating a low-level flip event, that is, the PWM signal level of each phase upper bridge output channel flips from a high level to a low level, thereby realizing flexible control of the PWM waveform.

[0156] In this embodiment, the second motor periodic control signal is set as the main channel, and each phase output channel of the second motor is set as a slave channel of the second motor periodic control signal channel, so that the cycle of the upper and lower bridge drive outputs of each phase of the second motor is strictly synchronized with the cycle of the second motor periodic control signal channel, and the count values ​​generated by the upper bridge output channel counter and the lower bridge output channel counter of each phase are consistent with the count value of the second motor.

[0157] Then, step S507 is executed to determine a phase shift time according to the working modes of the first motor and the second motor, and to adjust the waveform of the synchronization control signal according to the phase shift time.

[0158] In one embodiment, adjusting the waveform of the synchronization control signal according to the phase shift time includes:

[0159] The first flip value or the second flip value is modified according to the phase shift time.

[0160] Specifically, if the second motor cycle count value is reset when the waveform of the synchronous control signal is a rising edge, the first flip value is modified according to the phase shift time to adjust the time for the synchronous control signal to flip from a low level to a high level, that is, adjust the rising edge time of the synchronous control signal.

[0161] If the second motor cycle count value is reset when the synchronous control signal is at a falling edge, the second flip value is modified according to the phase shift time to adjust the time for the synchronous control signal to flip from a high level to a low level, that is, to adjust the falling edge time of the synchronous control signal.

[0162] This embodiment controls the rising edge or falling edge time of the synchronization control signal by modifying the first flip value or the second flip value, thereby adjusting the waveform of the synchronization control signal.

[0163] As an example, Figure 7The phase shift adjustment process is shown. The first motor is ISG and the second motor is TM: Initially, in cycle one, the dual-motor inverter works in the same phase output mode. The PWM signal waveforms of the upper and lower bridge PWM output channels of each phase of ISG and TM have the same period and phase (only the PWM waveforms of the upper bridge output channel of ISG and TM U phase and the PWM waveforms of the lower bridge output channel of U phase are shown in the figure). The phase shift angle is determined according to the working mode combination of ISG TM (generation / motor), and the need for adjustment is determined and the command is generated. The rising edge of the synchronous control signal PWM waveform is adjusted according to the desired phase shift phase (the time is delayed by △t). The rising edge of the synchronous control signal PWM waveform in cycle three is delayed by △t compared with the rising edge of the synchronous control signal PWM waveform in cycle two. △t is determined according to the combination of ISG TM generation / motor working conditions, and △t controls the phase shift of ISG and TM. During the phase shift adjustment process, the PWM signal waveform periods of the upper and lower bridge PWM output channels of each phase of ISG and TM are different. In order to ensure that the output voltage does not mutate, the TM PWM switching time should be adjusted according to the principle of equivalent duty cycle unchanged. The regulation follows the volt-second balance principle and is designed according to this specific transient process. For example, the steady-state switching cycle before regulation is 100us, and the opening time is 50us. During regulation, the transient switching cycle becomes 125us. According to the volt-second equivalent principle, the opening time becomes 62.5us. In cycle three, the PWM signal waveform cycle of the upper and lower bridge PWM output channels of each phase of ISG and TM is the same, and the starting time of the PWM signal waveform cycle of the upper and lower bridge PWM output channels of each phase of TM lags behind the PWM signal waveform of the upper and lower bridge PWM output channels of each phase of ISG by △t. At this point, the phase shift regulation is completed. When △t is zero, ISG and TM work in the same phase output mode.

[0164] This embodiment allows the output cycle start time of the three-phase PWM signal of the first motor to be staggered with the output cycle start time of the three-phase PWM signal of the second motor by any phase between 0-360 degrees, and the phase shift phase can be adjusted in real time to meet the phase shift requirements. At the same time, this embodiment can switch between the same-phase mode and the phase-shift mode in real time, and the switching process is rapid and there is no unexpected drive output during the process. The dual-motor inverter PWM control method of this embodiment realizes the phase shift between different motors, and the phase shift adjustment has the characteristics of strong real-time performance, high flexibility, and strong continuity. The dual-motor inverter PWM control method of this embodiment uses a relatively simple implementation method and moderate microcontroller resource consumption, which greatly improves the flexibility of the complex drive scheme of the dual-motor inverter PWM output, making it suitable for a wider range of applications, such as the dual-motor inverter bus capacitor ripple current suppression scheme, multi-phase motor control scheme and specific subharmonic voltage / current elimination scheme. After adopting this solution, the torque and speed of the whole vehicle will not change for the operation of the two motors, but the improvement can significantly reduce the ripple current and ripple voltage of the capacitor, thereby reducing the capacitance and volume of the capacitor. The volume of the inverter can be reduced, which is convenient for the layout of the whole vehicle.

[0165] Based on the same inventive concept, Figure 8 FIG. 1 is a schematic diagram of a dual-motor inverter PWM control device according to an embodiment of the present invention, comprising:

[0166] A first motor cycle count value generating module 801, used to control a first motor cycle control signal channel of an inverter to periodically generate a first motor cycle count value, and to control a PWM signal of each phase output channel of a first motor based on the first motor cycle count value;

[0167] A synchronous control signal generating module 802 is used to control a synchronous control signal channel of the inverter to generate a synchronous control signal count value, wherein the synchronous control signal count value is consistent with the first motor cycle count value, and a synchronous control signal is generated according to the synchronous control signal count value;

[0168] A second motor cycle count value generating module 803, configured to control a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, control a reset of the second motor cycle count value based on the waveform of the synchronization control signal, and control a PWM signal of each phase output channel of the second motor based on the second motor cycle count value;

[0169] The phase shift module 804 is used to determine the phase shift time according to the working modes of the first motor and the second motor, and adjust the waveform of the synchronization control signal according to the phase shift time.

[0170] The present invention controls the PWM signal of each phase output channel of the first motor based on the first motor cycle count value, and keeps the count value of the synchronous control signal consistent with the first motor cycle count value to generate a synchronous control signal. At the same time, the waveform of the waveform-controllable synchronous control signal is used to control the reset of the second motor cycle count value, thereby adjusting the period of the second motor cycle count value. Since the PWM signal of each phase output channel of the second motor is controlled based on the second motor cycle count value, when the phase shift time is determined according to the working mode of the first motor and the second motor, and the waveform of the synchronous control signal is adjusted according to the phase shift time, the period of the second motor cycle count value will be changed, and the period of the PWM signal of each phase output channel of the second motor will be changed synchronously. The present invention allows the output period start time of the three-phase PWM signal of the first motor to be staggered with the output period start time of the three-phase PWM signal of the second motor at any phase, and the phase shift phase can be adjusted in real time to meet the phase shift requirement.

[0171] In one embodiment, the synchronization control signal is a PWM signal, and the step of generating the synchronization control signal according to the count value of the synchronization control signal includes:

[0172] Compare the synchronous control signal count value with a first flip value and a second flip value, and if the synchronous control signal count value is equal to the first flip value, control the synchronous control signal output by the synchronous control signal channel to flip from a low level to a high level; if the synchronous control signal count value is equal to the second flip value, control the synchronous control signal output by the synchronous control signal channel to flip from a high level to a low level;

[0173] The step of adjusting the waveform of the synchronization control signal according to the phase shift time includes:

[0174] The first flip value or the second flip value is modified according to the phase shift time.

[0175] In one embodiment, the synchronous control signal channel of the control inverter generates a synchronous control signal count value, and the synchronous control signal count value is consistent with the first motor cycle count value, including:

[0176] The first motor periodic control signal is set as a master channel, the synchronous control signal channel is set as a slave channel of the first motor periodic control signal channel, and the synchronous control signal channel is controlled to generate a synchronous control signal count value.

[0177] In one embodiment, the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes:

[0178] The synchronous control signal is acquired from a synchronous control signal capture channel, and the synchronous control signal capture channel is communicatively connected with an output end of the synchronous control signal channel.

[0179] In one embodiment, the synchronous control signal is a PWM signal, and the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes:

[0180] The waveform of the synchronous control signal is detected, and when the waveform of the synchronous control signal is a rising edge, the second motor cycle count value is controlled to be reset.

[0181] In one embodiment, the controlling the PWM signal of each phase output channel of the first motor based on the first motor cycle count value comprises:

[0182] Setting the first motor periodic control signal as a master channel, and setting each phase output channel of the first motor as a slave channel of the first motor periodic control signal channel;

[0183] For each phase of the first motor:

[0184] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the first motor;

[0185] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0186] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0187] In one embodiment, the controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value comprises:

[0188] Setting the second motor period control signal as a master channel, and setting each phase output channel of the second motor as a slave channel of the second motor period control signal channel;

[0189] For each phase of the second motor:

[0190] Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the second motor;

[0191] If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level;

[0192] If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

[0193] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0194] like Fig. 9 The figure shows a hardware structure diagram of an electronic device of the present invention, including:

[0195] at least one processor 901; and,

[0196] A memory 902 that is communicatively connected to at least one of the processors 901; wherein:

[0197] The memory 902 stores instructions that can be executed by at least one of the processors. The instructions are executed by at least one of the processors so that the at least one of the processors can execute the dual-motor inverter PWM control method as described above.

[0198] Fig. 9 A processor 901 is taken as an example.

[0199] The electronic device may further include: an input device 903 and a display device 904 .

[0200] The processor 901, the memory 902, the input device 903 and the display device 904 may be connected via a bus or other means, and the figure takes the connection via a bus as an example.

[0201] The memory 902 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules, such as program instructions / modules corresponding to the dual-motor inverter PWM control method in the embodiment of the present application, for example, Figure 2 , Figure 5 The processor 901 executes various functional applications and data processing by running the non-volatile software programs, instructions and modules stored in the memory 902, that is, the dual-motor inverter PWM control method in the above embodiment is implemented.

[0202] The memory 902 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required by at least one function; the data storage area may store data created according to the use of the dual motor inverter PWM control method, etc. In addition, the memory 902 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 902 may optionally include a memory remotely arranged relative to the processor 901, and these remote memories may be connected to the device for executing the dual motor inverter PWM control method via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0203] The input device 903 can receive user clicks and generate signal inputs related to user settings and function control of the dual-motor inverter PWM control method. The display device 904 can include display devices such as a display screen.

[0204] The one or more modules are stored in the memory 902 , and when executed by the one or more processors 901 , the dual-motor inverter PWM control method in any of the above method embodiments is executed.

[0205] The present invention controls the PWM signal of each phase output channel of the first motor based on the first motor cycle count value, and keeps the count value of the synchronous control signal consistent with the first motor cycle count value to generate a synchronous control signal. At the same time, the waveform of the waveform-controllable synchronous control signal is used to control the reset of the second motor cycle count value, thereby adjusting the period of the second motor cycle count value. Since the PWM signal of each phase output channel of the second motor is controlled based on the second motor cycle count value, when the phase shift time is determined according to the working mode of the first motor and the second motor, and the waveform of the synchronous control signal is adjusted according to the phase shift time, the period of the second motor cycle count value will be changed, and the period of the PWM signal of each phase output channel of the second motor will be changed synchronously. The present invention allows the output period start time of the three-phase PWM signal of the first motor to be staggered with the output period start time of the three-phase PWM signal of the second motor at any phase, and the phase shift phase can be adjusted in real time to meet the phase shift requirement.

[0206] An embodiment of the present invention provides a storage medium, wherein the storage medium stores computer instructions. When a computer executes the computer instructions, it is used to execute all steps of the dual-motor inverter PWM control method as described above.

[0207] In the context of the present disclosure, a storage medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or apparatus. The storage medium may be a machine-readable signal medium or a machine-readable storage medium. Alternatively, the storage medium may be a non-temporary computer-readable storage medium, for example, a non-temporary computer-readable storage medium may be a ROM, a random access memory (Random Access Memory, RAM), a compact disc read-only memory (Compact Disc ROM, CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0208] An embodiment of the present invention provides a vehicle, comprising a dual-motor inverter PWM control device as described above, or an electronic device as described above, wherein the dual-motor inverter PWM control device or the electronic device controls the dual-motor inverter of the vehicle. It is understandable that the vehicle may also include: a processor, a memory, and a computer program. The computer program is stored in the memory and is configured to be executed by the processor to implement the dual-motor inverter PWM control method provided in the embodiment of the present disclosure. The processor and the memory are already in Fig. 9 The parts described in the illustrated embodiment are not repeated here.

[0209] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A dual-motor inverter PWM control method, It is characterized in that include: Controlling a first motor cycle control signal channel of the inverter to periodically generate a first motor cycle count value, and controlling a PWM signal of each phase output channel of the first motor based on the first motor cycle count value; Controlling a synchronous control signal channel of the inverter to generate a synchronous control signal count value, wherein the synchronous control signal count value is consistent with the first motor cycle count value, and generating a synchronous control signal according to the synchronous control signal count value; Controlling a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, controlling a reset of the second motor cycle count value based on the waveform of the synchronous control signal, and controlling a PWM signal of each phase output channel of the second motor based on the second motor cycle count value; A phase shift time is determined according to the working modes of the first motor and the second motor, and a waveform of the synchronization control signal is adjusted according to the phase shift time.

2. The dual-motor inverter PWM control method according to claim 1, It is characterized in that The synchronous control signal is a PWM signal, and the generating of the synchronous control signal according to the count value of the synchronous control signal includes: The synchronous control signal count value is compared with a first flip value and a second flip value. If the synchronous control signal count value is equal to the first flip value, the synchronous control signal output by the synchronous control signal channel is controlled to flip from a low level to a high level. If the synchronous control signal count value is equal to the second flip value, the synchronous control signal output by the synchronous control signal channel is controlled to flip from a high level to a low level.

3. The dual-motor inverter PWM control method according to claim 2, It is characterized in that The step of adjusting the waveform of the synchronization control signal according to the phase shift time includes: The first flip value or the second flip value is modified according to the phase shift time.

4. The dual-motor inverter PWM control method according to claim 1, It is characterized in that The synchronous control signal channel of the control inverter generates a synchronous control signal count value, and the synchronous control signal count value is consistent with the first motor cycle count value, including: The first motor periodic control signal is set as a master channel, the synchronous control signal channel is set as a slave channel of the first motor periodic control signal channel, and the synchronous control signal channel is controlled to generate a synchronous control signal count value.

5. The dual-motor inverter PWM control method according to claim 1, It is characterized in that The resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes: The synchronous control signal is acquired from a synchronous control signal capture channel, and the synchronous control signal capture channel is communicatively connected with an output end of the synchronous control signal channel.

6. The dual-motor inverter PWM control method according to claim 1, It is characterized in that The synchronous control signal is a PWM signal, and the resetting of the second motor cycle count value based on the waveform of the synchronous control signal includes: The waveform of the synchronous control signal is detected, and when the waveform of the synchronous control signal is a rising edge, the second motor cycle count value is controlled to be reset.

7. The dual-motor inverter PWM control method according to claim 1, It is characterized in that The method of controlling the PWM signal of each phase output channel of the first motor based on the first motor cycle count value includes: Setting the first motor periodic control signal as a master channel, and setting each phase output channel of the first motor as a slave channel of the first motor periodic control signal channel; For each phase of the first motor: Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the first motor; If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level; If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

8. The dual-motor inverter PWM control method according to claim 1, It is characterized in that The method of controlling the PWM signal of each phase output channel of the second motor based on the second motor cycle count value includes: Setting the second motor period control signal as a master channel, and setting each phase output channel of the second motor as a slave channel of the second motor period control signal channel; For each phase of the second motor: Controlling the upper bridge output channel counter and the lower bridge output channel counter of the phase to respectively generate count values ​​consistent with the count value of the second motor; If the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-on time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-on level; if the count value of the upper bridge output channel counter of the phase is equal to the preset upper bridge turn-off time comparison value, the PWM signal level of the upper bridge output channel of the phase is controlled to be flipped to the turn-off level; If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-on time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-on level. If the count value of the lower bridge output channel counter of the phase is equal to the preset lower bridge turn-off time comparison value, the PWM signal level of the lower bridge output channel of the phase is controlled to be flipped to the turn-off level.

9. A dual-motor inverter PWM control device, It is characterized in that include: A first motor cycle count value generating module, used for controlling a first motor cycle control signal channel of an inverter to periodically generate a first motor cycle count value, and controlling a PWM signal of each phase output channel of a first motor based on the first motor cycle count value; A synchronous control signal generating module, used for controlling a synchronous control signal channel of the inverter to generate a synchronous control signal count value, wherein the synchronous control signal count value is consistent with the first motor cycle count value, and generating a synchronous control signal according to the synchronous control signal count value; a second motor cycle count value generating module, configured to control a counter of a second motor cycle control signal channel of the inverter to generate a second motor cycle count value, control a reset of the second motor cycle count value based on the waveform of the synchronization control signal, and control a PWM signal of each phase output channel of the second motor based on the second motor cycle count value; The phase shift module is used to determine the phase shift time according to the working modes of the first motor and the second motor, and adjust the waveform of the synchronization control signal according to the phase shift time.

10. An electronic device, It is characterized in that include: at least one processor; as well as, a memory communicatively connected to at least one of the processors; wherein, The memory stores instructions that can be executed by at least one of the processors, and the instructions are executed by at least one of the processors to enable at least one of the processors to execute the dual-motor inverter PWM control method according to any one of claims 1 to 8.

11. A storage medium, It is characterized in that The storage medium stores computer instructions, and when a computer executes the computer instructions, it is used to execute all steps of the dual-motor inverter PWM control method according to any one of claims 1 to 8.

12. A vehicle, It is characterized in that It comprises the dual-motor inverter PWM control device as claimed in claim 9, or the electronic device as claimed in claim 10, wherein the dual-motor inverter PWM control device or the electronic device controls the dual-motor inverter of a vehicle.

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