Differential operational amplifier circuit based on flip voltage follower and cross coupling structure

Abstract

The invention discloses a differential operational amplifier circuit based on a flipping voltage follower and a cross coupling structure, and relates to the technical field of amplifiers, comprising: an input stage which adopts a differential flipping voltage follower, provides a constant bias current through a bias circuit, and is used for processing an input differential signal; the gain stage is coupled to the input stage in an operation mode, the gain stage adopts a cross coupling pair transistor structure, negative impedance is provided through a negative feedback mechanism, and the output impedance of differential signals is improved by combining the positive impedance; and an output stage operatively coupled to the input stage, the output stage employing a discrete-time common-mode negative feedback circuit, in a sampling phase in which a capacitor is jointly charged by an input reference level and a bias voltage, and in a holding phase in which charges are transferred to a feedback path, the common-mode voltage is adjusted, and an amplified differential signal is output in a stable and rapid manner. The invention can provide a high-performance analog circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of amplifiers, and in particular relates to a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure. Background Art

[0002] With the rapid development of electric vehicles, wearable devices, and smart terminals, the importance of battery management systems (BMS) in optimizing battery performance and ensuring system safety has become increasingly prominent. One of the core modules of BMS is the analog-to-digital converter (ADC), whose performance directly determines the accuracy of battery status monitoring. In order to meet the needs of modern portable electronic devices for low-energy, high-precision signal processing, low-energy Sigma-Delta ADC has become an important technical direction.

[0003] In this context, as a key component of Sigma-Delta ADC, operational amplifiers need to achieve high gain, low noise and wide dynamic range at extremely low power supply voltages. However, it is difficult for traditional Class-A structure operational amplifiers to meet these requirements at the same time under low energy consumption conditions. Traditional Class-A structure operational amplifiers have the following limitations: 1. Traditional Class-A structure limitations. Traditional single-stage Class-A operational amplifiers are limited by the size of tail current and it is difficult to balance low energy consumption and high gain; 2. DC gain is limited. Increasing the gain by increasing the size of transistors will introduce higher noise, limiting its application range; 3. Lack of flexibility. Existing technologies are difficult to optimize for different operating modes, especially the combination of low energy consumption and high performance.

[0004] Therefore, there is an urgent need to provide a differential operational amplifier circuit to meet the above requirements. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] In a first aspect, the present invention provides a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure, comprising:

[0007] The input stage uses a differential flip voltage follower and provides a constant bias current through a bias circuit to process the input differential signal;

[0008] A gain stage is operatively coupled to the input stage, the gain stage adopts a cross-coupled pair structure, provides negative impedance through a negative feedback mechanism, and combines with positive impedance to increase the output impedance of the differential signal;

[0009] The output stage is coupled to the input stage in an operational manner. The output stage adopts a discrete time common mode negative feedback circuit. In the sampling phase, the capacitor is charged by the input reference level and the bias voltage. In the holding phase, the charge is transferred to the feedback path to adjust the common mode voltage and output the amplified differential signal in a stable and fast manner.

[0010] Beneficial effects of the present invention:

[0011] The present invention provides a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure, which innovatively combines a differential flip voltage follower and a cross-coupling structure, and successfully realizes the design of an operational amplifier with high gain, low energy consumption and wide dynamic range. The input stage solves the contradiction between power consumption and linear performance, the gain stage achieves an extremely high gain target through structural optimization, and the output stage ensures stability and accuracy through an efficient CMFB circuit. The overall design breaks through the performance bottleneck of traditional operational amplifiers under low voltage and low energy consumption conditions, and provides a universal and efficient solution for high-performance analog circuit design, which is suitable for application scenarios such as analog-to-digital converters, signal conditioning circuits, and sensor interfaces that require high-precision signal processing.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic diagram of a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure provided by an embodiment of the present invention;

[0014] Figure 2 is another schematic diagram of a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure provided by an embodiment of the present invention;

[0015] Figure 3 It is a schematic diagram of a DFVF circuit structure and its small signal equivalent circuit provided by an embodiment of the present invention;

[0016] Figure 4 It is a schematic diagram of a discrete-time common-mode negative feedback circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0018] See also Figure 1 , Figure 1 1 is a schematic diagram of a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure provided by an embodiment of the present invention. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure provided by the present invention includes:

[0019] The input stage uses a differential flip voltage follower and provides a constant bias current through a bias circuit to process the input differential signal;

[0020] A gain stage is operatively coupled to the input stage, the gain stage adopts a cross-coupled pair structure, provides negative impedance through a negative feedback mechanism, and combines with positive impedance to increase the output impedance of the differential signal;

[0021] The output stage is coupled to the input stage in an operational manner in parallel with the gain stage. The output stage adopts a discrete time common mode negative feedback circuit. In the sampling phase, the capacitor is charged by the input reference level and the bias voltage. In the holding phase, the charge is transferred to the feedback path to adjust the common mode voltage and output the amplified differential signal in a stable and fast manner.

[0022] For more details, please see Figure 1 In this embodiment, a high-gain, low-energy differential operational amplifier circuit is provided that combines a differential flipped voltage follower (DFVF) with a cross-coupling structure, which has significant technical innovation and wide application value. This embodiment includes three core parts: an input stage, a gain stage, and an output stage, each of which is optimized and improved for key technical problems in traditional operational amplifier design.

[0023] First, the input stage adopts the DFVF structure, which breaks through the power consumption limitation problem in the traditional Class-A input stage design with its unique Class-AB working characteristics. The DFVF input stage provides a constant bias current through the bias circuit, making the current of the input transistor independent of the tail current, thereby reducing static power consumption and improving dynamic response capability.

[0024] Secondly, the gain stage significantly improves the output impedance of the circuit by introducing a cross-coupled pair structure and utilizing its negative resistance characteristics, thereby achieving extremely high DC gain. The cross-coupled structure provides negative impedance through a negative feedback mechanism, and combined with a positive impedance design, the total output impedance can be adjusted to infinity in the design, thereby achieving a gain of more than 90dB. This structure not only meets the design requirements of high gain, but also improves the working efficiency and performance stability of the circuit.

[0025] Finally, in order to solve the common-mode output voltage offset problem of fully differential operational amplifiers, this embodiment introduces a discrete-time common-mode negative feedback (CMFB) circuit in the output stage. The CMFB circuit achieves fast and accurate common-mode voltage regulation through a simple switch and capacitor structure, significantly improving the stability and response speed of the circuit. In the sampling phase (clock φ1), the capacitor is charged by the input reference level and bias voltage; in the transfer and hold phase (clock φ2), the charge is transferred to the feedback path to adjust the common-mode point; the design without the need for an additional clock not only reduces the circuit complexity, but also further improves the reliability of the system.

[0026] The present invention innovatively combines DFVF and cross-coupling structure, and successfully realizes the design of an operational amplifier with high gain, low energy consumption and wide dynamic range. Its input stage solves the contradiction between power consumption and linear performance, the gain stage achieves a very high gain target through structural optimization, and the output stage ensures stability and accuracy through an efficient CMFB circuit. The overall design breaks through the performance bottleneck of traditional operational amplifiers under low voltage and low energy consumption conditions, and provides a universal and efficient solution for high-performance analog circuit design, which is suitable for application scenarios that require high-precision signal processing, such as analog-to-digital converters (ADCs), signal conditioning circuits, and sensor interfaces.

[0027] In an optional embodiment of the present invention, see Figure 2 , Figure 2 is another schematic diagram of a differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure provided by an embodiment of the present invention, wherein the differential flip voltage follower includes a first flip voltage follower and a second flip voltage follower; wherein,

[0028] The first flip voltage follower includes a first transistor M1, a third transistor M3, a fifth transistor M5 and a ninth transistor M9. The gate of the first transistor M1 is connected to the first differential signal V IN The source of the first transistor M1 is connected to the drain of the fifth transistor M5, the drain of the first transistor M1 is connected to the drain of the ninth transistor M9, the source of the fifth transistor M5 is grounded GND, the source of the ninth transistor M9 is connected to the fixed voltage signal terminal VDD, the gate of the ninth transistor M9 is connected to the common mode reference level VB1, and the gate of the third transistor M3 is connected to the first differential signal V IN ;

[0029] The second flip voltage follower includes a second transistor M2, a fourth transistor M4, a sixth transistor M6 and a tenth transistor M10. The gate of the second transistor M2 is connected to the second differential signal V IPThe source of the second transistor M2 is connected to the drain of the sixth transistor M6, the drain of the second transistor M2 is connected to the drain of the tenth transistor M10, the source of the sixth transistor M6 is grounded GND, the source of the tenth transistor M10 is connected to the fixed voltage signal terminal VDD, the gate of the tenth transistor M10 is connected to the common mode reference level VB1, and the gate of the fourth transistor M4 is connected to the second differential signal V IP .

[0030] In an optional embodiment of the present invention, please continue to refer to Figure 2 , the first flip voltage follower further includes a seventh transistor M7, a gate of the seventh transistor M7 is connected to the first node N1, a source of the seventh transistor M7 is connected to the fixed voltage signal terminal VDD, a drain of the seventh transistor M7 is connected to the second node N2, a drain of the first transistor M1 and a drain of the ninth transistor M9 are both connected to the first node N1, and a gate of the fifth transistor M5 is connected to the second node N2;

[0031] The second flip voltage follower further includes an eighth transistor M8, a gate of the eighth transistor M8 is connected to the third node N3, a source of the eighth transistor M8 is connected to the fixed voltage signal terminal VDD, a drain of the eighth transistor M8 is connected to the fourth node N4, a drain of the second transistor M2 and a drain of the tenth transistor M10 are both connected to the third node N3, and a gate of the sixth transistor M6 is connected to the fourth node N4;

[0032] The seventh transistor M7 and the eighth transistor M8 form a common source stage to expand the voltage range of the input differential signal.

[0033] In an optional embodiment of the present invention, the first flip voltage follower further includes an eleventh transistor M11, a gate of the eleventh transistor M11 is connected to the fourth voltage signal VB4, a drain of the eleventh transistor M11 is connected to the second node N2, and a source of the eleventh transistor M11 is grounded GND;

[0034] The second inverted voltage follower further includes a twelfth transistor M12, a gate of the twelfth transistor M12 is connected to the fourth voltage signal VB4, a drain of the twelfth transistor M12 is connected to the fourth node N4, and a source of the twelfth transistor M12 is grounded GND.

[0035] Specifically, see Figure 3 , Figure 3 This is a schematic diagram of the DFVF circuit structure and its small signal equivalent circuit provided by an embodiment of the present invention, see Figure 3 In (a), the amplifier unit is composed of a PMOS tube M1', a PMOS tube M2', a PMOS tube M3', and an NMOS tube M4', wherein the current flowing through the input transistor M1' is a constant bias current I S, the current flowing through the input transistor M1' and the tail current I B It is irrelevant. It should be noted that the M1' tube is a common source follower, and its source voltage changes with the input voltage. At the same time, the DFVF structure constitutes voltage negative feedback, that is, the M3' tube samples the drain voltage of the M1' tube, which is intended to solve the problems of insufficient linearity and high power consumption of the traditional operational amplifier input stage. The following is a detailed description of the structure of the circuit and its working principle.

[0036] PMOS tubes M1' and M2' serve as the differential input stage of the circuit, receiving input signals V X and V Y The PMOS tube M3' is used to sample the drain voltage of M1, forming a voltage negative feedback to enhance the stability of the circuit. The NMOS tube M4' provides a constant bias current and controls the voltage V B Adjust the circuit operating point. The differential signal V X and V Y The gates of M1' and M2' are inputted respectively to control the conduction state of M1' and M2'. The sources of M1' and M2' are connected and then connected to the drain of M3' to form a differential transconductance structure. The gate of M3' is connected to the drain of M1', and its source is connected to the power supply potential VDD. M3' samples the voltage signal of the drain of M1' and feeds it back to the source of M1' to achieve dynamic voltage negative feedback; this negative feedback mechanism can quickly respond to changes in the input signal and improve the linearity and stability of the circuit. The source of M4' is grounded to the GND potential GND, the drain of M4' is connected to the drain of M1', and the gate of M4' is connected to the control potential V B , where the current flowing through the input transistor M1' is a constant bias current I S With tail current I B Not relevant.

[0037] As a source follower, the source voltage of M1' closely follows the input signal V X This characteristic ensures the linear transfer performance of the input signal. X and V Y The gates of M1' and M2' are applied to drive the two tubes to work in different conduction states, thereby generating differential transconductance output. M3' samples the voltage of the drain of M1' and introduces the feedback signal into the source of M1' to form a closed-loop feedback loop. This feedback mechanism can effectively suppress the circuit deviation caused by the input signal and ensure that the circuit has high stability during dynamic operation. S Completely independent of the tail current I B Therefore, the circuit has low static power consumption while maintaining high performance, and is particularly suitable for low-energy application scenarios.

[0038] Further, based on the above embodiments, see Figure 3 In (b), the open-loop gain of the circuit is:

[0039]

[0040] Among them, g m3 represents the transconductance of the transistor, r o3 represents the small signal output resistance of the transistor, and the open-loop output resistance of the output node X is:

[0041] R X.open ≈((1+r ob / r o1 ) / g m1 )||r o2 ;

[0042] Then the closed-loop output resistance of the output node X can be calculated as:

[0043]

[0044] In the actual circuit, there is r ob ≈r o1 , g m1 r o3 >>1, output resistance R X.closed Can be simplified to 2 / g m1 g m3 r o1 It can be seen that the output impedance of this structure is very low, so when the input differential voltage V X and V Y When the tail current I B It can continue to increase without being limited by the bias current, so a very small bias current can be used to generate a larger tail current, ultimately making the static power consumption of the op amp lower.

[0045] certainly, Figure 3 The amplifier unit described in the embodiment shown is composed of a PMOS tube M1', a PMOS tube M2', a PMOS tube M3', and an NMOS tube M4'. Figure 2 In the embodiment, the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are all NMOS transistors, and the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the tenth transistor M10 are PMOS transistors. Figure 3 The implementation principle is applied to Figure 2 In this way, the differential flip voltage follower in the differential operational amplifier circuit can achieve the same effect.

[0046] In an optional embodiment of the present invention, please continue to refer to Figure 2 The cross-coupled transistor structure includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16; wherein,

[0047] The drain of the thirteenth transistor M13 is connected to the fifth node N5, the source of the thirteenth transistor M13 is grounded GND, the drain of the fourteenth transistor M14 is connected to the sixth node N6, the source of the fourteenth transistor M14 is grounded GND, the drain of the fifteenth transistor M15 is connected to the fifth node N5, the source of the fifteenth transistor M15 is grounded GND, the gate of the fifteenth transistor M15 is connected to the sixth node N6, the drain of the sixteenth transistor M16 is connected to the sixth node N6, the source of the sixteenth transistor M16 is grounded GND, and the gate of the sixteenth transistor M16 is connected to the fifth node N5.

[0048] Specifically, the cross-coupling mentioned in this embodiment can bring about a high gain effect to the tube structure.

[0049] In an optional embodiment of the present invention, please continue to refer to Figure 2 , the output stage includes a current mirror structure, including a seventeenth transistor M17 and an eighteenth transistor M18; wherein,

[0050] The gate of the seventeenth transistor M17 is connected to the gate of the eighteenth transistor M18 and is connected to the common mode feedback voltage V CMFB , the drain of the seventeenth transistor M17 is connected to the drain of the third transistor M3, the drain of the seventeenth transistor M17 is also connected to the first node N1, and the source of the seventeenth transistor M17 is connected to the fixed voltage signal terminal VDD; the drain of the eighteenth transistor M18 is connected to the drain of the fourth transistor M4, the drain of the eighteenth transistor M18 is also connected to the third node N3, and the source of the eighteenth transistor M18 is connected to the fixed voltage signal terminal VDD;

[0051] Common mode feedback voltage V CMFB Provided by a discrete-time common-mode negative feedback circuit, the stable common-mode feedback voltage is provided in real time.

[0052] In an optional embodiment of the present invention, see Figure 4 , Figure 4 is a schematic diagram of a discrete-time common-mode negative feedback circuit provided by an embodiment of the present invention, wherein the discrete-time common-mode negative feedback circuit comprises a plurality of first switches, a plurality of second switches, a plurality of first capacitors and a plurality of second capacitors, wherein the number of the first switches is the same as the number of the second switches, and the number of the first capacitors is the same as the number of the second capacitors; wherein,

[0053] First switch Φ 1-1 The first end of the common mode reference level VB1 is connected, and the first switch Φ1-1 The second end of the first capacitor C 1-1 The first end of the second switch Φ 2-1 The first end of the first capacitor C 1-1 The first end of the second switch Φ 2-1 The second end of the second capacitor C 2-1 The first end of the second capacitor C 2-1 The first end is also connected to the amplified first differential signal V ON ;

[0054] First switch Φ 1-2 The first end of the first switch Φ 1-2 The second end of the first capacitor C 1-1 The second end of the second switch Φ 2-2 The first end of the first capacitor C 1-1 The second end of the second switch Φ 2-2 The second end of the second capacitor C 2-1 The second end of the second capacitor C 2-1 The second end also outputs a first common-mode feedback voltage;

[0055] First switch Φ 1-3 The first end of the common mode reference level VB1 is connected, and the first switch Φ 1-3 The second end of the first capacitor C 1-2 The first end of the second switch Φ 2-3 The first end of the first capacitor C 1-2 The first end of the second switch Φ 2-3 The second end of the second capacitor C 2-2 The first end of the second capacitor C 2-2 The first end is also connected to the amplified differential signal V OP ;

[0056] First switch Φ 1-4 The first end of the first switch Φ 1-4 The second end of the first capacitor C 1-2 The second end of the second switch Φ 2-4 The first end of the first capacitor C 1-2 The second end of the second switch Φ 2-4 The second end of the second capacitor C 2-2 The second end of the second capacitor C 2-2 The second end also outputs a second common-mode feedback voltage;

[0057] The first common-mode feedback voltage is combined with the second common-mode feedback voltage to form the common-mode feedback voltage.

[0058] In an optional embodiment of the present invention, the common-mode feedback voltage V CMFB The expression is:

[0059]

[0060] Among them, V CM represents the common mode reference level, VB1 represents the bias voltage, V ON Represents the first differential signal after amplification, V OP represents the amplified second differential signal.

[0061] Specifically, due to the inherent defect of the Class-AB input stage that the input voltage range is too low, a common source stage consisting of the seventh transistor M7 and the eighth transistor M8 is added to the DFVF unit structure to expand the input differential voltage range. In order to achieve a gain of up to 90dB, a cross-coupled transistor structure consisting of the thirteenth transistor M13, the fourteenth transistor M14, the fifteenth transistor M15 and the sixteenth transistor M16 is used in the traditional current mirror amplifier. In this structure, the fifteenth transistor M15 and the sixteenth transistor M16 form a negative feedback to form a negative resistance R 1 =-2 / g m1 , g m1 The thirteenth transistor M13 and the fourteenth transistor M14 form a positive feedback to form a positive resistance R 2 =2 / g m2 , so the total output resistance in parallel is:

[0062] R out =2 / (g m1 -g m2 );

[0063] When m1 ≈g m2 When , the output impedance is infinite, so high gain can be achieved. The final op amp DC gain expression is:

[0064]

[0065] In this formula, B is the current replication ratio of the current mirror amplifier, (g m19 r o19 r o21 )||(g m25 r o25 r o23 ) is the output impedance of the op amp output, and K represents the transconductance proportional factor of the cross-coupled tube.

[0066] In addition, due to device process mismatch, the output common-mode point of the fully differential operational amplifier may be offset, so it is necessary to introduce a common-mode negative feedback circuit to stabilize the output common-mode voltage. In the design of discrete-time Sigma-Delta modulators, discrete-time common-mode negative feedback circuits are usually used. Compared with continuous-time common-mode negative feedback circuits, this circuit has higher efficiency and simplified design. Compared with continuous-time common-mode negative feedback circuits, discrete-time common-mode negative feedback circuits are only composed of switches and capacitors, and do not require additional clocks.

[0067] Please continue to see Figure 4 , V ON and V OP Represents the differential output voltage of the op amp, V CM is the common-mode reference level of the input, V CMFB is the common-mode feedback input voltage of the op amp, VB1 is the bias voltage, and generally VB1≈V CMFB , Φ 1 and Φ 2 The working principle of the common-mode negative feedback circuit is: in the sampling stage Φ 2 , sampling capacitor C 2 By the input reference level V CM and the bias voltage VB1 are charged together. 1 , C 2 Charge transfer to C 1 and determine C at that moment 1 After multiple cycles, the common-mode feedback voltage V CMFB for:

[0068]

[0069] In this circuit, C 2 Capacitance Ratio C 1 The capacitor size is about 5 to 10 times larger. On the one hand, the common-mode negative feedback circuit can sink the output common-mode voltage faster and reduce the deviation between the op amp output common-mode voltage and the reference voltage; on the other hand, it can also increase the bandwidth of the negative feedback loop, better track fast common-mode level changes, and will not increase the load.

[0070] In an optional embodiment of the present invention, please continue to refer to Figure 2 The output stage further includes a current bias circuit, including a nineteenth transistor M19, a twentieth transistor M20, a twenty-first transistor M21, and a twenty-second transistor M22; wherein,

[0071] The source of the nineteenth transistor M19 is connected to the fixed voltage signal terminal VDD, the gate of the nineteenth transistor M19 is connected to the third voltage signal VB3, the drain of the nineteenth transistor M19 is connected to the source of the twenty-first transistor M21, the gate of the twenty-first transistor M21 is connected to the second voltage signal VB2, and the drain of the twenty-first transistor M21 is connected to the first signal output terminal;

[0072] The source of the twentieth transistor M20 is connected to the fixed voltage signal terminal VDD, the gate of the twentieth transistor M20 is connected to the third voltage signal VB3, the drain of the twentieth transistor M20 is connected to the source of the twenty-second transistor M22, the gate of the twenty-second transistor M22 is connected to the second voltage signal VB2, and the drain of the twenty-second transistor M22 is connected to the second signal output terminal.

[0073] In an optional embodiment of the present invention, please continue to refer to Figure 2 The output stage further includes a load circuit, including a twenty-third transistor M23, a twenty-fourth transistor M24, a twenty-fifth transistor M25 and a twenty-sixth transistor M26; wherein,

[0074] The drain of the twenty-third transistor M23 is connected to the first signal output terminal, and the gate of the twenty-third transistor M23 is connected to the first differential signal V IN , a source of the twenty-third transistor M23 is connected to a drain of the twenty-fifth transistor M25, a gate of the twenty-fifth transistor M25 is connected to the fifth node N5, and a source of the twenty-fifth transistor M25 is grounded GND;

[0075] The drain of the twenty-fourth transistor M24 is connected to the second signal output terminal, and the gate of the twenty-fourth transistor M24 is connected to the second differential signal V IP The source of the twenty-fourth transistor M24 is connected to the drain of the twenty-sixth transistor M26, the gate of the twenty-sixth transistor M26 is connected to the sixth node N6, and the source of the twenty-sixth transistor M26 is grounded GND.

[0076] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0077] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0078] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure, characterized in that: include: The input stage uses a differential flip voltage follower and provides a constant bias current through a bias circuit to process the input differential signal; A gain stage is operatively coupled to the input stage, wherein the gain stage adopts a cross-coupled pair structure and provides negative impedance through a negative feedback mechanism, combined with positive impedance, to increase the output impedance of the differential signal; The output stage is coupled to the input stage in an operational manner in parallel with the gain stage. The output stage adopts a discrete time common mode negative feedback circuit. In the sampling phase, the capacitor is charged by the input reference level and the bias voltage. In the holding phase, the charge is transferred to the feedback path to adjust the common mode voltage and output the amplified differential signal in a stable and fast manner.

2. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 1, characterized in that: The differential flip voltage follower includes a first flip voltage follower and a second flip voltage follower; wherein, The first flip voltage follower comprises a first transistor, a third transistor, a fifth transistor and a ninth transistor, the gate of the first transistor is connected to the first differential signal, the source of the first transistor is connected to the drain of the fifth transistor, the drain of the first transistor is connected to the drain of the ninth transistor, the source of the fifth transistor is grounded, the source of the ninth transistor is connected to the fixed voltage signal terminal, the gate of the ninth transistor is connected to the common mode reference level, and the gate of the third transistor is connected to the first differential signal; The second flip voltage follower includes a second transistor, a fourth transistor, a sixth transistor and a tenth transistor, the gate of the second transistor is connected to the second differential signal, the source of the second transistor is connected to the drain of the sixth transistor, the drain of the second transistor is connected to the drain of the tenth transistor, the source of the sixth transistor is grounded, the source of the tenth transistor is connected to the fixed voltage signal terminal, the gate of the tenth transistor is connected to the common mode reference level, and the gate of the fourth transistor is connected to the second differential signal.

3. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 2, characterized in that: The first flip voltage follower further includes a seventh transistor, the gate of the seventh transistor is connected to the first node, the source of the seventh transistor is connected to the fixed voltage signal terminal, the drain of the seventh transistor is connected to the second node, the drain of the first transistor and the drain of the ninth transistor are both connected to the first node, and the gate of the fifth transistor is connected to the second node; The second flip voltage follower further includes an eighth transistor, the gate of the eighth transistor is connected to the third node, the source of the eighth transistor is connected to the fixed voltage signal terminal, the drain of the eighth transistor is connected to the fourth node, the drain of the second transistor and the drain of the tenth transistor are both connected to the third node, and the gate of the sixth transistor is connected to the fourth node; The seventh transistor and the eighth transistor form a common source stage to expand the voltage range of the input differential signal.

4. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 3, characterized in that: The first flip voltage follower further includes an eleventh transistor, a gate of the eleventh transistor is connected to the fourth voltage signal, a drain of the eleventh transistor is connected to the second node, and a source of the eleventh transistor is grounded; The second inverted voltage follower further includes a twelfth transistor, a gate of the twelfth transistor is connected to a fourth voltage signal, a drain of the twelfth transistor is connected to the fourth node, and a source of the twelfth transistor is grounded.

5. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 1, characterized in that: The cross-coupled transistor structure includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; wherein, The drain of the thirteenth transistor is connected to the fifth node, the source of the thirteenth transistor is grounded, the drain of the fourteenth transistor is connected to the sixth node, the source of the fourteenth transistor is grounded, the drain of the fifteenth transistor is connected to the fifth node, the source of the fifteenth transistor is grounded, the gate of the fifteenth transistor is connected to the sixth node, the drain of the sixteenth transistor is connected to the sixth node, the source of the sixteenth transistor is grounded, and the gate of the sixteenth transistor is connected to the fifth node.

6. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 1, characterized in that: The output stage comprises a current mirror structure, including a seventeenth transistor and an eighteenth transistor; wherein, The gate of the seventeenth transistor is connected to the gate of the eighteenth transistor and connected to the common-mode feedback voltage, the drain of the seventeenth transistor is connected to the drain of the third transistor, the drain of the seventeenth transistor is also connected to the first node, and the source of the seventeenth transistor is connected to the fixed voltage signal terminal; the drain of the eighteenth transistor is connected to the drain of the fourth transistor, the drain of the eighteenth transistor is also connected to the third node, and the source of the eighteenth transistor is connected to the fixed voltage signal terminal; The common-mode feedback voltage is provided by the discrete-time common-mode negative feedback circuit, which provides the stable common-mode feedback voltage in real time.

7. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 6, characterized in that: The discrete-time common-mode negative feedback circuit comprises a plurality of first switches, a plurality of second switches, a plurality of first capacitors and a plurality of second capacitors, the number of the first switches is the same as the number of the second switches, and the number of the first capacitors is the same as the number of the second capacitors; wherein, First switch Φ 1-1 The first end of the common mode reference level VB1 is connected, and the first switch Φ 1-1 The second end of the first capacitor C 1-1 The first end of the second switch Φ 2-1 The first end of the first capacitor C 1-1 The first end of the second switch Φ 2-1 The second end of the second capacitor C 2-1 The first end of the second capacitor C 2-1 The first end is also connected to the amplified first differential signal; First switch Φ 1-2 The first end of the first switch Φ 1-2 The second end of the first capacitor C 1-1 The second end of the second switch Φ 2-2 The first end of the first capacitor C 1-1 The second end of the second switch Φ 2-2 The second end of the second capacitor C 2-1 The second end of the second capacitor C 2-1 The second end also outputs a first common-mode feedback voltage; First switch Φ 1-3 The first end of the common mode reference level VB1 is connected, and the first switch Φ 1-3 The second end of the first capacitor C 1-2 The first end of the second switch Φ 2-3 The first end of the first capacitor C 1-2 The first end of the second switch Φ 2-3 The second end of the second capacitor C 2-2 The first end of the second capacitor C 2-2 The first end is also connected to the amplified second differential signal; First switch Φ 1-4 The first end of the first switch Φ 1-4 The second end of the first capacitor C 1-2 The second end of the second switch Φ 2-4 The first end of the first capacitor C 1-2 The second end of the second switch Φ 2-4 The second end of the second capacitor C 2-2 The second end of the second capacitor C 2-2 The second end also outputs a second common-mode feedback voltage; The first common-mode feedback voltage is combined with the second common-mode feedback voltage to form the common-mode feedback voltage.

8. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 7, characterized in that: The common-mode feedback voltage V CMFB The expression is: Among them, V CM represents the common mode reference level, VB1 represents the bias voltage, V ON Represents the first differential signal after amplification, V OP represents the amplified second differential signal.

9. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 1, characterized in that: The output stage further includes a current bias circuit, including a nineteenth transistor, a twentieth transistor, a twenty-first transistor and a twenty-second transistor; wherein, The source of the nineteenth transistor is connected to the fixed voltage signal terminal, the gate of the nineteenth transistor is connected to the third voltage signal, the drain of the nineteenth transistor is connected to the source of the twenty-first transistor, the gate of the twenty-first transistor is connected to the second voltage signal, and the drain of the twenty-first transistor is connected to the first signal output terminal; The source of the 20th transistor is connected to the fixed voltage signal terminal, the gate of the 20th transistor is connected to the third voltage signal, the drain of the 20th transistor is connected to the source of the 22nd transistor, the gate of the 22nd transistor is connected to the second voltage signal, and the drain of the 22nd transistor is connected to the second signal output terminal.

10. The differential operational amplifier circuit based on a flip voltage follower and a cross-coupling structure according to claim 1, characterized in that: The output stage further includes a load circuit including a twenty-third transistor, a twenty-fourth transistor, a twenty-fifth transistor and a twenty-sixth transistor; wherein, The drain of the twenty-third transistor is connected to the first signal output terminal, the gate of the twenty-third transistor is connected to the first differential signal, the source of the twenty-third transistor is connected to the drain of the twenty-fifth transistor, the gate of the twenty-fifth transistor is connected to the fifth node, and the source of the twenty-fifth transistor is grounded; The drain of the 24th transistor is connected to the second signal output terminal, the gate of the 24th transistor is connected to the second differential signal, the source of the 24th transistor is connected to the drain of the 26th transistor, the gate of the 26th transistor is connected to the sixth node, and the source of the 26th transistor is grounded.

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