Amplifying device and transmitter

Abstract

Embodiments of the present application relate to an amplifying device and a transmitter. An amplifying device and a transmitter capable of compensating for a parasitic component of a circuit element without complicating a circuit structure are provided. The amplifying device includes a first amplifier that performs an amplifying operation on a signal; N-1 second amplifiers that perform an amplifying operation on the signal in sequence according to an amplitude of the signal in a case where the first amplifier performs the amplifying operation; N input networks connected to an input terminal that inputs the signal; N output networks connected between an output node of the first amplifier and a load connection node and connected between output nodes of the N-1 second amplifiers and the load connection node; and a first bias network that supplies a direct current bias voltage to at least one of the N output networks, an electrical length of the first bias network being less than 90 degrees.

Description

[0001] This application is a divisional application. The parent application was filed on February 23, 2018, with application number 201810154415.2, and the invention title is "Amplification Device and Transmitter".

[0002] This application is based on Japanese Patent Application No. 2017-180690 (filed on September 20, 2017), and enjoys priority under that application. This application includes all the contents of that Japanese application. Technical Field

[0003] Embodiments of the present invention relate to an amplification device and a transmitter. Background Technology

[0004] A Doherty amplifier is known to have a number of amplifiers that dynamically switch operation based on the amplitude of a high-frequency input signal. A Doherty amplifier consists of one main amplifier and one or more peak amplifiers. When the number of amplifiers used is N, it is called an N-channel Doherty amplifier. The main amplifier operates normally, while the peak amplifiers only operate under high power conditions. A 2-channel Doherty amplifier with one peak amplifier is common, but structures using two or more peak amplifiers also exist. Each amplifier uses a transistor (bipolar junction transistor, FET) as the amplifying element. Due to the parasitic components in transistors, it is possible for the amplification operation to deviate significantly from the ideal amplification. Summary of the Invention

[0005] The problem this invention aims to solve is to provide an amplification device and transmitter that can compensate for parasitic components of circuit elements without complicating the circuit structure.

[0006] In the amplification device, N input networks are connected to the input terminals of the input signals. A first amplifier amplifies one output signal from the N input networks. While the first amplifier is amplifying, N-1 second amplifiers amplify N-1 output signals from the N input networks, excluding the first output signal, based on the amplitude of the output signals from the N input networks, where N is an integer greater than or equal to 3. In the N output networks, one is connected between the output node of the first amplifier and the load connection node, and the remaining N-1 are connected sequentially between the output nodes of the N-1 second amplifiers and the load connection node. A first bias network supplies a DC bias voltage to at least one of the N output networks. The electrical length of the first bias network is less than 90 degrees.

[0007] Based on the above structure, the parasitic components of circuit elements can be compensated without complicating the circuit structure. Attached Figure Description

[0008] Figure 1 This is an equivalent circuit diagram of an amplification device in one implementation.

[0009] Figure 2 yes Figure 1 A conceptual block diagram of the amplification device.

[0010] Figure 3 This is an equivalent circuit diagram of an amplifier for a comparative example.

[0011] Figure 4A It is shown Figure 1 The circuit diagram of the basic structure of the main amplifier in the amplification device.

[0012] Figure 4B It is shown Figure 4A The graph shows the phase change caused by the frequency of S21 in the circuit and the amplitude change caused by the frequency of S21.

[0013] Figure 4C It is shown Figure 1 The circuit diagram of the basic structure of the peak amplifier in the amplification device.

[0014] Figure 5 Yes Figure 1 An amplification device with a second bias network is added.

[0015] Figure 6A It is shown Figure 5 The circuit diagram of the basic structure of the main amplifier in the amplification device.

[0016] Figure 6B It is shown on the Smith chart. Figure 6A The circuit characteristics are shown in the diagram.

[0017] Figure 7 It is an amplification device in which the output node of the peak amplifier on the right end is connected to the first bias network.

[0018] Figure 8 It is an amplification device in which the output nodes of the peak amplifiers other than the left and right ends are also connected to the first bias network.

[0019] Figure 9 From Figure 8 The amplification device of the second bias network is omitted.

[0020] Figure 10 It is an amplification device with inductor elements set as a bias network.

[0021] Figure 11 This is a block diagram illustrating an example of the internal structure of a transmitter.

[0022] (Symbol Explanation)

[0023] 1: Amplifier; 2: Input splitter; 3: Main amplifier; 4: Peak amplifier; 5: Input network; 6: Output network; 7: First bias network; 8: Output synthesizer; 9: DC voltage source; 10: Second bias network; 11: Transmitter; 12: Baseband processing unit; 13: Local oscillator; 14: Modulator; 15: High-frequency amplifier; 16: Antenna. Detailed Implementation

[0024] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, although some structural parts have been omitted, modified, or simplified in this specification and drawings for ease of understanding and illustration, the technical content to the extent that the same function can be expected is included in the explanation of these embodiments.

[0025] Figure 1 This is an equivalent circuit diagram of an amplifier device 1 according to one embodiment. Figure 2 yes Figure 1 A conceptual block diagram of the amplification device 1 is provided. Here, the transistor is represented as an ideal current source. The amplification device 1 of this embodiment is an N-channel Dougherty amplification device 1 that operates by dynamically switching the number of amplifiers according to the amplitude of the high-frequency input signal. N-channel indicates that it has N amplifiers. N is 3 or more. Unless otherwise specified, the electrical length is set to the electrical length relative to the fundamental frequency.

[0026] like Figure 1 as well as Figure 2 As shown, the amplification device 1 of this embodiment includes an input splitter 2, a main amplifier (first amplifier) ​​3, N-1 peak amplifiers (second amplifiers) 4 (N being an integer greater than or equal to 3) 4, N input networks 5, N output networks 6, a first bias network 7, an output synthesizer 8, and a DC voltage source 9. These main amplifiers 3 and N-1 peak amplifiers 4 are connected in parallel. The input networks 5, output networks 6, and bias network 7 can be implemented using transmission lines, components with lumped constants such as coils and capacitors, or waveguides. Alternatively, they can be implemented using combinations thereof. A single DC voltage from the DC voltage source 9 is supplied to the main amplifiers 3 and each peak amplifier 4. This single DC voltage is used as the bias voltage, as described later. Here, the bias voltage refers to the voltage applied to the drain of a FET or the collector of a bipolar transistor. Thus, applying bias using a single DC voltage is one of its features.

[0027] Through N output networks 6, the output nodes of the main amplifier 3 and each peak amplifier 4 are connected to a load connection node n1, to which a common load resistor R is connected. The main amplifier 3 amplifies the signal. The main amplifier 3 continuously amplifies the signal during the input signal period. The signal input to the main amplifier 3 is... Figure 2 The input signal of the input splitter 2 shown is divided into N signals and input to N input networks 5, and one of the signals output from the N input networks 5 is also input. When the output voltage of the main amplifier 3 is set to VM and the output current is set to IM, the main amplifier 3 is equivalently represented as follows: Figure 1 The diagram shows a structure that allows a current source to flow through it, the current being relative to... Figure 1 The phase of the current flowing through the peak amplifier 4 at the right end is shifted by -j×(N-2).

[0028] While the main amplifier 3 is amplifying the signal, N-1 peak amplifiers 4 sequentially amplify the signal according to its amplitude. That is, the number of peak amplifiers 4 amplifying the signal changes based on its amplitude. The larger the signal amplitude, the more peak amplifiers 4 are amplified. This allows for efficient signal amplification and reduces power consumption.

[0029] More specifically, Figure 1 The peak amplifier 4 at the right end of the N-1 peak amplifiers 4 shown is the first to perform amplification. As the amplitude of the signal input to the peak amplifier 4 increases, each peak amplifier 4 starts amplification sequentially from the right end to the left end.

[0030] The output currents flowing through the N-1 peak amplifiers 4 have different phases. Relative to the phase of the current flowing through the peak amplifier 4 at the right end, the phase of the current flowing through the peak amplifier 4 adjacent to the main amplifier 3 at the left end is shifted by the same amount as the main amplifier 3—-j×(N-2)—and the phase of the current flowing through the peak amplifier 4 adjacent to it is shifted by -j×(N-3). Thus, each peak amplifier 4 is equivalently represented as a current source structure with a current flowing through it, each possessing its own inherent phase. Figure 2 The input splitter 2 separates the input signal into multiple input networks 5, thereby generating the phase difference of these currents.

[0031] N input networks 5 are connected between the input terminals of the input signal to the input splitter 2 and the input node of the main amplifier 3, and are respectively connected between the input terminals and the input nodes of N-1 peak amplifiers 4. The phase offset between the input terminal and the load connection node n1, via the path through one of the N input networks 5 through the main amplifier 3, is designed to be equal to the phase offset between the input terminal and the load connection node, via the path through any one of the N input networks 5 (excluding the aforementioned input network) through one of the peak amplifiers 4. This design can be achieved by adjusting the circuitry constituting the input networks 5 (e.g., the electrical length and width of the microstrip lines).

[0032] N output networks 6 are connected between the output node of the main amplifier 3 and the load connection node n1, and also between the output nodes of N-1 peak amplifiers 4 and the load connection node n1. These output networks 6 are circuits implemented using microstrip lines, LC circuits, etc. These circuits have the characteristic of being able to control higher harmonic impedances, as described later. The ability to control higher harmonic impedances means that each circuit (e.g., the electrical length and width of the microstrip line) can be adjusted individually. For example, the electrical lengths of the N output networks 6 can be adjusted individually to achieve ideal transmission characteristics at the fundamental frequency, the second higher harmonic frequency, and the third higher harmonic frequency.

[0033] The first bias network 7 supplies DC bias voltage to at least one of the output nodes of the main amplifier 3 and the N-1 peak amplifiers 4, i.e., at least one of the N output networks 6. Figure 1 The DC voltage source 9 shown supplies this DC bias voltage. Figure 1 The example shown illustrates connecting the first bias network 7 to the output node of the main amplifier 3, but the first bias network 7 can also be connected to any output node of the N-1 peak amplifiers 4. For example, when multiple output networks 6 are connected to the first bias network 7 respectively, a single DC voltage is supplied to any first bias network 7. Thus, multiple bias power supplies are not required, simplifying the circuit structure of the amplifier 1.

[0034] The transistors and other circuit elements that constitute the main amplifier 3 and the N-1 peak amplifiers 4 have parasitic components. Figure 1 In this diagram, the parasitic components at the output nodes of each amplifier are equivalently represented by parallel capacitors and series inductors. For example, the parallel capacitor of the main amplifier 3 is denoted as CM, and the series inductor is denoted as LM. The parallel capacitor of the peak amplifier 4 on the right is denoted as CP1, and the series inductor is denoted as LP1. The parallel capacitor of the peak amplifier 4 on the left is denoted as CP(N-1), and the series inductor is denoted as LP(N-1).

[0035] exist Figure 1 as well as Figure 2 In the amplification device 1, the first bias network 7 connected to the output node of the main amplifier 3 is configured as a circuit with an electrical length of less than 90 degrees. This circuit supplies DC bias voltage to the N output networks 6 connected to all the output nodes of the main amplifier 3 and the N-1 peak amplifiers 4, and controls the higher harmonic impedance of these amplifiers 3 and 4.

[0036] In addition, Figure 1 as well as Figure 2 In the amplification device 1, the desired amplification operation is achieved by individually adjusting the electrical lengths of the N output networks 6 to be greater than or less than 90 degrees. For example, in the case of the 3-channel Dougherty amplification device 1, the desired amplification performance is obtained by making the electrical length of circuit T1 greater than 90 degrees and the electrical lengths of circuits T2 and T3 less than 90 degrees. The first bias network 7 can also be connected to any two or more output nodes of the main amplifier 3 and each peak amplifier 4, but in this case, a single DC bias voltage is supplied to each first bias network 7.

[0037] Figure 3 This is an equivalent circuit diagram of amplifier device 1 as a comparative example. (And...) Figure 1 The difference lies in Figure 3 The first bias network 7 is not present. Additionally,... Figure 3 The electrical lengths of the N output networks 6 are all 90 degrees. The phase configuration of the output currents of each peak amplifier 4 is designed to achieve phase balance. This is determined by the output nodes of each amplifier. Figure 3 The optimal phase balance in the amplifier device 1 is crucial. Because parasitic components such as those in the transistors constituting the amplifier device 1 have frequency and phase responses, these parasitic components must be considered when designing the N-channel Dougherty amplifier device 1. Parasitic components have the equivalent effect of lengthening or shortening the electrical length of the circuit; however, since the electrical length of the circuit is assumed to be 90 degrees in the ideal amplifier device 1, deviations will occur compared to the actual amplification operation of the amplifier device 1. Furthermore, the internal matching and package shape of the amplifier device 1 are also major reasons why the actual amplification operation of the amplifier device 1 is not ideal.

[0038] In contrast, in this embodiment, such as Figure 1 As shown, a first bias network 7, which supplies a single DC bias voltage, is connected to, for example, the output node of the main amplifier 3, such that the electrical length of the first bias network 7 is less than 90 degrees. Furthermore, the electrical lengths of the N output networks 6 are individually adjusted so that their electrical lengths are greater than or less than 90 degrees. This allows for the compensation of parasitic components in the output nodes of each amplifier.

[0039] Figure 4A as well as Figure 4B It is shown Figure 1 A diagram showing the characteristics of the main amplifier 3 in the amplification device 1. Figure 4A It is shown Figure 1 Circuit diagram of the basic structure of the main amplifier 3 of the amplification device 1. Figure 4B It is shown Figure 4A A graph showing the phase change and amplitude change caused by the frequency of S21 (through) of the circuit's S-parameters. This graph illustrates how to control the second and third higher harmonic impedances while performing amplification operation of the near-ideal N-channel Dougherty amplifier 1. Additionally, Figure 4C It is shown Figure 1 The circuit diagram of the basic structure of the peak amplifier 4 in the amplification device 1.

[0040] exist Figure 4A In the circuit, a parallel capacitor C and a series inductor L are connected to port 1 as parasitic components. Additionally, the output of the series inductor L is connected to port 2 via an output network 6T1 and is also connected to a first bias network 7 that supplies the DC bias voltage VDD. The electrical length of the first bias network 7 is set to be less than 90 degrees. Port 2 and... Figure 1 The load connection node n1 is equivalent.

[0041] Figure 4B The chart shows the proximity Figure 4A A graph showing the ideal characteristics of the circuit is provided. As can be seen from the graph, the phase of S21 at the fundamental frequency is approximately -90 degrees, and the amplitude is approximately 0.75. The phase at the fundamental frequency is set to -90 degrees through the interaction of parasitic components C and L, the first bias network 7, and the output network 6.

[0042] Furthermore, the phase of S21 at the second harmonic is approximately 180 degrees, and the amplitude is approximately 1. Additionally, the phase of S21 at the third harmonic is approximately 0, and the amplitude is minimized to approximately 0.5. The characteristics shown in this graph can be obtained by adjusting the electrical length of the output network 6 to be greater than or less than 90 degrees. In this way, the phase difference between ports 1 and 2 at the fundamental frequency becomes 90 degrees, the phase difference between ports 1 and 2 at the second harmonic becomes 180 degrees, and the phase difference between ports 1 and 2 at the third harmonic becomes 0 degrees.

[0043] As from Figure 4B As can be seen from the diagram, by connecting the output nodes of the main amplifier 3 and the peak amplifier 4 to the first bias network 7 with an electrical length of less than 90 degrees, supplying a single DC bias voltage to the output network 6, and adjusting the electrical length of the output network 6 to be greater than or less than 90 degrees, it is possible to achieve near-ideal amplification operation while taking into account the influence of parasitic components in the output nodes of the amplifier device 1.

[0044] However, if only N output networks 6 and the first bias network 7 are set, the high-order harmonic control is not sufficient. In order to achieve higher-order harmonic control with greater accuracy, the circuit needs to be further improved.

[0045] Figure 5 Yes Figure 1 This is achieved by adding a second bias network 10. The second bias network 10 is a circuit that provides bias to the load connection node n1 at a level similar to ground. Furthermore, while one end of the second bias network 10 does not necessarily need to be set to ground, this embodiment features the use of a single DC bias voltage. Therefore, the circuit structure is simplified by connecting one end of the second bias network 10 to the overall ground mode. Thus, the second bias network 10 is characterized by using a different voltage level than the first bias network 7 for biasing. The second bias network 10 is used to control the higher harmonics of the main amplifier 3 and the N-1 peak amplifiers 4. Like other networks such as the output network 6, the second bias network 10 can be implemented using transmission lines, components with lumped constants such as coils and capacitors, or waveguides. Alternatively, it can be implemented using combinations of these.

[0046] Figure 6A as well as Figure 6B It is shown Figure 5 A diagram showing the characteristics of the main amplifier 3 in the amplification device 1. Figure 6A It is shown Figure 5 Circuit diagram of the basic structure of the main amplifier 3 of the amplification device 1. Figure 6B It is shown on the Smith chart. Figure 6A The circuit characteristics are shown in the diagram. Figure 6A The circuit is Figure 4A The circuit is formed by adding a second bias network 10. One end of the second bias network 10 is set to ground voltage, and the other end is connected to port 2. Figure 6A In the circuit, with Figure 4A Similarly, in the circuit, the electrical length of the first bias network 7 is set to a value less than 90 degrees, and the electrical length of the output network 6 is set to a value greater than or less than 90 degrees. The electrical length of the second bias network 10 is set to, for example, 90 degrees when one end of it is set to ground level.

[0047] As from Figure 6B As can be seen from the Smith chart, in Figure 6AIn the circuit, by adjusting the electrical length of output network 6 to be greater than or less than 90 degrees, the fundamental frequency f0, the second harmonic 2f0, and the third harmonic 3f0 are roughly aligned in a straight line. More specifically, the second harmonic 2f0 is located at the right end of the Smith chart, approaching an open circuit value. Furthermore, the third harmonic is located at the left end of the Smith chart, approaching a short circuit value. Therefore, Figure 5 as well as Figure 6A The amplification device 1 performs ideal amplification.

[0048] exist Figure 1 as well as Figure 5 In the amplification device 1, the first bias network 7 is not symmetrically connected, but by making the first bias network 7 symmetrically connected, a more ideal amplification operation can be performed. Figure 7 Is it except Figure 5 In addition to the structure of the amplification device 1, the output node of the peak amplifier 4 on the right end is connected to the first bias network 7. Figure 7 In this case, the main amplifier 3 and peak amplifier 4 at the left and right ends are respectively connected to the first bias network 7, so the symmetry becomes better and more ideal amplification can be performed.

[0049] Figure 8 Is it except Figure 7 In addition to the structure of the amplification device 1, the output nodes of the peak amplifier 4, other than the left and right ends, are further connected to the first bias network 7. Figure 8 In the amplification device 1, because the number of first bias networks 7 connected to the output nodes of each peak amplifier 4 is increased, the parasitic components of the output nodes of each peak amplifier 4 can be compensated with higher precision, and the high-order harmonic impedance can be controlled with higher precision, enabling more precise control. Figure 7 It is closer to the ideal amplification action.

[0050] Figure 7 , Figure 8 The amplification device 1 has a second bias network 10, but it can also be like... Figure 9 The second bias network 10 is omitted from the diagram. Furthermore, in each of the above-described amplification devices 1, an example is shown where the first bias network 7 is constructed using transmission lines such as microstrip lines; however, the first bias network 7 can also be constructed as follows... Figure 10 The figure shows an inductor element with a lumped constant.

[0051] In the above Figure 1 , Figures 5-10In the amplification device 1, an example of adjusting the electrical lengths of the N output networks 6, the first bias network 7, and the second bias network 10 is given. However, not only the electrical lengths can be adjusted, but also the widths of the N output networks 6, the first bias network 7, and the second bias network 10. By adjusting the widths, the characteristic impedances of each network can be adjusted, allowing the amplification operation of the amplification device 1 to approach a more ideal operation.

[0052] The application of the amplification device 1 in this embodiment is not particularly limited, and it can be used, for example, inside a transmitter. Figure 11 This is a block diagram illustrating an example of the internal structure of transmitter 11. Figure 11 The transmitter 11 includes a baseband processing unit 12, a local oscillator 13, a modulator 14, a high-frequency amplifier 15, and an antenna 16. The baseband processing unit 12 performs signal processing on the baseband signal. The local oscillator 13 generates a local oscillation signal. The modulator 14 uses the local oscillation signal to modulate the baseband signal to generate a high-frequency signal. The high-frequency amplifier 15 amplifies the high-frequency signal and transmits it to the antenna 16. Figure 1 , Figures 5-10 The amplification device 1 shown can be used inside the high-frequency amplification device 15.

[0053] In addition, Figure 1 In this embodiment, different symbols are used to mark the DC bias voltage supplied to one end of each first bias network 7. However, as described above, a single DC bias voltage can be supplied in this embodiment. Alternatively, depending on the situation, DC bias voltages of their respective voltage levels can be supplied to multiple first bias networks 7.

[0054] Thus, in this embodiment, because the parasitic components of the circuit elements constituting each amplifier within the amplifier 1 are compensated and the higher harmonic impedances are controlled, the amplifier 1 can perform amplification operations close to ideal amplification operations. This improves the average power efficiency of signals with a large dynamic range. Furthermore, since a single DC bias voltage is used, only a single DC voltage source 9 is required, simplifying the overall structure of the amplifier 1.

[0055] More specifically, in this embodiment, by adjusting the electrical length of the first bias network 7 of the output network 6, parasitic component compensation and high-order harmonic impedance control are achieved, thus enabling the amplifier 1 to perform ideal amplification without complicating the circuit structure. Furthermore, by providing the second bias network 10, high-order harmonic impedance control can be achieved with even higher precision.

[0056] In this way, by controlling the higher harmonic impedance, the performance of the transistor used in the amplifier device 1 can be improved. Furthermore, while the analysis and countermeasures for parasitic elements in transistors are time-consuming, according to this embodiment, the effects of parasitic elements in transistors can be compensated for with high precision.

[0057] Furthermore, the above-described embodiments can be summarized into the following technical solutions.

[0058] (Technical Solution 1)

[0059] An amplification device comprising:

[0060] N input networks are connected to the input terminals of the input signals;

[0061] The first amplifier amplifies one output signal from the N input networks;

[0062] N-1 second amplifiers, when the first amplifier has performed an amplification operation, amplify N-1 output signals from the N input networks, excluding the first output signal, based on the amplitude of the output signals from the N input networks, where N is an integer greater than or equal to 3;

[0063] N output networks are connected between the output nodes of the first amplifier and the load connection nodes, and also connected between the output nodes of the N-1 second amplifiers and the load connection nodes; and

[0064] The first bias network supplies a DC bias voltage to at least one of the N output networks.

[0065] The electrical length of the first bias network is less than 90 degrees.

[0066] (Technical Solution 2)

[0067] According to the amplification device described in technical solution 1,

[0068] The phase offset between the input terminal and the load connection node via the path through the first amplifier via one of the N input networks is equal to the phase offset between the input terminal and the load connection node via the path through the second amplifier via any of the N input networks other than the one input network.

[0069] (Technical Solution 3)

[0070] According to the amplification device described in technical solution 1 or 2,

[0071] Each of the N output networks has a network capable of controlling the impedance of higher harmonics.

[0072] (Technical Solution 4)

[0073] According to the amplification device described in technical solution 3,

[0074] The electrical lengths of the N output networks are adjusted individually.

[0075] The electrical lengths of the N output networks are adjusted to values ​​greater than or less than 90 degrees.

[0076] (Technical Solution 5)

[0077] According to the amplification device described in technical solution 4,

[0078] The electrical lengths of the N output networks are individually adjusted so that the transmission characteristics of the input signal at the fundamental frequency, the second harmonic frequency, and the third harmonic frequency are ideal.

[0079] (Technical Solution 6)

[0080] The amplification device described in any one of technical solutions 1 to 5

[0081] Multiple first bias networks are configured to be connected to two or more of the N output networks respectively.

[0082] The same DC bias voltage is supplied to one end of each of the plurality of first bias networks.

[0083] (Technical Solution 7)

[0084] The amplification device described in any one of technical solutions 1 to 6,

[0085] The amplification device includes a second bias network, which sets a different voltage level for the load connection node than the first bias network.

[0086] (Technical Solution 8)

[0087] According to the amplification device described in technical solution 7,

[0088] The second bias network controls the higher harmonic impedance of the N output networks.

[0089] (Technical Solution 9)

[0090] According to the amplification device described in technical solution 7 or 8,

[0091] One end of the second bias network is set to ground level.

[0092] (Technical Solution 10)

[0093] The amplification device described in any one of technical solutions 7 to 9

[0094] The electrical length and width of the N output networks, the first bias network, and the second bias network are adjusted individually.

[0095] (Technical Solution 11)

[0096] A transmitter, comprising:

[0097] The baseband processing unit performs signal processing on the baseband signals;

[0098] A modulator that uses a local oscillation signal to modulate the baseband signal to generate a high-frequency signal; and

[0099] The high-frequency amplification device amplifies the high-frequency signal and sends it to the antenna.

[0100] The high-frequency amplification device includes:

[0101] N input networks are connected to the input terminals of the input signals;

[0102] The first amplifier amplifies one output signal from the N input networks;

[0103] N-1 second amplifiers, when the first amplifier has performed amplification, amplify N-1 output signals from the N input networks, excluding the first output signal, based on the amplitude of the output signals from the N input networks, where N is an integer greater than or equal to 3;

[0104] N output networks are connected between the output nodes of the first amplifier and the load connection nodes, and also connected between the output nodes of the N-1 second amplifiers and the load connection nodes; and

[0105] The first bias network supplies a DC bias voltage to at least one of the N output networks.

[0106] The electrical length of the first bias network is less than 90 degrees.

[0107] While several embodiments of the invention have been described, these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments, and their variations, are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. An amplification device, comprising: The first amplifier amplifies the first input signal; The second amplifier amplifies the second input signal; The third amplifier amplifies the third input signal; The first output network is connected to the output node of the first amplifier and the node connected to the load; The second output network is connected to the output node of the second amplifier and the node connected to the load; The third output network is connected to the output node of the third amplifier and the node connected to the load; A first bias network, one end of which is connected between the first amplifier and the first output network, supplies a first DC voltage to the first output network. The electrical length of the first bias network is less than 90 degrees. A second bias network, with one end connected to the node connected to the load, supplies the load a second DC voltage with a different voltage level than that of the first bias network. The electrical lengths of the first output network, the second output network, and the third output network are set to values ​​greater than or less than 90 degrees.

2. The amplification device according to claim 1, wherein, The first output network and the first bias network reduce the third harmonics contained in the first signal, the second signal, and the third signal amplified by the first amplifier, the second amplifier, and the third amplifier. The second bias network reduces the second harmonic of the first signal, the second signal, and the third signal after the third harmonic is reduced.

3. The amplification device according to claim 1 or 2, wherein, The first bias network also supplies the first DC voltage to at least one of the second output network and the third output network. At least two of the first to third output networks, which are supplied with the first DC voltage, reduce the second and third harmonic impedances of the signal amplified by the amplifier connected to the at least two output networks.

4. The amplification device according to any one of claims 1 to 3, wherein, The first to the third output networks can respectively make the second and third higher harmonic impedances variable and controllable.

5. The amplification device according to claim 3, wherein, The electrical length of at least one of the first output networks to the third output network, which is supplied with the first DC voltage, is greater than 90 degrees.

6. The amplification device according to claim 3, wherein, The electrical length of the second output network and the third output network that is not supplied with the first DC voltage is less than 90 degrees.

7. The amplification device according to any one of claims 1 to 6, wherein, The amplification device also includes: Input terminals are used to input signals. A first input network receives the input signal from the input terminal and outputs the first signal to the first amplifier; The second input network receives the input signal from the input terminal and outputs the second signal to the second amplifier; as well as The third input network receives the input signal from the input terminal and outputs the third signal to the third amplifier. The phase offset between the input terminal and the node connected to the load along the path through the first input network and the first amplifier is equal to the phase offset between the input terminal and the node connected to the load along the path through the second input network and the second amplifier, or the phase offset between the input terminal and the node connected to the load along the path through the third input network and the third amplifier.

8. The amplification device according to any one of claims 1 to 7, wherein, Multiple first bias networks are configured, and each of the multiple first bias networks is connected to any one of the output networks from the first output network to the third output network. Each of the plurality of the first bias networks is supplied with a DC bias voltage of the same voltage level at one end.

9. The amplification device according to any one of claims 1 to 8, wherein, One end of the second bias network is set to ground level.

10. The amplification device according to any one of claims 1 to 9, wherein, The electrical lengths and widths of the first output network to the third output network, the first bias network, and the second bias network can be variable and adjusted individually.

11. The amplification device according to any one of claims 1 to 10, wherein, At least two of the electrical lengths of the first output network to the third output network, the first bias network, and the second bias network are different electrical lengths. At least two of the widths of the first output network to the third output network, the first bias network, and the second bias network are different widths.

12. A transmitter, comprising: The baseband processing unit performs signal processing on the baseband signals; A modulator that uses a local oscillation signal to modulate the baseband signal to generate a high-frequency signal; and The high-frequency amplification device amplifies the high-frequency signal and sends it to the antenna. The high-frequency amplification device includes: A first amplifier amplifies the input first signal based on the high-frequency signal; The second amplifier amplifies the input second signal based on the high-frequency signal; A third amplifier amplifies the input third signal based on the high-frequency signal; The first output network is connected to the output node of the first amplifier and the node connected to the load; The second output network is connected to the output node of the second amplifier and the node connected to the load; The third output network is connected to the output node of the third amplifier and the node connected to the load; A first bias network, one end of which is connected between the first amplifier and the first output network, supplies a first DC voltage to the first output network. The electrical length of the first bias network is less than 90 degrees. A second bias network, with one end connected to the node connected to the load, supplies the load a second DC voltage with a different voltage level than that of the first bias network. The electrical lengths of the first output network, the second output network, and the third output network are set to values ​​greater than or less than 90 degrees.

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