Integrated circuit trimming method for trimming code separation

By calculating the initial value and target value of the parameters to be modified, the highest bit is reversed, and the mapping relationship between the code and the parameters is reconstructed, so that it presents a smooth and continuous linear curve, solving the problems of complex and inefficient adjustment logic in the existing technology, and significantly improving the debugging efficiency and chip yield.

CN120034172AActive Publication Date: 2025-05-23ANQING NORMAL UNIV
View PDF 13 Cites 0 Cited by

Patent Information

Application Number
CN202510101913.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-01-22
Publication Date
2025-05-23
Estimated Expiration
2045-01-22

AI Technical Summary

Technical Problem

The existing methods based on digital coding and coding have problems such as complex code search logic and low adjustment efficiency.

Method used

The adjustment code is calculated based on the initial value and target value of the parameter to be modified, and the mapping relationship between the adjustment code and the adjustment parameter is established. The highest bit of the adjustment code is reversed to obtain the application adjustment code, and the mapping relationship between the application adjustment code and the adjustment parameter is reconstructed to present it as a smooth and continuous linear curve.

Benefits of technology

It significantly reduces the logical complexity in the adjustment process, reduces the uncertainty and calculation amount across intervals, avoids the redundant judgment process, and greatly improves the adjustment efficiency, which helps to improve chip yield and reduce production costs.

✦ Generated by Eureka AI based on patent content.

Smart Images

  • Figure CN120034172A_ABST
    Figure CN120034172A_ABST
Patent Text Reader

Abstract

The invention provides an integrated circuit trimming method for trimming code separation, and belongs to the technical field of integrated circuit trimming, and the method comprises the steps: carrying out the calculation of a trimming code based on an initial value and a target value of a to-be-trimmed parameter, building a mapping relation between the trimming code and the trimming parameter, and carrying out the trimming of the to-be-trimmed parameter based on the mapping relation between the trimming code and the trimming parameter. Inverting the highest position of the trimming code to obtain an application trimming code, obtaining a mapping relation between the application trimming code and the trimming parameter, and trimming the integrated circuit chip based on the mapping relation between the application trimming code and the trimming parameter; the problems that in the prior art, a method based on digital trimming codes is complex in code searching logic and low in trimming efficiency are solved.
Need to check novelty before this filing date? Find Prior Art

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit trimming, and in particular to an integrated circuit trimming method oriented to trimming code separation. Background Art

[0002] With the widespread application of integrated circuits (ICs) in various smart devices, the functional complexity and performance requirements have increased, posing higher challenges to chip manufacturing processes and quality assurance. During the chip production process, due to process fluctuations and differences in device parameters, the key parameters of many chips will deviate from the design goals, directly affecting the stability and reliability of product performance. For this reason, trimming technology has become a key means to improve chip yield and performance.

[0003] Existing trimming methods mainly include laser trimming, fuse trimming, Zener diode trimming and trimming based on digital trimming codes. Among them, laser trimming has high precision, but the operation is complicated and expensive; fuse trimming has low cost and simple structure, but its one-time programming characteristics limit the ability of multiple debugging; Zener diode trimming is usually used in specific scenarios, but the design complexity is high and it is difficult to meet general needs. In contrast, the method based on digital trimming codes has gradually become the mainstream due to its flexibility and repeatability. In order to ensure that certain parameters of the chip meet the requirements of the product specification, trimming circuits are added when designing the chip, such as Figure 1 As shown, the trimming circuit adjusts the circuit parameters through circuit components (such as resistors, capacitors, switches, etc.), the multiplexer MUX is used to control the selection of signals, and the trimming process is controlled by switching different signal paths. SRAM is used to store temporary trimming parameters or intermediate state information, which can be read and written multiple times. OTP is used to store fixed trimming codes, and the stored content cannot be changed after writing, so that after the chip is trimmed, the trimming value will not be lost due to power failure or other factors. EEPROM is used to store temporary data, and the trimming signal Trim Signal is input into MUX to trim different parts of the chip. The control signal Control is used to adjust the working state of the memory unit, coordinate various tasks in the trimming process, and ensure that the trimming operation is carried out according to the predetermined process. When a certain trimming code is 1, the switch K1 is closed, and the resistor R1 is short-circuited at this time. When a certain trimming code is 0, the switch K1 is disconnected, thereby determining whether the resistor R1 is connected to the circuit. The access state of the resistor in the trimming circuit is controlled by the digital trimming code, thereby changing the corresponding parameters of the circuit and realizing efficient trimming of the chip.

[0004] Existing calibration technology based on digital trimming codes also faces challenges. The mapping relationship between the trimming codes and chip parameters is usually expressed as a segmented and discontinuous linear relationship, such as Figure 2As shown, taking temperature as the parameter to be trimmed as an example, the abscissa represents the trim code, and the ordinate represents the trimmed value of temperature. In the range of the trim code from 00000000 to 011111111, the trimmed value decreases from 24.0000 to 16.0000, while in the range of the trim code from 10000000 to 11111111, the trimmed value decreases from 32.0000 to 24.0625. The segmented characteristic between the trimmed value and the trim code increases the complexity of the code search logic. Especially when dealing with segmented curves, additional logical judgments are required to cross different segments, which prolongs the time of testing and calibration, resulting in low trimming efficiency. Summary of the Invention

[0005] The technical problem to be solved by the present invention is how to solve the problems of complex code search logic and low trimming efficiency existing in the prior art method based on digital trim codes.

[0006] The present invention solves the above technical problems through the following technical solutions: An adjustable method for an integrated circuit oriented to trim code separation, the method includes: calculating a trim code based on the initial value and the target value of the parameter to be trimmed, and establishing a mapping relationship between the trim code and the trim parameter; based on the mapping relationship between the trim code and the trim parameter, inverting the highest bit of the trim code to obtain an applied trim code, and obtaining a mapping relationship between the applied trim code and the trim parameter; trimming the integrated circuit chip based on the mapping relationship between the applied trim code and the trim parameter.

[0007] Based on the mapping relationship between the trim code and the trim parameter, the present invention inverts the highest bit of the trim code to obtain an applied trim code, reconstructs the mapping relationship between the applied trim code and the trim parameter, and presents the original segmented trim parameter and trim code as a smooth and continuous linear curve relationship, significantly reducing the logical complexity in the trimming process, reducing the uncertainty and calculation amount across intervals, avoiding redundant judgment processes, greatly improving the trimming efficiency, and helping to improve the chip yield and reduce the production cost.

[0008] Preferably, the mapping relationship between the trim code and the trim parameter is a segmented linear relationship, and the relationship between the trim code and the applied trim code is a logical operation relationship.

[0009] Preferably, the mapping relationship between the applied trim code and the trim parameter is a continuous curve.

[0010] Preferably, the method of inverting the highest bit of the trim code to obtain the applied trim code is to add an inverter between the highest bit at the output end of the multiplexer and the switch.

[0011] Preferably, inverters are respectively added between the highest bit at the output end of the multiplexer in the low-bit interval and high-bit interval of the trim code and the switch.

[0012] Preferably, one end of the inverter is connected to the highest bit output end of the first multiplexer, and the other end of the inverter is connected to the object to be adjusted. The adjustment code is respectively input into the first multiplexer and the second multiplexer, and a memory and a register are respectively connected between the output end of the second multiplexer and the input end of the first multiplexer, and the register is connected to the read-only memory.

[0013] Preferably, the method of obtaining the application adjustment code from the highest position of the adjustment code is implemented in a programming manner, and the logic value of the highest bit of the low-order interval adjustment code is set to 1, and the logic value of the highest bit of the high-order interval adjustment code is set to 0.

[0014] Preferably, the process of trimming the integrated circuit chip based on the mapping relationship between the application trimming code and the trimming parameters includes: finding the corresponding application trimming code in the mapping relationship between the application trimming code and the trimming parameters according to the parameters to be trimmed, trimming the chip with the application trimming code, and measuring the performance parameters after trimming, adjusting the application trimming code according to the deviation between the performance parameters and the target values, obtaining the optimal application trimming code after multiple iterations of code finding, and trimming the chip with the optimal application trimming code.

[0015] Preferably, the parameter to be adjusted is temperature or current or reference voltage or frequency.

[0016] Preferably, when the parameter to be adjusted is temperature, the corresponding relationship between the adjustment code, the application adjustment code, and the adjustment parameter is: in the interval of the adjustment code from 00000000 to 011111111, the adjustment parameter decreases from 24.0000 to 16.0000, and the interval of the application adjustment code corresponding to this interval is from 10000000 to 11111111; in the interval of the adjustment code from 10000000 to 11111111, the adjustment parameter decreases from 32.0000 to 24.0625, and the interval of the application adjustment code corresponding to this interval is from 00000000 to 011111111.

[0017] The advantages provided by the present invention are:

[0018] (1) Based on the mapping relationship between the trimming code and the trimming parameter, the present invention obtains the application trimming code by reversing the highest position of the trimming code, reconstructs the mapping relationship between the application trimming code and the trimming parameter, and presents the originally segmented trimming parameter and the trimming code as a smooth and continuous linear curve relationship, so that the logical complexity in the trimming process is significantly reduced, the uncertainty and calculation amount across intervals are reduced, and redundant judgment processes are avoided. The trimming efficiency is greatly improved, which helps to improve chip yield and reduce production costs.

[0019] (2) The present invention can be implemented by hardware or software by inverting the highest position of the adjustment code to obtain the application adjustment code. When the hardware is implemented, only an inverter needs to be added. The hardware circuit is more stable and more resistant to interference. It can speed up the data processing speed in the adjustment process, provide higher parallel processing capabilities, reduce data reading and calculation time, and thus accelerate the adjustment process. Hardware optimization can also reduce the impact of software errors or external interference in the system on the adjustment process; when implemented in software, it has high flexibility and can adapt to different application scenarios. It can be further optimized by updating the software in the future. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of a trimming circuit in the prior art;

[0021] Figure 2 A schematic diagram of segmented characteristics between a trimming parameter and a trimming code in an existing method based on a digital trimming code;

[0022] Figure 3 A schematic diagram of a mapping relationship between a trimming parameter and an application trimming code in a trimmable integrated circuit method for trimming code separation provided by an embodiment of the present invention;

[0023] Figure 4 A circuit diagram for inverting the highest position of a trimming code in a trimmable method for an integrated circuit for trimming code separation provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution of the present invention is clearly and completely described below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] The present embodiment provides an integrated circuit trimmable method for trimming code separation, comprising: calculating a trimming code based on an initial value and a target value of a parameter to be trimmed, and establishing a mapping relationship between the trimming code and the trimming parameter; based on the mapping relationship between the trimming code and the trimming parameter, reversing the highest position of the trimming code to obtain an application trimming code, obtaining a mapping relationship between the application trimming code and the trimming parameter, and trimming the integrated circuit chip based on the mapping relationship between the application trimming code and the trimming parameter.

[0026] The mapping relationship between the adjustment code and the adjustment parameter is a piecewise linear relationship, the mapping relationship between the adjustment code and the application adjustment code is a logical operation relationship, and the mapping relationship between the application adjustment code and the adjustment parameter is a continuous curve.

[0027] The parameter to be adjusted is temperature or current or reference voltage or frequency. A large amount of data shows that there is a good linear relationship between the adjustment parameter and the adjustment code based on the same step size. Among the many adjustment parameters, temperature affects chip performance and reliability, and its change will affect the threshold voltage, mobility, and device parameters such as resistance and capacitance of the transistor, thereby causing changes in circuit gain, linearity and noise performance. Here, the present invention takes the parameter to be adjusted as temperature and introduces the method of the present invention in detail:

[0028] Based on the specific relationship between the trimming parameters and the trimming codes, Table 1 gives the segmented characteristics between the trimming parameters (temperature) and the trimming codes: in the trimming code range from 00000000 to 011111111, the trimming value decreases from 24.0000 to 16.0000, and in the trimming code range from 10000000 to 11111111, the trimming value decreases from 32.0000 to 24.0625.

[0029] Table 1 Relationship between trimming parameters (temperature) and trimming codes

[0030] Modify code Adjustment parameters 00000000 24.0000 00000001 23.9375 00000010 23.8750 ... ... 01111111 16.0000 10000000 32.0000 10000001 31.9375 10000010 31.8750 ... ... 11111111 24.0625

[0031] See also Figure 1 In order to find the optimal adjustment code, it is necessary to perform iterative code search. In the segmented curve, each adjustment may need to be adjusted between multiple segments. Different adjustment codes may need to be tried multiple times. Each attempt requires testing a new intermediate adjustment code to check whether it is close to the target value until the optimal adjustment code is found. The process of continuous adjustment between multiple segments will increase the number of unnecessary adjustments. In addition, when the value of the adjustment code transitions from one interval to another, it will bring uncertainty across intervals, that is, the adjustment results (such as temperature, power, etc.) may suddenly change or be inconsistent. This situation requires additional judgment and calculation to ensure the correctness of the adjustment process, which will greatly increase the complexity of the adjustment and reduce the adjustment efficiency.

[0032] In order to solve the above problems, the present invention is based on the mapping relationship between the trimming code and the trimming parameter, and the highest position of the trimming code is reversed to obtain the application trimming code, and the mapping relationship between the application trimming code and the trimming parameter is obtained, and the original segmented trimming parameter and the trimming code are presented as a smooth and continuous linear curve relationship, so that the logic complexity in the trimming process is significantly reduced, and the trimming efficiency is greatly improved, which is helpful to improve the chip yield and reduce the production cost. The parameter to be trimmed is temperature or current or reference voltage or frequency.

[0033] The method of inverting the highest position of the adjustment code to obtain the applied adjustment code can be implemented by hardware or software. When implemented by hardware, an inverter is added between the highest position of the output end of the multiplexer and the switch, specifically, an inverter is added between the highest position of the output end of the multiplexer in the low-order interval and the high-order interval of the adjustment code and the switch. When implemented by software, the logic value of the highest position of the adjustment code in the low-order interval is set to 1 through software programming, and the logic value of the highest position of the adjustment code in the high-order interval is set to 0.

[0034] Taking the parameter to be adjusted as temperature as an example, the above two implementation methods are introduced:

[0035] Hardware implementation: Figure 4 As shown, in Figure 1 An inverter is introduced into the adjustment circuit shown, one end of the inverter is connected to the highest bit output end of the first multiplexer, the other end of the inverter is connected to the object to be adjusted, the adjustment code is input into the first multiplexer and the second multiplexer respectively, the output end of the second multiplexer and the input end of the first multiplexer are respectively connected to a memory and a register, and the register is connected to a read-only memory. The inverter is introduced to realize the logical inversion of the highest bit of the calculated adjustment code. In the low-order interval of 00000000 to 01111111, the inverter is used to flip the highest bit; in the high-order interval of 10000000 to 11111111, the inverter is used to flip the highest bit. Hardware optimization can significantly speed up the data processing speed in the adjustment process, provide higher parallel processing capabilities, reduce data reading and calculation time, and thus accelerate the adjustment process. Hardware optimization can also reduce the impact of software errors or external interference in the system on the adjustment process. For example, hardware circuits are usually more stable and more resistant to interference than software implementations, so they can ensure accuracy and consistency in the adjustment process.

[0036] Software implementation:

[0037] Based on software programming, it does not rely on hardware modification, but through software dynamic control to calculate the highest bit of the adjustment code, so that the adjustment curve can be smoothly transitioned logically. The specific implementation is as follows:

[0038] In the low range of the trimming parameter (temperature) (the calculated trimming code is 00000000 to 01111111), the logic value of the highest bit is set to 1 through programming; when the calculated trimming code enters the high range (10000000 to 11111111), the logic value of the highest bit is set to 0 through programming, so that the trimming parameter change in this range is connected to the curve of the low range to form a continuous curve. The program can directly invert the highest bit of the input trimming code through the exclusive OR operation (XOR):

[0039] trim_code^=(1<<7);

[0040] #include<stdint.h> #include<stdio.h>

[0041] / / Function: Toggle the highest bit (bit 8) of the trim code uint8_t toggle_highest_bit(uint8_ttrim_code) {

[0042] / / Invert the highest bit (bit 8) and use XOR operation to implement trim_code^=(1<<7);

[0043] return trim_code;

[0044] }

[0045] int main()

[0046] {

[0047] uint8_t trim_code = 0b00000000; / / Assume the input trim code

[0048] uint8_t modified_trim_code; modified_trim_code=toggle_highest_bit(trim_code);

[0049] / / Print results

[0050] printf("Original Trim Code: %02X\n",trim_code); / / Original trim code

[0051] printf("Modified Trim Code: %02X\n", modified_trim_code); / / inverted trim code return 0;

[0052] }

[0053] The continuity of adjustment parameters (temperature) can be achieved by controlling registers through software, thus avoiding the design complexity caused by hardware changes. It has high flexibility and can adapt to different application scenarios. It can be further optimized by updating the software in the future.

[0054] By reversing the highest position of the adjustment code, the corresponding relationship between the adjustment code, the application adjustment code, and the adjustment parameter is shown in Table 2. By reconstructing the mapping relationship, the original segmented curve can be merged into a continuous curve. After reversing, the two discontinuous and decreasing curves of the adjustment parameter (temperature) and the adjustment code can be merged into a continuous and smooth decreasing curve, as shown in Table 2. Figure 3This reconstruction of the logic path can reduce the uncertainty and calculation amount across intervals, avoid redundant judgment processes, and ultimately achieve the effect of reducing the number and time of adjustments and improving the efficiency of adjustments.

[0055] Table 2 Correspondence between adjustment code, application adjustment code and adjustment parameters

[0056] Modify code Application tuning code Adjustment parameters 00000000 10000000 24.0000 00000001 10000001 23.9375 00000010 10000010 23.8750 ... ... ... 01111111 11111111 16.0000 10000000 00000000 32.0000 10000001 00000001 31.9375 10000010 00000010 31.8750 ... ... ... 11111111 01111111 24.0625

[0057] According to the parameter to be adjusted, the corresponding application adjustment code is found in the mapping relationship between the application adjustment code and the adjustment parameter, the chip is adjusted with the application adjustment code, and the performance parameters after adjustment are measured. The application adjustment code is adjusted according to the deviation between the performance parameter and the target value, and the optimal application adjustment code is obtained after multiple iterations of code finding, and the chip is adjusted with the optimal application adjustment code. The present invention uses two algorithms (curve fitting and interpolation optimization algorithm) to conduct experiments, and the experimental results are shown in Tables 3 and 4. Wherein Target is the target value of the chip to be tested, Initial is the initial value of the parameter to be adjusted of the chip to be tested, T1 in Table 3 is the code search time before the optimization of the mapping relationship using the curve fitting algorithm, and T2 is the code search time after the optimization of the mapping relationship using the curve fitting algorithm, and T1 in Table 4 is the code search time before the optimization of the mapping relationship using the interpolation optimization algorithm, and T2 is the code search time after the optimization of the mapping relationship using the interpolation optimization algorithm, and Red (%) is the percentage reduction of the time after optimization compared to the time before optimization. Under the two algorithms, the adjustment time was reduced by 44.97% and 40.00% on average, respectively, which fully verified the efficiency and feasibility of the method of the present invention.

[0058] Table 3 Comparison of time before and after curve optimization under curve fitting algorithm

[0059]

[0060]

[0061] Table 4 Comparison of time before and after curve optimization under interpolation optimization algorithm

[0062] Target Initial T1(us) T2(us) Red(%) 23.852 27.063 7.000 2.600 64.29 24.055 28.188 5.300 2.200 48.84 24.156 27.250 3.500 2.100 47.22 24.227 27.063 3.700 2.100 52.38 24.266 27.813 2.700 2.000 27.59 24.234 27.125 9.300 6.400 48.39 24.312 28.375 6.200 2.800 55.56 24.484 26.938 10.300 6.500 42.39 24.156 27.250 7.100 3.600 40.21 24.844 27.813 10.000 6.200 38.00

[0063] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for adjusting integrated circuits for adjusting code separation, characterized in that: Methods include: Based on the initial value and target value of the parameter to be adjusted, the adjustment code is calculated, and a mapping relationship between the adjustment code and the adjustment parameter is established. Based on the mapping relationship between the adjustment code and the adjustment parameter, the highest position of the adjustment code is inverted to obtain the application adjustment code, and the mapping relationship between the application adjustment code and the adjustment parameter is obtained. Based on the mapping relationship between the application adjustment code and the adjustment parameter, the integrated circuit chip is adjusted.

2. The integrated circuit tunable method for trim code separation according to claim 1, characterized in that: The mapping relationship between the adjustment code and the adjustment parameter is a piecewise linear relationship, and the mapping relationship between the adjustment code and the application adjustment code is a logical operation relationship.

3. The integrated circuit tunable method for trim code separation according to claim 1, characterized in that: The mapping relationship between the application adjustment code and the adjustment parameter is a continuous curve.

4. The integrated circuit tunable method for trim code separation according to claim 1, characterized in that: The method of inverting the highest position of the adjustment code to obtain the applied adjustment code is to add an inverter between the highest position of the output end of the multiplexer and the switch.

5. The integrated circuit tunable method for trim code separation according to claim 4, characterized in that: Inverters are respectively added between the highest bit of the multiplexer output end and the switch in the low-order interval and the high-order interval of the trimming code.

6. The integrated circuit tunable method for trim code separation according to claim 5, characterized in that: One end of the inverter is connected to the highest bit output end of the first multiplexer, and the other end of the inverter is connected to the object to be adjusted. The adjustment code is respectively input into the first multiplexer and the second multiplexer. A memory and a register are respectively connected between the output end of the second multiplexer and the input end of the first multiplexer, and the register is connected to the read-only memory.

7. The integrated circuit tunable method for trim code separation according to claim 1, characterized in that: The method of obtaining the application adjustment code from the highest position of the adjustment code is implemented in a programming manner, and the logic value of the highest bit of the low-order interval adjustment code is set to 1, and the logic value of the highest bit of the high-order interval adjustment code is set to 0.

8. The integrated circuit tunable method for trim code separation according to claim 1, characterized in that: The process of trimming the integrated circuit chip based on the mapping relationship between the application trimming code and the trimming parameter includes: finding the corresponding application trimming code in the mapping relationship between the application trimming code and the trimming parameter according to the parameter to be trimmed, trimming the chip with the application trimming code, measuring the performance parameters after trimming, adjusting the application trimming code according to the deviation between the performance parameters and the target value, obtaining the optimal application trimming code after multiple iterations of code finding, and trimming the chip with the optimal application trimming code.

9. The integrated circuit tunable method for trim code separation according to claim 1, characterized in that: The parameter to be adjusted is temperature or current or reference voltage or frequency.

10. The integrated circuit tunable method for trim code separation according to claim 1 or 9, characterized in that: When the parameter to be adjusted is temperature, the corresponding relationship between the adjustment code, the application adjustment code, and the adjustment parameter is: in the interval of the adjustment code from 00000000 to 011111111, the adjustment parameter decreases from 24.0000 to 16.0000, and the interval of the application adjustment code corresponding to this interval is from 10000000 to 11111111; in the interval of the adjustment code from 10000000 to 11111111, the adjustment parameter decreases from 32.0000 to 24.0625, and the interval of the application adjustment code corresponding to this interval is from 00000000 to 011111111.

Citation Information

Patent Citations

  • Voltage trimming circuit, memory device and test method of memory device

    CN115019868A

  • Chip parameter trimming method and device

    CN115394672A

  • High-precision voltage trimming circuit and current trimming circuit

    CN115729294A

  • Low-dropout linear voltage stabilizing circuit, trimming control method, chip and electronic equipment

    CN116520930A

  • Method for testing reliability of flash memory

    CN117409850A