Protection circuit for latch of satellite-borne self-closed loop device

Abstract

The invention discloses a protection circuit for a latch of a satellite-borne self-closed loop device. The protection circuit comprises a voltage stabilization module, a power resistor, an amplification comparison module, a D trigger module and an FPGA. The first end of the power resistor is jointly connected with the first end of the voltage stabilizing module and the first end of the amplification comparison module; an external power supply is jointly connected with a second end of the power resistor and a second end of the amplification comparison circuit, a first end of the D trigger module is connected with a fourth end of the amplification comparison circuit, and a second end of the D trigger module is connected with a fifth end of the amplification comparison circuit; through the feedback self-control mode of each module, the self-closed loop of the on-orbit latch protection action of a protected device is effectively ensured, and the power supply of a single machine or a system does not need to be restarted. And the single event latch (SEL) protection capability is improved. The technical problem that in the prior art, a device with insufficient single-particle latch (SEL) protection capacity cannot be applied to aerospace application is solved.

Description

Technical Field

[0001] The invention belongs to the field of digital-analog hybrid circuits and relates to a protection circuit, in particular to a protection circuit for latching a satellite-borne self-closed-loop device. Background Art

[0002] In recent years, a large number of digital-analog hybrid circuits and RF devices based on silicon-based processes have been used in various satellite payload systems, such as various direct digital frequency synthesizers (DDS), digital-to-analog converters (ADC), broadband signal generators, etc. Due to process factors, these devices have different degrees of single-particle latch-up risks in space. Since the consequence of device latch-up is often a sharp increase in the working current, causing the device to burn out in a short period of time, circuit protection for devices with single-particle latch-up (SEL) risks is a prerequisite for the aerospace application of such devices. At present, the latch-up protection design of such devices generally uses chip-level design process protection to avoid the possibility of latch-up from the source. However, for some devices that do not have latch-up protection design or whose latch-up protection design capabilities do not meet aerospace requirements, they can only be protected by latch-up protection circuits before they can be used in aerospace.

[0003] Therefore, there is an urgent need for a protection circuit for locking a satellite-borne self-closed-loop device, which has the advantages of simple circuit, wide application range, and on-orbit self-closed-loop control. Summary of the invention

[0004] In view of the deficiencies in the prior art, an object of the present invention is to provide a protection circuit for latch-up of a satellite-borne self-closed-loop device, so as to solve the technical problem that devices in the prior art with insufficient single-event latch-up (SEL) protection capability cannot be used in aerospace applications.

[0005] In order to solve the above technical problems, the present invention adopts the following technical solutions to achieve the above problems:

[0006] A protection circuit for latching of a satellite-borne self-closed-loop device, comprising a voltage stabilizing module, a power resistor, an amplifying and comparing module, a D trigger module and an FPGA;

[0007] The first end of the power resistor is commonly connected to the first end of the voltage stabilizing module and the first end of the amplifying and comparing module; the external power supply is commonly connected to the second end of the power resistor and the second end of the amplifying and comparing module; the first end of the D trigger module is connected to the fourth end of the amplifying and comparing circuit, and the second end of the D trigger module is connected to the fifth end of the amplifying and comparing circuit; the third end of the D trigger module is commonly connected to the first end of the FPGA and the third end of the voltage stabilizing module; the fourth end of the D trigger module is connected to the second end of the FPGA;

[0008] The power resistor is used to connect to an external power supply, and the potential difference between the two ends is used to characterize the working current of the protected device;

[0009] The voltage stabilizing module is used to stabilize the DC power supply voltage transmitted by the external power supply through the power resistor and to control the opening and closing of the protected device by controlling the level control enabling terminal;

[0010] The amplification and comparison module is used to amplify the potential difference generated at both ends of the power resistor and compare the amplified voltage Vin with the set comparison voltage Vref. When Vin<Vref, the output voltage Vout is a high level; when Vin>Vref, the output level Vout is a low level.

[0011] The D flip-flop module is used to use the output voltage of the amplification comparison module as the input control signal of the reset end, which is divided into two paths, one path is used as the control signal of the voltage stabilization module, and the other path is output to the FPGA as level monitoring; and the negative pulse given by the FPGA is used as the set end as the control signal to restart the circuit;

[0012] The FPGA is used to complete the self-closing function of the protection circuit for latching the on-board self-closing device. One I / 0 port is configured as an input level monitoring pin to monitor the reset end level of the D flip-flop module; another I / 0 port is configured as a reset action pin. When it is monitored that the reset end of the D flip-flop module is converted from a high level to a low level, after a time delay, the reset action pin sends a negative pulse to the set end of the D flip-flop module to restart the protected device.

[0013] The present invention also includes the following technical features:

[0014] The voltage stabilizing module includes a voltage stabilizer N2, a resistor R51, a resistor R52, a resistor R53, a capacitor C51, a capacitor C52, a capacitor C53 and a capacitor C54. The pin 2 of the voltage stabilizer N2 is connected to one end of the resistor R53 and one end of the capacitor C54. The second end of the resistor R53 is connected to the third end of the D trigger module and the FPGA as the third end of the voltage stabilizing module. The second end of the capacitor C54 is grounded. The pin 3 and the pin 4 of the voltage stabilizer N2 are connected to one end of the capacitor C51, the first end of the power resistor and the amplification comparison circuit as the first end of the voltage stabilizing module. The first end of the capacitor C51 is connected together, the second end of the capacitor C51 is grounded, the second end of the power resistor is connected to the external power supply and the second end of the amplification and comparison circuit; the pin 9 of the regulator N2 is connected together with one end of the resistor R51 and one end of the resistor R52, the second end of the resistor R51 is grounded, the second end of the resistor R52 is connected together with the positive electrode of the capacitor C52, the protected device and the pin 6 and pin 7 of the regulator N2, the negative electrode of the capacitor C52 is connected to the positive electrode of the capacitor C53, and the negative electrode of the capacitor C53 is grounded; the pins 1, 5, 8 and 10 of the regulator N2 are suspended.

[0015] The amplification and comparison circuit includes an operational amplifier N3, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61 and a resistor R24, wherein the pin 5 of the operational amplifier N3 is commonly connected to one end of the resistor R57 and one end of the resistor R56, the second end of the resistor R57 is grounded, and the second end of the resistor R56 is commonly connected to the second end of the power resistor and the voltage stabilizing module as the second end of the amplification and comparison circuit; the pin 6 of the operational amplifier N3 is commonly connected to one end of the resistor R55 and one end of the resistor R58, and the second end of the resistor R55 is commonly connected to the first end of the power resistor and the voltage stabilizing module as the first end of the amplification and comparison circuit The first end of the D flip-flop module is connected together, the second end of the resistor R58 is connected together with the pin 7 of the operational amplifier N3 and one end of the resistor R59, and the second end of the resistor R59 is connected to the pin 2 of the operational amplifier N3; the pin 8 of the operational amplifier N3 is connected to one end of the resistor R24 ​​as the fourth end of the amplification and comparison circuit, and the second end of the resistor R24 ​​is connected together with one end of the resistor R61 and the first end of the D flip-flop module; the second end of the resistor R61 is connected together with one end of the resistor R60 and the pin 3 of the operational amplifier N3, and the pin 4 of the operational amplifier N3 is grounded; the pin 1 of the operational amplifier N3 is connected to the second end of the D flip-flop module as the fifth end of the amplification and comparison circuit.

[0016] The D trigger module includes a D trigger N4, a resistor R62, a resistor R63, a resistor R64 and a resistor R23, wherein a pin 1 of the D trigger N4 is connected to one end of the resistor R62, a second end of the resistor R62 is connected to the fifth end of the amplification comparison circuit as the second end of the D trigger module, a pin 14 of the D trigger N4 is connected to one end of the resistor R23, and a second end of the resistor R23 is connected to the fourth end of the amplification comparison circuit as the first end of the D trigger module; a pin 2 of the D trigger N4 is connected to one end of the resistor R63, a second end of the resistor R63 is connected to one end of the resistor R64 and is grounded, and a second end of the resistor R64 is connected to a pin 3 of the D trigger N4; a pin 5 of the D trigger N4 is connected to the first end of the FPGA and the third end of the voltage regulator module as the third end of the D trigger module, and a pin 4 of the D trigger N4 is connected to the second end of the FPGA as the fourth end of the D trigger module; and the remaining pins of the D trigger N4 are suspended.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects:

[0018] (I) The present invention effectively ensures the self-closed loop of the on-orbit latch protection action of the protected device through the feedback self-control of each module, without restarting the power supply of the single machine or system. The single-particle latch (SEL) protection capability is improved. The technical problem that the devices with insufficient single-particle latch (SEL) protection capability in the prior art cannot be used in aerospace applications is solved.

[0019] (II) The present invention can monitor the working current of the protected device as the judgment basis of the latching protection circuit, and can adapt to the normal working current of different protected devices by adjusting the parameter configuration of each sub-circuit (such as the value of the power resistor, the amplification factor of the differential amplifier, and the voltage value of the comparison voltage of the voltage comparator). Therefore, the circuit can theoretically meet the needs of all devices that require latching protection.

[0020] (III) The core components of the present invention are all commonly used components with high circuit reliability. Meanwhile, the circuit form is simple, the circuit size is small, and the circuit power consumption is extremely small. Meanwhile, the above components are all bipolar processes and have radiation resistance. The FPGA can use the FPGA used for control of the system or a single machine to separate two I / O pin resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is an overall block diagram of the present invention;

[0022] Figure 2 It is a schematic diagram of a specific circuit structure of the present invention.

[0023] The specific contents of the present invention are further explained in detail below in conjunction with embodiments. DETAILED DESCRIPTION

[0024] It should be noted that, unless otherwise specified, all components in the present invention are components known in the art.

[0025] Specific embodiments of the present invention are given below. It should be noted that the present invention is not limited to the following specific embodiments, and all equivalent changes made on the basis of the technical solution of this application fall within the protection scope of the present invention.

[0026] The present invention provides a protection circuit for locking a satellite-borne self-closed loop device, comprising a voltage stabilizing module, a power resistor, an amplifying and comparing module, a D trigger module and an FPGA;

[0027] The first end of the power resistor is commonly connected to the first end of the voltage stabilizing module and the first end of the amplifying and comparing module; the external power supply is commonly connected to the second end of the power resistor and the second end of the amplifying and comparing module; the first end of the D trigger module is connected to the fourth end of the amplifying and comparing circuit, and the second end of the D trigger module is connected to the fifth end of the amplifying and comparing circuit; the third end of the D trigger module is commonly connected to the first end of the FPGA and the third end of the voltage stabilizing module; the fourth end of the D trigger module is connected to the second end of the FPGA;

[0028] The power resistor is used to connect an external power supply, and the potential difference between the two ends is used to characterize the working current of the protected device;

[0029] The voltage stabilizing module is used to stabilize the DC power supply voltage transmitted by the external power supply through the power resistor and to control the opening and closing of the protected device by controlling the level control enable terminal;

[0030] The amplification and comparison module is used to amplify the potential difference generated at both ends of the power resistor and compare the amplified voltage Vin with the set comparison voltage Vref. When Vin<Vref, the output voltage Vout is a high level; when Vin>Vref, the output level Vout is a low level.

[0031] The D flip-flop module is used to use the output voltage of the amplification comparison module as the input control signal of the reset terminal, which is divided into two paths, one path is used as the control signal of the voltage regulator module, and the other path is output to the FPGA as a level monitoring; and the negative pulse given by the FPGA is used as the set terminal as a control signal to restart the circuit;

[0032] FPGA is used to complete the self-closing function of the protection circuit for latching the onboard self-closing device. One I / 0 port is configured as the input level monitoring pin to monitor the reset end level of the D flip-flop module. Another I / 0 port is configured as the reset action pin. When it is detected that the reset end of the D flip-flop module is converted from a high level to a low level, after a time delay, the reset action pin sends a negative pulse to the set end of the D flip-flop module to restart the protected device.

[0033] In the above technical solution, after the power supply voltage passes through the power resistor, a potential difference is generated at both ends of the power resistor (the potential difference represents the working current of the protected device). The potential difference is amplified by the amplification and comparison module and then compared with the comparison voltage in the amplification and comparison module. The output level of the amplification and comparison module is used as an input control signal to the reset end (set to 0 input end) of the D flip-flop module. Under normal circumstances, the output of the amplification and comparison module is a high level, and the output end Q of the D flip-flop module is a high level. In this way, the voltage regulator module is in a normally open state, and the output voltage is supplied to the protected device. If the protected device is in When single-particle lock occurs in the space environment, its working current will increase sharply. At this time, the current flowing through the power resistor will also increase sharply, and the potential difference between the two ends of the power resistor will also increase sharply. After the potential difference is amplified by the amplification comparison module, it is compared with the comparison voltage set by the amplification comparison module. When the working current of the protected device increases to a certain extent, the output of the amplification comparison module will be converted to a low level, the reset end of the D flip-flop module will be low, and its output pin Q will be cleared to a low level, thereby turning off the enable end of the voltage regulator module, and the output voltage of the voltage regulator module will become 0V, thereby turning off the power supply of the protected device. Since the output pin Q of the D flip-flop module is also connected to a level monitoring pin of the FPGA, when the FPGA detects that the level of the pin is converted from a high level to a low level, after a certain delay, the FPGA sends a negative pulse control signal to the set end (set 1 input end) of the D flip-flop module through another pin, controlling the output Q of the D flip-flop module to flip and output a high level, thereby turning on the voltage regulator module to output a normal voltage.

[0034] Through the feedback and self-control of each module, the protected device is effectively guaranteed to have a self-closed loop in the on-orbit latch protection action, without the need to restart the power supply of the single machine or system. The single event latch (SEL) protection capability is improved. The technical problem that devices with insufficient single event latch (SEL) protection capability in the prior art cannot be used in aerospace applications is solved.

[0035] In addition, by monitoring the working current of the protected device as the judgment basis of the latching protection circuit, the normal working current of different protected devices can be adapted by adjusting the parameter configuration of each sub-circuit (such as the value of the power resistor, the amplification factor of the differential amplifier, and the voltage value of the comparison voltage of the voltage comparator). Therefore, this circuit can theoretically meet the needs of all devices that require latching protection.

[0036] Power resistors generally have smaller values ​​but can withstand higher power.

[0037] See also Figure 2 , wherein the magnetic bead Z2, capacitor C55, capacitor C56, capacitor C57 and capacitor C58 are peripheral circuits of the protected device, wherein pin 1 of the magnetic bead Z2 is connected to the voltage stabilizing module.

[0038] The voltage stabilizing module includes a voltage stabilizer N2, a resistor R51, a resistor R52, a resistor R53, a capacitor C51, a capacitor C52, a capacitor C53 and a capacitor C54. The pin 2 of the voltage stabilizer N2 is connected to one end of the resistor R53 and one end of the capacitor C54. The second end of the resistor R53 is connected as the third end of the voltage stabilizing module to the third end of the D trigger module and the FPGA. The second end of the capacitor C54 is grounded. The pin 3 and the pin 4 of the voltage stabilizer N2 are connected as the first end of the voltage stabilizing module to one end of the capacitor C51, the first end of the power resistor and the amplification ratio The first end of the comparison circuit is connected together, the second end of the capacitor C51 is grounded, and the second end of the power resistor is connected to the external power supply and the second end of the amplification comparison circuit; the pin 9 of the regulator N2 is connected together with one end of the resistor R51 and one end of the resistor R52, the second end of the resistor R51 is grounded, the second end of the resistor R52 is connected together with the positive electrode of the capacitor C52, the protected device and the pin 6 and pin 7 of the regulator N2, the negative electrode of the capacitor C52 is connected to the positive electrode of the capacitor C53, and the negative electrode of the capacitor C53 is grounded; the pins 1, 5, 8 and 10 of the regulator N2 are suspended.

[0039] In the above technical solution, resistors R51 and R52 are used to adjust the output voltage; capacitor C51 is used to filter the input voltage; capacitor C54 is used to filter the enable voltage; capacitor C52 is used to filter the output voltage; and resistor R53 only serves as a connection.

[0040] Preferably, the model of the voltage regulator N2 is MSK5101; the values ​​of the resistor R51, the resistor R52, the resistor R53, the capacitor C51, the capacitor C52, the capacitor C53 and the capacitor C54 are 120Ω, 51Ω, 51Ω, 0.1uF, 10uF, 10uF and 300pF respectively;

[0041] The amplification comparison circuit includes an operational amplifier N3, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61 and a resistor R24, wherein a pin 5 of the operational amplifier N3 is connected to one end of the resistor R57 and one end of the resistor R56, the second end of the resistor R57 is grounded, and the second end of the resistor R56 is connected to the second end of the power resistor and the voltage stabilizing module as the second end of the amplification comparison circuit; a pin 6 of the operational amplifier N3 is connected to one end of the resistor R55 and one end of the resistor R58, and the second end of the resistor R55 is connected to the first end of the power resistor and the voltage stabilizing module as the first end of the amplification comparison circuit. The first ends are connected together, the second end of resistor R58 is connected together with pin 7 of operational amplifier N3 and one end of resistor R59, and the second end of resistor R59 is connected to pin 2 of operational amplifier N3; pin 8 of operational amplifier N3 is connected to one end of resistor R24 ​​as the fourth end of the amplification and comparison circuit, and the second end of resistor R24 ​​is connected together with one end of resistor R61 and the first end of the D trigger module; the second end of resistor R61 is connected together with one end of resistor R60 and pin 3 of operational amplifier N3, and pin 4 of operational amplifier N3 is grounded; pin 1 of operational amplifier N3 is connected to the second end of the D trigger module as the fifth end of the amplification and comparison circuit.

[0042] In the above technical solution, resistors R56, R57, R55 and R58 are used to adjust the amplification factor; resistors R60 and R61 are used to adjust the comparison voltage; and resistors R59 and R24 only play a connecting role.

[0043] Preferably, the model of the operational amplifier is LM158; the values ​​of resistors R55, R56, R57, R58, R59, R60, R61 and R24 are 2KΩ, 2KΩ, 8.2KΩ, 8.2KΩ, 2KΩ, 2KΩ, 4.7ΩK and 1KΩ respectively.

[0044] The D trigger module includes a D trigger N4, a resistor R62, a resistor R63, a resistor R64 and a resistor R23, wherein a pin 1 of the D trigger N4 is connected to one end of the resistor R62, a second end of the resistor R62 is connected to the fifth end of the amplifying and comparing circuit as the second end of the D trigger module, a pin 14 of the D trigger N4 is connected to one end of the resistor R23, a second end of the resistor R23 is connected to the fourth end of the amplifying and comparing circuit as the first end of the D trigger module; a pin 2 of the D trigger N4 is connected to one end of the resistor R63, a second end of the resistor R63 is connected to one end of the resistor R64 and is grounded, and a second end of the resistor R64 is connected to a pin 3 of the D trigger N4; a pin 5 of the D trigger N4 is connected to the first end of the FPGA and the third end of the voltage regulator module as the third end of the D trigger module, a pin 4 of the D trigger N4 is connected to the second end of the FPGA as the fourth end of the D trigger module; and the remaining pins of the D trigger N4 are left floating.

[0045] In the above technical solution, the resistor R23 is used for current limiting; the resistor R63 and the resistor R54 are used as pull-down resistors.

[0046] Preferably, the D flip-flop N4 uses B54AC74, and the values ​​of the resistors R62, R63, R64 and R23 are 51K, 10K, 10K and 1K respectively.

[0047] Example:

[0048] This embodiment provides a protection circuit for latch-up of a satellite-borne self-closed-loop device. The device protected by the circuit is an AD9910 direct digital frequency synthesizer produced by ADI. Since the device is developed using a silicon-based CMOS process and is not designed with radiation resistance and latch-up protection, a special latch-up protection design is required for its aerospace application.

[0049] like Figure 2 As shown, the voltage regulator N2 uses MSK5101, the operational amplifier N3 uses the operational amplifier LM158, the D flip-flop N4 uses B54AC74, and the FPGA uses the FPGA in the external system controller;

[0050] The normal operating current of the 1.8V power supply of the protected device AD9910 is about 200mA. The secondary power supply voltage provided by the external power supply is +6V. The voltage regulator MSK5101 stabilizes the voltage to 1.8V. The power resistor value is selected as 1Ω. Therefore, under normal circumstances, the potential difference across the power resistor is 0.2V. The amplification factor of the operational amplifier N3 is 4.1 times. The output voltage after amplification by the operational amplifier N3 is 0.82V. The comparison voltage of the operational amplifier N3 is set to 1.5V.

[0051] When the protected device AD9910 works normally, the output voltage of the operational amplifier N3 (the operational amplifier N3 is a dual-gate operational amplifier, which is a combination of a differential amplifier and a voltage comparator. The output voltage here is the input voltage of the voltage comparator) is 0.82V, which is less than the comparison voltage 1.5V. Therefore, the output of the operational amplifier N3 is high, and the reset terminal (set to 0 input terminal, pin 1) of the subsequent D-type flip-flop N4 is also high. At this time, the D-type flip-flop N4 outputs a high level to the enable terminal of the voltage regulator. In this state, the protected device AD9910 works normally.

[0052] When the protected device AD9910 is latched, its current will increase geometrically, and then the device will be burned out due to the thermal effect. Therefore, it is necessary to initiate the latch protection action at the initial stage of latching, that is, when the current of the protected device AD9910 increases to about 360 mA. The output voltage of the operational amplifier N3 is higher than the comparison voltage by 1.5 V. At this time, the output of the operational amplifier N3 is at a low level. After the reset terminal (reset input terminal) of the D flip-flop N4 becomes low, the output of the D flip-flop N4 becomes low, that is, the voltage regulator is turned off to protect the protected device AD9910.

[0053] Since the reset terminal of the D flip-flop is also used as the monitoring level pin of the FPGA, when the FPGA detects that the reset terminal of the D flip-flop N4 changes from high level to low level, it is equivalent to knowing that the AD9910 has been latched. According to the pre-set action, about 5 seconds after detecting the level change, a negative pulse is sent to the set terminal (set input terminal, i.e., pin 4) of the D flip-flop N4. In this way, the output terminal of the D flip-flop N4 changes from the original low level to high level, the voltage regulator block is restarted, the power supply of the protected device AD9910 is restored, and the circuit resumes normal operation.

Claims

1. A protection circuit for latching a satellite-borne self-closed loop device, characterized in that: It includes a voltage regulator module, a power resistor, an amplification and comparison module, a D trigger module and an FPGA; The first end of the power resistor is commonly connected to the first end of the voltage stabilizing module and the first end of the amplifying and comparing module; the external power supply is commonly connected to the second end of the power resistor and the second end of the amplifying and comparing module; the first end of the D trigger module is connected to the fourth end of the amplifying and comparing circuit, and the second end of the D trigger module is connected to the fifth end of the amplifying and comparing circuit; the third end of the D trigger module is commonly connected to the first end of the FPGA and the third end of the voltage stabilizing module; the fourth end of the D trigger module is connected to the second end of the FPGA; The power resistor is used to connect to an external power supply, and the potential difference between the two ends is used to characterize the working current of the protected device; The voltage stabilizing module is used to stabilize the DC power supply voltage transmitted by the external power supply through the power resistor and to control the opening and closing of the protected device by controlling the level control enabling terminal; The amplification and comparison module is used to amplify the potential difference generated at both ends of the power resistor and compare the amplified voltage Vin with the set comparison voltage Vref. When Vin<Vref, the output voltage Vout is a high level; when Vin>Vref, the output level Vout is a low level. The D flip-flop module is used to use the output voltage of the amplification comparison module as the input control signal of the reset end, which is divided into two paths, one path is used as the control signal of the voltage stabilization module, and the other path is output to the FPGA as level monitoring; and the negative pulse given by the FPGA is used as the set end as the control signal to restart the circuit; The FPGA is used to complete the self-closing function of the protection circuit for latching the on-board self-closing device. One I / 0 port is configured as an input level monitoring pin to monitor the reset end level of the D flip-flop module; another I / 0 port is configured as a reset action pin. When it is monitored that the reset end of the D flip-flop module is converted from a high level to a low level, after a time delay, the reset action pin sends a negative pulse to the set end of the D flip-flop module to restart the protected device.

2. The protection circuit for latching of a satellite-borne self-closed loop device as claimed in claim 1, characterized in that: The voltage stabilizing module includes a voltage stabilizer N2, a resistor R51, a resistor R52, a resistor R53, a capacitor C51, a capacitor C52, a capacitor C53 and a capacitor C54. The pin 2 of the voltage stabilizer N2 is connected to one end of the resistor R53 and one end of the capacitor C54. The second end of the resistor R53 is connected to the third end of the D trigger module and the FPGA as the third end of the voltage stabilizing module. The second end of the capacitor C54 is grounded. The pin 3 and the pin 4 of the voltage stabilizer N2 are connected to one end of the capacitor C51, the first end of the power resistor and the amplification comparison circuit as the first end of the voltage stabilizing module. The first end of the capacitor C51 is connected together, the second end of the capacitor C51 is grounded, the second end of the power resistor is connected to the external power supply and the second end of the amplification and comparison circuit; the pin 9 of the regulator N2 is connected together with one end of the resistor R51 and one end of the resistor R52, the second end of the resistor R51 is grounded, the second end of the resistor R52 is connected together with the positive electrode of the capacitor C52, the protected device and the pin 6 and pin 7 of the regulator N2, the negative electrode of the capacitor C52 is connected to the positive electrode of the capacitor C53, and the negative electrode of the capacitor C53 is grounded; the pins 1, 5, 8 and 10 of the regulator N2 are suspended.

3. The protection circuit for latching of a satellite-borne self-closed loop device as claimed in claim 1, characterized in that: The amplification and comparison circuit includes an operational amplifier N3, a resistor R55, a resistor R56, a resistor R57, a resistor R58, a resistor R59, a resistor R60, a resistor R61 and a resistor R24, wherein the pin 5 of the operational amplifier N3 is commonly connected to one end of the resistor R57 and one end of the resistor R56, the second end of the resistor R57 is grounded, and the second end of the resistor R56 is commonly connected to the second end of the power resistor and the voltage stabilizing module as the second end of the amplification and comparison circuit; the pin 6 of the operational amplifier N3 is commonly connected to one end of the resistor R55 and one end of the resistor R58, and the second end of the resistor R55 is commonly connected to the first end of the power resistor and the voltage stabilizing module as the first end of the amplification and comparison circuit The first end of the D flip-flop module is connected together, the second end of the resistor R58 is connected together with the pin 7 of the operational amplifier N3 and one end of the resistor R59, and the second end of the resistor R59 is connected to the pin 2 of the operational amplifier N3; the pin 8 of the operational amplifier N3 is connected to one end of the resistor R24 ​​as the fourth end of the amplification and comparison circuit, and the second end of the resistor R24 ​​is connected together with one end of the resistor R61 and the first end of the D flip-flop module; the second end of the resistor R61 is connected together with one end of the resistor R60 and the pin 3 of the operational amplifier N3, and the pin 4 of the operational amplifier N3 is grounded; the pin 1 of the operational amplifier N3 is connected to the second end of the D flip-flop module as the fifth end of the amplification and comparison circuit.

4. The protection circuit for latching of a satellite-borne self-closed loop device as claimed in claim 1, characterized in that: The D trigger module includes a D trigger N4, a resistor R62, a resistor R63, a resistor R64 and a resistor R23, wherein a pin 1 of the D trigger N4 is connected to one end of the resistor R62, a second end of the resistor R62 is connected to the fifth end of the amplification comparison circuit as the second end of the D trigger module, a pin 14 of the D trigger N4 is connected to one end of the resistor R23, and a second end of the resistor R23 is connected to the fourth end of the amplification comparison circuit as the first end of the D trigger module; a pin 2 of the D trigger N4 is connected to one end of the resistor R63, a second end of the resistor R63 is connected to one end of the resistor R64 and is grounded, and a second end of the resistor R64 is connected to a pin 3 of the D trigger N4; a pin 5 of the D trigger N4 is connected to the first end of the FPGA and the third end of the voltage regulator module as the third end of the D trigger module, and a pin 4 of the D trigger N4 is connected to the second end of the FPGA as the fourth end of the D trigger module; and the remaining pins of the D trigger N4 are suspended.

Images