Fractional frequency divider

Abstract

The invention relates to a fractional divider. The device (110) includes a counter (202) having a clock input, a count value input, a third input, and an output. A multiplexer (218) has a first input, a second input, a selection input, and an output. A delay circuit (210) has a first input coupled to the clock input of the counter (202), a second input coupled to the output of the counter (202), a first output, and a second output. The first output is coupled to the first input of the multiplexer (218), and the second output is coupled to the second input of the multiplexer (218). A fractional control circuit (214) has a first output coupled to the selection input of the multiplexer (218), and has a second output coupled to the third input of the counter (202).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Indian Provisional Application No. 202341079142 filed on November 21, 2023, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of electronics. Background Art

[0004] Many clock circuits include a frequency divider that divides the frequency of an input clock to produce an output clock at a lower frequency. Some frequency dividers are integer frequency dividers. An integer frequency divider can divide the frequency by an integer value (e.g., 2, 3, 4, etc.). Summary of the invention

[0005] In one example, a device includes a counter having a clock input, a count value input, a third input, and an output. A multiplexer has a first input, a second input, a select input, and an output. A delay circuit has a first input, a second input, a first output, and a second output, the first input being coupled to the clock input of the counter, the second input being coupled to the output of the counter. The first output is coupled to the first input of the multiplexer, and the second output is coupled to the second input of the multiplexer. A fractional control circuit has a first output coupled to the select input of the multiplexer, and has a second output coupled to the third input of the counter.

[0006] In another example, a device includes a counter having a clock input, a count value input, an enable offset input, and an output. A synchronizer has a first input, a second input, a third input, and an output. The first input is coupled to the clock input, and the second input is coupled to the output of the counter. A fractional control circuit has a fractional control input and an output. The output of the fractional control circuit is coupled to the third input of the synchronizer. The fractional control circuit is configured to program a delay of the synchronizer based on a signal at the fractional control input and a clock output signal.

[0007] In yet another example, an apparatus includes a resonator and a counter, the resonator having an output, the counter having a clock input, a count value input, an enable offset input, and an output, the clock input being coupled to the output of the resonator. A multiplexer having a first input, a second input, a third input, a select input, and an output. A delay circuit having an input coupled to the clock input of the counter and having a first output, a second output, and a third output. The first output is coupled to the first input of the multiplexer, the second output is coupled to the second input of the multiplexer, and the third output is coupled to the third input of the multiplexer. A fractional control circuit having a control output coupled to the select input of the multiplexer and having an enable offset output coupled to the enable offset input of the counter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram of a resonator circuit including a fractional frequency divider in an example.

[0009] Figure 2 is in the instance Figure 1 Block diagram of a fractional divider.

[0010] Figure 3 is shown in the example Figure 2 A flow chart of the operation of the fractional divider.

[0011] Figure 4 is a block diagram of a fractional frequency divider in another example.

[0012] Figure 5 is a block diagram of a fractional frequency divider in yet another example.

[0013] Figure 6 is a schematic diagram of a counter included in a fractional divider in an example.

[0014] Figure 7 is in the instance Figure 6 Schematic diagram of each of the ripple stages of the ripple counter within the ripple counter.

[0015] Figure 8 is a schematic diagram of a synchronizer and a fractional control circuit of a fractional frequency divider in an example.

[0016] Fig. 9 is in the instance Figure 8 Schematic diagram of the selection logic circuit of the score control circuit.

[0017] Fig.10 is shown in the example Figure 5 Timing diagram of the operation of the fractional divider.

[0018] Fig.11 is shown in the example Figure 4 Timing diagram of the operation of the fractional divider. DETAILED DESCRIPTION

[0019] The same reference numerals or other reference designators are used in the drawings to designate the same or similar features (either functionally and / or structurally).

[0020] Some frequency dividers are programmable. By programming a specific divide value into the frequency divider, the frequency divider can divide the input clock by the specific divide value. The number of different output frequencies depends on the number of different divide values ​​that the frequency divider can adapt to. The frequency divider described herein is a fractional frequency divider that can adapt to fractional divide values. In one example, the divide value has a resolution of 0.5. The 0.5 resolution means that the frequency divider can adapt to, for example, a divide value of 8, 8.5, 9, 9.5, etc. The disclosed fractional frequency divider also generates an output clock having a duty cycle equal to or approximately equal to 50%. The disclosed fractional frequency divider is also a low power frequency divider.

[0021] Figure 11 is a block diagram of a clock generator circuit 100, which includes a resonator 102, a fractional divider 110, an output driver 118, a temperature sensor 120, a control logic 122, a digital-to-analog converter (DAC) 124, and a filter 126. The resonator 102 may include a bulk acoustic wave (BAW) resonator or other type of resonator. The output of the resonator 102 is coupled to an input 110a of the fractional divider 110. The resonator 102 generates a clock signal (CLK_IN) to the divider 110. The fractional divider 110 includes an output 110b, which is coupled to an input of the output driver 118. The fractional divider 110 divides the frequency of the clock signal CLK_IN by a programmable division value. The division value is provided to the fractional divider 110 by means of an integer division value N<7:0> and an enable fractional division signal EN_OP5. In this example, the integer partition value N<7:0> is an 8-bit value, but in other examples, the integer partition value may not be 8 bits. The enable fractional partition signal EN_0P5 is a single bit signal. If the enable fractional partition signal EN_0P5 is a logic "1", the fractional frequency division is enabled, and if the enable fractional partition signal EN_0P5 is a logic "0", the fractional frequency division is not enabled. For example, in order to specify a partition value of 12.5, the value of N<7:0> is "00001000", and the enable fractional partition signal EN_0P5 is "1". In order to specify a partition value of 12, the value of N<7:0> is "00001000", and the signal EN_0P5 is "0". In the examples described herein, the fractional frequency divider 110 is capable of having a 0.5 resolution (e.g., divided by 8, 8.5, 9, 9.5, etc.). The divided output clock from fractional frequency divider 110 is the output clock signal CLK_OUT, which is provided to output driver 118. The output signal from output driver 118 is OP.

[0022] The frequency of the clock signal CLK_IN from the resonator 102 may have a temperature dependency. For example, the frequency of the clock signal CLK_IN may increase as the temperature increases and decrease as the temperature decreases. The combination of the temperature sensor 120, the control logic 122, the DAC 124, and the filter 126 provides temperature compensation for the resonator 102. The control logic 122 may amplify the temperature signal from the temperature sensor 120 and generate a digital code to be provided to the DAC 124. The digital code helps maintain the CLK_IN signal of the resonator at a substantially constant frequency. The DAC 124 converts the digital code from the control logic 122 from a digital value to an analog signal. The filter 126 filters (e.g., low pass filters) the analog signal from the DAC 124 to generate a control signal Vcont to the resonator 102. The resonator 102 adjusts the frequency of its output signal CLK_IN based on the magnitude of the control signal Vcont, thereby maintaining the frequency of the signal CLK_IN relatively unaffected by temperature changes.

[0023] Figure 21 is a block diagram of a fractional frequency divider 110 in an example. The fractional frequency divider 110 includes a counter 202, a synchronizer 208, a fractional control circuit 214, and a T flip-flop 224. The synchronizer 208 includes a delay circuit 210 and a multiplexer (MUX) 218. The counter 202 has a clock input 202a, a count value input 202b, an enable offset input 202c, and an output 202d. The synchronizer 208 has inputs 208a, 208b, and 208c and an output 208d. The fractional control circuit 214 has a fractional control input 214a, an input 214b, and an input 214c, and outputs 214d and 214e. The clock signal CLK_IN is provided to the clock input 202a of the counter 202 and the input 208a of the synchronizer 208, respectively. The output 202d of the counter 202 is coupled to the input 208b of the synchronizer 208. The Q output of the T flip-flop 224, which provides the output signal CLK_OUT from the fractional divider 110, is coupled to the input 214c of the fractional control circuit 214. The T flip-flop changes the logic state of its output signal CLK_OUT at each rising edge of the signal at its clock input. The output 214d of the fractional control circuit 214 is coupled to the enable offset input 202c of the counter 202. The output 214e of the fractional control circuit 214 is coupled to the input 208c of the synchronizer 208 and provides the multiplexer select signal to the multiplexer. The least significant bit N of the fractional division value N<7:0> <0> is provided to input 214b of fraction control circuit 214. <0> The remaining bits N<7:1> other than 0 are provided to the count value input 202b of the counter 202 as the initial count value. The enable fraction division signal EN_OP5 is provided to the input 214a of the fraction control circuit 214.

[0024] Delay circuit 210 has inputs 210a and 210b and outputs 210c and 210d. Input 210a of delay circuit 210 is coupled to input 208a of synchronizer 208, and input 210b is coupled to input 208b. Multiplexer has inputs 218a and 218b, select input 218c, and output 218d. The output signal from MUX 218 is signal MUX_OUT. Output 210c is coupled to input 218a, and output 210d is coupled to input 218b. Although delay circuit 210 and multiplexer 218 are in Figure 2 In the example of , the delay circuit and the multiplexer are shown as having two outputs and two inputs, respectively, but the delay circuit and the multiplexer may have more than two outputs and inputs. The output 218d of the multiplexer 218 is coupled to the output 208d of the synchronizer 208. The select input 218c of the multiplexer 218 is coupled to the input 208c of the synchronizer 208.

[0025] The counter 202 includes a ripple counter whose output is coupled to a logic circuit, both of which are described below. In operation, the ripple counter of the counter 202 is loaded with a count value that includes the least significant bits N of the fractional divided value. <0> . The ripple counter decrements its output count value at each rising edge of the clock signal CLK_IN. The logic circuit determines when the output count value from the ripple counter reaches 0 or 1 based on the control signal EN_OFFSET generated by the fractional control circuit 214 at its output 214d, and changes the output signal LD ​​of the counter 202 from a logic low to a logic high. After two cycles of the clock signal CLK_IN, the logic circuit within the counter 202 forces the output signal LD ​​to return to a logic low state. The output signal LD ​​is used in two aspects. First, the output signal LD ​​is used to reload the ripple counter with its count value (N<7:1>). Secondly, the output signal LD ​​is used by the synchronizer 208 to generate the output clock signal MUX_OUT from the synchronizer. The delay circuit 210 of the synchronizer 208 provides multiple different delayed versions of the signal LD ​​to the input of the multiplexer 218. In one example, the delay circuit 210 generates an incremental half-clock cycle delayed version of the signal LD ​​at its outputs 210c and 210d. For example, the signal at the output 210 c is the signal LD ​​delayed by half a clock cycle of the input clock signal CLK_IN, and the signal at the output 210 d is the signal LD ​​delayed by a full cycle of the input clock signal CLK_IN.

[0026] As described below, the fractional control circuit 214 controls the output clock signal CLK_OUT based on the least significant bit N of the fractional division value. <0> The fractional control circuit 214 controls which delayed versions of the signal LD ​​will be provided to the clock input of the T flip-flop 224, thereby generating the output clock signal CLK_OUT of the clock generator circuit 100.

[0027] Figure 3 is shown in the example Figure 2300 of the operation of the fractional divider 110 of the embodiment of the present invention. At operation 302, a count value is loaded into the counter 202. In one example, the count value is all bits N<7:1> except the least significant bit of the integer division value. At the rising edge of the signal LD, the count value is loaded into the ripple counter within the counter 202. At operation 304, the counter 202 is programmed to count down to a final value of 0 or 1. In one example, the fractional control circuit 214 generates a control signal EN_OFFSET to the counter 202 to configure the counter to count down to a value of 0 or 1. For example, the control signal EN_OFFSET as a logic 0 configures the counter 202 to count down to a final value of 1, and the control signal EN_OFFSET as a logic 1 configures the counter 202 to count down to a final value of 0.

[0028] At operation 306, the ripple counter within the counter 202 begins to count down. At decision 308, the logic circuit within the counter 202 determines whether the ripple counter output count value has reached the corresponding value of 0 or 1. If the ripple counter output count value has not yet reached the corresponding value of 0 or 1, the ripple counter continues to count down. However, if the logic circuit determines that the output count value of the ripple counter has reached the value of 0 or 1, then at operation 310, the logic circuit forces the signal LD ​​to a logic high state within multiple (e.g., two) cycles of the input clock signal CLK_IN. At operation 312, the synchronizer 208 introduces a delay of one or more half-clock cycle increments of CLK_IN into the LD signal to generate MUX_OUT. Operation 302 is also performed again to load the count value into the counter 202. Subsequently, at operation 314, the logic state output clock CLK_OUT is switched at the net rising edge of MUX_OUT.

[0029] Figure 4 is a block diagram of the fractional frequency divider 110 in another example. Figure 4 An example similar to Figure 2 224. The fractional control circuit 214 has an additional input 214f ​​coupled to the Q output of the T flip-flop 414. Because the T flip-flop 414 is clocked with the signal at the Q output of the T flip-flop 224, the signal BY2_OP at the Q output of the T flip-flop 414 has half the frequency of the signal at the Q output of the T flip-flop 224. The fractional control circuit 214 has an additional input 214f ​​coupled to the Q output of the T flip-flop 414.

[0030] The delay circuit 210 generates two delayed signals OP5 and 1P0 at its outputs 210c and 210d, respectively. The delayed signal OP5 is a signal LD ​​that is delayed by half a clock cycle of CLK_IN. The delayed signal 1P0 is a signal LD ​​that is delayed by a full clock cycle of CLK_IN. The multiplexer 218 provides the signal OP5 or 1P0 to the clock input of the T flip-flop 224 based on the selection signal from the fractional control circuit 214 at its selection input 218c.

[0031] The fraction control circuit 214 outputs the clock signal CLK_OUT, the signal BY2_OP, the least significant bit N of the fractional division value, and the fractional division value. <0> and enable fractional division signal EN_0P5 to generate a multiplexer selection signal at its output 214e, the multiplexer selection signal being Figure 4 The fractional control circuit 214 generates a selection signal to the multiplexer 218 to select the signal 0P5 delayed by a half clock cycle or the signal 1P0 delayed by a full clock cycle.

[0032] Figure 4 The output clock signal CLK_OUT in the example fractional frequency divider 110 may be characterized by having a subharmonic frequency. Some applications of the frequency divider may not be affected by any subharmonic frequencies. For those applications that are adversely affected by subharmonic frequencies, the Figure 5 The fractional divider 110 is provided. Figure 5 The fractional divider 110 reduces or eliminates the Figure 4 The sub-harmonic frequencies that may exist in a fractional divider.

[0033] Figure 5 The fractional divider 110 is largely related to Figure 4 The multiplexer 218 is the same as the fractional frequency divider 110 of FIG. The difference is that the delay circuit 210 has an additional output 210e that provides a third LD delayed signal 1P5. In addition, the multiplexer 218 has an additional input 218e coupled to the output 210e of the delay circuit 210. The signal 1P5 is a delayed version of the signal LD ​​delayed by 1.5 cycles of the input clock CLK_IN. By using any of the three half-cycle delayed versions of the signal LD ​​to generate the output clock signal CLK_OUT, subharmonics are reduced or eliminated in CLK_OUT.

[0034] Figure 66 is a schematic diagram of a counter 202 in an example. Counter 202 includes a ripple counter 610 and a logic circuit 660. In this example, ripple counter 610 is a 7-bit ripple counter, and the 7-bit ripple counter includes seven ripple counter stages 661a, 661b, 661c, 661d, 661e, 661f and 661g. Each ripple counter stage 661a-661g has a clock input, a load control input, a load input and a Q output. For example, ripple counter stage 661a has a clock input 663, a load control input 667, a load input 669 and a Q output (Q1) 671. The outputs of ripple counter stages 661a-661g are Q1, Q2, Q3, Q4, Q5, Q6 and Q7 respectively. Output Q1 is the least significant bit of the output count value of the ripple counter, and Q7 is the most significant bit of the output count value. The input clock CLK_IN is provided to the clock input 663 of the ripple counter stage 661a. The output of each stage is coupled to the clock input of the next stage. For example, the output 671 of the ripple counter stage 661a is coupled to the clock input of the ripple counter stage 661b, the output (Q2) of the ripple counter stage 661b is coupled to the clock input of the ripple counter stage 661c, and so on.

[0035] The signal LD ​​is provided to the load control input of each of the ripple counter stages 661a-661g (e.g., the load control input 667 of the ripple counter stage 661a). Each bit of the initial count value N<7:1> is provided to the load input (e.g., the load input 667) of each corresponding ripple counter stage. When the signal LD ​​is logic high, the corresponding bit value (N<7:1>) of the initial count value is set to <1> 、N <2> etc.) are loaded into the corresponding ripple counter stage.

[0036] Logic circuit 660 includes OR gates 662 and 664, NOR gates 666, 670 and 678, NAND gate 668, inverter 680, flip-flops 674 and 676, and multiplexer 672. As shown, the Q3-Q7 outputs of ripple counter stages 663-667 are coupled to the inputs of OR gates 662 and 664. The output of OR gate 662 is coupled to the input of OR gate 664. The ripple counter stage output bits Q3-Q7 are logically ORed together by means of OR gates 662 and 664. The output of OR gate 664 is coupled to the input of NOR gate 666. The Q2 output of ripple counter stage 661b is coupled to the other input of NOR gate 666. The output of NOR gate 666 is coupled to the input of NAND gate 668. Control signal EN_OFFSET is provided to the select (S) input of multiplexer 672. The Q1 output of ripple counter stage 661 (the least significant bit of the output count value of the ripple counter) is provided to the 0 input of multiplexer 672, and the logical inverse of the Q1 output (Q1b) is provided to the 1 input of the multiplexer. The output of multiplexer 672 is coupled to the other input of NAND gate 668.

[0037] The output of NAND gate 668 is coupled to the input of NOR gate 670, and the output of inverter 680 that generates signal LD ​​is coupled to the other input of NOR gate 670. The output of NOR gate 670 is coupled to the data input of flip-flop 674, and the signal ALL_ZEROS is provided to the data input of the flip-flop. The Q output of flip-flop 674 is coupled to the data input of flip-flop 676, and the signal LD_FAST is provided to flip-flop 676. The clock inputs of flip-flops 674 and 676 receive the input clock CLK_IN. The Q output of flip-flop 676 is coupled to the input of NOR gate 678, and the Q output of flip-flop 674 is coupled to the other input of NOR gate 678. The output of NOR gate 678 is coupled to the input of inverter 680.

[0038] In response to all Q2-Q7 bits being logic 0, the output signal from NOR gate 666 becomes logic 1. Regardless of which bit Q1 or Q1b from multiplexer 672 also becomes logic 1, the output signal from NAND gate 668 becomes logic 0 in accordance with the selection signal EN_OFFSET. Initially, signal LD ​​is logic 0. In the case where both inputs to NOR gate 670 are logic 0, NOR gate 670 forces its output signal ALL_ZEROS to logic 1, indicating that all output bits Q1 (or Q1b) and Q2-Q7 are logic 0. At the next rising edge of CLK_IN, flip-flop 674 switches its output signal LD_FAST to a logic 1 state. At the next subsequent rising edge of CLK_IN, flip-flop 676 also switches its output signal to a logic 1 state. In the case where LD_FAST is logic 1, the output signal from NOR gate 678 is logic 0, causing inverter 680 to force signal LD ​​to a logic 1 state. Therefore, after the signal ALL_ZEROS becomes logic 1, the signals LD_FAST and LD become logic 1 at the next rising edge CLK_IN. The signal LD_FAST remains at a logic 1 state for one cycle of CLK_IN, and the signal LD ​​remains at a logic 1 state for two cycles of CLK_IN.

[0039] When signal LD ​​becomes logic 1, the corresponding input of NOR gate 670 becomes logic 1, causing NOR gate 670 to force its output signal ALL_ZEROS to logic 0. At the next rising edge of CLK_IN, flip-flop 674 forces its output signal LD_FAST to logic 0. At the next subsequent rising edge of CLK_IN, flip-flop 676 forces its output signal to a logic 0 state. The output signal from NOR gate 678 then becomes logic 1, and via inverter 680, signal LD ​​becomes logic 0.

[0040] Figure 7is a schematic diagram of an individual ripple counter stage of ripple counter 610. Each ripple counter stage 661a-661g includes a D flip-flop 702, inverters 704 and 708, and AND gates 706 and 710. The Q output of flip-flop 702 is coupled to the input of inverter 704, and the output of inverter 704 is coupled to the D input of D flip-flop 702. The LD signal and the initial count bit (e.g., N for ripple counter stage 661a) are coupled to the D input of inverter 704. <1> ) is provided to the input of AND gate 706. The output of AND gate 706 is coupled to the input of inverter 708 and to the PRESET input of D flip-flop 702. The output of inverter 708 is coupled to the input of AND gate 710. The LD signal is also provided to another input of AND gate 710. The output of AND gate 710 is coupled to the CLEAR input of the D flip-flop. When signal LD ​​is logic high, the output of AND gate 706 is ANDed to the initial count bit (e.g., N <1> ) and the output of AND gate 710 has the opposite logic state to the initial count bit. For example, when signal LD ​​is logic high, if N <1> is logic 1, PRESET is logic 1, CLEAR is logic 0, and the Q output is forced to its initial state of logic 1. Conversely, if N <1> is logic 0 (when LD is logic 1), then PRESET is logic 0, CLEAR is logic 1, and the Q output is forced to an initial state of logic 0.

[0041] As described above, the signal provided to the clock input of the D flip-flop 702 is CLK_IN in the case of the ripple counter stage 661a, or the Q output of the previous ripple counter stage in the case of the ripple counter stages 661b-661g. When the signal LD ​​is a logic 0, when a rising edge occurs at the clock input of the D flip-flop 702, the Q output of the flip-flop 702 changes logic state. Based on the state of the signal at the PRESET input, the Q output of the D flip-flop 702 can be forced to a logic 0 or a logic 1. AND gate 706 performs a logic AND on the signal LD ​​and the initial count bit together. Therefore, if the initial count bit is a logic 1 when the signal LD ​​is a logic 1, the flip-flop 702 sets its output Q to a logic 1.

[0042] Figure 8is a schematic diagram of synchronizer 208 and fractional control circuit 214 in an example. Delay circuit 210 includes inverter 802 and D flip-flops 804, 806, and 808. Fractional control circuit 214 includes inverter 830, buffer 832, D flip-flops 834 and 836, selection logic circuit 840, and NAND gates 854, 856, and 858. Input 208a of synchronizer 208 is coupled to the clock input of D flip-flop 806 and to the input of inverter 802. The output of inverter 802 is coupled to the clock input of D flip-flop 804. Input 208b is coupled to the D input of D flip-flop 806. Input 208c is coupled to the D input of D flip-flop 804. The Q output of D flip-flop 806 is coupled to output 210d of delay circuit 210 and to input 210b of multiplexer 218. The Q output of D flip-flop 804 is coupled to the D input of D flip-flop 808 and to input 218a of multiplexer 218 via output 210c of delay circuit 210. The Q output of D flip-flop 808 is coupled to output 210e of delay circuit 210 and to input 218a of multiplexer 218.

[0043] The D flip-flop 806 is timed by the rising edge of the clock signal CLK_IN. Via the inverter 802, the D flip-flops 804 and 808 are timed by the falling edge of the clock signal CLK_IN. The output signal from the D flip-flop 804 is a delay signal OP5, which is a signal LD_FAST that delays a half cycle of the clock signal CLK_IN due to the D flip-flop 804 being timed by the falling edge of CLK_IN. The output signal from the D flip-flop 806 is a delay signal 1P0, which is a signal LD ​​that delays a full cycle of CLK_IN due to the D flip-flop 806 being timed by the rising edge of CLK_IN. The output signal from the D flip-flop 808 is a delay signal 1P5, which is a signal LD_FAST that delays one and half cycles of the clock signal CLK_IN.

[0044] As described above, the selection logic circuit 840 receives the signals EN_0P5, N <0> / Nb <0> (N <0> 1P0), CLK_OUT / CLK_OUTb (the logical inverse of CLK_IN), and BY2_OP / BY2_OPb (the logical inverse of BY2_OP) as inputs. The selection logic circuit 840 has outputs 840a and 840b. Output 840a is coupled to the D input of D flip-flop 834, and output 840b is coupled to the D input of D flip-flop 836. The signal at output 840a is signal SEL_DLY_1P5, and the signal at output 840b is signal SEL_POS_EDGE. Via inverter 830, D flip-flops 834 and 836 are timed by the logical inverse of delay signal 1P0. The selection input 218c of multiplexer 218 is two-bit selection inputs S0 and S1. The Q outputs of D flip-flops 834 and 836, which provide signals SEL_DLY_1P5_SYNC and SEL_POS_EDGE_SYNC, respectively, are coupled to S0 and S1, respectively, and provide signals SEL_DLY_1P5_SYNC and SEL_POS_EDGE_SYNC. Table I below is a truth table that specifies which input of multiplexer 218 is selected to provide its signal as output signal MUX_OUT.

[0045] Table I

[0046] SEL_POS_EDGE_SYNC SEL_DLY_1P5_SYNC Output 0 0 0P5 (MUX input 0 / 218a) 0 1 1P5(MUX input 1 / 218e) 1 X 1P0 (MUX input 2 / 218b)

[0047] Figure 4 and 5 Involving T flip-flops 224 and 414. Figure 8 In the embodiment, T flip-flops 224 and 414 are implemented as D flip-flops 224a and 414a, respectively. In addition to D flip-flops 224a and 414a, fractional frequency divider 110 includes inverters 850 and 852. The Qb output of D flip-flop 224a is coupled to the input of inverter 850 and to the input of NAND gate 856, and also provides clock signal CLK_OUTb. The other input of NAND gate 856 receives N <0> . The output of inverter 850 is coupled to the input of NAND gate 854 and to the clock input of D flip-flop 414a, and also provides clock signal CLK_OUT. The Qb output of D flip-flop 414a is coupled to the input of inverter 852 and to the input of NAND gate 854, and also provides signal BY2_OPb. Inverter 852 generates signal BY2_OP at its output. Enable fractional division signal EN_0P5 is coupled to another input of NAND gate 854. The outputs of NAND gates 854 and 856 are coupled to the input of NAND gate 858. The output signal of NAND gate 858 is control signal EN_OFFSET.

[0048] Fig. 9 8 is a schematic diagram of a selection logic circuit 840 in an example. The selection logic circuit 840 includes NAND gates 902, 904, 906, 908, 910 and 912, NOR gates 914, 916, 918, 920 and 924, and an OR gate 922. <0> The NAND gate 904 performs a logical NOT AND on Nb <0> The NAND gate 906 performs a logical NOT with the signal BY2_OP. <0> The NAND gate 908 performs a logical AND operation on the signal EN_0P5 and CLK_OUTb. The NAND gate 910 performs a logical AND operation on the signal Nb. <0> The NAND gate 904 performs a logical NOT with the signal BY2_OPb. <0> Performs logical AND NOT with signal BY2_OPb.

[0049] The output of NAND gate 902 is coupled to the input of each of NOR gates 916 and 918. The output of NAND gate 904 is coupled to the input of NOR gate 914. The output of NAND gate 906 is coupled to the input of NOR gate 916. The output of NAND gate 908 is coupled to the input of each of NOR gates 914 and 920. The output of NAND gate 910 is coupled to the input of NOR gate 918. The output of NAND gate 912 is coupled to the input of NOR gate 920. The output from NOR gate 914 is coupled to the input of OR gate 922. The output of NOR gate 916 is coupled to the input of OR gate 922 and NOR gate 924. The output of NOR gate 918 is coupled to the input of NOR gate 924. The output of NOR gate 920 is coupled to the input of NOR gate 924. The output signal from OR gate 922 is signal SEL_DEL_1P5, and the output signal from NOR gate 924 is signal SEL_POS_EDGE.

[0050] When any of the following conditions is true, the signal SEL_DEL_1P5 is logic 1. First, when the enable fractional division signal EN_0P5 is logic 1 and the least significant bit N of the fractional division value N<7:0> is <0> is logic 0 and signal BY2_OP is logic 1, then when the falling edge of CLK_OUT occurs, signal SEL_DEL_1P5 will be logic 1. Secondly, when the following signals / bits are all logic 1: the least significant bit N <0> , BY2_OP, and CLK_OUT, signal SEL_DEL_1P5 will be a logic 1. If none of the preceding conditions are true, signal SEL_DEL_1P5 is a logic 0. Fig. 9The logic for generating the signal SEL_POS_EDGE in takes into account various situations, depending on, for example, whether fractional division is enabled (enable signal EN_0P5), the logic state of the output clock CLK_OUT, and whether the integer part N<7:0> is an even value or an odd value.

[0051] Fig.10 It is shown Figure 5 1 is a timing diagram of an example where the fractional divider 110 divides the clock signal CLK_IN by a division value of 8.5. In this case, N<7:0> is 4, and the enable fractional division signal EN_OP5 is a logic 1. Fig.10 The signals in the timing diagram include CLK_IN, ALL_ZEROS, LD, LD_FAST, 0P5, 1P0, 1P5, SEL_DLY_1P5_SYNC, SEL_POS_EDGE_SYNC, MUX_OUT, CLK_OUT, BY2_OP and EN_OFFSET.

[0052] As previously described, when counter 202 counts down to its final value (0 or 1 based on the state of control signal EN_OFFSET), signals LD and LD_FAST transition from logic low to logic high, as indicated at 1011. Signal LD_FAST remains high for one cycle of CLK_IN, and then transitions back to logic low at 1012. Signal LD ​​remains high for two cycles of CLK_IN, and then transitions back to logic low at 1013. Because signal LD ​​is provided to NOR gate 670 ( Figure 6 ), so once the signal LD ​​becomes logic high, the signal ALL_ZEROS becomes logic low at 1014. Fig.10 Shown in Figure 5 The delay signals 0P5, 1P0 and 1P5 are shown in FIG. 1 . The rising edge 1015 of the delay signal 0P5 is delayed by half a cycle from the signals LD and LD_FAST. The rising edge 1016 of the delay signal 1P0 is delayed by another half cycle relative to the delay signal 0P5. The rising edge 1017 of the delay signal 1P5 is delayed by half a cycle relative to the delay signal 1P0.

[0053] 1P0, which has been selected by the multiplexer 218 based on the logic states of the signals SEL_DLY_1P5_SYNC and SEL_POS_EDGE_SYNC. The D flip-flop 224a is clocked based on MUX_OUT and initiates a rising edge 1018 of CLK_OUT that is commensurate with the rising edge 1025 of MUX_OUT. A subsequent falling edge 1019 of CLK_OUT is triggered by the next rising edge 1026 of MUX_OUT, which is itself based on the rising edge 1020 of the delayed signal 1P0. In the next cycle of CLK_OUT, a rising edge 1021 is triggered by a rising edge 1022 of the delayed signal 1P5 (via the output signal MUX_OUT of the multiplexer 218) because the fractional control circuit 214 has selected the delayed signal 1P5 from the multiplexer 218. The subsequent falling edge 1023 of CLK_OUT coincides with the rising edge 1024 of the delayed signal OP5 because the fractional control circuit 214 has selected the delayed signal OP5 at that point.

[0054] Fig.11 It is shown Figure 4 The fractional divider 110 of FIG. 1 is a timing diagram of an example of dividing the clock signal CLK_IN by a division value of 8.5. Fig.10 In the example, N<7:0> is 4 and the enable fractional division signal EN_0P5 is logic 1. Fig.11 The signals in the timing diagram include CLK_IN, ALL_ZEROS, LD, LD_FAST, 0P5, 1P0, SEL_MUX, MUX_OUT, CLK_OUT, BY2_OP and EN_OFFSET.

[0055] As previously described, when counter 202 counts down to its final value (0 or 1 based on the state of control signal EN_OFFSET), signals LD and LD_FAST transition from logic low to logic high, as indicated at 1111. Signal LD_FAST remains high for one cycle of CLK_IN, and then transitions back to logic low at 1112. Signal LD ​​remains high for two cycles of CLK_IN, and then transitions back to logic low at 1113. Because signal LD ​​is provided to NOR gate 670 ( Figure 6 ), so once the signal LD ​​becomes logic high, the signal ALL_ZEROS becomes logic low at 1114. Fig.11 Shown in Figure 4The rising edge 1115 of the delayed signal 0P5 is a half cycle delayed from the signals LD and LD_FAST. The rising edge 1116 of the delayed signal 1P0 is another half cycle delayed relative to the delayed signal 0P5.

[0056] 1P0, which has been selected by the multiplexer 218 based on the logic state of the signal SEL_MUX. The T flip-flop 224 is clocked based on MUX_OUT and initiates a rising edge 1118 of CLK_OUT that is commensurate with the rising edge 1125 of MUX_OUT. A subsequent falling edge 1119 of CLK_OUT is triggered by the next rising edge 1126 of MUX_OUT, which is itself based on the rising edge 1120 of the delayed signal 1P0. In the next cycle of CLK_OUT, a rising edge 1121 is triggered by a rising edge 1122 of the delayed signal OP5 (via the output signal MUX_OUT of the multiplexer 218) because the fractional control circuit 214 has selected the delayed signal OP5 from the multiplexer 218. The subsequent falling edge 1123 of CLK_OUT coincides with the rising edge 1124 of the delayed signal 1P0 because the fractional control circuit 214 has selected the delayed signal 1P0 at that point.

[0057] In this specification, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0058] Moreover, in this specification, the statement “based on” means “based at least in part on.” Thus, if X is based on Y, then X may depend on Y and any number of other factors.

[0059] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof.

[0060] As used herein, the terms "terminal", "node", "interconnect", "lead" and "pin" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnects between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0061] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0062] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A device comprising: a counter having a clock input, a count value input, a third input and an output; a multiplexer having a first input, a second input, a select input, and an output; a delay circuit having a first input, a second input, a first output, and a second output, the first input being coupled to the clock input of the counter, the second input being coupled to the output of the counter, the first output being coupled to the first input of the multiplexer, and the second output being coupled to the second input of the multiplexer; as well as A fractional control circuit has a first output coupled to the select input of the multiplexer and has a second output coupled to the third input of the counter.

2. The apparatus of claim 1 , wherein the delay circuit is configured to: generating a first signal at the first output by delaying the signal at the output of the counter based on a falling edge of a clock signal at the clock input; and A second signal is generated at the second output by delaying the signal at the output of the counter based on a rising edge of the clock signal.

3. The apparatus according to claim 1, wherein: The multiplexer has a third input; and The delay circuit has a third output coupled to the third input.

4. The apparatus of claim 3, wherein the delay circuit is configured to: generating a first signal at the first output by delaying the signal at the output of the counter based on a rising edge of a clock signal at the clock input; generating a second signal at the second output by delaying the signal at the output of the counter based on a first falling edge of the clock signal; and A third signal is generated at the third output by delaying the signal at the output of the counter based on a second falling edge of the clock signal.

5. The apparatus of claim 1, wherein the counter comprises a ripple counter.

6. The apparatus of claim 5, wherein the multiplexer is a first multiplexer, the ripple counter has an output comprising a bit, the bit comprising a first bit, and wherein the counter comprises: a second multiplexer having a first input, a second input, and an output, the first input of the second multiplexer being configured to receive the first bit, and the second input of the second multiplexer being configured to receive a logical inversion of the first bit; a first logic gate having an input coupled to the output of the second multiplexer and having an output; as well as A second logic gate has an input coupled to the output of the first logic gate.

7. The apparatus of claim 1, wherein: The fractional control circuit has a first input, a second input, and a third input, and the fractional control circuit is configured to receive an output clock at the first input, a least significant bit of a divide value at the second input, and an enable fractional divide signal at the third input; and The counter is configured to receive bits of the partition value other than the least significant bit at the count value input.

8. The apparatus of claim 7 , further comprising a flip-flop having a clock input and an output, the clock input of the flip-flop being configured to receive the output clock, and wherein the fractional control circuit has a fourth input coupled to the output of the flip-flop, the fractional control circuit being configured to generate a select signal at the first output based on the output clock, a signal from the flip-flop at the fourth input, the least significant bit, and the enable fractional division signal.

9. A device comprising: a counter having a clock input, a count value input, an enable offset input, and an output; a synchronizer having a first input, a second input, a third input, and an output, the first input being coupled to the clock input and the second input being coupled to the output of the counter; as well as a fractional control circuit having a fractional control input and an output, the output of the fractional control circuit being coupled to the third input of the synchronizer, the fractional control circuit being configured to program a delay of the synchronizer based on a signal at the fractional control input and an output clock signal from the device.

10. The apparatus of claim 9, wherein the fraction control circuit has a second input configured to receive a least significant bit of a partition value, and wherein the counter is configured to receive bits of the partition value other than the least significant bit of the partition value at the count value input.

11. The apparatus of claim 9, wherein the synchronizer comprises a multiplexer having a select input coupled to the third input.

12. The apparatus of claim 11, wherein the multiplexer has a first input and a second input, and the synchronizer comprises a delay circuit having a first delayed output and a second delayed output, the first delayed output coupled to the first input of the multiplexer, and the second delayed output coupled to the second input of the multiplexer.

13. The apparatus of claim 11 , wherein the multiplexer has a first input, a second input, and a third input, and the synchronizer comprises a delay circuit having a first delayed output, a second delayed output, and a third delayed output, the first delayed output coupled to the first input of the multiplexer, the second delayed output coupled to the second input of the multiplexer, and the third delayed output coupled to the third input of the multiplexer.

14. The apparatus of claim 9, wherein the counter comprises a ripple counter.

15. The apparatus of claim 9, wherein: The output of the fractional control circuit is a first output and the fractional control circuit has a second output; and The counter includes a ripple counter having an output and a first circuit having an input coupled to a corresponding output of the ripple counter, the first circuit having a fractional control input coupled to the second output of the fractional control circuit.

16. An apparatus comprising: a resonator having an output; a counter having a clock input, a count value input, an enable offset input, and an output, the clock input being coupled to the output of the resonator; a multiplexer having a first input, a second input, a third input, a select input, and an output; a delay circuit having an input coupled to the clock input of the counter and having a first output coupled to the first input of the multiplexer, a second output coupled to the second input of the multiplexer, and a third output coupled to the third input of the multiplexer; as well as A fractional control circuit has a control output coupled to the select input of the multiplexer and has an enable offset output coupled to the enable offset input of the counter.

17. The apparatus of claim 16, wherein the resonator is a bulk acoustic wave (BAW) resonator.

18. The apparatus of claim 16, wherein the counter comprises a ripple counter.

19. The apparatus of claim 16, wherein: The fraction control circuit has an input configured to receive a least significant bit of a partition value; and The counter is configured to receive bits of the partition value other than the least significant bit at the count value input.

20. The apparatus of claim 19, wherein the input of the fractional control circuit is a first input, the fractional control circuit having a second input configured to receive an output clock and a third input configured to receive an enable fractional division signal, and the fractional control circuit is configured to generate a signal at the control output based on the output clock, the least significant bit, and the enable fractional division signal.

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