Scan mode of asynchronous counter
By introducing an asynchronous counter test stage into the integrated circuit and using existing hardware for data comparison in scan mode, the problem of the inability to test asynchronous counters in the prior art is solved, achieving efficient asynchronous counter testing and reducing costs and time.
CN122159860APending Publication Date: 2026-06-05RENESAS DESIGN AUSTRIA GMBH
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Patent Information
- Application Number
- CN202511819447.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-12-05
- Filing Date
- 2025-12-04
- Publication Date
- 2026-06-05
AI Technical Summary
Technical Problem
The inability to effectively test asynchronous counters in existing integrated circuits increases the risk of delivering defective integrated circuits, and adding special test hardware increases chip area and complexity.
Method used
An asynchronous counter test stage is introduced into the integrated circuit. The test data stored in the shift register is compared with the count data in the asynchronous counter in scan mode by a comparator. The test is performed using the existing shift register and asynchronous counter hardware, avoiding the addition of additional hardware.
Benefits of technology
It enables the effective testing of asynchronous counters without increasing chip area and complexity, saving testing time and reducing manufacturing costs.
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Smart Images
Figure CN122159860A_ABST
Abstract
An integrated circuit is provided for processing data in a functional mode and testing the integrated circuit in a scan mode. The integrated circuit comprises a processing unit, a digital function block, an asynchronous counter, an asynchronous counter test stage, a comparator. The processing unit is configured to process and store data in the functional mode of the integrated circuit based on a system clock. The digital function block is implemented by registers and N scan flip-flops, each of which is connected to the system clock. The asynchronous counter is implemented by M flip-flops connected in a chain. The asynchronous counter test stage is configured to reset count data and store test data in the digital function block in preparation for testing the asynchronous counter in a scan mode of the asynchronous counter.
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