Offset compensated analog-to-digital converter

Abstract

The invention relates to an offset compensated analog-to-digital converter. An oversampled analog-to-digital converter (ADC) may include a quantizer that adds an offset error to each oversampled sample. If not, the offset error may limit the performance of the ADC. Existing methods of eliminating offsets may increase circuit size and slow ADC operation. An oversampling ADC that can reduce or remove offset errors is disclosed. The disclosed ADCs may be small and fast, and still remove offsets. Thus, the disclosed ADCs can be used in high performance applications, such as high speed image sensors.

Description

Technical Field

[0001] The present disclosure relates to analog-to-digital converters (ADCs), and more particularly to an oversampling ADC with logic and circuitry to reduce offset voltage. Background Art

[0002] Σ-Δ ADCs can provide higher resolution and lower noise than other ADC types because they utilize oversampling. Oversampling involves sampling the input signal at a higher frequency than required (i.e., the Nyquist frequency) to obtain a sample stream, and then filtering and downsampling (i.e., decimating) the sample stream to generate output samples at the output of the Σ-Δ ADC. Summary of the invention

[0003] Generating (oversampling) sample streams may include comparators with voltage offsets (i.e., input offset voltages) that may produce error sample streams that may reduce the accuracy of the ADC. An ADC configured to compensate for the offset voltage is needed in order to improve the accuracy of the output samples. The disclosed Σ-Δ ADC may use methods and circuitry that are smaller and faster than other methods to compensate for the offset voltage.

[0004] In some aspects, the technology described herein relates to a method for compensating for an offset voltage in a Σ-Δ ADC, the method comprising: replacing an input voltage of a first conversion in a set of conversions at an input of the Σ-Δ ADC with a reference voltage; quantizing the reference voltage at a quantizer of the Σ-Δ ADC to obtain a virtual sample, the virtual sample including an offset voltage added by the quantizer of the Σ-Δ ADC; decoupling a decimation filter of the Σ-Δ ADC; generating a feedback voltage corresponding to the virtual sample, the feedback voltage including an offset voltage; inverting the feedback voltage to generate an inverted feedback voltage; applying the inverted feedback voltage to an integrator of the Σ-Δ ADC, the inverted feedback voltage including an inverted offset voltage; and storing the inverted offset voltage in the integrator to generate an offset charge integrator.

[0005] In some aspects, the technology described herein relates to a method for compensating for offset error in a Σ-Δ ADC: performing a set of conversions to generate output samples, wherein for a first conversion in the set of conversions, the method includes: replacing an input voltage at an input terminal of the Σ-Δ ADC with a reference voltage; bypassing an integrator of the Σ-Δ ADC; quantizing the reference voltage at a quantizer of the Σ-Δ ADC to obtain virtual samples, the virtual samples including an offset error added by the quantizer of the Σ-Δ ADC; and applying the virtual samples to a decimation filter configured to store the offset error to generate an offset compensated decimation filter, the offset compensated decimation filter being configured to subtract the offset error added by the quantizer of the Σ-Δ ADC for conversions other than the first conversion in the set of conversions.

[0006] In some aspects, the technology described herein relates to a Σ-Δ ADC, which includes: a Σ-Δ modulator, the Σ-Δ modulator including: an integrator, the integrator configured to store a difference between an input voltage and a feedback voltage; and a quantizer, the quantizer configured to generate oversampled samples based on an integrator output voltage of the integrator, the oversampled samples including an offset error; a decimation filter, the decimation filter coupled to the output of the Σ-Δ modulator and configured to receive the oversampled samples from the quantizer; and control logic, the control logic configured by instructions and / or logic circuitry to: configure the Σ-Δ modulator to perform a set of conversions to generate output samples; for a first conversion in the set of conversions, replace the input voltage with a zero voltage; and for a first conversion in the set of conversions, decouple the decimation filter from the quantizer so that the feedback voltage from the output of the quantizer is an offset voltage corresponding to the offset error, the offset voltage being stored in the integrator.

[0007] In some aspects, the technology described herein relates to a sigma-delta ADC comprising: a sigma-delta modulator, the sigma-delta modulator comprising: an integrator configured to store a difference between an input voltage and a feedback voltage; a quantizer configured to generate oversampled samples based on an integrator output voltage, the oversampled samples including an offset error; and a digital-to-analog converter in a feedback loop of the sigma-delta modulator, the digital-to-analog converter configured to convert the oversampled samples to the feedback voltage; a decimation filter coupled to an output of the sigma-delta modulator and configured to receive the oversampled samples from the quantizer; and control logic configured by instructions and / or logic circuitry to: configure the sigma-delta modulator to perform a set of conversions; for a first conversion in the set of conversions, replace the input voltage with a zero voltage; for a first conversion in the set of conversions, bypass the integrator so that the quantizer generates a virtual sample based on the zero voltage, the virtual sample including an offset error; and configure the decimation filter to store the offset error to compensate for the offset error added by the quantizer during subsequent conversions in the set of conversions.

[0008] The foregoing illustrative summary, as well as other exemplary objects and / or advantages of the present disclosure, and implementations are further explained in the following detailed description and its accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a schematic diagram of an image processor according to a specific implementation of the present disclosure.

[0010] Figure 2 is a system block diagram of an ADC according to a possible implementation of the present disclosure.

[0011] Figure 3A sigma-delta modulator for an ADC according to a possible implementation of the present disclosure is schematically shown.

[0012] Figure 4 The operation of a decimation filter for an ADC according to a possible implementation of the present disclosure is shown.

[0013] Figure 5 is a flow chart of a method of generating an offset charge integrator to compensate for an offset voltage according to a possible implementation of the present disclosure.

[0014] Figure 6 is a flow chart of a method of generating output samples with an offset charge integrator according to a possible implementation of the present disclosure.

[0015] Figure 7 is a flow chart of a method of generating an offset compensation decimation filter to compensate for an offset voltage according to a possible implementation of the present disclosure.

[0016] Figure 8 is a flowchart of a method for generating output samples using an offset compensated decimation filter according to a possible implementation of the present disclosure.

[0017] The components in the drawings are not necessarily drawn to scale relative to each other. Like reference numerals indicate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION

[0018] A Σ-Δ ADC (i.e., Δ-Σ ADC) is an oversampling ADC. The number of oversampled samples for one output sample is referred to as the oversampling rate (OSR). A high OSR can provide output samples with higher resolution (i.e., bit depth) and higher signal-to-noise ratio (SNR). However, a high OSR may result in a decrease in the speed of the Σ-Δ ADC due to the increased number of oversampled samples per output sample. An oversampling ADC is needed that has a resolution and SNR suitable for high dynamic range signals of an image sensor (e.g., 150 dB for a single exposure) and is also fast enough to handle the frame rate required for image sensing (e.g., 60 frames per second). In addition, a smaller circuit size may be advantageous for image sensors having multiple columns (e.g., 2000 columns in a 3 megapixel display and 3200 columns in an 8 megapixel display), each of which requires an ADC. The disclosed Σ-Δ ADC can provide these advantages and can be used in high-speed applications, such as image sensors.

[0019] Figure 11 is a schematic block diagram of an image sensor according to a possible specific implementation of the present disclosure. Image sensor 100 includes a pixel array 101, which includes rows and columns of pixels. Each pixel can be configured to store a charge (i.e., a voltage) based on the amount of light collected by the pixel. The pixels in pixel array 101 can be addressed (e.g., read) according to their row / column positions to couple the charge stored by the pixel to the column. For example, row driver 110 can configure each pixel in a pixel row to couple its charge to the column. Read circuit system 120 for each column can convert the charge into a column voltage, which can be received by an ADC for each column (i.e., column ADC). Column ADC 130 is configured to convert the voltage into a digital signal, which can then be buffered by memory 140 and transferred to another device (e.g., a processor) using register transfer logic 150.

[0020] Due to the high frame rate of the image sensor 100, the voltage for the pixel (i.e., the pixel voltage) will not change significantly during the conversion performed by the column ADC. Therefore, the pixel voltage (i.e., the input voltage) can be regarded as a DC input voltage to the ADC. The ADC can convert this DC voltage (i.e., Vin) to output samples (i.e., Q(Vin)) row by row (in a time multiplexed manner). Therefore, the ADC for each column can be an incremental oversampling ADC that can be reset to an initial state after the pixel voltage of each row is converted to an output sample.

[0021] Variations in the column ADCs may generate artifacts in the sensed image. For example, if the ADCs of a pair of columns have different responses (i.e., different ADC codes) for the same intensity (i.e., input voltage (Vin)), visible artifacts may appear in the image produced by the image sensor 100. For example, a flat intensity image may have vertical lines corresponding to the differences in the ADCs for each row. Therefore, it may be desirable to reduce or eliminate variations between ADCs.

[0022] One source of variation between ADCs results from an offset voltage (i.e., offset) added by an oversampled ADC during analog-to-digital conversion. Offset can be defined as a non-zero ADC code resulting from a conversion of an input voltage equal to zero (i.e., zero voltage). Offset can be caused by manufacturing variations (i.e., process corners) in circuit components. Mitigating offset variation by design can result in larger circuit area, which is not ideal for analog-to-digital converters. Figure 1 This may not be desirable for the application of the image sensor shown.

[0023] Various techniques can be used to reduce the offset in an oversampled ADC. For example, the offset can be reduced by a technique called digital correlated double sampling (DCDS), in which a zero input is converted to obtain a sample of the offset for the ADC (i.e., an offset sample). The offset sample can then be subtracted from subsequent samples to eliminate the offset. A technical problem with offset elimination by DCDS is that it is time consuming. The slow response of DCDS becomes worse in an oversampled ADC, which has a throughput that is negatively correlated with the OSR.

[0024] The offset can also be reduced by a technique called chopper stabilization, in which the input voltage is modulated so that the offset can be filtered. Figure 1 For applications of the image sensor shown, the required circuitry may be too complex and / or too large.

[0025] The disclosed technology is well suited for Figure 1 image sensor shown because it can reduce or eliminate offset in the oversampled ADC faster than DCDS and with lower complexity than chopper stabilization.

[0026] Figure 2 is a system block diagram of an oversampling ADC 200 according to a possible implementation of the present disclosure. The ADC 200 includes a sigma-delta modulator 300 (i.e., a delta-sigma modulator) configured to receive an input voltage Vin at an input terminal of the ADC 200. The ADC 200 also includes a decimation filter 400 (e.g., an accumulator) configured to receive oversampled samples from the sigma-delta modulator 300. The decimation filter 400 is also configured to output output samples at an output terminal of the ADC 200.

[0027] The input voltage Vin is an analog signal, and the output samples Q(Vin) are N-bit digital numbers (e.g., digital words, digital codes) corresponding to the relative levels of the input voltage within the dynamic range of the ADC. The resolution of the digital representation is related to the least significant bit (LSB), which is the dynamic range divided by the number of bits in the digital word (N).

[0028] The Σ-Δ modulator 300 is configured to encode the input signal Vin into a low bit depth (e.g., 1 bit) bit stream. The bit stream can be fed back to the input as negative feedback to correct quantization errors and shape (i.e., shift) noise (e.g., quantization noise) to higher frequencies. The bit stream is also low-pass filtered by a decimation filter 400 to remove its high frequency noise, and the bit stream is averaged over time to achieve a high-precision (N-bit) measurement of the amplitude of the input signal.

[0029] The decimation filter 400 outputs the output samples at a higher resolution (bit depth) than the resolution of each oversampled sample. For example, each oversampled sample can be a 1-bit sample that is high (e.g., 1) or low (e.g., 0) based on the error signal between the input Vin and the negative (i.e., inverted) feedback signal. Therefore, the decimation filter 400 can be configured to accumulate the oversampled samples to generate a higher resolution (N-bit) signal at the end of a set of oversampled conversions.

[0030] The output sample Q(Vin) is generated based on the number of oversampled samples (i.e., OSR). Therefore, the sigma-delta modulator 300 can be configured to perform oversampled conversions (i.e., conversions) at a rate (OSR·fs) that is higher than the rate (fs) at which the output samples are generated. In other words, a set of conversions can be performed to generate one output sample. For example, multiple conversions can be performed by the sigma-delta modulator 300 from the decimation filter 400.

[0031] ADC 200 also includes control logic 230. Control logic 230 may include a controller, processor, and / or logic circuitry (such as logic gates, registers, etc.) that manages the flow and operation of the oversampling conversion process. For example, control logic 230 may generate a rate (fs) per output sample to couple the input signal to Σ-Δ modulator 300 (i.e., sample the input signal). Control logic 230 may be configured by instructions (e.g., programming code) and / or logic circuitry to perform a method of generating output samples based on an input voltage. In particular, the method may include the step of compensating for an offset voltage generated by the circuitry in ADC 200.

[0032] The ADC 200 may be implemented as an incremental sigma-delta ADC, wherein the storage elements of the sigma-delta modulator 300 and / or the decimation filter 400 are reset (i.e., cleared) after each output sample is generated. Thus, the control logic 230 may be configured to transmit a reset signal (RST) to the sigma-delta modulator 300 and / or the decimation filter 400 before starting a new set of oversampled conversions.

[0033] Figure 3 A sigma-delta modulator 300 according to a possible implementation of the present disclosure is shown. The sigma-delta modulator 300 includes a summer 305 configured to invert a feedback voltage (Vdac) generated by a digital-to-analog converter 310 based on the latest oversampled sample (dADC). The summer 305 is also configured to sum the inverted feedback voltage with the input voltage to generate a residual voltage (Vres). In other words, the residual voltage Vres is the difference between the input voltage Vin and the feedback voltage Vdac.

[0034] The sigma-delta modulator 300 also includes an integration stage (i.e., integrator 315). Only one integrator is shown because the sigma-delta modulator 300 is first order, but the disclosed techniques can be used with higher order ADCs. Integrator 315 is configured to integrate (i.e., store) the residual voltage. Therefore, the integrator may include a storage element, such as a capacitor, to store the residual voltage. The integrator may be reset after a set of conversions by draining charge from the capacitor. Each conversion in a set of conversions for oversampling may include a residual signal passing through integrator 315. In other words, each conversion may be one feedback loop iteration. The output voltage of the integrator or the integrator output voltage is Figure 3 Shown as Vint.

[0035] The storage quality of the integrator 315 allows the voltage stored by the integrator 315 at the first conversion to have an effect on each subsequent conversion in a set of conversions for oversampling (i.e., OSR conversions). Thus, the first conversion in a set of conversions can be used to initialize certain voltages for the remaining conversions in the oversampling set. As shown, a substrate voltage based on a substrate signal (dpedestal) can be added as negative feedback to the first conversion in order to bias (i.e., boost) the negative input voltage to the positive input voltage. Because the substrate voltage is stored in the integrator, this injection of the substrate signal dpedestal (which includes decoupling the output from the feedback) can only occur at the beginning of a set of oversampling conversions.

[0036] The Σ-Δ modulator 300 also includes a quantizer 320 configured to digitize the integrated signal. As shown, the quantizer 320 can be configured to generate a digital 1-bit oversampled sample dADC based on the integrator output voltage Vint, which is transmitted to the quantizer 320 by the integrator 315. As shown in the illustration 330, the quantizer 320 can be implemented as a comparator 331. The comparator 331 is configured to compare the integrator output voltage Vint with a threshold value and output a high voltage or a low voltage corresponding to the 1-bit digital signal based on the comparison result. Undesirably, the comparator 331 can add an offset voltage Voff to the integrator output voltage Vint. For some values, the offset may prevent the quantizer 320 from accurately digitizing the integrator output voltage Vint. In other words, due to the offset, the conversion may include an offset error.

[0037] The sigma-delta modulator 300 disclosed herein can measure an offset voltage Voff added by the quantizer 320 to a first oversampled conversion in a set of oversampled conversions. The offset voltage Voff can then be stored in the integrator 315 (e.g., as a charged capacitor) to form an offset charge integrator. The offset charge integrator is then configured with a voltage to compensate for (e.g., cancel) the offset voltage Voff added by the quantizer 320 in subsequent conversions in the set of oversampled conversions.

[0038] The first sample generated by the first conversion may not be coupled to the decimation filter 400 and therefore not accumulated as part of the output samples. Therefore, in this implementation, the first sample may be referred to as a virtual sample because its purpose is to measure and store the offset. Samples other than the first sample (i.e., subsequent samples) may be referred to as oversampled samples because they are accumulated by the decimation filter 400 to generate the output samples.

[0039] Figure 4 The operation of a decimation filter 400 for an ADC according to a possible implementation of the present disclosure is shown. As shown, the decimation filter 400 receives oversampled samples at its input and transmits output samples at its output. The oversampled samples have a lower resolution (i.e., bit depth) than the output samples. For example, the oversampled samples may form a digital bit stream.

[0040] The oversampled samples can be grouped into conversion groups corresponding to output samples. As shown, the first group of conversions (CONV_1) corresponds to the first output sample (SAMP_1), and the second group of conversions (CONV_2) corresponds to the second output sample (SAMP_2). The first conversion in each group of conversions produces a virtual sample. For example, the first conversion of the second group CONV_2 is a virtual sample 410, and all subsequent conversions of the second group CONV_2 are oversampled samples 420. The virtual sample is not coupled to the decimation filter 400. The virtual sample is used to generate an offset charge integrator. The subsequent conversions in each group of conversions produce oversampled samples. The oversampled samples are coupled to the decimation filter 400. The output sample may correspond to a plurality of oversampled samples accumulated at the decimation filter. In this way, output samples such as SAMP_1 and SAMP_2 are output at a frequency lower than the oversampled conversion.

[0041] The first conversion (i.e., virtual sample) is used to compensate for the offset voltage associated with each subsequent conversion (i.e., oversampled sample). Therefore, when the output sample is delayed by the additional virtual sample, the output sample may have little or no offset error. Because the rate of oversampled conversions can be fast, this delay can be relatively small (e.g., 350 nanoseconds).

[0042] This offset reduction technique is very general and can be combined with other techniques to improve performance. For example, increasing the number (OSR) can increase the resolution of the output samples, but may limit the speed of the ADC. Additionally or alternatively, a successive approximation register (SAR) can be used in the oversampling loop of the ADC to increase the resolution of the oversampled ADC without increasing its OSR. SAR uses a binary search algorithm and a capacitor bank to determine the bits used for the ADC. Thus, the disclosed ADC can utilize a SAR conversion algorithm that is well suited for high resolution image sensors, such as Figure 1 shown.

[0043] Figure 5 Flowchart of a method for generating an offset charge integrator to compensate for an offset voltage in a sigma-delta ADC. The method 500 is performed for (eg, only for) a first conversion in a set of conversions for generating an output sample. In other words, the method 500 is performed for a first conversion 505 corresponding to a virtual sample.

[0044] The method 500 may include resetting 515 an integrator of the sigma-delta modulator so that it is not charged by an offset from a previous output sample. Other circuitry may also be reset, such as a decimation filter. For example, a value stored in a decimation filter may be reset (e.g., to zero) so that oversampled samples accumulated for any previous output sample are not included in the accumulator along with oversampled samples from the current output sample.

[0045] The method 500 also includes replacing 520 the input voltage Vin with a reference voltage. The reference voltage may be zero volts or a zero voltage, or may be a non-zero voltage. The replacing step may include controlling one or more switches to decouple the input voltage from the input of the sigma-delta modulator. The replacing step may also include controlling one or more switches to couple the input of the sigma-delta modulator to ground or a reference voltage.

[0046] In a possible implementation, the method 500 further includes adding 530 a base level to the reference voltage. Figure 3 As shown, the pedestal level (i.e., dpedestal) can be a digital signal of the digital-to-analog converter 310 applied to the feedback loop of the sigma-delta modulator 300 so that it can be combined with the reference voltage at the input of the sigma-delta modulator 300 and stored in the integrator 315. In other words, the offset charge integrator can also store the pedestal level. Resetting the integrator 515 can also clear the pedestal value from the integrator. Therefore, the pedestal level can be added once for each output sample (e.g., during a dummy sample conversion).

[0047] The method 500 further includes quantizing 540 the reference voltage to obtain a virtual sample. Quantization includes digitizing the reference voltage. Figure 4As shown, the virtual sample corresponds to the first conversion in a set of conversions for the output sample, and each output sample has a corresponding virtual sample. The virtual sample is a conversion for sensing (e.g., measuring) an offset voltage. Therefore, the virtual sample can be a digital value (dADC) representing the offset voltage added by the quantizer 320 of the Σ-Δ ADC. However, the digital value of the virtual sample does not represent the input voltage because the input voltage is replaced by a reference voltage (e.g., zero volts) for the virtual sample conversion. Therefore, the virtual sample is not accumulated to determine the output sample. Therefore, the method 500 also includes decoupling 550 the decimation filter 400 so that the virtual sample is not received by the decimation filter of the Σ-Δ ADC. In some specific implementations, the decoupling 550 step can be performed at any time earlier in the process.

[0048] The method 500 also includes generating 560 a feedback voltage (Vdac) based on the virtual samples. The feedback voltage (Vdac) is an analog voltage converted from the virtual samples by the digital-to-analog converter 310 in the feedback loop of the sigma-delta modulator 300. The feedback voltage includes an offset voltage corresponding to an offset error added by the quantizer 320. The feedback voltage (Vdac) also includes a quantization voltage corresponding to a quantization error added by the digital-to-analog converter 310.

[0049] The method 500 also includes inverting 570 the feedback voltage to generate an inverted feedback voltage (-Vdac). The inverted feedback voltage (-Vdac) includes an inverted offset voltage (-Voffset).

[0050] The method 500 also includes storing 580 the inverted offset voltage (-Vdac) in the integrator 315 to generate an offset charge integrator 590. The offset charge integrator 590 is configured to add the inverted offset voltage (-Voffset) to the output (Vint) of the integrator. The offset charge integrator adds the inverted offset voltage (-Voffset) to compensate for (i.e., cancel, negate, zero) the offset voltage (+Voffset) added by the quantizer in a subsequent conversion. After the offset charge integrator is generated, a method for generating oversampled samples using the offset charge integrator may be initiated (see Figure 6 ).

[0051] Figure 6 6 is a flow chart of a method for generating output samples with an offset charge integrator according to a possible implementation of the present disclosure. The method 600 is performed for (e.g., only for) conversions other than the first conversion in the set of conversions (i.e., after the first conversion). In other words, the method 600 is performed for subsequent conversions 605 corresponding to oversampled (i.e., OS) samples.

[0052] The method 600 includes recoupling 610 the decimation filter 400 to the output of the sigma-delta modulator 300 so that each oversampled sample following the virtual sample may be accumulated by the decimation filter.

[0053] The method 600 also includes receiving 615 an input voltage Vin at an input of the ADC. The input voltage is combined with negative feedback from an output of the quantizer 320. For example, a summing circuit (e.g., summer 305) may add the input voltage (Vin) to an inverted feedback voltage (-Vdac). In other words, the method 600 includes applying 620 the difference between the input voltage and the feedback voltage (i.e., Vin-Vdac) to an offset charge integrator.

[0054] The method 600 also includes quantizing 630 the output of the offset charge integrator (i.e., the integrator output) to generate an oversampled sample (i.e., the OS sample). The OS sample may have a smaller offset error (e.g., no offset error) because the inverted offset voltage stored in the offset charge integrator cancels the (non-inverted) offset voltage added by the quantizer 320.

[0055] The method 600 also includes applying 635 the OS samples to a decimation filter 400 configured to accumulate the OS samples as they are generated over iterations of the oversampled conversions in the set of conversions.

[0056] The method 600 may be repeated 640 times (OSR) iterations in the set of conversions to generate a time series of OS samples. The sequence of OS samples may be filtered and downsampled by the decimation filter 400 to generate output samples 650 after an OSRth conversion.

[0057] After method 600 has generated output sample 650, the method of generating an offset charge integrator may be restarted for a subsequent (next) output sample (see Figure 5 ). In other words, after output samples have been generated by a first set of transformations, a second set of transformations may begin generating a second output sample, and so on.

[0058] Compensation for the offset added by the quantizer can be performed in the analog domain, such as described so far, where the integrator of the sigma-delta modulator acts as a means for storing an analog voltage corresponding to the offset. In this specific implementation, an inverted offset voltage is stored in the integrator and added at the input of the quantizer to cancel the (non-inverted) offset added by the quantizer.

[0059] In an alternative implementation, compensation for the offset may be performed in the digital domain. In this implementation, the digital offset error is stored in a decimation filter (e.g., an accumulator) in a first conversion. In a subsequent conversion, the decimator is configured to subtract the stored offset error from the output of the quantizer in order to cancel the offset error added by the quantizer.

[0060] Figure 7 7 is a flow chart of a method for generating an offset compensation decimation filter to compensate for offset errors in a Σ-Δ ADC. The method 700 is performed for (eg, only for) a first conversion in a set of conversions for generating an output sample. In other words, the method 700 is performed for a first conversion 705 corresponding to a virtual sample.

[0061] The method 700 includes resetting 715 the decimation filter 400. The decimation filter 400 may be reset by clearing the value stored in the decimation filter 400 so that oversampled samples accumulated for a previous output sample are not included with the oversampled samples from the current output sample. Other circuitry may also be reset, for example, the integrator 315 of the sigma-delta modulator may be reset so that it is not charged by an offset or other signal (e.g., floor, quantization error, etc.) from any previous output sample.

[0062] The method 700 also includes replacing 720 the input voltage (i.e., Vin) with a reference voltage. The reference voltage may be zero volts or a zero voltage, or may be a non-zero voltage. The replacing step may include controlling one or more switches to decouple the input voltage from the input of the sigma-delta modulator. The replacing step may also include controlling one or more switches to couple the input of the sigma-delta modulator to ground or a reference voltage.

[0063] The method 700 also includes adding 730 the base level to zero voltage. Figure 3 As shown, the pedestal level (ie, dpedestal) may be a digital signal of the digital-to-analog converter 310 applied to the feedback loop of the sigma-delta modulator 300 so that it may be combined with a reference voltage at the input of the sigma-delta modulator 300 .

[0064] The method 700 also includes bypassing 740 the integrator 315 to prevent it from storing the reference voltage and the substrate level. Bypassing 740 the integrator may include passing the reference voltage and the substrate level through the integrator, but not storing these voltages. Alternatively, bypassing the integrator may include disabling the functionality of the integrator and / or routing the signal in a path (e.g., a short circuit) around the integrator 315 so that the reference voltage and / or the substrate voltage are not stored in the integrator 315. Disabling the functionality of the integrator may advantageously save power that would otherwise be used by the integrator during the (first) conversion corresponding to the dummy sample.

[0065] The method 700 also includes quantizing 750 the reference voltage and the floor level to obtain a virtual sample. Thus, the virtual sample is a digital value (dADC) representing the offset error added by the quantizer 320 of the Σ-Δ ADC. The digital value (dADC) of the virtual sample does not include the input voltage because the input voltage is replaced by the reference voltage converted by the virtual sample. Thus, the virtual sample may correspond to (e.g., be equal to) the offset error.

[0066] The method 700 also includes applying 760 the virtual samples (dADC) to the decimation filter 400. In other words, the decimation filter 400 can be configured to store the offset error added by the quantizer 320. The decimation filter 400 is not decoupled from the signal path during the virtual samples because, in this implementation, the decimation filter 400 is used as a storage element. Therefore, the method 700 also includes storing 770 the offset error to generate an offset compensated decimation filter 780. The offset compensated decimation filter is configured to use the stored offset error to compensate (e.g., cancel) the offset error added by the quantizer during a subsequent conversion. For using the offset compensated decimation filter (see Figure 8 )The method of generating oversampled samples can begin after generating the offset compensation decimation filter.

[0067] Figure 8 is a flow chart of a method for generating output samples using an offset compensated decimation filter according to a possible implementation of the present disclosure.

[0068] The method 800 is performed for (e.g., only for) the conversions in the set of conversions except for the first conversion. In other words, the method 800 is performed for all conversions in the set of conversions except for the first conversion. In other words, the method 800 is performed for subsequent conversions 805 corresponding to the oversampled samples. After the first conversion, the method 800 includes converting the virtual sample process (e.g., see Figure 7 , step 740) is restored 807 (ie, reactivated, recoupled) to the ADC.

[0069] The method 800 includes receiving 815 an input voltage (Vin) at an input of the ADC. The input voltage is combined with negative feedback from an output of the quantizer 320. For example, a summing circuit (ie, summer 305) may add the input voltage (Vin) to an inverting feedback voltage (-Vdac).

[0070] The method 800 also includes applying 820 the difference of the input voltage and the feedback voltage to an integrator to generate an integrator output at an output terminal of the integrator 315 .

[0071] The method 800 also includes applying 830 (i.e., inputting, transmitting, etc.) the integrator output to a quantizer to generate oversampled samples. The oversampled samples include an offset error added by the quantizer. Therefore, the method 800 also includes applying 835 the oversampled samples to an offset compensation decimation filter. The offset compensation decimation filter is configured to reduce (e.g., remove) the offset error from the oversampled samples to generate offset-corrected oversampled samples.

[0072] The method 800 also includes accumulating the offset-corrected oversampled samples in the offset compensation decimation filter until an OSR number of oversampled samples in a set of conversions are accumulated. Thus, the method 800 may be repeated 840 times (OSR) iterations in the set of conversions to generate a time sequence of OS samples. The sequence of OS samples may be filtered and downsampled by the decimation filter 400 to generate output samples 850 after the OSRth conversion.

[0073] After method 800 has generated output sample 850, generation of the offset compensation decimation filter may be restarted for the subsequent (next) output sample (see Figure 7 In other words, after output samples have been generated by a first set of transformations, a second set of transformations may begin generating a second output sample, and so on.

[0074] Hereinafter, some embodiments of the present disclosure are described.

[0075] Embodiment 1 A method for compensating for an offset voltage in a Σ-Δ ADC, the method comprising: replacing an input voltage of a first conversion in a set of conversions at an input end of the Σ-Δ ADC with a reference voltage; quantizing the reference voltage at a quantizer of the Σ-Δ ADC to obtain a virtual sample, the virtual sample comprising the offset voltage added by the quantizer of the Σ-Δ ADC; decoupling a decimation filter of the Σ-Δ ADC; generating a feedback voltage corresponding to the virtual sample, the feedback voltage comprising the offset voltage; inverting the feedback voltage to generate an inverted feedback voltage; applying the inverted feedback voltage to an integrator of the Σ-Δ ADC, the inverted feedback voltage comprising an inverted offset voltage; and storing the inverted offset voltage in the integrator to generate an offset charge integrator.

[0076] Embodiment 2 is a method according to embodiment 1, wherein: the group conversion is performed to generate output samples; and for conversions in the group conversion other than the first conversion, the inverted offset voltage added by the offset charge integrator cancels the offset voltage added by the quantizer while generating the output samples.

[0077] Embodiment 3 The method according to Embodiment 2, wherein the group of conversions is a first group of conversions and the output samples are first output samples, and wherein after performing the first group of conversions to generate the first output samples, the method further includes: resetting the offset charge integrator by clearing the inverting offset voltage before starting a second group of conversions to generate a second output sample; and generating a second offset charge integrator for the second group of conversions.

[0078] Embodiment 4 is a method according to embodiment 3, wherein performing the group conversion to generate the output samples also includes: receiving the input voltage at the input end of the Σ-Δ ADC; applying the input voltage to the offset charge integrator; applying the integrator output of the offset charge integrator to the quantizer, the integrator output including the inverted offset voltage to eliminate the offset voltage added by the quantizer; generating oversampled samples, the oversampled samples having no offset error; and applying the oversampled samples to the decimation filter.

[0079] Embodiment 5 is a method according to any one of Embodiments 2 to 4, wherein: the first conversion in the group of conversions is the virtual sample that is not accumulated by the decimation filter; and the conversions in the group of conversions other than the first conversion are oversampled samples accumulated by the decimation filter.

[0080] Embodiment 6 The method according to embodiment 5, wherein: the anti-phase offset voltage stored in the integrator is based on the virtual sample and is not based on the oversampled sample.

[0081] Embodiment 7 The method according to embodiment 5 or 6 further includes: the output sample corresponding to the input voltage output at the output terminal of the decimation filter is based on the oversampled sample and not based on the virtual sample.

[0082] Embodiment 8 A method according to any one of the preceding embodiments, wherein for the first conversion in the group of conversions, the method further comprises: adding a base voltage to the reference voltage; and storing the base voltage together with the inverted offset voltage in the integrator.

[0083] Embodiment 9 The method according to Embodiment 8 further comprises: not adding the base voltage to transitions in the group of transitions other than the first transition.

[0084] Embodiment 10 A method according to any one of the preceding embodiments, wherein the reference voltage is zero volts.

[0085] Embodiment 11 A method for compensating for an offset error in a Σ-Δ ADC: performing a group of conversions to generate output samples, wherein for a first conversion in the group of conversions, the method comprises: replacing an input voltage at an input terminal of the Σ-Δ ADC with a reference voltage; bypassing an integrator of the Σ-Δ ADC; quantizing the reference voltage at a quantizer of the Σ-Δ ADC to obtain a virtual sample, the virtual sample comprising the offset error added by the quantizer of the Σ-Δ ADC; and applying the virtual sample to a decimation filter configured to store the offset error to generate an offset compensation decimation filter, the offset compensation decimation filter being configured to subtract the offset error added by the quantizer of the Σ-Δ ADC for conversions other than the first conversion in the group of conversions.

[0086] Embodiment 12 is a method according to embodiment 11, wherein the group of conversions is a first group of conversions and the output samples are first output samples, and wherein after performing the first group of conversions to generate the first output samples, the method further includes: resetting the offset compensation decimation filter by clearing the offset error before starting a second group of conversions to generate second output samples; and generating a second offset compensation decimation filter configured for the second group of conversions.

[0087] Embodiment 13 is a method according to embodiment 11 or 12, wherein performing the group conversion to generate the output samples also includes: receiving the input voltage and feedback voltage at the integrator; applying the integrator output to the quantizer to generate oversampled samples, the oversampled samples including the offset error added by the quantizer; applying the oversampled samples to the offset compensation decimation filter, the offset compensation decimation filter subtracting the offset error added by the quantizer from the oversampled samples; and accumulating the oversampled samples in the decimation filter, the decimation filter being configured to accumulate the oversampled samples generated by the conversions other than the first conversion.

[0088] Embodiment 14 is a method according to Embodiment 13, wherein: the first conversion in the group of conversions does not include the integrator for generating the virtual samples; and the conversions in the group of conversions other than the first conversion include the integrator to generate the oversampled samples.

[0089] Embodiment 15 The method according to embodiment 14 further includes: the output samples are based on the oversampled samples and are not based on the virtual samples.

[0090] Embodiment 16 The method according to any one of Embodiments 11 to 15, wherein the method further comprises: adding a substrate voltage as negative feedback to the input terminal of the Σ-Δ ADC at the beginning of each conversion in the group of conversions.

[0091] Embodiment 17 A Σ-Δ ADC comprises: a Σ-Δ modulator, the Σ-Δ modulator comprising: an integrator, the integrator being configured to store a difference between an input voltage and a feedback voltage; and a quantizer, the quantizer being configured to generate oversampled samples based on an integrator output voltage of the integrator, the oversampled samples comprising an offset error; a decimation filter, the decimation filter being coupled to an output of the Σ-Δ modulator and being configured to receive the oversampled samples from the quantizer; and control logic, the control logic being configured by instructions and / or a logic circuit system to: configure the Σ-Δ modulator to perform a set of conversions to generate output samples; for a first conversion in the set of conversions, replace the input voltage with a zero voltage; and for the first conversion in the set of conversions, decouple the decimation filter from the quantizer so that the feedback voltage from the output of the quantizer is an offset voltage corresponding to the offset error, the offset voltage being stored in the integrator.

[0092] Embodiment 18 is a Σ-Δ ADC according to Embodiment 17, wherein the control logic is further configured to: replace the zero voltage with the input voltage for a subsequent conversion in the group of conversions; and recouple the decimation filter to the output of the quantizer for the subsequent conversion, the decimation filter being configured to output output samples based on oversampled samples generated by the subsequent conversion.

[0093] Embodiment 19 is a Σ-Δ ADC according to Embodiment 17 or 18, wherein: the group of conversions is a first group of conversions and the output samples are first output samples, and the control logic is also configured by the instructions and / or the logic circuit system to: reset the offset voltage stored in the integrator after outputting the first output sample and before starting a second group of conversions.

[0094] Embodiment 20 is a Σ-Δ ADC according to any one of Embodiments 17 to 19, wherein the control logic is also configured by the instructions and / or the logic circuit system to: add a substrate voltage to the zero voltage during the first conversion in the group of conversions; and not add the substrate voltage to the input voltage during subsequent conversions after the first conversion in the group of conversions.

[0095] Embodiment 21 A Σ-Δ ADC according to any one of Embodiments 17 to 20, wherein: the first conversion in the group of conversions generates virtual samples, and the virtual samples are not accumulated by the decimation filter to generate output samples; and subsequent conversions after the first conversion in the group of conversions generate oversampled samples, and the oversampled samples are accumulated by the decimation filter to generate the output samples.

[0096] Embodiment 22 A Σ-Δ ADC comprises: a Σ-Δ modulator, the Σ-Δ modulator comprising: an integrator, the integrator being configured to store a difference between an input voltage and a feedback voltage; a quantizer, the quantizer being configured to generate oversampled samples based on an integrator output voltage, the oversampled samples comprising an offset error; and a digital-to-analog converter in a feedback loop of the Σ-Δ modulator, the digital-to-analog converter being configured to convert the oversampled samples to the feedback voltage; a decimation filter, the decimation filter being coupled to an output of the Σ-Δ modulator and being configured to receive the oversampled samples from the quantizer; and control logic, the control logic being configured by instructions and / or a logic circuit system to: configure the Σ-Δ modulator to perform a set of conversions; for a first conversion in a set of conversions, replace the input voltage with a zero voltage; for the first conversion in the set of conversions, bypass the integrator so that the quantizer generates a virtual sample based on the zero voltage, the virtual sample comprising the offset error; and configure the decimation filter to store the offset error to compensate for an offset error added by the quantizer during subsequent conversions in the set of conversions.

[0097] Embodiment 23 is a Σ-Δ ADC according to Embodiment 22, wherein the control logic is further configured to: replace the zero voltage with the input voltage for the subsequent conversion; and recouple the integrator to store the difference between the input voltage and the feedback voltage for the subsequent conversion.

[0098] Embodiment 24 is a Σ-Δ ADC according to embodiment 22 or 23, wherein: the group of conversions is a first group of conversions, and the control logic is also configured by the instructions and / or the logic circuit system to: reset the offset error stored in the extraction filter after outputting the first output sample and before starting the second group of conversions.

[0099] Embodiment 25 is a Σ-Δ ADC according to any one of Embodiments 22 to 24, wherein the group of conversions is a first group of conversions, and the control logic is also configured by the instructions and / or the logic circuit system to: add a base voltage to the zero voltage during the first conversion and during the subsequent conversions; and add the base voltage to the input voltage during the subsequent conversions.

[0100] Embodiment 26 is a Σ-Δ ADC according to any one of Embodiments 22 to 25, wherein: the first conversion in the group of conversions generates virtual samples, and the virtual samples are not accumulated by the decimation filter to generate output samples; and the subsequent conversions after the first conversion in the group of conversions generate oversampled samples, and the oversampled samples are accumulated by the decimation filter to generate the output samples.

[0101] In the specification and / or drawings, typical embodiments have been disclosed. The present disclosure is not limited to such exemplary embodiments. The use of the term "and / or" includes any and all combinations of one or more associated listed items. The drawings are schematic representations and are therefore not necessarily drawn to scale. Unless otherwise specified, specific terms have been used in a general and descriptive sense, not for limiting purposes.

[0102] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those of ordinary skill in the art. Methods and materials similar or equivalent to those described herein may be used in the practice or testing of the present disclosure. As used in this specification and in the appended claims, the singular forms "one", "a", "the" include multiple referents unless the context clearly specifies otherwise. The term "include" and its variants as used herein are used synonymously with the term "include" and its variants, and are open-ended, non-restrictive terms. The term "optional" or "optionally" used herein refers to the features, events or situations described subsequently that may or may not occur, and the description includes instances where the features, events or situations occur and instances where they do not occur. The range can be expressed herein as from "about" a specific value, and / or to "about" another specific value. When such a range is expressed, one aspect includes from a specific value and / or to another specific value. Similarly, when a value is expressed as an approximation by using the antecedent "about", it should be understood that the specific value forms another aspect. It will be further understood that the endpoints of each of the ranges are significant both relative to the other endpoint, and independently of the other endpoint.

[0103] Some implementations may be implemented using various semiconductor processing and / or packaging technologies. Some implementations may be implemented using various types of semiconductor processing technologies associated with semiconductor substrates, including but not limited to, for example, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), etc.

[0104] Although certain features of the described implementations have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the implementations. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The implementations described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different implementations described.

[0105] It will be understood that in the foregoing description, when an element is referred to as being located on another element, connected to another element, electrically connected to another element, coupled to another element, or electrically coupled to another element, the element may be directly located on another element, connected or coupled to another element, or one or more intermediate elements may be present. On the contrary, when an element is referred to as being directly on another element, directly connected to another element, or directly coupled to another element, there is no intermediate element. Although the term directly on, directly connected to, or directly coupled to may not be used throughout the specific embodiments, the element shown as being directly located on an element, directly connected, or directly coupled can be mentioned in this manner. The claims of the present application, if present, may be revised to narrate the example relationships described in the specification or shown in the accompanying drawings.

[0106] As used in this specification, singular forms may include plural forms unless the context clearly indicates a particular case. Spatially relative terms (e.g., above, above, above, below, below, below, below, etc.) are intended to cover different orientations of the device in use or operation, in addition to the orientations shown in the drawings. In some specific implementations, the relative terms above and below may include vertically above and vertically below, respectively. In some specific implementations, the term adjacent can include lateral adjacent or horizontal adjacent.

Claims

1. A method for compensating an offset voltage in a sigma-delta ADC, the method comprising: replacing an input voltage of a first conversion in a set of conversions at an input of the sigma-delta ADC with a reference voltage; quantizing the reference voltage at a quantizer of the sigma-delta ADC to obtain virtual samples, the virtual samples comprising the offset voltage added by the quantizer of the sigma-delta ADC; decoupling a decimation filter of the Σ-Δ ADC; generating a feedback voltage corresponding to the virtual sample, the feedback voltage including the offset voltage; inverting the feedback voltage to generate an inverted feedback voltage; applying the inverted feedback voltage to an integrator of the sigma-delta ADC, the inverted feedback voltage comprising an inverted offset voltage; as well as The inverted offset voltage is stored in the integrator to generate an offset charge integrator.

2. The method according to claim 1, wherein: performing the set of transformations to generate output samples; and For transitions other than the first transition in the set of transitions, the inverted offset voltage added by the offset charge integrator cancels the offset voltage added by the quantizer while generating the output samples.

3. The method of claim 2, wherein the set of transformations is a first set of transformations and the output sample is a first output sample, and wherein after performing the first set of transformations to generate the first output sample, the method further comprises: resetting the offset charge integrator by clearing the inverted offset voltage prior to commencing a second set of conversions to generate a second output sample; as well as A second offset charge integrator is generated for the second set of conversions.

4. The method of claim 3, wherein performing the set of transformations to generate the output samples further comprises: receiving the input voltage at the input of the Σ-Δ ADC; applying the input voltage to the offset charge integrator; applying an integrator output of the offset charge integrator to the quantizer, the integrator output including the inverted offset voltage to cancel the offset voltage added by the quantizer; generating oversampled samples, the oversampled samples being free of offset errors; as well as The oversampled samples are applied to the decimation filter.

5. The method according to claim 2, wherein: The first transform in the set of transforms is the virtual sample that is not accumulated by the decimation filter; and Transformations other than the first transform in the set of transforms are oversampled samples accumulated by the decimation filter.

6. The method according to claim 5, wherein: The inverse offset voltage stored in the integrator is based on the virtual sample and not based on the oversampled sample.

7. The method according to claim 5, further comprising: Outputting the output samples corresponding to the input voltage at an output of the decimation filter is based on the oversampled samples and not on the virtual samples.

8. The method of claim 1, wherein for the first transformation in the set of transformations, the method further comprises: adding a substrate voltage to the reference voltage; as well as The base voltage is stored in the integrator along with the inverted offset voltage.

9. The method according to claim 8, further comprising: The base voltage is not added to transitions in the set of transitions other than the first transition.

10. The method of claim 1, wherein the reference voltage is zero volts.

11. A method for compensating offset error in a Σ-Δ ADC: A set of transformations is performed to generate output samples, wherein for a first transformation in the set of transformations, the method comprises: replacing an input voltage at an input terminal of the Σ-Δ ADC with a reference voltage; Bypassing the integrator of the Σ-Δ ADC; quantizing the reference voltage at a quantizer of the sigma-delta ADC to obtain virtual samples, the virtual samples including the offset error added by the quantizer of the sigma-delta ADC; as well as The virtual samples are applied to a decimation filter configured to store the offset error to generate an offset compensated decimation filter configured to subtract the offset error added by the quantizer of the sigma-delta ADC for conversions in the set of conversions other than the first conversion.

12. The method of claim 11, wherein the set of transformations is a first set of transformations and the output samples are first output samples, and wherein after performing the first set of transformations to generate the first output samples, the method further comprises: resetting the offset compensated decimation filter by clearing the offset error before starting a second set of conversions to generate a second output sample; as well as A second offset compensated decimation filter configured for the second set of conversions is generated.

13. The method of claim 11, wherein performing the set of transformations to generate the output samples further comprises: receiving the input voltage and the feedback voltage at the integrator; applying the integrator output to the quantizer to generate oversampled samples, the oversampled samples including the offset error added by the quantizer; applying the oversampled samples to the offset compensating decimation filter, the offset compensating decimation filter subtracting the offset error added by the quantizer from the oversampled samples; as well as The oversampled samples are accumulated in the decimation filter, the decimation filter being configured to accumulate oversampled samples generated by conversions other than the first conversion.

14. The method according to claim 13, wherein: The first transform in the set of transforms does not include the integrator to generate the virtual sample; and The conversions other than the first conversion in the set of conversions include the integrator to generate the oversampled samples.

15. The method according to claim 14, further comprising: The output samples are based on the oversampled samples and not on the virtual samples.

16. The method according to claim 11, wherein the method further comprises: At the beginning of each conversion in the set of conversions, a substrate voltage is added as negative feedback to the input of the sigma-delta ADC.

17. A Σ-Δ ADC, comprising: A sigma-delta modulator, the sigma-delta modulator comprising: an integrator configured to store a difference between an input voltage and a feedback voltage; and a quantizer configured to generate oversampled samples based on an integrator output voltage of the integrator, the oversampled samples including an offset error; a decimation filter coupled to an output of the sigma-delta modulator and configured to receive the oversampled samples from the quantizer; and Control logic, the control logic being configured by instructions and / or logic circuitry to: configuring the sigma-delta modulator to perform a set of conversions to generate output samples; For a first transition in the set of transitions, replacing the input voltage with a zero voltage; and For the first conversion in the set of conversions, the decimation filter is decoupled from the quantizer so that the feedback voltage from the output of the quantizer is an offset voltage corresponding to the offset error, the offset voltage being stored in the integrator.

18. The Σ-Δ ADC of claim 17, wherein the control logic is further configured to: replacing the zero voltage with the input voltage for a subsequent conversion in the set of conversions; and The decimation filter is recoupled to the output of the quantizer for the subsequent conversion, the decimation filter being configured to output output samples based on the oversampled samples generated by the subsequent conversion.

19. The Σ-Δ ADC of claim 17, wherein the control logic is further configured by the instructions and / or the logic circuitry to: adding a substrate voltage to the zero voltage during the first transition in the set of transitions; and The base voltage is not added to the input voltage during subsequent conversions after the first conversion in the set of conversions.

20. The Σ-Δ ADC of claim 17, wherein: The first transform in the set of transforms generates virtual samples that are not accumulated by the decimation filter to generate the output samples; and Subsequent conversions after the first conversion in the set of conversions generate oversampled samples that are accumulated by the decimation filter to generate the output samples.

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