Interpolation position calculation method, device and equipment of parallel time synchronizer

By using multiplication, subtraction and fixed constant division operations in the parallel time synchronizer to calculate the interpolation position and perform overflow correction, the problems of long time to calculate the interpolation position and large feedback delay in the prior art are solved, and faster and more accurate interpolation position calculation is achieved.

CN120034309AActive Publication Date: 2025-05-23PENG CHENG LAB
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Patent Information

Application Number
CN202510520379.7
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-04-24
Publication Date
2025-05-23
Estimated Expiration
2045-04-24

AI Technical Summary

Technical Problem

Existing parallel time synchronizers consume longer time when calculating interpolation positions and have higher feedback delays.

Method used

By determining the output data based on the interpolation position and input data at the current time, determining the sampling period based on the output data and the output valid flag, multiplication, subtraction and fixed constant division operation processing are performed, the initial interpolation position of the target time is obtained, and overflow correction is performed.

Benefits of technology

The calculation process of interpolation position is simplified, the calculation time is reduced, the feedback delay is reduced, and the interpolation position is updated in real time, avoiding the additional delay introduced by the serial chain structure, and ensuring the accuracy of the interpolation position through overflow correction.

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Abstract

The invention discloses an interpolation position calculation method, device and equipment of a parallel time synchronizer, and relates to the technical field of wireless communication, and the method comprises the steps: determining the output data of the current moment based on the interpolation position and input data of the current moment; determining a sampling period of the current moment based on the output data and the output effective mark of the current moment; operation processing is carried out on the sampling period of the current moment, the initial interpolation position of the target moment is obtained, and the operation processing at least comprises multiplication processing, subtraction processing and division processing based on a fixed constant; and performing overflow correction on the initial interpolation position of the target moment to obtain the interpolation position of the target moment. Through the above mode, the interpolation position is calculated by using a fixed constant value, the calculation complexity is simplified, the calculation time of the interpolation position is reduced, the feedback time delay is reduced, the interpolation position is updated in real time, and the introduction of additional feedback time delay due to a serial chain structure can be avoided.
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Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to an interpolation position calculation method, device and equipment for a parallel time synchronizer. Background Art

[0002] The Gardner algorithm is a time synchronization algorithm commonly used in wireless communications. It can compensate for the sampling point deviation caused by the sampling rate error and find the best sampling point. In specific implementation, it uses an interpolation filter to achieve signal resampling, and uses the "early-late gate" algorithm to detect the sampling point error of the signal. According to the output of the error value through the loop filter, the interpolation position is calculated, and the interpolation position is fed back to the interpolation filter, thereby achieving real-time adjustment of the interpolation position and finding the best sampling point.

[0003] In a traditional parallel time synchronizer (Gardner time synchronizer) using the Gardner algorithm, the interpolation position is calculated by dividing the current value of the numerically controlled oscillator by the estimated sampling period. Since both the current value of the numerically controlled oscillator and the estimated sampling period are variables, high-precision variable division is involved, which consumes a lot of time during calculation, resulting in a certain delay in the feedback of the interpolation position. In addition, when calculating the interpolation position, the interpolation position is updated only when the valid signal is high, otherwise the value of the last calculation is maintained. It can be seen that the calculation input of each path depends on the calculation output of the previous path, which will introduce a serial chain structure and cause additional feedback delay.

[0004] The above contents are only used to assist in understanding the technical solution of the present invention and do not constitute an admission that the above contents are prior art. Summary of the invention

[0005] The main purpose of the present application is to provide a method, device and equipment for calculating the interpolation position of a parallel time synchronizer, aiming to solve the technical problem in the prior art that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay.

[0006] To achieve the above object, the present application provides a method for calculating an interpolation position of a parallel time synchronizer, the method comprising: Determining output data at the current moment based on the interpolation position and input data at the current moment; Determine the sampling period at the current moment based on the output data and the output valid flag at the current moment; Performing operation processing on the sampling period of the current moment to obtain an initial interpolation position of the target moment, wherein the operation processing at least includes multiplication operation processing, subtraction operation processing and division operation processing based on a fixed constant; An overflow correction is performed on the initial interpolation position at the target time to obtain the interpolation position at the target time.

[0007] In one embodiment, the step of determining the output data at the current moment based on the interpolation position and the input data at the current moment includes: Inputting the input data at the current moment into a plurality of parallel filters with different coefficients respectively, to obtain initial output data of the parallel filters at the current moment; Obtaining a first correspondence between the initial output data at the current moment, the interpolation position at the current moment, the filter weight and the output data at the current moment; The output data at the current moment is obtained based on the initial output data of the parallel filter at the current moment, the interpolation position at the current moment, the filter weight and the first corresponding relationship.

[0008] In one embodiment, the step of determining the sampling period at the current moment based on the output data and the output valid flag at the current moment includes: Determine the parallel error amount based on the output data and the output valid flag at the current moment; Based on the parallel error amount, determining an average error amount; Inputting the average error amount into a loop filter for filtering to obtain loop filtering data; Based on the loop filtering data, a sampling period at the current moment is determined.

[0009] In one embodiment, the step of determining the parallel error amount based on the output data and the output valid flag at the current moment includes: When the output valid flag at the current moment is a first value, using the first value as the parallel error amount; When the output valid flag at the current moment is a second value, a second corresponding relationship between the output data at the current moment and the parallel error amount is obtained, and the parallel error amount is obtained based on the output data at the current moment and the second corresponding relationship.

[0010] In one embodiment, the step of performing calculation processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment includes: Based on a preset constant sequence, a multiplication operation is performed on the sampling period at the current moment to obtain a multiplication operation result; Subtracting the multiplication result from the stored value at the current moment to obtain a subtraction result, and updating the stored value at the target moment based on the subtraction result; Based on the fixed constant, the subtraction result is divided to obtain the initial interpolation position of the target time.

[0011] In one embodiment, before the step of performing overflow correction on the initial interpolation position at the target time to obtain the interpolation position at the target time, the step further includes: Determining an adjacent road subtraction result based on the subtraction result at the target time, the adjacent road subtraction result; Based on the adjacent path subtraction operation result, an output valid flag at the target time is determined.

[0012] In one embodiment, the adjacent road subtraction result includes a subtraction result of a current road and a subtraction result of a preceding road, and the step of determining the output valid flag at the target time based on the adjacent road subtraction result includes: When the subtraction result of the current path is less than or equal to the subtraction result of the previous path, the first value is used as the output valid flag corresponding to the current path; When the subtraction operation result of the current path is equal to the subtraction operation result of the previous path, the second value is used as the output valid flag corresponding to the current path.

[0013] In one embodiment, the step of performing overflow correction on the initial interpolation position at the target time to obtain the interpolation position at the target time includes: Acquire a third correspondence between an initial interpolation position at a target time, an output valid flag at a target time, and an interpolation position at a target time; Based on the initial interpolation position at the target time, the output valid flag at the target time, and the third corresponding relationship, the interpolation position at the target time is obtained.

[0014] In addition, to achieve the above-mentioned purpose, the present application also proposes an interpolation position calculation device for a parallel time synchronizer, and the interpolation position calculation device for a parallel time synchronizer includes: A parallel filtering module, used for determining output data at the current moment based on the interpolation position and input data at the current moment; A sampling period estimation module, used to determine the sampling period at the current moment based on the output data and the output valid flag at the current moment; A numerically controlled oscillation module, used for performing arithmetic processing on the sampling period at the current moment to obtain an initial interpolation position at the target moment, wherein the arithmetic processing at least includes a multiplication operation processing, a subtraction operation processing, and a division operation processing based on a fixed constant; The digital controlled oscillation module is further used to perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0015] In addition, to achieve the above-mentioned purpose, the present application also proposes an interpolation position calculation device for a parallel time synchronizer, and the interpolation position calculation device for a parallel time synchronizer includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the interpolation position calculation method for the parallel time synchronizer as described above.

[0016] In addition, to achieve the above-mentioned purpose, the present invention also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the interpolation position calculation method of the parallel time synchronizer as described above are implemented.

[0017] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of the interpolation position calculation method of the parallel time synchronizer as described above are implemented.

[0018] The present application provides a method for calculating the interpolation position of a parallel time synchronizer, which determines the output data at the current moment based on the interpolation position and input data at the current moment; determines the sampling period at the current moment based on the output data and the output valid flag at the current moment; performs operation processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the operation processing at least includes multiplication operation processing, subtraction operation processing and division operation processing based on a fixed constant; performs overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment. The present application uses a fixed constant value to calculate the interpolation position, which can simplify the complexity of the calculation, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Regardless of whether the valid signal is high, the interpolation position will be updated, which can avoid the introduction of additional feedback delay due to the serial chain structure. In addition, the overflow correction process is added to avoid the error caused by the overflow of the interpolation position, ensure the accuracy of the calculated interpolation position, and solve the technical problem that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0021] Figure 1 A flowchart of a first embodiment of an interpolation position calculation method for a parallel time synchronizer of the present application; Figure 2 A schematic diagram of the overall structure of a parallel time synchronizer according to the interpolation position calculation method of the parallel time synchronizer provided in the first embodiment of the present application; Figure 3 This is a flow chart of Embodiment 2 of the interpolation position calculation method of the parallel time synchronizer of the present application; Figure 4 A schematic diagram of the structure of a digitally controlled oscillator for the interpolation position calculation method of a parallel time synchronizer provided in the second embodiment of the present application; Figure 5 This is a flow chart of Embodiment 3 of the interpolation position calculation method of the parallel time synchronizer of the present application; Figure 6 A schematic diagram of a brief flow chart of an interpolation position calculation method for a parallel time synchronizer provided in Embodiment 3 of the present application; Figure 7 This is a schematic diagram of the module structure of an interpolation position calculation device of a parallel time synchronizer according to an embodiment of the present application; Figure 8 Schematic diagram of the device structure of the hardware operating environment involved in the interpolation position calculation method of the parallel time synchronizer in the embodiment of the present application.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0023] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0024] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0025] The main solution of the embodiment of the present application is: based on the interpolation position and input data at the current moment, determine the output data at the current moment; based on the output data and the output valid flag at the current moment, determine the sampling period at the current moment; perform calculation processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the calculation processing at least includes multiplication processing, subtraction processing and division processing based on a fixed constant; perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0026] At present, in the traditional parallel time synchronizer (Gardner time synchronizer) using the Gardner algorithm, the interpolation position is calculated by dividing the current value of the numerically controlled oscillator by the estimated sampling period. Since the current value of the numerically controlled oscillator and the estimated sampling period are variables, high-precision variable division is involved, which consumes a lot of time during calculation, resulting in a certain delay in the feedback of the interpolation position. In addition, when calculating the interpolation position, the interpolation position is updated only when the valid signal is high, otherwise the value of the last calculation is maintained. It can be seen that the calculation input of each channel depends on the calculation output of the previous channel, which will introduce a serial chain structure and cause additional feedback delay.

[0027] The present application provides a solution, which uses a fixed constant value to calculate the interpolation position, which can simplify the complexity of the calculation, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Regardless of whether the valid signal is high, the interpolation position will be updated, which can avoid the introduction of additional feedback delay due to the serial chain structure. In addition, an overflow correction process is added to avoid the huge error caused by overflow of the interpolation position, ensure the accuracy of the calculated interpolation position, and solve the technical problem that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay.

[0028] It should be noted that the execution subject of this embodiment can be a parallel time synchronizer, or an electronic device capable of realizing the above functions, an interpolation position calculation device of a parallel time synchronizer, etc., and this embodiment does not specifically limit this. The following takes a parallel time synchronizer as an example to illustrate this embodiment and the following embodiments.

[0029] The present application embodiment provides a method for calculating an interpolation position of a parallel time synchronizer, referring to Figure 1 , Figure 1 This is a flow chart of a first embodiment of an interpolation position calculation method for a parallel time synchronizer of the present application.

[0030] In this embodiment, the interpolation position calculation method of the parallel time synchronizer includes steps S10 to S40: Step S10, determining the output data at the current moment based on the interpolation position and input data at the current moment; It should be noted that the parallel time synchronizer may be a Gardner time synchronizer. Figure 2The parallel time synchronizer includes a parallel filtering module, a sampling period estimation module and a numerically controlled oscillation module, wherein the parallel filtering module generally includes a plurality of parallel filters, and the numerically controlled oscillation module generally includes a numerically controlled oscillator. The parallel filtering module can calculate the output data according to the input data and the interpolation position fed back by the numerically controlled oscillation module, and the sampling period estimation module can estimate the sampling period according to the output valid flag and the output data fed back by the numerically controlled oscillator. The numerically controlled oscillation module can calculate the interpolation position at the next moment according to the estimated sampling period and feed it back to the parallel filtering module, and calculate the output valid flag at the next moment and feed it back to the sampling period estimation module.

[0031] In addition, it should be noted that the current moment is the current time, usually recorded as the moment The input data refers to the data input to the parallel time synchronizer, and the output data refers to the data output by the parallel time synchronizer. The output valid flag is usually used to indicate the level of the valid signal, and contains two states, namely "0" and "1". Generally speaking, "0" indicates that the valid signal is at a low level, and "1" indicates that the valid signal is at a high level. The interpolation position refers to the position corresponding to the interpolation, and the sampling period refers to the estimated sampling period.

[0032] It can be understood that, assuming the number of parallel paths (greater than 2) of the parallel time synchronizer is , then the parallel time synchronizer is at time take over parallel input data, generating Output data in parallel Output valid flag of parallel path, The interpolation position and sampling period of the parallel path. In the specific implementation, at time , The parallel input data can be recorded as , The output data of the parallel path can be recorded as , The output valid flag of the parallel path can be recorded as , The interpolation position of the parallel path can be recorded as , the sampling period can be recorded as For example, for the time , the input data of the 16-way parallel time synchronizer can be recorded as , the output data of the 16-way parallel time synchronizer can be recorded as , the output valid flag of the 16-way parallel time synchronizer can be recorded as , the interpolation position of the 16-way parallel time synchronizer can be recorded as .

[0033] It should be understood that during the initialization phase, the parallel time synchronizer will always Initialize to 0, and set the time The interpolation position All are initialized to 0, and the time Output valid flag All initialized to 0.

[0034] In a feasible implementation, step S10 may include steps S101 to S103: Step S101, inputting the input data at the current moment into a plurality of parallel filters with different coefficients respectively, to obtain initial output data of the parallel filters at the current moment; It should be noted that, in this embodiment, a plurality of parallel filters are provided, the coefficients of these parallel filters are all different, the number of parallel filters is usually set to 3, and the number of parallel paths of each parallel filter is the same as the number of parallel paths of the parallel time synchronizer, both of which are The data obtained after the input data at the current moment is input into the parallel filter is the initial output data, which needs to be further processed to obtain the output data at the current moment. For example, the coefficients of the parallel filter 1 are , the coefficients of parallel filter 2 are , the coefficients of parallel filter three are .

[0035] It is understandable that the time Input data Sent to 3 different coefficients parallel filter, assuming that the coefficient of parallel filter one is , then the first parallel filter The road is at the moment The initial output data can be expressed as:

[0036] In the formula, represents the first The road is at the moment The initial output data, Indicates the number of parallel paths, represents the floor function, Represents the remainder function.

[0037] Accordingly, assume that the coefficients of parallel filter 2 are , then the second parallel filter The road is at the moment The initial output data can be expressed as:

[0038] In the formula, represents the second parallel filter The road is at the moment The initial output data, Indicates the number of parallel paths, represents the floor function, Represents the remainder function.

[0039] Accordingly, assume that the coefficients of parallel filter three are , then the third parallel filter The road is at the moment The initial output data can be expressed as:

[0040] In the formula, represents the third parallel filter The road is at the moment The initial output data, Indicates the number of parallel paths, represents the floor function, Represents the remainder function.

[0041] Step S102, obtaining a first corresponding relationship between the initial output data at the current moment, the interpolation position at the current moment, the filter weight and the output data at the current moment; It can be understood that after obtaining the initial output data of each parallel filter at the current moment, weighted accumulation is performed to obtain the final output data. The filter weight is the weight coefficient set when calculating the output data. The first corresponding relationship between the initial output data at the current moment, the interpolation position at the current moment, the filter weight and the output data at the current moment, that is, the calculation relationship of the output data at the current moment, is as follows:

[0042] In the formula, , , The first The road is at the moment The initial output data, , , represents the filter weights of each parallel filter, Indicates time The interpolation position of Indicates time The output data, Indicates the number of parallel paths of the parallel filter.

[0043] Step S103, obtaining the output data at the current moment based on the initial output data of the parallel filter at the current moment, the interpolation position at the current moment, the filter weight and the first corresponding relationship.

[0044] It is understandable that the parallel filters are Initial output data, time The interpolation position and the filter weights of each parallel filter are substituted into the first corresponding relationship to calculate the time Output data.

[0045] Step S20, determining the sampling period at the current moment based on the output data and the output valid flag at the current moment; In a feasible implementation, step S20 may include steps S201 to S204: Step S201, determining a parallel error amount based on the output data and the output valid flag at the current moment; It should be noted that each output data has a corresponding output valid flag, so that the corresponding parallel error can be calculated. The parallel error is The error of the output data of the parallel path. ,according to parallel output data and The output valid flag of the parallel path is calculated The parallel error amount.

[0046] In a feasible implementation, step S201 may include: when the output valid flag at the current moment is a first value, using the first value as the parallel error amount; when the output valid flag at the current moment is a second value, obtaining a second correspondence between the output data at the current moment and the parallel error amount, and obtaining the parallel error amount based on the output data at the current moment and the second correspondence.

[0047] It can be understood that the first value is 0 and the second value is 1. Output valid flag of the route , then the corresponding parallel error is 0. The second corresponding relationship between the output data at the current moment and the parallel error, that is, the output valid flag The calculation formula of the parallel error is: Output valid flag of the route , then the parallel error is calculated as follows:

[0048] In the formula, Indicates The road is at the moment The parallel error, , Indicates the number of parallel paths, Indicates time The output data, represents the floor function, represents the remainder function. Substitute the output data of into the above second corresponding relationship to calculate the time The parallel error corresponding to each output data is obtained The parallel error amount.

[0049] Step S202, determining an average error amount based on the parallel error amount; It is understandable that the average error is The average value of the parallel error of the path. After calculating the parallel error of each path, the average error is obtained.

[0050] Step S203, inputting the average error amount into a loop filter for filtering to obtain loop filtering data; It should be noted that by inputting the average error amount into the loop filter for filtering, two loop filter outputs can be obtained, that is, two loop filter data can be obtained, as shown below:

[0051]

[0052] In the formula, and Separately for the moment The two loop filter data, Indicates The road is at the moment The parallel error, Indicates time The average error of Indicates time The corresponding loop filter data, Indicates the number of parallel paths.

[0053] Step S204: determining the sampling period at the current moment based on the loop filtering data.

[0054] It can be understood that the sampling period at the current moment is calculated based on the two loop filtering data, and the calculation relationship is as follows:

[0055] In the formula, Indicates time The sampling period, and Separately for the moment The two loop filter data of Substitute the two loop filter data into the above calculation formula to get the time The sampling period.

[0056] Step S30, performing arithmetic processing on the sampling period of the current moment to obtain an initial interpolation position of the target moment, wherein the arithmetic processing at least includes a multiplication processing, a subtraction processing, and a division processing based on a fixed constant; It should be noted that the target moment is the next moment, recorded as moment Based on the estimated sampling period Calculate the time of The parallel output valid flag and The interpolation position of the parallel path.

[0057] It is understandable that in the process of calculating the interpolation position at the target moment, an intermediate process value, namely the initial interpolation position at the target moment, will be calculated first. The corresponding initial interpolation position is obtained by performing a series of operations on the sampling period of the current moment. The entire operation process at least includes multiplication operation processing, subtraction operation processing and division operation processing based on a fixed constant. The fixed constant is a fixed constant value set, and the division operation processing based on the fixed constant is to use the fixed constant value for division operation.

[0058] It should be understood that the conventional method calculates the interpolation position by dividing the current storage value of the numerically controlled oscillator by the estimated sampling period, which involves high-precision variable division, consumes a lot of time, and has a certain feedback delay. Therefore, this embodiment uses constant division instead of variable division to simplify the calculation process, which can reduce the time spent on calculation and reduce feedback delay.

[0059] Step S40, performing overflow correction on the initial interpolation position at the target time to obtain the interpolation position at the target time.

[0060] It should be noted that since this embodiment uses a fixed constant for division operation, the initial interpolation position is finally calculated approximately, which introduces a certain error and may cause data overflow. It cannot be directly used as the final interpolation position, and an overflow correction operation is required to prevent the interpolation position from overflowing.

[0061] It is understandable that by The initial interpolation position is corrected for overflow, and the moment is obtained The exact interpolation position.

[0062] It should be understood that the interpolation position can be calculated at each moment according to the process of steps S10 to S40.

[0063] This embodiment provides a method for calculating the interpolation position of a parallel time synchronizer, which determines the output data at the current moment based on the interpolation position and input data at the current moment; determines the sampling period at the current moment based on the output data and the output valid flag at the current moment; performs operation processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the operation processing at least includes multiplication operation processing, subtraction operation processing and division operation processing based on a fixed constant; performs overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment. This embodiment uses a fixed constant value to calculate the interpolation position, which can simplify the complexity of the calculation, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Regardless of whether the valid signal is high, the interpolation position will be updated, which can avoid the introduction of additional feedback delay due to the serial chain structure. In addition, the overflow correction process is added to avoid the huge error caused by the overflow of the interpolation position, and ensure the accuracy of the calculated interpolation position.

[0064] Based on the first embodiment of the present application, in the second embodiment of the present application, the same or similar contents as those in the above-mentioned embodiment 1 can refer to the above introduction, and will not be repeated later. Figure 3 , step S30 may include steps S301 to S303: Step S301, performing a multiplication operation on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication result; It should be noted that the numerically controlled oscillator calculates the time according to the estimated sampling period of The initial interpolation position of the parallel path. Figure 4 In this embodiment, the digital controlled oscillator maintains a memory to record the state, and the value of the memory is the stored value. The storage value of The digitally controlled oscillator also includes The multiplier, subtractor and constant divider are parallel in each path, and each path includes a multiplier, a subtractor and a constant divider. The multiplier is used to perform multiplication processing, the subtractor is used to perform subtraction processing, and the constant divider is used to perform division processing based on a fixed constant.

[0065] In addition, it should be noted that the preset constant sequence is a sequence composed of constants used in each path when performing multiplication processing, that is, The value of the multiplier needs to be set according to a preset constant sequence. For example, assuming that the preset constant sequence is ,but The values ​​of the parallel multipliers are .

[0066] It is understandable that the time The sampling period Input to The parallel multipliers are multiplied by the constant values ​​in the preset constant sequence respectively, and the obtained The result of multiplying the paths is the result of the multiplication operation.

[0067] Step S302, performing a subtraction operation on the multiplication result and the stored value at the current moment to obtain a subtraction result, and updating the stored value at the target moment based on the subtraction result; It should be noted that the stored value at the current moment is the moment The stored value of . Use the subtractor to add the multiplication result and the time The stored value of is subtracted and the obtained The result is the result of the subtraction operation, as shown below:

[0068] In the formula, Indicates The road is at the moment The result of the subtraction operation is , Indicates the number of parallel paths, Indicates time The storage value of Indicates time The sampling period, Represents the floor function.

[0069] It is understandable that in getting After the subtraction result of the last subtractor is calculated, the subtraction result obtained by the last subtractor is fed back to the memory as the value of the memory at the next moment, that is, the storage value at the target moment, that is, the moment The storage value is as follows:

[0070] In the formula, Indicates time The storage value of Indicates The subtraction result of the subtractor of the path, Indicates the number of parallel paths.

[0071] Step S303: Based on the fixed constant, divide the subtraction result to obtain the initial interpolation position of the target time.

[0072] It should be noted that the value of the fixed constant can be flexibly adjusted according to actual needs, and no specific limitation is made to this. In this embodiment, the fixed constant can be set to 0.5. At this time, the calculation relationship of the constant divider using the fixed constant for division processing is as follows:

[0073] In the formula, Indicates The road is at the moment The initial interpolation position of Indicates The road is at the moment The result of the subtraction operation is Indicates The road is at the moment The result of the subtraction operation.

[0074] It can be understood that the subtraction results of two adjacent paths are compared. The road is at the moment The result of the subtraction operation is greater than The road is at the moment The subtraction result of The road is at the moment The subtraction result is divided by the fixed constant 0.5 to obtain the The road is at the moment The initial interpolation position of The road is at the moment The result of the subtraction operation is less than or equal to The road is at the moment The subtraction result of The road is at the moment The subtraction result is divided by the fixed constant 0.5 and then subtracted from the value 1 to obtain the The road is at the moment The initial interpolation position of .

[0075] Furthermore, in a feasible implementation manner, based on the subtraction result of the target moment, the adjacent road subtraction result is determined; based on the adjacent road subtraction result, the output valid flag of the target moment is determined.

[0076] It should be noted that the adjacent path subtraction result is the subtraction result of the subtractors of the two adjacent paths. The subtraction results of the subtractors of the two adjacent paths are compared to obtain the output valid flag of the next moment. The adjacent path subtraction result includes the subtraction result of the current path and the subtraction result of the previous path. The subtraction result of the current path is the subtraction result of the first path. The road is at the moment The result of the subtraction operation of the preceding path is the subtraction result of The road is at the moment The result of the subtraction operation.

[0077] It can be understood that when the subtraction result of the current path is less than or equal to the subtraction result of the previous path, the first value is used as the output valid flag corresponding to the current path; when the subtraction result of the current path is greater than the subtraction result of the previous path, the second value is used as the output valid flag corresponding to the current path. The calculation relationship is as follows:

[0078] In the formula, Indicates The road is at the moment The output valid flag, Indicates The road is at the moment The result of the subtraction operation is Indicates The road is at the moment The result of the subtraction operation is Indicates the number of parallel paths.

[0079] It should be understood that if The road is at the moment The result of the subtraction operation is greater than The road is at the moment The subtraction result of The road is at the moment The output valid flag is set to 1; if The road is at the moment The result of the subtraction operation is less than or equal to The road is at the moment The subtraction result of The road is at the moment The output valid flag is set to 0.

[0080] The present embodiment provides a method for calculating the interpolation position of a parallel time synchronizer. Based on a preset constant sequence, a multiplication operation is performed on the sampling period of the current moment to obtain a multiplication result; the multiplication result is subtracted from the stored value at the current moment to obtain a subtraction result, and the stored value at the target moment is updated based on the subtraction result; based on a fixed constant, a division operation is performed on the subtraction result to obtain an initial interpolation position at the target moment. The present embodiment uses a fixed constant value to calculate the interpolation position, which can simplify the complexity of the calculation, reduce the calculation time of the interpolation position, reduce the feedback delay, and update the interpolation position in real time. Regardless of whether the valid signal is high, the interpolation position will be updated, which can avoid the introduction of additional feedback delay due to the serial chain structure.

[0081] Based on the above embodiments of the present application, in the third embodiment of the present application, the same or similar contents as those in the above embodiments can be referred to the above introduction, and will not be described in detail later. Figure 5 , step S40 may include steps S401~S402: Step S401, obtaining a third correspondence between an initial interpolation position at a target time, an output valid flag at a target time, and an interpolation position at a target time; It should be noted that using a constant divider to approximately calculate the interpolation position will introduce a certain error, which may cause data overflow. In order to prevent overflow, this embodiment combines the initial interpolation position at the target moment and the output valid flag to perform an overflow correction operation to obtain the interpolation position at the next moment. The third corresponding relationship between the initial interpolation position at the target moment, the output valid flag at the target moment, and the interpolation position at the target moment, that is, the calculation relationship of the interpolation position at the target moment, is as follows:

[0082] In the formula, Indicates The road is at the moment The interpolation position of Indicates The road is at the moment The output valid flag, Indicates The road is at the moment The initial interpolation position of Indicates the number of parallel paths.

[0083] Step S402: obtaining the interpolation position of the target time based on the initial interpolation position of the target time, the output valid flag of the target time, and the third corresponding relationship.

[0084] It is understandable that if The road is at the moment The output valid flag is 1 and the The road is at the moment The initial interpolation position of is greater than 1, then the moment The interpolation position is 1; if The road is at the moment The output valid flag is 0 and the The road is at the moment The initial interpolation position is less than 0, then the moment The interpolation position is 0; in other cases, the moment The interpolation position is equal to The road is at the moment The initial interpolation position of .

[0085] The present embodiment provides an interpolation position calculation method for a parallel time synchronizer, obtaining an initial interpolation position at a target time, a third correspondence between an output valid flag at the target time and the interpolation position at the target time; based on the initial interpolation position at the target time, the output valid flag at the target time and the third correspondence, the interpolation position at the target time is obtained. The present embodiment adds an overflow correction process, which can avoid huge errors caused by overflow of the interpolation position and ensure the accuracy of the calculated interpolation position.

[0086] For example, to help understand the implementation process of the interpolation position calculation method of the parallel time synchronizer obtained by combining this embodiment with the above-mentioned embodiment 3, please refer to Figure 6 , Figure 6 A brief flowchart of an interpolation position calculation method for a parallel time synchronizer is provided, specifically: During the initialization phase, the parallel time synchronizer will Initialize to 0, and set the time The interpolation positions are all initialized to 0, and the moment The output valid flags are all initialized to 0.

[0087] In the operation phase, for each moment , the parallel filter is based on the time The interpolation position and time Input data, calculation time The output data of the sampling period estimation module is based on the time Output data, time The output valid flag calculation time The sampling period of the numerically controlled oscillator is based on the time The sampling period calculation time The interpolation position and time of The output valid flag. After completion, the time Increase by 1, and execute the above steps again, repeating the cycle until the shutdown ends.

[0088] It should be noted that the above examples are only used to understand the present application and do not constitute a limitation on the interpolation position calculation method of the parallel time synchronizer of the present application. More forms of simple transformations based on this technical concept are all within the protection scope of the present application.

[0089] The present application also provides an interpolation position calculation device for a parallel time synchronizer, please refer to Figure 7 , the interpolation position calculation device of the parallel time synchronizer includes: A parallel filtering module 10, for determining output data at the current moment based on the interpolation position and input data at the current moment; A sampling period estimation module 20, used to determine the sampling period at the current moment based on the output data and the output valid flag at the current moment; A numerically controlled oscillation module 30, configured to perform arithmetic processing on the sampling period at the current moment to obtain an initial interpolation position at the target moment, wherein the arithmetic processing at least includes a multiplication processing, a subtraction processing, and a division processing based on a fixed constant; The digital controlled oscillation module 30 is further used to perform overflow correction on the initial interpolation position at the target time to obtain the interpolation position at the target time.

[0090] In a feasible implementation manner, the parallel filtering module 10 is further used to input the input data at the current moment into a plurality of parallel filters with different coefficients respectively, to obtain initial output data of the parallel filters at the current moment; Obtaining a first correspondence between the initial output data at the current moment, the interpolation position at the current moment, the filter weight and the output data at the current moment; The output data at the current moment is obtained based on the initial output data of the parallel filter at the current moment, the interpolation position at the current moment, the filter weight and the first corresponding relationship.

[0091] In a feasible implementation manner, the sampling period estimation module 20 is further used to determine the parallel error amount based on the output data and the output valid flag at the current moment; Based on the parallel error amount, determining an average error amount; Inputting the average error amount into a loop filter for filtering to obtain loop filtering data; Based on the loop filtering data, a sampling period at the current moment is determined.

[0092] In a feasible implementation manner, the sampling period estimation module 20 is further configured to use the first value as the parallel error amount when the output valid flag at the current moment is a first value; When the output valid flag at the current moment is a second value, a second corresponding relationship between the output data at the current moment and the parallel error amount is obtained, and the parallel error amount is obtained based on the output data at the current moment and the second corresponding relationship.

[0093] In a feasible implementation manner, the digital control oscillation module 30 is further used to perform a multiplication operation on the sampling period at the current moment based on a preset constant sequence to obtain a multiplication result; Subtracting the multiplication result from the stored value at the current moment to obtain a subtraction result, and updating the stored value at the target moment based on the subtraction result; Based on the fixed constant, the subtraction result is divided to obtain the initial interpolation position of the target time.

[0094] In a feasible implementation manner, the digital control oscillation module 30 is further used to determine the adjacent road subtraction operation result based on the subtraction operation result at the target time, the adjacent road subtraction operation result; Based on the adjacent path subtraction operation result, an output valid flag at the target time is determined.

[0095] In a feasible implementation manner, the digital control oscillation module 30 is further configured to use the first value as an output valid flag corresponding to the current path when the subtraction result of the current path is less than or equal to the subtraction result of the previous path; When the subtraction operation result of the current path is equal to the subtraction operation result of the previous path, the second value is used as the output valid flag corresponding to the current path.

[0096] In a feasible implementation manner, the digital control oscillation module 30 is further used to obtain a third corresponding relationship between the initial interpolation position at the target time, the output valid flag at the target time, and the interpolation position at the target time; Based on the initial interpolation position at the target time, the output valid flag at the target time, and the third corresponding relationship, the interpolation position at the target time is obtained.

[0097] The interpolation position calculation device of the parallel time synchronizer provided by the present application adopts the interpolation position calculation method of the parallel time synchronizer in the above-mentioned embodiment, which can solve the technical problem that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the interpolation position calculation device of the parallel time synchronizer provided by the present application are the same as the beneficial effects of the interpolation position calculation method of the parallel time synchronizer provided by the above-mentioned embodiment, and the other technical features in the interpolation position calculation device of the parallel time synchronizer are the same as the features disclosed in the above-mentioned embodiment method, which will not be repeated here.

[0098] The present application provides an interpolation position calculation device for a parallel time synchronizer, and the interpolation position calculation device for the parallel time synchronizer includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the interpolation position calculation method for the parallel time synchronizer in the above-mentioned embodiment one.

[0099] Reference below Figure 8 , which shows a schematic diagram of the structure of an interpolation position calculation device suitable for implementing the parallel time synchronizer of the embodiment of the present application. The interpolation position calculation device of the parallel time synchronizer in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The interpolation position calculation device of the parallel time synchronizer shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0100] like Figure 8As shown, the interpolation position calculation device of the parallel time synchronizer may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in a ROM (Read Only Memory) 1002 or a program loaded from a storage device 1003 to a RAM (Random Access Memory) 1004. Various programs and data required for the operation of the interpolation position calculation device of the parallel time synchronizer are also stored in the RAM 1004. The processing device 1001, the ROM 1002, and the RAM 1004 are connected to each other via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to the I / O interface 1006: input devices 1007 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 1008 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 1003 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 1009. The communication device 1009 can allow the interpolation position calculation device of the parallel time synchronizer to communicate wirelessly or wired with other devices to exchange data. Although the figure shows an interpolation position calculation device of the parallel time synchronizer with various systems, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems may be implemented or have alternatively.

[0101] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a ROM 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0102] The interpolation position calculation device of the parallel time synchronizer provided by the present application adopts the interpolation position calculation method of the parallel time synchronizer in the above-mentioned embodiment, which can solve the technical problem that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the interpolation position calculation device of the parallel time synchronizer provided by the present application are the same as the beneficial effects of the interpolation position calculation method of the parallel time synchronizer provided by the above-mentioned embodiment, and the other technical features in the interpolation position calculation device of the parallel time synchronizer are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0103] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0104] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0105] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, the computer-readable program instructions being used to execute the interpolation position calculation method of the parallel time synchronizer in the above-mentioned embodiment.

[0106] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0107] The computer-readable storage medium may be included in the interpolation position calculation device of the parallel time synchronizer; or may exist independently without being assembled into the interpolation position calculation device of the parallel time synchronizer.

[0108] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the interpolation position calculation device of the parallel time synchronizer, the interpolation position calculation device of the parallel time synchronizer: determines the output data at the current moment based on the interpolation position and input data at the current moment; determines the sampling period at the current moment based on the output data and the output valid flag at the current moment; performs operation processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment, and the operation processing at least includes multiplication operation processing, subtraction operation processing and division operation processing based on a fixed constant; performs overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

[0109] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0110] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0111] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0112] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the interpolation position calculation method of the above-mentioned parallel time synchronizer, and can solve the technical problem that the parallel time synchronizer consumes a long time when calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the interpolation position calculation method of the parallel time synchronizer provided by the above-mentioned embodiment, and will not be repeated here.

[0113] The present application also provides a computer program product, including a computer program which, when executed by a processor, implements the steps of the interpolation position calculation method of the parallel time synchronizer as described above.

[0114] The computer program product provided by the present application can solve the technical problems that the parallel time synchronizer consumes a long time in calculating the interpolation position and has a high feedback delay. Compared with the prior art, the beneficial effects of the computer program product provided by the present application are the same as those of the interpolation position calculation method of the parallel time synchronizer provided by the above embodiments, and will not be elaborated herein.

[0115] The above are only partial embodiments of the present application, and thus do not limit the patent scope of the present application. Any equivalent structural transformation made under the technical concept of the present application by using the content of the specification and drawings of the present application, or any direct / indirect application in other related technical fields, is included in the patent protection scope of the present application.

Claims

1. A method for calculating an interpolation position of a parallel time synchronizer, characterized in that: The method comprises: Determining output data at the current moment based on the interpolation position and input data at the current moment; Determine the sampling period at the current moment based on the output data and the output valid flag at the current moment; Performing operation processing on the sampling period of the current moment to obtain an initial interpolation position of the target moment, wherein the operation processing at least includes multiplication operation processing, subtraction operation processing and division operation processing based on a fixed constant; Overflow correction is performed on the initial interpolation position at the target time to obtain the interpolation position at the target time.

2. The method according to claim 1, characterized in that The step of determining the output data at the current moment based on the interpolation position at the current moment and the input data comprises: Inputting the input data at the current moment into a plurality of parallel filters with different coefficients respectively, to obtain initial output data of the parallel filters at the current moment; Obtaining a first correspondence between the initial output data at the current moment, the interpolation position at the current moment, the filter weight and the output data at the current moment; The output data at the current moment is obtained based on the initial output data of the parallel filter at the current moment, the interpolation position at the current moment, the filter weight and the first corresponding relationship.

3. The method according to claim 1, characterized in that The step of determining the sampling period at the current moment based on the output data and the output valid flag at the current moment comprises: Determine the parallel error amount based on the output data and the output valid flag at the current moment; Based on the parallel error amount, determining an average error amount; Inputting the average error amount into a loop filter for filtering to obtain loop filtering data; Based on the loop filtering data, a sampling period at the current moment is determined.

4. The method according to claim 3, characterized in that The step of determining the parallel error amount based on the output data and the output valid flag at the current moment comprises: When the output valid flag at the current moment is a first value, using the first value as the parallel error amount; When the output valid flag at the current moment is a second value, a second corresponding relationship between the output data at the current moment and the parallel error amount is obtained, and the parallel error amount is obtained based on the output data at the current moment and the second corresponding relationship.

5. The method according to claim 1, characterized in that The step of performing calculation processing on the sampling period at the current moment to obtain the initial interpolation position at the target moment comprises: Based on a preset constant sequence, a multiplication operation is performed on the sampling period at the current moment to obtain a multiplication operation result; Subtracting the multiplication result from the stored value at the current moment to obtain a subtraction result, and updating the stored value at the target moment based on the subtraction result; Based on the fixed constant, the subtraction result is divided to obtain the initial interpolation position of the target time.

6. The method according to claim 5, characterized in that Before the step of performing overflow correction on the initial interpolation position at the target time to obtain the interpolation position at the target time, the method further includes: Determining an adjacent road subtraction result based on the subtraction result at the target time, the adjacent road subtraction result; Based on the adjacent path subtraction operation result, an output valid flag at the target time is determined.

7. The method according to claim 6, characterized in that The adjacent road subtraction result includes a subtraction result of a current road and a subtraction result of a preceding road. The step of determining the output valid flag at the target time based on the adjacent road subtraction result includes: When the subtraction result of the current path is less than or equal to the subtraction result of the previous path, the first value is used as the output valid flag corresponding to the current path; When the subtraction operation result of the current path is equal to the subtraction operation result of the previous path, the second value is used as the output valid flag corresponding to the current path.

8. The method according to claim 1, characterized in that The step of performing overflow correction on the initial interpolation position at the target time to obtain the interpolation position at the target time comprises: Acquire a third correspondence between an initial interpolation position at a target time, an output valid flag at a target time, and an interpolation position at a target time; Based on the initial interpolation position at the target time, the output valid flag at the target time, and the third corresponding relationship, the interpolation position at the target time is obtained.

9. An interpolation position calculation device for a parallel time synchronizer, characterized in that: The device comprises: A parallel filtering module, used for determining output data at the current moment based on the interpolation position and input data at the current moment; A sampling period estimation module, used to determine the sampling period at the current moment based on the output data and the output valid flag at the current moment; A numerically controlled oscillation module, used for performing arithmetic processing on the sampling period at the current moment to obtain an initial interpolation position at the target moment, wherein the arithmetic processing at least includes a multiplication operation processing, a subtraction operation processing, and a division operation processing based on a fixed constant; The digital controlled oscillation module is further used to perform overflow correction on the initial interpolation position at the target moment to obtain the interpolation position at the target moment.

10. An interpolation position calculation device for a parallel time synchronizer, characterized in that: The device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the interpolation position calculation method of the parallel time synchronizer according to any one of claims 1 to 8.

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