Signal period synchronization method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention discloses a signal period synchronization method and device, electronic equipment and a computer readable storage medium. The method comprises the following steps: determining a signal period corresponding to a vertical synchronization signal of a display controller; and adjusting the decoding frame rate of the decoding module according to the signal period. According to the signal period synchronization method provided by the embodiment of the invention, the decoding frame rate of the decoding module in the terminal equipment can be adjusted according to the signal period of the vertical synchronization signal, so that the phenomena of tearing and lagging of a display picture are avoided.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a signal period synchronization method, device, electronic device, and computer-readable storage medium. Background Art

[0002] In existing terminal devices, taking Android devices as an example, the signal frequency of the vertical synchronization signal (Vsync) received by the display hardware (such as a display or a graphics processing component, etc.) is usually 50Hz, while the frame rate (FPS) set by the terminal device for the graphics function component (such as an image synthesis component, etc.) in the display mode (Display Mode) is usually 60FPS, resulting in a mismatch between the vertical synchronization signal received by the display hardware and the frame rate set by the graphics function component, and ultimately the picture displayed on the display has problems such as tearing and freezing.

[0003] In order to solve the problems of tearing and freezing in the display screen, in the prior art, the Android device synthesizes the graphic data into multiple buffer data through the image synthesis component (Surface Flinger), and outputs the buffer data to the frame buffer of the hardware display, waiting for the graphics processing component (HWC) to process the buffer data before displaying it on the screen. The graphics processing group processes the buffer data instead of directly processing the data synthesized by the image synthesis component, which avoids the problems of tearing and freezing in the final display screen to a certain extent.

[0004] However, in actual applications, affected by various factors, the frame rate at which the image synthesis component (Surface Flinger) synthesizes and processes graphic data may not be the standard 60FPS. In this case, if the frame rate difference between the vertical synchronization signal received by the display hardware and the graphics function component is large, even if the buffer data is processed by the graphics processing group, the frame rate difference cannot be compensated, which will still cause the frame rate of the graphics function component to not match the signal period of the vertical synchronization signal received by the display hardware, and ultimately cause problems such as display screen tearing and freezes, affecting the user experience. Summary of the invention

[0005] The embodiments of the present application provide a signal period synchronization method, device, electronic device and computer-readable storage medium, which can adjust the decoding frame rate of the decoding module in the terminal device according to the signal period of the vertical synchronization signal, thereby avoiding tearing and freezing in the display screen.

[0006] In a first aspect, an embodiment of the present application provides a signal cycle synchronization method, which is applied to a terminal device, wherein the terminal device includes a display, a display controller, and a decoding module, and the method includes:

[0007] Determine a signal period corresponding to a vertical synchronization signal of the display controller;

[0008] The decoding frame rate of the decoding module is adjusted according to the signal period.

[0009] Optionally, in some embodiments of the present application, adjusting the image synthesis rate of the image synthesis component according to the signal period includes:

[0010] Adjusting the image synthesis rate of the image synthesis component according to the signal period, wherein the image synthesis rate is associated with a decoding frame rate;

[0011] or,

[0012] The image synthesis time of the image synthesis component is adjusted according to the signal cycle, and the graphics processing time of the graphics processing component is adjusted according to the signal cycle, wherein the image synthesis time and the graphics processing time are associated with a decoding frame rate.

[0013] Optionally, in some embodiments of the present application, adjusting the image synthesis rate of the image synthesis component according to the signal period includes:

[0014] Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second;

[0015] Determining a target synthesis rate of the image synthesis component according to the refresh frequency;

[0016] The image synthesis rate of the image synthesis component is adjusted to the target synthesis rate.

[0017] Optionally, in some embodiments of the present application, adjusting the image synthesis rate of the image synthesis component to the target synthesis rate includes:

[0018] Determining that the target synthesis rate satisfies a preset condition of the image synthesis component, wherein the preset condition is that a maximum image synthesis rate of the image synthesis component is greater than or equal to the target synthesis rate;

[0019] The image synthesis component is controlled to set the image synthesis rate to the target synthesis rate.

[0020] Optionally, in some embodiments of the present application, after adjusting the image synthesis rate of the image synthesis component to the target synthesis rate, the method further includes:

[0021] storing the target synthesis rate;

[0022] In response to a vertical synchronization signal having a signal cycle identical to a signal cycle corresponding to the target synthesis rate, the image synthesis component is controlled to perform an image synthesis operation according to the target synthesis rate.

[0023] Optionally, in some embodiments of the present application, before adjusting the image synthesis time of the image synthesis component according to the signal cycle and adjusting the graphics processing time of the graphics processing component according to the signal cycle, the method further includes:

[0024] The refresh time of the display is determined according to the signal period.

[0025] Optionally, in some embodiments of the present application, adjusting the decoding frame rate of the decoding module according to the signal period includes:

[0026] In response to the vertical synchronization signal, calling a time calculation function through a callback function;

[0027] Determining a target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining a target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining a target refresh time of the display according to the signal cycle and the time calculation function;

[0028] The image synthesis time of the image synthesis component is adjusted to the target synthesis time, the graphics processing time of the graphics processing component is adjusted to the target processing time, and the refresh time of the display is adjusted to the target refresh time.

[0029] Optionally, in some embodiments of the present application, determining the target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining the target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining the target refresh time of the display according to the signal cycle and the time calculation function include:

[0030] Determine the timestamp information of the vertical synchronization signal according to the signal period;

[0031] Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second;

[0032] The target synthesis time, the target processing time, and the target refresh time are determined according to the timestamp information and the refresh frequency.

[0033] In a second aspect, an embodiment of the present application further provides a signal cycle synchronization device, which is applied to a terminal device, wherein the terminal device includes a display, a display controller, and a decoding module. The device includes:

[0034] A processing module, used to determine a signal period corresponding to a vertical synchronization signal of the display controller;

[0035] The processing module is further used to adjust the decoding frame rate of the decoding module and the refresh time of the display according to the signal period.

[0036] Optionally, in some embodiments of the present application, the processing module is further used to:

[0037] Adjusting the image synthesis rate of the image synthesis component according to the signal period, wherein the image synthesis rate is associated with a decoding frame rate;

[0038] or,

[0039] The image synthesis time of the image synthesis component is adjusted according to the signal cycle, and the graphics processing time of the graphics processing component is adjusted according to the signal cycle, wherein the image synthesis time and the graphics processing time are associated with a decoding frame rate.

[0040] Optionally, in some embodiments of the present application, the processing module is further used to:

[0041] Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second;

[0042] Determining a target synthesis rate of the image synthesis component according to the refresh frequency;

[0043] The image synthesis rate of the image synthesis component is adjusted to the target synthesis rate.

[0044] Optionally, in some embodiments of the present application, the processing module is further used to:

[0045] Determining that the target synthesis rate satisfies a preset condition of the image synthesis component, wherein the preset condition is that a maximum image synthesis rate of the image synthesis component is greater than or equal to the target synthesis rate;

[0046] The image synthesis component is controlled to set the image synthesis rate to the target synthesis rate.

[0047] Optionally, in some embodiments of the present application, the processing module is further used to:

[0048] storing the target synthesis rate;

[0049] In response to a vertical synchronization signal having a signal cycle identical to a signal cycle corresponding to the target synthesis rate, the image synthesis component is controlled to perform an image synthesis operation according to the target synthesis rate.

[0050] Optionally, in some embodiments of the present application, the processing module is further used to:

[0051] The refresh time of the display is determined according to the signal period.

[0052] Optionally, in some embodiments of the present application, the processing module is further used to:

[0053] In response to the vertical synchronization signal, calling a time calculation function through a callback function;

[0054] Determining a target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining a target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining a target refresh time of the display according to the signal cycle and the time calculation function;

[0055] The image synthesis time of the image synthesis component is adjusted to the target synthesis time, the graphics processing time of the graphics processing component is adjusted to the target processing time, and the refresh time of the display is adjusted to the target refresh time.

[0056] Optionally, in some embodiments of the present application, the processing module is further used to:

[0057] Determine the timestamp information of the vertical synchronization signal according to the signal period;

[0058] Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second;

[0059] The target synthesis time, the target processing time, and the target refresh time are determined according to the timestamp information and the refresh frequency.

[0060] In a third aspect, an embodiment of the present application further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the steps in the above-mentioned signal period synchronization method are implemented when the computer program is executed by the processor.

[0061] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps in the above-mentioned signal period synchronization method are implemented.

[0062] In a fifth aspect, the embodiments of the present application further provide a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. The processor of the computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in various optional implementations described in the embodiments of the present application.

[0063] In summary, the embodiment of the present application adopts a technical solution of determining the signal period corresponding to the vertical synchronization signal of the display controller; adjusting the decoding frame rate of the decoding module according to the signal period. The decoding frame rate of the decoding module of the terminal device can be adjusted according to the signal period of the vertical synchronization signal, thereby achieving the technical effect of avoiding tearing and freezing in the display screen and improving the smoothness of the display animation. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0065] Figure 1 It is a timing diagram of a signal cycle mismatch in the prior art;

[0066] Figure 2 It is a schematic diagram of a method for avoiding screen freeze in the prior art;

[0067] Figure 3 A schematic diagram of a scenario of a signal cycle synchronization method provided in an embodiment of the present application;

[0068] Figure 4 It is a schematic diagram of a scenario in which a smart device according to an embodiment of the present application executes the signal cycle synchronization method;

[0069] Figure 5 This is a schematic diagram of a process for adjusting the image synthesis rate of an image synthesis component provided by an embodiment of the present application;

[0070] Figure 6 This is a schematic diagram of a flow chart for adjusting image synthesis time, graphics processing time and refresh time provided by an embodiment of the present application;

[0071] Figure 7 is a structural diagram of a signal period synchronization device provided in an embodiment of the present application;

[0072] Figure 8 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] The following will be combined with the drawings in this application to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments in the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0074] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include one or more of the above features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0075] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the invention. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the invention can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the invention with unnecessary details. Therefore, the present invention is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

[0076] First, the terms involved in this application are explained:

[0077] HWC: Hardware Composer, a hardware abstraction layer (HAL) component in the Android system decoding module, is responsible for managing and optimizing the image synthesis process (hereinafter referred to as: graphics processing component).

[0078] Surface Flinger: It is the core component of the system services layer (System Services) in the Android system decoding module. It is responsible for image synthesis and display management to ensure that the graphics content of the application can be correctly displayed on the device screen (hereinafter referred to as: image synthesis component).

[0079] Vsync: vertical synchronization signal, a signal generated by the hardware (display controller) in Android devices, used to coordinate the refresh rate of the display device (display, graphics processing component, image synthesis component, etc.). For example, the hardware abstraction layer can use this signal to notify the display to perform refresh, drawing, and other operations.

[0080] Vsync-SF: can be used to indicate the time interval for the image synthesis component to receive the vertical synchronization signal. The vertical synchronization signal can be used by the image synthesis component to synthesize and update image frames. Generally, the signal frequency is equal to Vsync-APP.

[0081] Vsync-APP: can be used to indicate the time interval for an application to receive a vertical synchronization signal. The vertical synchronization signal can be used by the application to send graphic data. Generally, the signal frequency is equal to Vsync-SF.

[0082] Vsync-HWC: can be used to indicate the time interval for the graphics processing component to receive the vertical synchronization signal, which can be used by the graphics processing component to perform graphics combination, rendering and other operations.

[0083] Choreographer: A core class in the Android system that handles and coordinates drawing and animation on the user interface (UI) thread.

[0084] Binder IPC: A mechanism for inter-process communication in the Android system that allows different applications or components to communicate securely and efficiently.

[0085] Surface object: An important concept in the Android system, used to provide a drawing surface on which drawing operations can be performed. It can also be used to draw images and perform graphics rendering on the screen, and then display the results on the display.

[0086] In the prior art, such as Figure 1 As shown in the timing diagram of the signal period mismatch situation, the vertical synchronization signal sent by the display controller received by the display hardware such as the display and graphics processing component of the terminal device is usually 50Hz, while the frame rate set by the terminal device for functional components such as the image synthesis component through the display controller in the display mode is usually 60FPS. Therefore, there is a phenomenon that the frequency of display hardware displaying images is inconsistent with the frequency of functional components processing images, and some synthesized images cannot be displayed normally, resulting in tearing, stuttering and other problems in the picture finally displayed by the monitor.

[0087] For example, if a region adopts the PAL (Phase Alternating Line, a broadcast television standard) standard, under this standard, the refresh rate of the display is 50 Hz, that is, the display refreshes 50 times per second, and the graphics processing component can perform graphics processing 50 times per second (corresponding to 50FPS, and the corresponding vertical synchronization signal period is 20ms); and the display controller sets the frame rate of the image synthesis component to 60FPS under the PAL standard, and the corresponding vertical synchronization signal period is 16.67ms. Therefore, the frame rate of the image synthesis component synthesizing the image is greater than the frame rate of the graphics processing component processing the image, resulting in the following error: Figure 1 The image at time T5 shown cannot be combined and displayed in time, resulting in problems of freezing and tearing in the final displayed image.

[0088] In the prior art, in order to avoid the above-mentioned problems such as image freeze and tearing, Figure 2 The schematic diagram of the method for avoiding screen freeze in the prior art is shown, and the display controller sends the corresponding vertical synchronization signals to the graphics processing component, the image synthesis component and the application APP respectively (it is also possible not to send the vertical synchronization signal to the application). The application generates a Surface object based on the graphics data, and the image synthesis component of the system service layer synthesizes the Surface object into multiple buffer data according to the vertical synchronization signal, and then outputs the buffer data to the buffer for caching, and waits for the graphics processing component to process the buffer data according to the vertical synchronization signal to obtain the final image data for display on the screen. Since the graphics processing component processes the buffer data instead of directly processing the data synthesized by the image synthesis component, even if the signal periods of the vertical synchronization signals of the graphics processing component and the image synthesis component are inconsistent, the tearing, freeze and other problems of the final display screen can be avoided to a certain extent.

[0089] However, in actual applications, it may be affected by various factors, resulting in the frame rate of the image synthesis component performing synthesis processing on the graphic data being different from the frame rate corresponding to the vertical synchronization signal sent by the display controller. In this case, if the vertical synchronization signal received by the graphics processing component is significantly different from the frame rate of the synthesis processing performed by the image synthesis component, for example, the synthesis rate of the image synthesis component is much greater than the processing rate of the graphics processing component (that is, the frame rate of the graphics processing component is greater than the refresh rate of the display, and the refresh rate of the display corresponds to the processing rate of the graphics processing component), even if there is a buffer, the frame rate of the image synthesis component will still not match the signal period of the vertical synchronization signal received by the display hardware, and eventually problems such as display screen tearing and freezing will occur, affecting the user experience.

[0090] Therefore, the existing methods for avoiding screen freezes still have the problem of screen tearing and freezes caused by the mismatch between the frame rate of the image synthesis component and the signal cycle of the graphics processing, which will directly affect the user experience.

[0091] The embodiment of the present application provides a signal cycle synchronization method, device, electronic device and computer readable storage medium. A technical solution is adopted to determine the signal cycle corresponding to the vertical synchronization signal of the display controller; and adjust the decoding frame rate of the decoding module and the refresh time of the display according to the signal cycle.

[0092] In summary, the signal period synchronization method in the embodiment of the present application can adjust the decoding frame rate of the terminal device decoding module and the refresh time of the display according to the signal period of the vertical synchronization signal, so that the decoding frame rate corresponds to the refresh time, thereby achieving the technical effect of avoiding display screen tearing and freezing and improving the smoothness of display animation.

[0093] It should be noted that the order of description of the following embodiments is not intended to limit the priority order of the embodiments.

[0094] See also Figure 3 , Figure 3 The schematic diagram of the scenario of the signal cycle synchronization method provided in the embodiment of the present application, the signal cycle synchronization system may include a terminal device 100, the terminal device 100 includes a display 200, a display controller 300 and a decoding module 400, the display 200, the display controller 300 and the decoding module 400 may be connected to each other in any manner, including but not limited to signal communication through electronic circuits, communication through wireless signals, and the wireless signal may be a computer network communication of the TCP / IP protocol suite (TCP / IP Protocol Suite, TCP / IP), the user datagram protocol (User Datagram Protocol, UDP), etc. The terminal device 100 may receive a control signal from a remote control or a control panel, and the terminal device 100 may send the control signal to the display 200 and the decoding module 400 through the display controller 300, the display 200 and the decoding module 400 may receive the instruction information sent by the display controller 300, and the display 200 and the decoding module 400 may perform corresponding operations according to the corresponding instruction information.

[0095] In the embodiment of the present application, the terminal device 100 includes but is not limited to a television, a mobile phone, a tablet, a computer, etc.

[0096] Those skilled in the art will understand that Figure 3 The application environment shown in the figure is only one application scenario of the present application solution and does not constitute a limitation on the application scenario of the present application solution. Other application environments may also include Figure 3 More or fewer terminal devices as shown in, for example Figure 3 Only one terminal device is shown, and no specific limitation is given here.

[0097] In addition, if Figure 3 As shown, the display 200 may include any physical display device capable of displaying images, such as a screen or a projector embedded in the terminal device, and the specific details are not limited here.

[0098] In addition, Figure 3 As shown, the display controller 300 may include any hardware device capable of data processing and instruction sending, such as a CPU, a GPU, a chip SOC, a single-chip microcomputer, etc., which is embedded in the terminal device, and the specific details are not limited here.

[0099] In addition, Figure 3 As shown, the decoding module 400 may include any hardware device and / or software component capable of processing graphic data, such as a graphic processing component and an image synthesis component embedded in the terminal device, which is not specifically limited here.

[0100] It should be noted that Figure 3 The scenario diagram of the signal period synchronization system shown is merely an example. The signal period synchronization system and scenario described in the embodiment of the present application are intended to more clearly illustrate the technical solution of the embodiment of the present application, and do not constitute a limitation on the technical solution provided in the embodiment of the present application. A person of ordinary skill in the art can appreciate that with the evolution of the signal period synchronization system and the emergence of new business scenarios, the technical solution provided in the embodiment of the present application is equally applicable to similar technical problems.

[0101] For details, please refer to Figure 4 , Figure 4 : is a schematic diagram of a scenario in which a terminal device according to an embodiment of the present application performs the signal cycle synchronization method, wherein the specific execution process of the terminal device performing the signal cycle synchronization method is as follows:

[0102] S401: Determine a signal period corresponding to a vertical synchronization signal of a display controller.

[0103] In the embodiment of the present application, the terminal device includes a display, a display controller and a decoding module, and the decoding module also includes at least a graphics processing component and an image synthesis component. In the terminal device of the embodiment of the present application, the display controller sends a vertical synchronization signal to the graphics processing component in the decoding module. Therefore, the signal period of the vertical synchronization signal can be determined according to the time interval at which the display controller of the terminal device sends the vertical synchronization signal.

[0104] In the embodiment of the present application, the display and the decoding module can be controlled by a display controller, and can also be controlled by other controllers other than the display controller (for example, a processor CPU, etc.).

[0105] Specifically, the vertical synchronization signal sent by the display controller can be determined according to the refresh frequency of the display. For example, the refresh frequency of the display is 50 Hz, that is, the display is refreshed 50 times per second. Accordingly, the graphics processing component can process at a rate of 50 images per second. The display controller can determine that the signal period of the vertical synchronization signal sent to the graphics processing component is 20ms according to the refresh frequency of the display, that is, the vertical synchronization signal is sent every 20ms to control the graphics processing component to process one image data every 20ms.

[0106] Optionally, the refresh rate of the display may be set by the user, or may be automatically selected by the display controller according to the hardware or software properties of the terminal device. When the user sets the refresh rate, the display controller may determine the transmission period of the vertical synchronization signal according to the user's setting value; when the display controller automatically selects the refresh rate according to the hardware or software properties of the terminal device, the display controller may send the selected refresh rate to the display to control the display to perform a refresh operation.

[0107] As an optional embodiment, the vertical synchronization signal and the signal period corresponding to the vertical synchronization signal may also be directly obtained through the interface for interaction between the display controller and the graphics processing system, for example, by detecting the state of the vertical synchronization signal through a vertical synchronization pin.

[0108] It should be noted that the interface may include but is not limited to: a VGA interface, a DVI interface, an HDMI interface, a DisplayPort interface, etc.

[0109] It should also be noted that the display controller can also determine the refresh frequency of the display through an interactive interface with the display, and the method for determining the refresh frequency of the display is not specifically limited in the embodiments of the present application.

[0110] Specifically, in the process of directly acquiring the vertical synchronization signal and the signal period corresponding to the vertical synchronization signal through the interface for interaction between the display controller and the graphics processing system, a corresponding signal acquisition function (for example: DisplayDevice:getVsyncPeriodFromHWC) can be pre-set for the relevant interaction interface to obtain the signal period of the vertical synchronization signal. The pre-set signal acquisition function is defined in the DisplayDevice class (an object used to represent and manage display devices) or a related graphics rendering class, and the signal acquisition function can be used to communicate with the graphics processing component to obtain the signal period of the vertical synchronization signal of the current graphics processing component.

[0111] It should be noted that in the Android system, each physical display device (such as a display screen, a projector, etc.) can be represented by a DisplayDevice class. The DisplayDevice class provides properties and methods related to the terminal device so that the system can correctly manage and control the terminal device.

[0112] It should also be noted that the getVsyncPeriodFromHWC function is used to obtain the vertical synchronization period from the graphics processing component. The implementation of the DisplayDevice class and the getVsyncPeriodFromHWC function may vary depending on the specific application or hardware platform. The embodiment of the present application is only an example, and the actual implementation method may be adjusted according to the needs.

[0113] As an optional embodiment, the frame callback monitoring may also be registered through Choreographer to obtain the signal period corresponding to the vertical synchronization signal received by the graphics processing system.

[0114] Specifically, a vertical synchronization signal listener may be registered in the ViewRootImpl class of the Android system to sense changes in the signal frequency, thereby determining the signal period of the vertical synchronization signal.

[0115] It should be noted that the ViewRootImpl class is a key class in the Android system, which can be used to manage the view hierarchy of an application and handle user interactions.

[0116] S402: Adjust the decoding frame rate of the decoding module and the refresh time of the display according to the signal period.

[0117] In an embodiment of the present application, after determining the signal period of the vertical synchronization signal, the graphics processing rate of the graphics processing component in the decoding module and / or the image synthesis rate of the image synthesis component can be adjusted according to the signal period, thereby adjusting the decoding frame rate of the decoding module; the refresh time of the display can also be adjusted according to the signal period, that is, the time for the display to refresh the screen.

[0118] Optionally, the signal period synchronization method provided in the embodiment of the present application further includes: adjusting the image synthesis rate of the image synthesis component according to the signal period.

[0119] In the embodiment of the present application, the image synthesis rate is associated with the decoding frame rate. The image synthesis rate is used to characterize the number of times the image synthesis component performs image synthesis per second. The image synthesis rate can be understood as the frame rate of the image synthesis component, such as Figure 5 As shown in the flowchart of adjusting the image synthesis rate of the image synthesis component, the terminal device can send a vertical synchronization signal to the graphics processing component at a certain period according to the refresh frequency of the display through the display controller, and after determining the signal period of the vertical synchronization signal, calculate the frame rate corresponding to the signal period, and apply the frame rate to the image synthesis component, so that the image synthesis component performs image synthesis processing according to the image synthesis rate corresponding to the frame rate.

[0120] It should be noted that the graphics processing component will perform graphics processing operations according to the vertical synchronization signal. After determining the frame rate corresponding to the signal period of the vertical synchronization signal and applying it to the image synthesis component, the graphics processing rate of the graphics processing component can be made consistent with the image synthesis rate of the image synthesis component, thereby avoiding tearing and stuttering problems in the display screen.

[0121] Optionally, the signal cycle synchronization method provided in the embodiment of the present application also includes: determining the refresh frequency corresponding to the display under the signal cycle, wherein the refresh frequency is the number of times the display is refreshed per second; determining the target synthesis rate of the image synthesis component based on the refresh frequency; and adjusting the image synthesis rate of the image synthesis component to the target synthesis rate.

[0122] In an embodiment of the present application, the vertical synchronization signal received by the graphics processing component is the data of the hardware abstraction layer in the Android system, and the image synthesis component is a functional component of the system service layer. The functional components of the system service layer cannot directly use the data of the hardware abstraction layer. Therefore, the system middle layer is required to calculate the refresh frequency of the display according to the signal period of the vertical synchronization signal received by the graphics processing component, and determine the image synthesis rate of the image synthesis component according to the refresh frequency, so as to realize the application of the frame rate corresponding to the data of the hardware abstraction layer to the functional components of the system service layer.

[0123] For example, if the vertical synchronization signal received by the graphics processing component has a signal period of 20ms (corresponding to 50FPS), the refresh rate of the display can be reversely calculated to be 50Hz. Accordingly, it can be determined that the image synthesis component needs to perform image synthesis processing every 20ms.

[0124] In the embodiment of the present application, after the image synthesis rate of the image synthesis component is calculated, the image synthesis component can be adjusted to the image synthesis rate.

[0125] Optionally, the rate at which the application generates Surface objects based on graphics data can also be set to the same rate as the image synthesis rate of the image synthesis component.

[0126] For example, after determining that the image synthesis component needs to perform image synthesis processing every 20ms, the rate at which the application generates Surface objects based on graphic data can also be set to perform Surface object generation operations every 20ms, so that the image synthesis component has enough Surface objects for image synthesis within every 20ms.

[0127] Optionally, the signal period synchronization method provided in the embodiment of the present application further includes: determining that the target synthesis rate satisfies a preset condition of the image synthesis component; and controlling the image synthesis component to set the image synthesis rate to the target synthesis rate.

[0128] In the embodiment of the present application, the preset condition is that the maximum image synthesis rate of the image synthesis component is greater than or equal to the target synthesis rate, that is, the maximum image synthesis rate of the image synthesis component is greater than or equal to the refresh frequency corresponding to the target synthesis rate.

[0129] For example, the maximum image synthesis rate of the image synthesis component is 144 image synthesis processes per second (144FPS, the corresponding refresh frequency is 144Hz), and the target synthesis rate is 50 image synthesis processes per second (50FPS, the corresponding refresh frequency is 50Hz), that is, the maximum image synthesis rate is greater than the target synthesis rate. If the preset conditions are met, the image synthesis rate of the image synthesis component can be set to the target synthesis rate.

[0130] It should be noted that the maximum image synthesis rate of the image synthesis component can be determined according to the hardware and software properties of the terminal device.

[0131] Specifically, when the preset conditions are met, the frame rate setting function (setFrameRate) can be used to set the image synthesis rate of the image synthesis component to be consistent with the refresh frequency of the display (the refresh frequency of the display corresponds to the graphics processing rate of the graphics processing component), that is, the graphics processing component performs graphics processing according to the frame rate corresponding to the signal period of the vertical synchronization signal, the display will also be refreshed according to the refresh frequency corresponding to the frame rate, and the image synthesis component will also perform image synthesis according to the frame rate, thereby achieving consistency between the image synthesis rate of the image synthesis component, the processing rate of the graphics processing component and the refresh frequency of the display, thereby avoiding tearing, stuttering and other phenomena in the display.

[0132] Optionally, the frame rate setting function (setFrameRate) can be used to set the generation rate of the Surface object to be consistent with the refresh rate of the display (the refresh rate of the display corresponds to the graphics processing rate of the graphics processing component). In this process, the display will refresh according to the graphics processing rate of the graphics processing component (or the graphics processing component will perform graphics processing according to the refresh rate of the display), and the image synthesis component will also perform image synthesis according to the refresh frequency or the graphics processing rate; setting the generation rate of the Surface object to be consistent with the image synthesis rate through the frame rate setting function can ensure that the image synthesis component has enough Surface objects for image synthesis operations, thereby further avoiding the occurrence of image tearing and jamming.

[0133] After adjusting the image synthesis rate of the image synthesis component to the target synthesis rate, optionally, the signal period synchronization method provided in the embodiment of the present application also includes: storing the target synthesis rate; in response to a vertical synchronization signal having a signal period identical to the signal period corresponding to the target synthesis rate, controlling the image synthesis component to perform an image synthesis operation according to the target synthesis rate.

[0134] In an embodiment of the present application, if the hardware and software performance of the image synthesis component support the target synthesis rate, the target synthesis rate (or the frame rate corresponding to the target synthesis rate) can be stored. When the frame rate corresponding to the signal period of the vertical synchronization signal sent by the display controller next time (or each time thereafter) is the same as the frame rate corresponding to the target synthesis rate, the stored target synthesis rate can be directly called to perform image synthesis operations.

[0135] For example, if the hardware and software support the requested frame rate, the image composition component can convert the target composition rate into a SurfaceFlinger\Client object and store the converted SurfaceFlinger\Client object in the terminal device.

[0136] Optionally, the terminal device may also store the generation rate of the Surface object, so that when the frame rate corresponding to the signal period of the vertical synchronization signal sent by the display controller next time (or each time thereafter) is the same as the frame rate corresponding to the generation rate of the Surface object, the stored Surface object generation rate can be directly called to perform the Surface object generation operation.

[0137] It should be noted that the terminal device can send the target synthesis rate from the display controller to the image synthesis component through the Binder IPC mechanism.

[0138] Optionally, the signal cycle synchronization method provided in the embodiment of the present application further includes: adjusting the image synthesis time of the image synthesis component according to the signal cycle, and adjusting the graphics processing time of the graphics processing component according to the signal cycle.

[0139] In the embodiment of the present application, the image synthesis time and the graphics processing time are associated with the decoding frame rate. The image synthesis time is the time it takes for the image synthesis component to perform image synthesis, and the graphics processing time is the time it takes for the graphics processing component to perform graphics processing.

[0140] Before adjusting the image synthesis time of the image synthesis component according to the signal period and adjusting the graphics processing time of the graphics processing component according to the signal period, optionally, the signal period synchronization method provided in the embodiment of the present application further includes: determining the refresh time of the display according to the signal period.

[0141] In the embodiment of the present application, the refresh time refers to the time it takes for the display to refresh the screen.

[0142] In the embodiments of the present application, Figure 6 As shown in the flowchart of adjusting the image synthesis time, graphics processing time and refresh time, the terminal device can send a vertical synchronization signal to the graphics processing component at a certain period through the display controller, and in response to the vertical synchronization signal, call other functions through the callback function, and calculate the image synthesis time, graphics processing time and refresh time according to the vertical synchronization signal through the other functions, so that the image synthesis component performs image synthesis at this time, the graphics processing component performs graphics processing at this time, and the display refreshes the screen at this time, thereby avoiding the problems of tearing and freezing in the display.

[0143] It should be noted that adjusting the image synthesis rate is different from adjusting the image synthesis time. The image synthesis rate corresponds to the frame rate of the image synthesis component. Adjusting the rate will cause the frame rate to change. For example, adjusting from 120FPS to 60FPS means that the image synthesis component is adjusted from synthesizing 120 images per second to synthesizing 60 images per second. The image synthesis time is the time it takes for the image synthesis component to perform synthesis. Only by adjusting the synthesis time, the frame rate may not necessarily change (correspondingly, the frame rate can also be adjusted to be different from before). For example, the image synthesis time is adjusted from synthesis at X1 second, X2 second, ..., Xn second (the difference between X1 second and X2 second is 1 second, ..., the difference between Xn-1 second and Xn second is 1 second) to synthesis at M1 second, M2 second, ..., Mn second (the difference between M1 second and M2 second is 1 second, ..., the difference between Mn-1 second and Mn second is 1 second). Although the synthesis time has changed, the overall synthesis rate has not changed.

[0144] It should also be noted that the graphics processing time, refresh time and image synthesis time are the same and will not be elaborated here. In addition, the above values ​​are only examples and can be adjusted or modified according to actual conditions in actual applications.

[0145] Optionally, the signal cycle synchronization method provided by the embodiment of the present application also includes: in response to a vertical synchronization signal, calling a time calculation function through a callback function; determining a target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining a target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining a target refresh time of the display according to the signal cycle and the time calculation function; adjusting the image synthesis time of the image synthesis component to the target synthesis time, adjusting the graphics processing time of the graphics processing component to the target processing time, and adjusting the refresh time of the display to the target refresh time.

[0146] In an embodiment of the present application, in response to a vertical synchronization signal sent by a display controller, a time calculation function can be called through a callback function, and the time calculation function can calculate the target synthesis time of the image synthesis component, the target processing time of the graphics processing component and the target refresh time of the display based on the timestamp of the vertical synchronization signal.

[0147] Optionally, the signal cycle synchronization method provided in an embodiment of the present application also includes: determining the timestamp information of the vertical synchronization signal based on the signal cycle; determining the refresh frequency of the display corresponding to the signal cycle, wherein the refresh frequency is the number of times the display refreshes per second; determining the target synthesis time, target processing time, and target refresh time based on the timestamp information and the refresh frequency.

[0148] In the embodiment of the present application, the time calculation function can be used to calculate the next refresh time and the graphics processing time. The formula is as follows:

[0149] NextVsyncTimeNanos=frameTimeNanos+(long)(1000000000 / (1000 / framePeriod));

[0150] Among them, NextVsyncTimeNanos: the time of the next synchronous refresh; frameTimeNanos: the timestamp of the current vertical synchronization signal; framePeriod: the refresh period of the current screen; 1000 / framePeriod calculates the refresh frequency of one second, in Hz.

[0151] In an embodiment of the present application, after calculating the target synthesis time of the synthesis component, the target processing time of the graphics processing component and the target refresh time of the display, the image synthesis component is controlled to adjust the next image synthesis time to the target synthesis time, the graphics processing component is controlled to adjust the next graphics processing time to the target processing time, and the display is controlled to adjust the next refresh time to the target refresh time, thereby avoiding tearing and freezing problems in the display.

[0152] Through the embodiments of the present application, a technical solution is adopted to determine the signal period corresponding to the vertical synchronization signal of the display controller; the decoding frame rate of the decoding module and the refresh time of the display are adjusted according to the signal period. The decoding frame rate of the decoding module of the terminal device and the refresh time of the display can be adjusted according to the signal period of the vertical synchronization signal, so that the decoding frame rate corresponds to the refresh time, thereby achieving the technical effect of avoiding display screen tearing and freezing and improving the smoothness of display animation.

[0153] In order to better implement the signal cycle synchronization method of the present application, the present application also provides a signal cycle synchronization device based on the above signal cycle synchronization method. The meanings of the terms are the same as those in the above signal cycle synchronization method, and the specific implementation details can refer to the description in the method embodiment.

[0154] See also Figure 7 , Figure 7 : is a schematic diagram of the structure of a signal cycle synchronization device provided in an embodiment of the present application, wherein the signal cycle synchronization device 700 is applied to a terminal device, and specifically can be as follows:

[0155] The processing module 701 is used to determine the signal period corresponding to the vertical synchronization signal of the display controller;

[0156] The processing module 701 is further configured to adjust the decoding frame rate of the decoding module according to the signal period.

[0157] Optionally, in some embodiments of the present application, the processing module 701 is further configured to:

[0158] Adjusting the image synthesis rate of the image synthesis component according to the signal period, wherein the image synthesis rate is associated with a decoding frame rate;

[0159] or,

[0160] The image synthesis time of the image synthesis component is adjusted according to the signal cycle, and the graphics processing time of the graphics processing component is adjusted according to the signal cycle, wherein the image synthesis time and the graphics processing time are associated with a decoding frame rate.

[0161] Optionally, in some embodiments of the present application, the processing module 701 is further used to:

[0162] Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second;

[0163] Determining a target synthesis rate of the image synthesis component according to the refresh frequency;

[0164] The image synthesis rate of the image synthesis component is adjusted to the target synthesis rate.

[0165] Optionally, in some embodiments of the present application, the processing module 701 is further used to:

[0166] Determining that the target synthesis rate satisfies a preset condition of the image synthesis component, wherein the preset condition is that a maximum image synthesis rate of the image synthesis component is greater than or equal to the target synthesis rate;

[0167] The image synthesis component is controlled to set the image synthesis rate to the target synthesis rate.

[0168] Optionally, in some embodiments of the present application, the processing module 701 is further used to:

[0169] storing the target synthesis rate;

[0170] In response to a vertical synchronization signal having a signal cycle identical to a signal cycle corresponding to the target synthesis rate, the image synthesis component is controlled to perform an image synthesis operation according to the target synthesis rate.

[0171] Optionally, in some embodiments of the present application, the processing module 701 is further used to:

[0172] The refresh time of the display is determined according to the signal period.

[0173] Optionally, in some embodiments of the present application, the processing module 701 is further used to:

[0174] In response to the vertical synchronization signal, calling a time calculation function through a callback function;

[0175] Determining a target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining a target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining a target refresh time of the display according to the signal cycle and the time calculation function;

[0176] The image synthesis time of the image synthesis component is adjusted to the target synthesis time, the graphics processing time of the graphics processing component is adjusted to the target processing time, and the refresh time of the display is adjusted to the target refresh time.

[0177] Optionally, in some embodiments of the present application, the processing module 701 is further used to:

[0178] Determine the timestamp information of the vertical synchronization signal according to the signal period;

[0179] Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second;

[0180] The target synthesis time, the target processing time, and the target refresh time are determined according to the timestamp information and the refresh frequency.

[0181] In the embodiment of the present application, the processing module 701 first determines the signal period corresponding to the vertical synchronization signal of the display controller, and then the processing module 701 adjusts the decoding frame rate of the decoding module and the refresh time of the display according to the signal period.

[0182] Among them, the embodiment of the present application determines the signal period corresponding to the vertical synchronization signal of the display controller; and adjusts the decoding frame rate of the decoding module and the refresh time of the display according to the signal period. The decoding frame rate of the decoding module of the terminal device can be adjusted according to the signal period of the vertical synchronization signal, thereby achieving the technical effect of avoiding display screen tearing and freezing and improving the smoothness of display animation.

[0183] In addition, the present application also provides an electronic device, such as Figure 8 As shown, it shows a schematic diagram of the structure of the electronic device involved in this application, specifically:

[0184] The electronic device may include components such as a processor 801 with one or more processing cores, a memory 802 with one or more computer-readable storage media, a power supply 803, and an input unit 804. Those skilled in the art will appreciate that Figure 8The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0185] The processor 801 is the control center of the electronic device. It uses various interfaces and lines to connect various parts of the entire electronic device. By running or executing software programs and / or modules stored in the memory 802 and calling data stored in the memory 802, it performs various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole. Optionally, the processor 801 may include one or more processing cores; preferably, the processor 801 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 801.

[0186] The memory 802 can be used to store software programs and modules. The processor 801 executes various functional applications and data processing by running the software programs and modules stored in the memory 802. The memory 802 may mainly include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area may store data created according to the use of the electronic device, etc. In addition, the memory 802 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other volatile solid-state storage devices. Accordingly, the memory 802 may also include a memory controller to provide the processor 801 with access to the memory 802.

[0187] The electronic device also includes a power supply 803 for supplying power to each component. Preferably, the power supply 803 can be logically connected to the processor 801 through a power management system, so as to manage charging, discharging, and power consumption through the power management system. The power supply 803 can also include any components such as one or more DC or AC power supplies, recharging systems, power supply device debugging circuits, power converters or inverters, and power status indicators.

[0188] The electronic device may further include an input unit 804, which may be used to receive input digital or character information and generate keyboard, mouse, joystick, optical or trackball signal input related to user settings and function control.

[0189] Although not shown, the electronic device may further include a display unit, etc., which will not be described in detail herein. Specifically in this embodiment, the processor 801 in the electronic device will load the executable file corresponding to the process of one or more application programs into the memory 802 according to the following instructions, and the processor 801 will run the application program stored in the memory 802, thereby implementing the steps in any one of the signal cycle synchronization methods provided in the embodiments of the present application.

[0190] The embodiment of the present application determines the signal period corresponding to the vertical synchronization signal of the display controller; and adjusts the decoding frame rate of the decoding module and the refresh time of the display according to the signal period. The decoding frame rate of the decoding module of the terminal device can be adjusted according to the signal period of the vertical synchronization signal, thereby achieving the technical effect of avoiding display screen tearing and freezing and improving the smoothness of display animation.

[0191] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0192] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0193] To this end, the present application provides a computer-readable storage medium, on which a computer program is stored. The computer program can be loaded by a processor to execute the steps in any one of the signal period synchronization methods provided in the present application.

[0194] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0195] The computer-readable storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0196] Since the instructions stored in the computer-readable storage medium can execute the steps in any signal period synchronization method provided in the present application, the beneficial effects that can be achieved by any signal period synchronization method provided in the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0197] The above is a detailed introduction to a signal period synchronization method, device, electronic device and computer-readable storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A signal cycle synchronization method, characterized in that: Applied to a terminal device, the terminal device includes a display, a display controller and a decoding module, characterized in that the method includes: Determine a signal period corresponding to a vertical synchronization signal of the display controller; The decoding frame rate of the decoding module is adjusted according to the signal period.

2. The method according to claim 1, characterized in that The decoding module includes a graphics processing component and an image synthesis component, and the step of adjusting the decoding frame rate of the decoding module according to the signal period includes: Adjusting the image synthesis rate of the image synthesis component according to the signal period, wherein the image synthesis rate is associated with a decoding frame rate; or, The image synthesis time of the image synthesis component is adjusted according to the signal cycle, and the graphics processing time of the graphics processing component is adjusted according to the signal cycle, wherein the image synthesis time and the graphics processing time are associated with a decoding frame rate.

3. The method according to claim 2, characterized in that The step of adjusting the image synthesis rate of the image synthesis component according to the signal period includes: Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second; Determining a target synthesis rate of the image synthesis component according to the refresh frequency; The image synthesis rate of the image synthesis component is adjusted to the target synthesis rate.

4. The method according to claim 3, characterized in that The adjusting the image synthesis rate of the image synthesis component to the target synthesis rate includes: Determining that the target synthesis rate satisfies a preset condition of the image synthesis component, wherein the preset condition is that a maximum image synthesis rate of the image synthesis component is greater than or equal to the target synthesis rate; The image synthesis component is controlled to set the image synthesis rate to the target synthesis rate.

5. The method according to claim 4, characterized in that After adjusting the image synthesis rate of the image synthesis component to the target synthesis rate, the method further includes: storing the target synthesis rate; In response to a vertical synchronization signal having a signal cycle identical to a signal cycle corresponding to the target synthesis rate, the image synthesis component is controlled to perform an image synthesis operation according to the target synthesis rate.

6. The method according to claim 2, characterized in that Before adjusting the image synthesis time of the image synthesis component according to the signal cycle and adjusting the graphics processing time of the graphics processing component according to the signal cycle, the method further includes: The refresh time of the display is determined according to the signal period.

7. The method according to claim 6, characterized in that The step of adjusting the decoding frame rate of the decoding module according to the signal period includes: In response to the vertical synchronization signal, calling a time calculation function through a callback function; Determining a target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining a target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining a target refresh time of the display according to the signal cycle and the time calculation function; The image synthesis time of the image synthesis component is adjusted to the target synthesis time, the graphics processing time of the graphics processing component is adjusted to the target processing time, and the refresh time of the display is adjusted to the target refresh time.

8. The method according to claim 7, characterized in that The step of determining the target synthesis time of the image synthesis component according to the signal cycle and the time calculation function, determining the target processing time of the graphics processing component according to the signal cycle and the time calculation function, and determining the target refresh time of the display according to the signal cycle and the time calculation function comprises: Determine the timestamp information of the vertical synchronization signal according to the signal period; Determine a refresh frequency of the display corresponding to the signal period, wherein the refresh frequency is the number of refreshes of the display per second; The target synthesis time, the target processing time, and the target refresh time are determined according to the timestamp information and the refresh frequency.

9. A signal cycle synchronization device, characterized in that: Applied to a terminal device, the terminal device includes a display, a display controller and a decoding module, and the device includes: A processing module, used to determine a signal period corresponding to a vertical synchronization signal of the display controller; The processing module is further used to adjust the decoding frame rate of the decoding module and the refresh time of the display according to the signal period.

10. An electronic device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps in the signal period synchronization method according to any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in the signal period synchronization method according to any one of claims 1 to 8 are implemented.

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