Circuit board and electronic component package including same

Abstract

The invention provides a circuit board and an electronic component package including the same. The circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other, and having a cavity recessed from the first surface; a first heat dissipation pattern disposed on the second surface of the first insulating layer; and a heat dissipation portion connected to the first heat dissipation pattern and protruding into the cavity by penetrating through the first insulating layer.

Description

Technical Field

[0001] The present disclosure relates to a circuit board and an electronic component package including the circuit board. Background Art

[0002] The circuit board may have a circuit pattern formed using a conductive material such as copper on an insulating material. As electronic devices such as mobile phones in the field of information technology (IT) become smaller, a method of forming a cavity in a circuit board and accommodating an electronic component such as an integrated circuit (IC), an active element, or a passive element in the cavity has been proposed.

[0003] Electronic components housed in a cavity of a circuit board, such as an application processor (AP) or a dynamic random access memory (DRAM), have evolving performance, thereby causing a large amount of heat to be generated in the electronic components during rapid transmission of larger amounts of data.

[0004] Therefore, there is a need to develop a circuit board and an electronic component package including the circuit board, the circuit board having heat dissipation characteristics for the electronic components to exhibit more stable performance. Summary of the invention

[0005] The present disclosure provides a circuit board that can effectively absorb and dissipate heat generated in an electronic component while ensuring a mounting space for the electronic component, and an electronic component package including the same.

[0006] The present disclosure also provides a circuit board and an electronic component package including the same, which circuit board can use a structure having a heat dissipation effect for electronic components of various thicknesses and effectively absorbs and dissipates heat generated in the electronic components even when a circuit pattern layer has a complex design.

[0007] However, the problems to be solved by the embodiments of the present disclosure are not limited to the above-mentioned problems, and various extensions can be made within the scope of the spirit of the present disclosure included in the embodiments.

[0008] According to an embodiment, a circuit board includes: a first insulating layer having a first surface and a second surface opposite to each other and having a cavity recessed from the first surface; a first heat dissipation pattern disposed on the second surface of the first insulating layer; and a heat dissipation portion connected to the first heat dissipation pattern and protruding into the cavity by penetrating the first insulating layer.

[0009] The circuit board may further include a second insulating layer disposed on the second surface along a first direction to cover the first heat dissipation pattern and at least one circuit pattern layer disposed on the second surface. The first insulating layer may include an upper region overlapping the cavity in the first direction and a side region overlapping the cavity in a second direction perpendicular to the first direction, and the heat dissipation portion may protrude from the upper region.

[0010] The heat dissipation portion may include: a first portion buried in the first insulating layer; and a second portion extending from the first portion and protruding from the upper region.

[0011] The first insulating layer may have a groove in the upper region where the second portion is disposed, and the groove may surround the second portion.

[0012] The circuit board may further include a first pattern layer including the first heat dissipation pattern and a first circuit pattern layer disposed around the first heat dissipation pattern, wherein the first heat dissipation pattern may be connected to at least one other pattern layer.

[0013] The circuit board may further include a second heat dissipation pattern disposed on the first surface of the first insulating layer, wherein the first heat dissipation pattern may be connected to the second heat dissipation pattern.

[0014] The circuit board may further include: a second insulating layer disposed on the second surface along the first direction to cover at least one pattern layer including the first pattern layer; and a third heat dissipation pattern disposed on a fourth surface of the second insulating layer opposite to a third surface of the second insulating layer, the third surface of the second insulating layer being opposite to the second surface of the first insulating layer. The first heat dissipation pattern may be connected to the third heat dissipation pattern.

[0015] The heat dissipation portion may extend parallel to an edge of the cavity.

[0016] The circuit board may include a plurality of the heat dissipation portions, and the plurality of the heat dissipation portions may include partial heat dissipation portions aligned with each other in one direction.

[0017] The circuit board may include a plurality of the heat dissipation parts, and the plurality of the heat dissipation parts may be spaced apart from each other.

[0018] The heat dissipation part can be made of metal material.

[0019] According to another embodiment, an electronic component package includes: a first circuit board, having a cavity on one surface of the first circuit board; a second circuit board connected to the first circuit board; and an electronic component mounted on one surface of the second circuit board and accommodated in the cavity, wherein the first circuit board includes a first insulating layer, a first heat dissipation pattern and a heat dissipation portion, the first insulating layer having a first surface and a second surface opposite to each other and having the cavity recessed from the first surface, the first heat dissipation pattern being arranged on the second surface of the first insulating layer, and the heat dissipation portion being connected to the first heat dissipation pattern and protruding into the cavity by penetrating the first insulating layer.

[0020] The electronic component package may further include a second insulating layer disposed on the second surface along a first direction to cover the first heat dissipation pattern and at least one circuit pattern layer disposed on the second surface. The first insulating layer may include an upper region overlapping the cavity in the first direction and a side region overlapping the cavity in a second direction perpendicular to the first direction, and the heat dissipation portion may protrude from the upper region.

[0021] The heat dissipation portion may include: a first portion buried in the first insulating layer; and a second portion extending from the first portion and protruding from the upper region.

[0022] The first insulating layer may have a groove in the upper region where the second portion is disposed, and a width of the groove may be greater than a width of the second portion.

[0023] The electronic component package may further include a first pattern layer including the first heat dissipation pattern and a first circuit pattern layer disposed around the first heat dissipation pattern, and the first heat dissipation pattern may be connected to at least one other pattern layer.

[0024] The electronic component package may further include a second heat dissipation pattern disposed on the first surface of the first insulating layer, wherein the first heat dissipation pattern may be connected to the second heat dissipation pattern.

[0025] The electronic component package may also include: a second insulating layer, arranged on the second surface along the first direction to cover at least one pattern layer including the first pattern layer; and a third heat dissipation pattern, arranged on a fourth surface of the second insulating layer opposite to the third surface of the second insulating layer, the third surface of the second insulating layer is opposite to the second surface of the first insulating layer, wherein the first heat dissipation pattern is connected to the third heat dissipation pattern.

[0026] The heat dissipation portion may extend parallel to an edge of the cavity.

[0027] The circuit board may include the plurality of heat dissipation portions, and the plurality of heat dissipation portions may include partial heat dissipation portions aligned with each other in one direction. As described above, the present disclosure may provide a circuit board and an electronic component package including the circuit board, which may effectively absorb and dissipate heat generated in the electronic component while ensuring an installation space for the electronic component.

[0028] The present disclosure may also provide a circuit board and an electronic component package including the same, which circuit board may use a structure having a heat dissipation effect for electronic components of various thicknesses and effectively absorb and dissipate heat generated in the electronic components even when the circuit pattern layer has a complex design. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a cross-sectional view of a circuit board according to an embodiment.

[0030] Figure 2 It is schematically shown Figure 1 A plan view of one surface of a circuit board.

[0031] Figures 3 to 15 is a cross-sectional view illustrating a method of manufacturing a circuit board according to an embodiment.

[0032] Fig.16 is a cross-sectional view schematically showing an electronic component package according to another embodiment.

[0033] Fig.17 is a cross-sectional view of a circuit board in another example.

[0034] Fig.18 is a plan view schematically showing one surface of a circuit board in still another example. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure belongs can easily practice the present disclosure. Parts not related to the description are omitted to clearly describe the present disclosure, and the same or similar components are represented by the same or similar reference numerals throughout the specification. In addition, some components are exaggerated, omitted or schematically shown in the drawings, and the size of each of the components in the drawings does not fully reflect its actual size.

[0036] It should be understood that the drawings are provided only to facilitate understanding of the embodiments of the present disclosure, and the spirit of the present disclosure is not limited by the drawings, and includes all modifications, equivalents, and substitutes included in the spirit and scope of the present disclosure.

[0037] Terms including ordinal numbers such as "first", "second", etc. may be used to describe various components. However, these components are not limited by these terms. These terms are only used to distinguish one component from another component.

[0038] In addition, when an element such as a layer, film, region, or plate is referred to as being "on" or "over" another element, the element may be "directly on" the other element, or other elements may be present between them. On the other hand, when an element is referred to as being "directly on" another element, there are no other elements present between them. In addition, when an element is referred to as being "on" or "over" a reference element, the element may be disposed under or below the reference element, and may not necessarily be located "on" or "over" the reference element in a direction opposite to the direction of gravity.

[0039] It should be understood that the terms "including" and "having" used in the specification specify the presence of the features, quantities, steps, operations, components, parts or combinations thereof mentioned in the specification, and do not exclude the presence or addition of one or more other features, quantities, steps, operations, components, parts or combinations thereof. Therefore, unless explicitly described to the contrary, "including" any component should be understood to mean including other components rather than excluding other components.

[0040] Furthermore, throughout the specification, the expression “on a plane” may refer to a case where a target is viewed from the top, and the expression “on a cross section” may refer to a case where a cross section taken in a vertical direction of a target is viewed from a side thereof.

[0041] Throughout the specification, when an element is referred to as being “coupled to” another element, this may mean not only that the element and the other element are “directly or physically coupled to” each other, but also that the element and the other element are “indirectly or non-contact coupled to” each other with other elements interposed therebetween.

[0042] Furthermore, when it is mentioned that any one component is “connected to” another component, this may mean not only that two or more components are directly connected to each other but also that two or more components are indirectly connected to each other through other components, not only that two or more components are physically connected to each other but also that two or more components are electrically connected to each other, or that two or more components are a single entity although referred to by different names based on their positions or functions.

[0043] Hereinafter, various embodiments and modified examples of the present disclosure are described in detail with reference to the accompanying drawings.

[0044] Reference Figure 1 and Figure 2 A circuit board according to an embodiment is described. Figure 1 is a cross-sectional view of a circuit board according to an embodiment, Figure 2It is schematically shown Figure 1 A plan view of one surface of a circuit board.

[0045] Reference Figure 1 , the circuit board 10 according to this embodiment may include: a first insulating layer 110 having a first surface and a second surface opposite to each other and having a cavity 111 recessed from the first surface; a first heat dissipation pattern 131 disposed on the second surface of the first insulating layer 110; and a heat dissipation portion 200 connected to the first heat dissipation pattern 131. The heat dissipation portion 200 may protrude into the cavity 111 by penetrating the first insulating layer 110.

[0046] The circuit board 10 according to this embodiment may include a plurality of insulating layers 110 and 120. The plurality of insulating layers may include a first insulating layer 110 and a second insulating layer 120 disposed on the first insulating layer 110. Each of the plurality of insulating layers may be made of an insulating material, and the insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material formed by impregnating an inorganic filler such as silica and a reinforcing material such as glass fiber in such a resin. For example, each of the plurality of insulating layers may be made of a prepreg or a resin coated copper (RCC) foil, but is not limited thereto, and a material that does not include a reinforcing material such as glass fiber, such as an Ajinomoto deposited film (ABF), may be used. When necessary, each of the plurality of insulating layers may be made of a photosensitive insulating material such as a photosensitive dielectric (PID).

[0047] The first insulating layer 110 may have a first surface and a second surface opposite to each other. The cavity 111 may be provided in the first surface of the first insulating layer 110. The first insulating layer 110 may have a cavity 111 recessed from the first surface. The cavity 111 may be recessed by recessing from the first surface of the first insulating layer 110. The cavity 111 may be formed by an etching process. In addition, the circuit board 10 may be an interposer connected to a board of an electronic component. In this case, the sealant 23 (see Fig.16 ) can be set in the cavity 111.

[0048] The second insulating layer 120 may be stacked along a first direction on the second surface of the first insulating layer 110. The first direction may refer to a direction in which a plurality of insulating layers are stacked. The second insulating layer 120 may bury at least one circuit pattern layer therein.

[0049] Reference Figure 1 , the second insulating layer 120 is shown as a layer in which one circuit pattern layer is buried, and is not limited thereto. Compared with the number of circuit pattern layers shown in the drawings, the second insulating layer 120 may bury more circuit pattern layers therein, or may not bury any circuit pattern layer.

[0050] The circuit board 10 according to one embodiment may further include a plurality of pattern layers. Each of the plurality of pattern layers may be located on one surface of the first insulating layer 110 or the second insulating layer 120. Each of the plurality of pattern layers 130, 140, and 150 may include heat dissipation patterns 131, 141, and 151. Each of the plurality of pattern layers 130, 140, and 150 may further include circuit pattern layers 132, 142, and 152. Each of the circuit pattern layers 132, 142, and 152 may be disposed around the corresponding heat dissipation patterns 131, 141, and 151.

[0051] Reference Figure 1 , the first pattern layer 130 may include a first heat dissipation pattern 131 and a first circuit pattern layer 132 disposed around the first heat dissipation pattern 131. The second pattern layer 140 may include a second heat dissipation pattern 141 and a second circuit pattern layer 142 disposed around the second heat dissipation pattern 141. The third pattern layer 150 may include a third heat dissipation pattern 151 and a third circuit pattern layer 152 disposed around the third heat dissipation pattern 151. Figure 1 Each of the second pattern layer 140 and the third pattern layer 150 is illustrated as including a heat dissipation pattern and a circuit pattern layer, but is not limited thereto, and the second pattern layer 140 and the third pattern layer 150 may include any one of the heat dissipation pattern and the circuit pattern layer.

[0052] exist Figure 1 In the figure, only the first circuit pattern layer 132, the second circuit pattern layer 142 and the third circuit pattern layer 152 are shown, but it is not limited thereto, and a greater number of circuit pattern layers may be provided or a fewer number of circuit pattern layers may be provided than the number shown.

[0053] The circuit board 10 according to this embodiment may include a plurality of circuit pattern layers 132, 142 and 152. Each of the plurality of circuit pattern layers may be arranged in or on a corresponding one of the insulating layers 110 and 120. The circuit pattern layers 132, 142 and 152 may transmit the signal of the circuit board 10. The circuit pattern layers 132, 142 and 152 may be made of metal materials. The metal materials may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), their alloys, etc. The circuit pattern layers 132, 142 and 152 may perform various functions based on their design, such as being used as ground patterns, power patterns or signal patterns. Each of these patterns may have a linear shape, a planar shape or a pad shape. The circuit pattern layer arranged as the outermost layer among the plurality of circuit pattern layers 132, 142 and 152 may be used as a pad for connecting to another board or component.

[0054] The plurality of circuit pattern layers 132 , 142 , 152 may include a first circuit pattern layer 132 , a second circuit pattern layer 142 , and a third circuit pattern layer 152 .

[0055] The first circuit pattern layer 132 may be disposed on the second surface of the first insulating layer 110. The first circuit pattern layer 132 may be buried in the second insulating layer 120. As an example, the first circuit pattern layer 132 may include copper.

[0056] The second circuit pattern layer 142 may be disposed on the first surface of the first insulating layer 110, but is not limited thereto. Figure 1 As shown in FIG. 1 , the second circuit pattern layer 142 may be buried in the first insulating layer 110. The second circuit pattern layer 142 may be used as a pad for connecting to another board or component. As an example, the second circuit pattern layer 142 may include copper.

[0057] The third circuit pattern layer 152 may be disposed on one surface of the second insulating layer 120. The third circuit pattern layer 152 may be disposed on a fourth surface of the second insulating layer 120 opposite to the third surface of the second insulating layer 120, the third surface of the second insulating layer 120 being opposite to the second surface of the first insulating layer 110. The third circuit pattern layer 152 may be used as a pad for connection to another board or component. As an example, the third circuit pattern layer 152 may include copper.

[0058] Figure 1 Only the first circuit pattern layer 132, the second circuit pattern layer 142, and the third circuit pattern layer 152 are shown. However, the present disclosure is not limited thereto, and more or less circuit pattern layers may be provided compared to the number of circuit pattern layers shown in the drawings.

[0059] The circuit board 10 according to this embodiment may include a plurality of via layers 160 and 170. The plurality of via layers 160 and 170 may be arranged to electrically connect the first circuit pattern layer 132, the second circuit pattern layer 142, and the third circuit pattern layer 152 to each other. Each via electrode in the plurality of via layers 160 and 170 may have a tapered shape in which the width of one surface is greater than the width of another surface opposite to the one surface. Each of the plurality of via layers 160 and 170 may be made of a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, and the like.

[0060] Each of the plurality of via layers 160 and 170 may include a signal via, a ground via, a power via, etc. based on its design. Each via electrode of the via layers 160 and 170 may have a form in which the via hole is completely filled with a metal material, or may have a form in which the metal material is formed along the wall surface of the via hole. Each of the plurality of via layers 160 and 170 may be formed by a plating process (e.g., an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), or a sealing hole (TT) process). Each of the plurality of via layers 160 and 170 may include a seed layer (electroless plating layer) and an electrolytic plating layer formed based on the seed layer.

[0061] The plurality of via layers 160 and 170 may include a first via layer 160 disposed in the first insulating layer 110 and a second via layer 170 disposed in the second insulating layer 120 .

[0062] The first via layer 160 may penetrate the first insulating layer 110 to be connected to the first circuit pattern layer 132 and the second circuit pattern layer 142. Thus, through the first via layer 160, the first circuit pattern layer 132 and the second circuit pattern layer 142 may be electrically connected to each other.

[0063] The second via layer 170 may penetrate the second insulating layer 120 to be connected to the first circuit pattern layer 132 and the third circuit pattern layer 152. Thus, through the second via layer 170, the first circuit pattern layer 132 and the third circuit pattern layer 152 may be electrically connected to each other.

[0064] Figure 1 Only the first via layer 160 and the second via layer 170 are shown, the present disclosure is not limited thereto, and more or less via layers may be provided when necessary.

[0065] The circuit board 10 according to this embodiment may include a heat dissipation portion 200. The heat dissipation portion 200 may be connected to a first heat dissipation pattern 131. The first heat dissipation pattern 131 may be provided on the first insulating layer 110. The first heat dissipation pattern 131 may be connected to at least one other pattern layer to be connected to the outside of the circuit board 10. As an example, the first heat dissipation pattern 131 may be a dummy electrode or a heat dissipation electrode. Specifically, the first heat dissipation pattern 131 may be used to transfer heat generated in the circuit board 10 of the embodiment, rather than performing a signal transmission function. However, the present disclosure is not limited thereto, and the first heat dissipation pattern 131 may be used to transfer heat generated in the circuit board 10 while performing a signal transmission function.

[0066] Reference Figure 1, the first heat dissipation pattern 131 can be connected to the second heat dissipation pattern 141 through the first via layer 160. Specifically, the first via layer 160 may include a first heat dissipation via electrode 161 that connects the first heat dissipation pattern 131 to the second heat dissipation pattern 141. The first heat dissipation via electrode 161 can be used to transfer heat generated in the circuit board 10 of the embodiment. In addition, the first heat dissipation pattern 131 can be connected to the third heat dissipation pattern 151 through the second via layer 170. Specifically, the second via layer 170 may include a second heat dissipation via electrode 171 that connects the first heat dissipation pattern 131 to the third heat dissipation pattern 151. The second heat dissipation via electrode 171 can be used to transfer heat generated in the circuit board 10 of the embodiment. The heat generated in the electronic component 22 ( Fig.16 shown in) in the cavity 111 can be dissipated to the top and bottom of the circuit board 10 through the first heat dissipation via electrode 161 and the second heat dissipation via electrode 171.

[0067] The second heat dissipation pattern 141 can be connected to the first heat dissipation pattern 131 through the first heat dissipation via electrode 161. Due to this connection, the second heat dissipation pattern 141 can receive heat from the first heat dissipation pattern 131 through the first heat dissipation via electrode 161, and can transfer the heat generated by the electronic component 22 disposed in the cavity 111 to one side of the circuit board 10. In this way, the heat dissipation characteristics of the circuit board 10 can be improved.

[0068] The third heat dissipation pattern 151 can be connected to the first heat dissipation pattern 131 through the second heat dissipation via electrode 171. The third heat dissipation pattern 151 can receive heat from the first heat dissipation pattern 131 through the second heat dissipation via electrode 171, and can transfer the heat generated by the electronic component 22 disposed in the cavity 111 to the other side of the circuit board 10, thereby improving the heat dissipation characteristics of the circuit board 10.

[0069] The first insulating layer 110 may include an upper region 110a that overlaps the cavity 111 in a first direction and a side region 110b that overlaps the cavity 111 in a second direction perpendicular to the first direction (as Figure 1 shown in). The side region 110b can surround the upper region 110a. The heat dissipation part 200 can penetrate through the first insulating layer 110 and thus protrude into the cavity 111.

[0070] Refer to Figure 2, a plurality of heat dissipating portions 200 may be provided. The plurality of heat dissipating portions 200 may include some heat dissipating portions aligned with each other in one direction. Here, the one direction may be a second direction perpendicular to the first direction, but is not limited thereto. As a non-limiting example, the one direction may be any direction perpendicular to the first direction. Specifically, the plurality of heat dissipating portions 200 may include some heat dissipating portions aligned with each other in one direction and other heat dissipating portions aligned with each other in another direction perpendicular to the one direction. The plurality of heat dissipating portions 200 may be spaced apart from each other, respectively.

[0071] The heat dissipation unit 200 may be made of metal materials, such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

[0072] The heat dissipation part 200 may include a first portion 201 buried in the first insulating layer 110 and a second portion 202 extending from the first portion 201 and protruding from the upper region 110 a .

[0073] The first portion 201 may include a portion of a via electrode formed in the first via layer 160. The first portion 201 may include a portion whose width decreases as the first portion 201 moves away from the first heat dissipation pattern 131.

[0074] The second portion 202 may protrude into the cavity 111. A side portion of the second portion 202 may be exposed in the upper region 110a of the first insulating layer 110, thereby effectively absorbing and dissipating heat generated in the electronic components mounted in the cavity 111.

[0075] The length of the second portion 202 protruding into the cavity 111 and the plane area of ​​the second portion 202 may be changed based on the purpose. As an example, when the electronic component accommodated in the cavity 111 has a low height, the length of the second portion 202 may be made longer to improve the heat dissipation efficiency. As another example, the second portion 202 may have a larger plane area, thereby expanding the surface area of ​​the heat dissipation portion 200, thereby improving the heat dissipation efficiency.

[0076] The first insulating layer 110 may have a groove 110c in the upper region 110a. The groove 110c may be recessed in the first direction. The second portion 202 may be disposed in the groove 110c. The second portion 202 may protrude from the groove 110c. The width of the groove 110c in the second direction may be greater than the width of the second portion 202 in the second direction. In other words, there may be an empty space between the groove 110c and the second portion 202, and the inner surface of the groove 110c and the second portion 202 may be spaced apart from each other.

[0077] The first solder resist layer 180 may be disposed on the first surface of the first insulating layer 110 to cover a portion of the second circuit pattern layer 142, thereby preventing an unnecessary short circuit. The first solder resist layer 180 may be disposed to expose at least a portion of the second circuit pattern layer 142. The first solder resist layer 180 may include a photosensitive resin material.

[0078] The second solder resist layer 190 may be disposed on one surface of the second insulating layer 120 to cover a portion of the third circuit pattern layer 152, thereby preventing an unnecessary short circuit. The second solder resist layer 190 may be disposed to expose at least a portion of the third circuit pattern layer 152. The second solder resist layer 190 may include a photosensitive resin material.

[0079] According to the circuit board according to this embodiment, the heat dissipation portion having a protruding structure can be arranged in a cavity containing an electronic component, thereby effectively absorbing and dissipating heat generated in the electronic component while ensuring the installation space of the electronic component. In addition, the length of the heat dissipation portion can be adjusted, so the heat dissipation portion can be applied to electronic components of various thicknesses.

[0080] In the following, reference is made to Figures 3 to 15 A method of manufacturing a circuit board according to an embodiment is described. Figures 3 to 15 is a cross-sectional view illustrating a method of manufacturing a circuit board according to an embodiment.

[0081] Reference Figure 3 , a second pattern layer 140 may be formed on a carrier plate CS, the carrier plate CS including a core CO and a thin film metal layer MS stacked on each of the two sides of the core CO. A second heat dissipation pattern 141 and a second circuit pattern layer 142 may be formed on the carrier plate CS. Here, a first sacrificial layer 1111 may be formed at a position where the cavity 111 is to be formed. Both the second pattern layer 140 and the first sacrificial layer 1111 may be formed by a plating process. The second pattern layer 140 and the first sacrificial layer 1111 may be formed by, but not limited to, any one of SAP (semi-additive process), MSAP (modified semi-additive process), TT (sealing hole) process and subtractive process or any process capable of forming a pattern on a circuit board. The second circuit pattern layer 142 and the first sacrificial layer 1111 may each include, but not limited to, an electroless plating layer (e.g., chemical copper plating) as a seed layer and an electrolytic plating layer (e.g., electrolytic copper plating) as a plating layer. As a method for forming an electroless plating layer, a sputtering layer may be used instead of a chemical copper plating layer. Alternatively, the second pattern layer 140 may not include a copper foil, or may further include a copper foil.

[0082] The first sacrificial layer 1111 may be formed together with the second pattern layer 140. The first sacrificial layer 1111 may be made of the same material as the second pattern layer 140 and may have the same thickness as the second pattern layer 140. The thickness of the first sacrificial layer 1111 may correspond to the depth of the cavity 111 formed later.

[0083] Reference Figure 4 , a second sacrificial layer 2021 may be formed on the first sacrificial layer 1111. The second sacrificial layer 2021 may include a plurality of portions disposed on the first sacrificial layer 1111 and spaced apart from each other. The second sacrificial layer 2021 may be formed by a plating process. For example, the second sacrificial layer 2021 may be formed by forming a photoresist on the first sacrificial layer 1111, patterning the photoresist by an exposure and development process, plating to fill the patterned region, and stripping the photoresist. The second sacrificial layer 2021 may include nickel, and is not limited thereto.

[0084] Reference Figure 5 The first insulating layer 110 may be formed to bury the second pattern layer 140, the first sacrificial layer 1111, and the second sacrificial layer 2021. The first insulating layer 110 may be made of a material such as prepreg (PPG), Ajinomoto built-up film (ABF), or resin coated copper (RCC) foil.

[0085] Reference Figure 6 , a first pattern layer 130 may be formed on the first insulating layer 110, and a first via layer 160 may be formed by penetrating at least a portion of the first insulating layer 110. Specifically, a first pattern layer 130 including a first heat dissipation pattern 131 and a first circuit pattern layer 132 may be formed on the first insulating layer 110. Some via electrodes in the first via layer 160 may be formed to contact the first circuit pattern layer 132 and the second circuit pattern layer 142. In other words, some via electrodes of the first via layer 160 may be formed to connect the first circuit pattern layer 132 to the second circuit pattern layer 142.

[0086] In addition, other portions of the first insulating layer 110 may be penetrated to form the first heat dissipation via electrode 161. The first heat dissipation via electrode 161 (as some other via electrodes of the first via layer 160) may be formed to contact the first heat dissipation pattern 131 and the second heat dissipation pattern 141. In other words, the first heat dissipation via electrode 161 may be formed to connect the first heat dissipation pattern 131 to the second sacrificial layer 2021, and the first heat dissipation via electrode 161 may be formed to connect the first heat dissipation pattern 131 to the second heat dissipation pattern 141.

[0087] The first pattern layer 130 may be formed by any one of, but not limited to, a semi-additive process (SAP), a modified semi-additive process (MSAP), a hole sealing (TT) process, and a subtractive process, or any process capable of forming a pattern on a circuit board. For example, the first pattern layer 130 may be formed by forming a seed layer on a copper foil by electroless plating, forming a photoresist on the seed layer, patterning the photoresist by an exposure and development process, filling the patterned area with electrolytic plating, and stripping the photoresist. The first pattern layer 130 may include, but is not limited to, an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer. As a method for forming an electroless plating layer, a sputtering layer may be used instead of a chemical copper plating layer. Alternatively, the first pattern layer 130 may not include a copper foil, or may further include a copper foil.

[0088] The first via layer 160 may be formed by laser, mechanical drilling, etc. In one example, the first via layer 160 may be formed by forming a via hole passing through at least a portion of the first insulating layer 110 by laser, etc., and filling the via hole with a conductive material.

[0089] Reference Figure 7 , the second insulating layer 120 may be formed on the first insulating layer 110 to bury the first circuit pattern layer 132 and the first heat dissipation pattern 131 in the second insulating layer 120. The second insulating layer 120 may be made of a material such as prepreg (PPG), Ajinomoto built-up film (ABF), or resin coated copper (RCC) foil.

[0090] Reference Figure 8 , the third pattern layer 150 may be formed on the second insulating layer 120, and the second via layer 170 may be formed by penetrating at least a portion of the second insulating layer 120. Specifically, the third pattern layer 150 including the third heat dissipation pattern 151 and the third circuit pattern layer 152 may be formed on the second insulating layer 120. Some via electrodes of the second via layer 170 may be formed to contact the first circuit pattern layer 132 and the third circuit pattern layer 152. In other words, some via electrodes of the second via layer 170 may be formed to connect the first circuit pattern layer 132 to the third circuit pattern layer 152.

[0091] In addition, the second heat dissipation via electrode 171 may be formed by penetrating another portion of the second insulating layer 120. The second heat dissipation via electrode 171 (as another portion of the via electrode of the second via layer 170) may be formed to abut the first heat dissipation pattern 131 and the third heat dissipation pattern 151. In other words, the second heat dissipation via electrode 171 may be formed so that the first heat dissipation pattern 131 and the third heat dissipation pattern 151 are connected.

[0092] The third pattern layer 150 may be formed by, but not limited to, any one of a semi-additive process (SAP), a modified semi-additive process (MSAP), a sealing process, and a subtractive process, or any process capable of forming a pattern on a circuit board. For example, the third pattern layer 150 may be formed by forming a seed layer on a copper foil by electroless plating, forming a photoresist on the seed layer, patterning the photoresist by an exposure and development process, filling the patterned area with electrolytic plating, and stripping the photoresist. The third pattern layer 150 may include, but is not limited to, an electroless plating layer (e.g., a chemical copper plating layer) as a seed layer and an electrolytic plating layer (e.g., an electrolytic copper plating layer) as a plating layer. As a method for forming an electroless plating layer, a sputtering layer may be used instead of a chemical copper plating layer. Alternatively, the third pattern layer 150 may not include a copper foil, or may further include a copper foil.

[0093] The second via layer 170 may be formed by laser, mechanical drilling, etc. In one example, the second via layer 170 may be formed by forming a via hole passing through at least a portion of the second insulating layer 120 by laser, etc., and filling the via hole with a conductive material.

[0094] Reference Fig. 9 , the board unit SUB can be separated from each of the two sides of the carrier board CS.

[0095] In the following, one board unit SUB separated from the carrier board CS is described.

[0096] Reference Fig.10 , a first solder resist layer 180 may be formed on the first surface of the first insulating layer 110. The first solder resist layer 180 may be formed to expose a portion of the second circuit pattern layer 142. In addition, a second solder resist layer 190 may be formed on the fourth surface of the second insulating layer 120. The second solder resist layer 190 may be formed to expose a portion of the third circuit pattern layer 152.

[0097] As a specific example, the first solder resist layer 180 may be formed by an exposure and development process. The first solder resist layer 180 may include an opening exposing at least a portion of the second circuit pattern layer 142.

[0098] The second solder resist layer 190 may be formed through an exposure and development process. The second solder resist layer 190 may include an opening exposing at least a portion of the third circuit pattern layer 152.

[0099] Reference Fig.11, the cavity 111 may be formed by etching and removing the first sacrificial layer 1111. The etching process may utilize, but is not limited to, dry etching or wet etching. In one example, a resist may be formed on an area other than the first sacrificial layer 1111 to be etched, and the first sacrificial layer 1111 may be removed by etching. The resist may include a dry film.

[0100] Reference Fig.12 , the second sacrificial layer 2021 may be etched and removed to form a groove 110c in the upper region 110a of the first insulating layer 110. The etching process may utilize, but is not limited to, dry etching or wet etching. For example, the first sacrificial layer 1111 may be etched using an etchant. The second sacrificial layer 2021 may then be etched using another etchant. The first sacrificial layer 1111 and the second sacrificial layer 2021 may include metal materials that may be selectively removed by different etchants. As described above, for example, the first sacrificial layer 1111 may include copper, and the second sacrificial layer 2021 may include nickel. However, the present disclosure is not limited thereto. Here, the first portion 201 of the heat dissipation portion 200 (see Figure 1 ) may be exposed to the outside through the groove 110c.

[0101] The second pattern layer 140 and the second sacrificial layer 2021 may include different metal materials. Therefore, the second pattern layer 140 and the second sacrificial layer 2021 may be selectively removed by different etchants.

[0102] Furthermore, it is feasible to selectively etch the second sacrificial layer 2021 without separately masking the exposed second pattern layer 140 .

[0103] In the embodiments, reference Figures 10 to 12 , the formation of the first solder resist layer 180 and the second solder resist layer 190 and the etching and removal of the first sacrificial layer 1111 and the second sacrificial layer 2021 have been described, but are not limited thereto. For example, an etchant may be formed, the first sacrificial layer 1111 and the second sacrificial layer 2021 may be removed, and the etchant may be removed. Thereafter, the first solder resist layer 180 may be formed on the first insulating layer 110, and the second solder resist layer 190 may be formed on the second insulating layer 120.

[0104] Reference Fig.13 , a seed layer SD1 may be formed on one surface of the first portion 201. The seed layer SD1 may be formed in the groove 110c. The seed layer SD1 may be formed by a chemical copper plating process. For example, after patterning a region where the seed layer SD1 is to be formed using a dry film or the like, a chemical copper plating process may be performed to form the seed layer SD1.

[0105] Reference Fig.14, a mask layer MSK may be disposed on the first solder resist layer 180, the upper region 110a of the first insulating layer 110, the side region 110b of the first insulating layer 110, and the second solder resist layer 190. In other words, the mask layer MSK may cover the entire surface except for the portion where the second portion 202 (see Figure 1 ) area. Then, the conductive portion 2022 may be formed on the seed layer SD1. A plurality of conductive portions 2022 may be provided. The conductive portion 2022 may be formed to protrude from one surface of the first insulating layer 110. The conductive portion 2022 may be formed by a plating process. The mask layer MSK may include a dry film. By forming the conductive portion 2022 on the seed layer SD1 (as a chemical copper plating layer), even if the area of ​​one surface of the first portion 201 on which the conductive portion 2022 is formed is small, the conductive portion 2022 may be more reliably protruded by ensuring the necessary adhesion. However, directly electroplating on one surface of the first portion 201 to form the second portion 202 (see Figure 1 ) is also feasible, but the present disclosure is not limited to this.

[0106] Reference Fig.15 , the mask layer MSK may be removed to form a Figure 1 In the embodiment, refer to the circuit board shown in Figures 13 to 15 , showing that a seed layer SD1 is formed on one surface of the first portion 201, but is not limited thereto; in reference to Fig.13 In the described seed layer forming step, it is feasible to respectively form seed layers on one surface of the first portion 201, one surface of the second circuit pattern layer 142, and one surface of the third circuit pattern layer 152. For example, the seed layer SD2 may be formed on one surface of the third circuit pattern layer 152.

[0107] Here, the conductive portion 2022 may be formed on a portion of the seed layer disposed on one surface of the first portion 201, and the remaining portion of the seed layer may be removed to form a conductive portion 2022 as shown in FIG. Figure 1 circuit board in. The remaining portion of the seed layer SD1 may be removed by an etching process. The etching process may utilize but is not limited to dry etching or wet etching. In one example, a resist may be formed on an area other than the portion of the seed layer SD1 to be etched, and the remaining portion of the seed layer SD1 may be removed by etching. The resist may include a dry film. Here, the conductive portion 2022 may have a greater thickness in the stacking direction than the portion of the seed layer SD1 to be etched. Therefore, even if the conductive portion 2022 is etched together with a portion of the seed layer SD1 during the process of etching the second seed layer SD2, the conductive portion 2022 may be protected. The seed layer SD1 may be formed to include the same material as the conductive portion 2022, although the present disclosure is not limited thereto. In this case, as Figure 1As shown in FIG. 2 , a boundary between the seed layer SD1 and the conductive portion 2022 may not exist, although the present disclosure is not limited thereto.

[0108] According to the method of manufacturing a circuit board according to this embodiment, a heat dissipation portion having a protruding structure can be formed in a cavity containing an electronic component, thereby effectively absorbing and dissipating heat generated in the electronic component while ensuring an installation space for the electronic component. In addition, the length of the heat dissipation portion can be adjusted during the manufacturing process, so the heat dissipation portion can be applied to electronic components of various thicknesses.

[0109] In the following, reference is made to Fig.16 An electronic component package according to another embodiment is described. Fig.16 is a cross-sectional view schematically showing an electronic component package according to another embodiment.

[0110] Reference Fig.16 The electronic component package 20 according to this embodiment may include a first circuit board 11, which is the same as the circuit board 10 according to the above embodiment. Hereinafter, the description of the circuit board 10 according to the above embodiment may be applied to the description of the first circuit board 11 as it is.

[0111] According to another embodiment, an electronic component package 20 may include: a first circuit board 11; a second circuit board 21 connected to the first circuit board 11; an electronic component 22 mounted on a surface of the second circuit board 21 and accommodated in a cavity 111 of the first circuit board 11; a sealant 23 disposed between the first circuit board 11 and the second circuit board 21 to fill the cavity 111 and cover at least a portion of the electronic component 22; a conductive member 24 electrically connecting the first circuit board 11 and the second circuit board 21 to each other; an electrode 25 electrically connecting the second circuit board 21 and the electronic component 22 to each other; and a bottom filler 26.

[0112] The second circuit board 21 may be a circuit board on which the electronic components 22 are mounted, and includes an insulating layer, a wiring layer, a via layer, and a solder resist layer.

[0113] The electronic component 22 can be a bare die of an integrated circuit (IC) that integrates hundreds to millions of components into one chip. For example, the electronic component 22 can be a processor chip, such as a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor or a microcontroller. Specifically, the electronic component 22 can be an application processor (AP), but is not limited thereto, and can also be a memory, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM), a flash memory), or can also be a logic chip (such as an analog-to-digital converter or an application-specific IC (ASIC)). When necessary, the electronic component 22 can be a passive component in chip form, for example, a chip capacitor such as a multilayer ceramic capacitor (MLCC) or a chip inductor such as a power inductor (PI). The electronic component 22 can be covered by a sealant 23 and has at least one surface in physical contact with the sealant 23.

[0114] The sealant 23 may cover at least a portion of one surface of the first solder resist layer 180, one surface of the second circuit board 21, and the outer surface of the electronic component 22. In addition, the sealant 23 may fill at least a portion of the cavity 111, and thus, the sealant 23 may cover at least a portion of the upper surface of the electronic component 22. For example, the sealant 23 may be in physical contact with at least a portion of each of the upper surface, the lower surface, and the side surface of the electronic component 22. The sealant 23 may have fluidity in a pre-cured state, and thus flow along the outer surface of the electronic component 22 and the surface of the first insulating layer 110, thereby filling the interior of the cavity 111.

[0115] The sealant 23 can be made of an insulating material, and the insulating material can use a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. In addition, the sealant 23 can use such a resin including an inorganic filler such as silicon dioxide. For example, the sealant 23 can be made of an Ajinomoto stacked film (ABF). The ABF can be provided in the form of a resin coated copper (RCC) foil, and the sealant 23 is not limited thereto. When necessary, the sealant 23 can be made of a photosensitive material such as a photosensitive medium (PID). In addition, the sealant 23 can be a known epoxy molding compound (EMC), and is not limited thereto.

[0116] The conductive member 24 may be disposed in at least a portion of the opening of the second circuit board 21. The conductive member 24 may physically and / or electrically connect the second circuit board 21 to the first circuit board 11. For example, the conductive member 24 may electrically connect the exposed circuit pattern layer of the second circuit board 21 to the second circuit pattern layer 142 of the first circuit board 11. The conductive member 24 may be made of tin (Sn) or an alloy including tin (Sn) (e.g., solder), and is not limited thereto. For example, the conductive member 24 may be a solder ball, a solder pad, a pin, or a columnar metal column, or a column consisting of a plurality of solder balls.

[0117] The bottom filler 26 may be a material that fills a space between the electronic component 22 mounted in the cavity 111 of the first circuit board 11 and the second circuit board 21, and fixes the electronic component 22 in the cavity 111. In particular, when the electrode 25 protrudes and thus a gap is generated between one surface of the electronic component 22 and the second circuit board 21, the bottom filler 26 may fill the gap.

[0118] According to the electronic component package according to this embodiment, the heat dissipation portion having a protruding structure is arranged in the cavity of the first circuit board containing the electronic component, thereby effectively absorbing and dissipating the heat generated in the electronic component while ensuring the installation space of the electronic component. In addition, the length of the heat dissipation portion can be adjusted, so the heat dissipation portion can be applied to electronic components of various thicknesses.

[0119] Fig.17 and Fig.18 are diagrams respectively describing circuit boards in various examples. Fig.17 is a cross-sectional view of a circuit board in another example; and Fig.18 is a plan view schematically showing one surface of a circuit board in still another example.

[0120] Reference Fig.17 , the circuit board 10A in another example is similar to the reference Figure 1 and Figure 2 The circuit board 10 according to the embodiment is described, and thus a detailed description of the same components is omitted.

[0121] Reference Fig.17 ,and Figure 1 Unlike the circuit board according to the embodiment shown in , in the circuit board 10A in another example, the via layer 160 may not include the first heat dissipation via electrode 161, and the second via layer 170 may not include the second heat dissipation via electrode 171. In other words, the first heat dissipation pattern 131 may not be connected to another pattern layer. As described above, each of the heat dissipation pattern and the heat dissipation portion may have a simple structure, so the heat dissipation portion may be formed on the circuit board, thereby effectively absorbing and dissipating the heat generated in the electronic component even when it is difficult to connect the circuit pattern layer to the heat dissipation pattern due to the complex design of the circuit pattern layer.

[0122] Reference Fig.18 , the circuit board 10B in another example is similar to the reference Figure 1 and Figure 2 The circuit board according to the embodiment is described, and thus a detailed description of the same components is omitted.

[0123] Reference Fig.18 ,and Figure 1 Unlike the circuit board 10 according to the embodiment shown in , in the circuit board 10B in another example, the heat dissipation portion 200B may extend parallel to the edge of the cavity 111. The heat dissipation portion 200B may extend in a direction perpendicular to the first direction. As a non-limiting example, the heat dissipation portion 200B may extend in the second direction. In a plan view, the heat dissipation portion 200B may have a rectangular planar shape or a strip shape, and is not limited thereto. As an example, the heat dissipation portion 200B may be formed by forming a via with a laser or the like in a via stacking method. As described above, the heat dissipation portion may have a wider planar area to expand the surface area of ​​the heat dissipation portion exposed in the cavity containing the electronic components, thereby improving the heat dissipation efficiency.

[0124] Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure is not limited to the disclosed embodiments. Various modifications can be made within the scope disclosed in the claims, specific embodiments and drawings of the present disclosure, and these modifications also fall within the scope of the present disclosure.

Claims

1. A circuit board, comprising: a first insulating layer having a first surface and a second surface opposite to each other and having a cavity recessed from the first surface; a first heat dissipation pattern, disposed on the second surface of the first insulating layer; as well as A heat dissipation portion is connected to the first heat dissipation pattern and protrudes into the cavity by penetrating the first insulating layer.

2. The circuit board according to claim 1, further comprising: a second insulating layer disposed on the second surface along a first direction to cover the first heat dissipation pattern and at least one circuit pattern layer disposed on the second surface, wherein the first insulating layer includes an upper region overlapping the cavity in the first direction and a side region overlapping the cavity in a second direction, the second direction being perpendicular to the first direction, and The heat dissipation portion protrudes from the upper region.

3. The circuit board according to claim 2, wherein: The heat dissipation unit comprises: A first portion, buried in the first insulating layer; and A second portion extends from the first portion and protrudes from the upper region.

4. The circuit board according to claim 3, wherein: The first insulating layer has a groove in the upper region where the second portion is provided, and The groove surrounds the second portion.

5. The circuit board according to claim 1, further comprising: a first pattern layer, comprising the first heat dissipation pattern and a first circuit pattern layer arranged around the first heat dissipation pattern, Wherein, the first heat dissipation pattern is connected to at least one other pattern layer.

6. The circuit board according to claim 5, further comprising: a second heat dissipation pattern, disposed on the first surface of the first insulating layer, Wherein, the first heat dissipation pattern is connected to the second heat dissipation pattern.

7. The circuit board according to claim 5, further comprising: a second insulating layer disposed on the second surface along a first direction to cover at least one pattern layer including the first pattern layer; as well as a third heat dissipation pattern, disposed on a fourth surface of the second insulating layer opposite to a third surface of the second insulating layer, the third surface of the second insulating layer opposite to the second surface of the first insulating layer, Wherein, the first heat dissipation pattern is connected to the third heat dissipation pattern.

8. The circuit board according to claim 1, wherein: The heat dissipation portion extends parallel to an edge of the cavity.

9. The circuit board according to claim 1, wherein: The circuit board includes a plurality of the heat dissipation parts, and The plurality of heat dissipating portions include some heat dissipating portions aligned with each other in one direction.

10. The circuit board according to claim 1, wherein: The circuit board includes a plurality of the heat dissipation parts, and The plurality of heat dissipation portions are spaced apart from each other.

11. The circuit board according to claim 1, wherein: The heat dissipation part is made of metal material.

12. An electronic component package, comprising: a first circuit board having a cavity therein on one surface thereof; a second circuit board connected to the first circuit board; as well as an electronic component mounted on one surface of the second circuit board and accommodated in the cavity, Wherein, the first circuit board comprises: a first insulating layer having a first surface and a second surface opposite to each other, and having the cavity recessed from the first surface, a first heat dissipation pattern disposed on the second surface of the first insulating layer, and A heat dissipation portion is connected to the first heat dissipation pattern and protrudes into the cavity by penetrating the first insulating layer.

13. The electronic component package of claim 12, further comprising: a second insulating layer disposed on the second surface along a first direction to cover the first heat dissipation pattern and at least one circuit pattern layer disposed on the second surface, wherein the first insulating layer includes an upper region overlapping the cavity in the first direction and a side region overlapping the cavity in a second direction, the second direction being perpendicular to the first direction, and The heat dissipation portion protrudes from the upper region.

14. The electronic component package of claim 13, wherein: The heat dissipation unit comprises: A first portion, buried in the first insulating layer; and A second portion extends from the first portion and protrudes from the upper region.

15. The electronic component package of claim 14, wherein: The first insulating layer has a groove in the upper region where the second portion is provided, and The width of the groove is greater than the width of the second portion.

16. The electronic component package of claim 12, further comprising: a first pattern layer, comprising the first heat dissipation pattern and a first circuit pattern layer arranged around the first heat dissipation pattern, Wherein, the first heat dissipation pattern is connected to at least one other pattern layer.

17. The electronic component package of claim 16, further comprising: a second heat dissipation pattern, disposed on the first surface of the first insulating layer, Wherein, the first heat dissipation pattern is connected to the second heat dissipation pattern.

18. The electronic component package of claim 16, further comprising: a second insulating layer disposed on the second surface along a first direction to cover at least one pattern layer including the first pattern layer; as well as a third heat dissipation pattern, disposed on a fourth surface of the second insulating layer opposite to a third surface of the second insulating layer, the third surface of the second insulating layer opposite to the second surface of the first insulating layer, Wherein, the first heat dissipation pattern is connected to the third heat dissipation pattern.

19. The electronic component package of claim 12, wherein: The heat dissipation portion extends parallel to an edge of the cavity.

20. The electronic component package of claim 12, wherein: The circuit board includes a plurality of the heat dissipation parts, and The plurality of heat dissipating portions include some heat dissipating portions aligned with each other in one direction.

Images