Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The method for manufacturing the semiconductor structure comprises the steps that a plurality of sacrificial structures which penetrate through an initial semiconductor column, extend in the third direction and are arranged in the first direction are formed, every two of the first direction, the second direction and the third direction intersect, and the sacrificial structures divide the initial semiconductor column into a plurality of semiconductor columns extending in the second direction; removing part of the sacrifice structure along the second direction to form a sacrifice gap; replacing the residual sacrificial structure with a semiconductor doping layer; and forming a gate structure in the sacrificial gap, wherein the gate structure and the semiconductor doping layer are adjacently distributed along the second direction.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a semiconductor structure, a method for manufacturing the semiconductor structure, and a storage system. Background Art

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices and cloud storage, the requirements for the storage density of semiconductor structures such as three-dimensional semiconductor memory devices are becoming higher and higher. However, as the storage density of semiconductor structures increases, the number of storage units increases, the size decreases, and the spatial density increases, which makes the manufacturing process of semiconductor structures more and more complicated. Summary of the invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies proposed in the above background technology section or other deficiencies in the prior art.

[0004] The present application provides a method for manufacturing a semiconductor structure. The semiconductor layer includes a plurality of initial semiconductor columns extending along a first direction and a second direction. The method includes: forming a plurality of sacrificial structures that pass through the initial semiconductor columns and extend along a third direction and are arranged along the first direction, wherein the first direction, the second direction and the third direction intersect each other, and the plurality of sacrificial structures divide the initial semiconductor columns into a plurality of semiconductor columns extending along the second direction; removing a portion of the sacrificial structures along the second direction to form a sacrificial gap; replacing the remaining sacrificial structures with a semiconductor doping layer; and forming a gate structure in the sacrificial gap, wherein the gate structure and the semiconductor doping layer are adjacently distributed along the second direction.

[0005] In one embodiment, the semiconductor column includes a first end and a second end arranged opposite to each other along the second direction, wherein the first end is close to the semiconductor doping layer relative to the second end, and the method further includes: forming a doping portion at the first end, wherein the doping portion overlaps with a projection portion of the gate structure along the first direction.

[0006] In one embodiment, the method includes: forming the doping portion by diffusing doping ions in the semiconductor doping layer to the first end.

[0007] In one embodiment, a plurality of sacrificial structures are formed that pass through the initial semiconductor column, extend along a third direction, and are arranged along a first direction, including: forming the sacrificial structures and isolation structures that pass through the initial semiconductor column, extend along the third direction, and are alternately arranged along the first direction, wherein the sacrificial structures and the isolation structures divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction.

[0008] In one embodiment, replacing the remaining sacrificial structure with a semiconductor doping layer includes: forming a barrier layer on the sidewall of the sacrificial gap; removing the remaining sacrificial structure to form a gap; and forming the semiconductor doping layer in the gap.

[0009] In one embodiment, forming a gate structure in the sacrificial gap includes: forming a dielectric layer on the sidewall of the barrier layer and on the surface of the semiconductor doping layer; and forming a gate conductive layer on the surface of the dielectric layer.

[0010] In one embodiment, the doping ions include N-type doping ions, and the method includes: performing an annealing process on the semiconductor doping layer to diffuse the N-type doping ions to the first end.

[0011] In one embodiment, the method further includes: forming a capacitor connected to the second end.

[0012] In one embodiment, the sacrificial structure and the isolation structure are formed to pass through the initial semiconductor column, extend along the third direction, and are alternately arranged along the first direction, including: forming a plurality of the initial semiconductor columns extending along the first direction and the second direction in the semiconductor layer; forming a first trench and a second trench passing through the initial semiconductor column, extending along the third direction, and alternately arranged along the first direction; and forming the sacrificial structure and the isolation structure in the first trench and the second trench, respectively.

[0013] In one embodiment, a first trench and a second trench are formed that pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction, including: forming an initial first trench and a second trench in the semiconductor layer that pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction; forming a first sacrificial layer and a second sacrificial layer in the initial first trench and the second trench, respectively; removing the second sacrificial layer along the second direction and forming the isolation structure in the removed space; and removing the first sacrificial layer and increasing the width and depth of the initial first trench to form the first trench.

[0014] In one embodiment, the method further includes: forming a lead-out structure connected to the isolation structure on a side close to the semiconductor doping layer.

[0015] In one embodiment, the method further includes: forming a bit line on a side close to the semiconductor doping layer, the bit line being in contact with the doping portion and extending along the first direction.

[0016] On the other hand, the present application provides a semiconductor structure, which includes: a semiconductor column; a gate structure located on at least one side of the semiconductor column along a first direction; and a semiconductor doping layer located on one side of the gate structure along a second direction, wherein the second direction intersects the first direction.

[0017] In one embodiment, the semiconductor column includes a first end and a second end oppositely disposed along the second direction, wherein the semiconductor column further includes a doped portion located at the first end, the doped portion partially overlapping with a projection of the gate structure along the first direction.

[0018] In one embodiment, the gate structure is located at the first side wall of the semiconductor column and extends along a third direction intersecting the second direction, and the semiconductor structure also includes: an isolation structure located at the second side wall of the semiconductor column opposite to the first side wall and extending along the third direction.

[0019] In one embodiment, the gate structure includes: a gate conductive layer located on at least one side of the semiconductor column along the first direction, wherein the semiconductor doping layer is located on one side of the gate conductive layer along the second direction; and a gate dielectric layer located between the gate conductive layer and the semiconductor column and between the gate conductive layer and the semiconductor doping layer.

[0020] In one embodiment, the gate dielectric layer includes: a blocking layer located on at least one side wall of the semiconductor column along the first direction and extending along the second direction to the surface of the semiconductor doped layer; and a dielectric layer located between the gate conductive layer and the blocking layer and between the gate conductive layer and the semiconductor doped layer.

[0021] In one embodiment, the semiconductor structure further includes: a capacitor connected to the second end.

[0022] In one embodiment, the semiconductor structure further includes: a lead-out structure located on a side close to the semiconductor doping layer and connected to the isolation structure.

[0023] In one embodiment, the semiconductor structure further includes: a bit line located on a side close to the semiconductor doping layer and in contact with the doping portion.

[0024] On the other hand, the present application provides a storage system, which includes at least one three-dimensional memory, each three-dimensional memory including the semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the three-dimensional memory to store data.

[0025] In one or more embodiments of the present application, by disposing the semiconductor doping layer on one side of the gate structure along the second direction, it is beneficial to reasonably set the formation position of the gate structure by controlling the positional relationship between the semiconductor doping layer and the gate structure, thereby improving the overall performance of the semiconductor structure. For example, it is possible to dispose the gate structure above the semiconductor doping layer, that is, the gate structure and the semiconductor doping layer can be adjacently distributed along the second direction. Furthermore, it is beneficial to make the positional relationship between the gate structure and the end of the semiconductor column (which can be used to form the source or drain subsequently) relatively controllable, and reduce the leakage risk between the gate structure and the end of the semiconductor column. Description of the Drawings

[0026] In conjunction with the drawings, other features, objects, and advantages of the present application will become more apparent through the following detailed description of non-limiting embodiments. In the drawings:

[0027] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present application;

[0028] Figure 2 and Figure 3 are respectively partial structural schematic diagrams of a semiconductor layer formed on planes in the first direction and the third direction and on a plane formed in the third direction and the second direction according to an exemplary embodiment of the present application;

[0029] Figure 4 and Figure 5 are respectively structural schematic diagrams of forming an initial semiconductor column and an isolation column according to an exemplary embodiment of the present application, wherein, Figure 5 is Figure 4 a cross-sectional schematic diagram along the A-A direction;

[0030] Figure 6 and Figure 7 are respectively structural schematic diagrams of forming an initial first trench and a second trench according to an exemplary embodiment of the present application, wherein, Figure 7 is Figure 6 a cross-sectional schematic diagram along the B-B direction;

[0031] Figure 8 and Fig. 9 are structural schematic diagrams of forming a first sacrificial layer and a second sacrificial layer according to an exemplary embodiment of the present application, wherein, Fig. 9 is Figure 8 a cross-sectional schematic diagram along the B-B direction;

[0032] Fig.10 and Fig.11 are structural schematic diagrams of forming an isolation structure according to an exemplary embodiment of the present application, wherein, Fig.11 is Fig.10Schematic diagram of the cross section along the BB direction;

[0033] Fig.12 and Fig.13 is a schematic diagram of a structure for forming a first groove according to an exemplary embodiment of the present application, wherein: Fig.13 for Fig.12 Schematic diagram of the cross section along the BB direction;

[0034] Fig.14 and Fig.15 is a schematic diagram of a structure for forming a sacrificial structure according to an exemplary embodiment of the present application, wherein: Fig.15 for Fig.14 Schematic diagram of the cross section along the BB direction;

[0035] Fig.16 is a schematic diagram of a structure for forming a sacrificial gap according to an exemplary embodiment of the present application;

[0036] Fig.17 is a schematic diagram of a structure for forming a barrier layer according to an exemplary embodiment of the present application;

[0037] Fig.18 is a schematic diagram of a structure for forming a gap according to an exemplary embodiment of the present application;

[0038] Fig.19 is a schematic diagram of a structure for forming a semiconductor doping layer and a doping part according to an exemplary embodiment of the present application;

[0039] Fig. 20 is a schematic diagram of a structure for forming a dielectric layer and a gate conductive layer according to an exemplary embodiment of the present application;

[0040] Fig.21 is a schematic diagram of a structure for forming a gap according to an exemplary embodiment of the present application;

[0041] Fig. 22 and Fig.23 is a schematic diagram of a structure for forming a dielectric layer and a separation structure according to an exemplary embodiment of the present application, wherein: Fig.23 for Fig. 22 Schematic diagram of the cross section along the BB direction;

[0042] Fig.24 is a schematic diagram of a structure for forming a capacitor according to an exemplary embodiment of the present application;

[0043] Fig.25 is a schematic diagram of a structure for forming a bit line according to an exemplary embodiment of the present application;

[0044] Fig.26is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of the present application; and

[0045] Fig.27A and Fig.27B is a schematic diagram of a storage system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0046] In order to better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and do not limit the scope of the present application in any way.

[0047] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first groove discussed in this application may also be referred to as the second groove, the first direction may also be referred to as the second direction, the third direction, and vice versa.

[0048] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0049] In addition, in this document, when describing that one part is located "on" another part, for example, the meaning of "on", "above" and "over" should be interpreted in the broadest manner, so that "on" not only means "directly on something", but also includes the meaning of "on something" with intervening features or layers in between, and "above" or "over" does not absolutely mean being above based on the direction of gravity, nor does it only mean the meaning of "on something" or "above something", but also includes the meaning of "on something" or "over something" with no intervening features or layers in between (i.e., directly on something).

[0050] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0051] This document is described with reference to schematic diagrams of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the specific shapes and sizes shown, but include various equivalent structures that can achieve the same functions and shape and size deviations caused by, for example, manufacturing. The positions shown in the drawings are schematic in nature and are not intended to limit the positions of the components.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0053] As used in this article, the term "layer" refers to a material portion including an area with a height. A layer can be an area of ​​a uniform or non-uniform continuous structure, whose height is less than the height of the continuous structure. For example, a layer can be located between the top surface and the bottom surface of the continuous structure or between any set of horizontal planes therebetween. A layer can extend horizontally, vertically and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers thereon, above it and / or below it. A layer can include multiple layers.

[0054] In addition, in the present application, when “connected” or “coupled” is used, it may indicate that the corresponding components are in direct contact or indirect contact, unless otherwise clearly defined or can be inferred from the context.

[0055] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method described in this application are not necessarily limited to the order described, but can be performed in any order or in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0056] Figure 1 is a flow chart of a method 1000 of fabricating a semiconductor structure according to an exemplary embodiment of the present application.

[0057] The semiconductor layer may include a plurality of initial semiconductor pillars extending along a first direction and a second direction. Figure 1 As shown, the method 1000 for manufacturing a semiconductor structure may include: S1100, forming a plurality of sacrificial structures that pass through an initial semiconductor column and extend along a third direction and are arranged along a first direction, wherein the first direction, the second direction, and the third direction intersect each other, and the plurality of sacrificial structures divide the initial semiconductor column into a plurality of semiconductor columns extending along a second direction; S1200, removing a portion of the sacrificial structures along the second direction to form a sacrificial gap; S1300, replacing the remaining sacrificial structures with a semiconductor doping layer; and S1400, forming a gate structure in the sacrificial gap, wherein the gate structure and the semiconductor doping layer are adjacently distributed along the second direction. Steps S1100 to S1400 will be described in detail below.

[0058] In the exemplary embodiment of the present application, Figure 4 and Figure 5 As shown, the semiconductor layer 1100 may include a plurality of initial semiconductor pillars 1110-1 extending along the first direction X and the second direction Z. For example, Fig.14 and Fig.15 As shown, a plurality of sacrificial structures 1400 may be formed that pass through the initial semiconductor column 1110-1 and extend along the third direction Y and are arranged along the first direction X, wherein the first direction X, the second direction Z and the third direction Y intersect in pairs, and the plurality of sacrificial structures 1400 divide the initial semiconductor column 1110-1 into a plurality of semiconductor columns 1110 extending along the second direction Z.

[0059] Figures 2 to 15 The present application provides a process step diagram for forming a semiconductor column 1110 and a sacrificial structure 1400. It should be understood that the process for forming the semiconductor column 1110 and the sacrificial structure 1400 provided in the present application is only an example and is not specifically limited. In the actual process, the process for forming the semiconductor column 1110 and the sacrificial structure 1400 can be reasonably set according to actual needs.

[0060] For example, Figure 2 and Figure 3 1 and 2 are partial structural schematic diagrams of the semiconductor layer 1100 provided according to an exemplary embodiment of the present application on a plane formed by the first direction X and the third direction Y and on a plane formed by the third direction Y and the second direction Z. Figure 3As shown, a first dielectric layer 110 and a second dielectric layer 120 stacked in sequence may be formed on the surface of the semiconductor layer 1100. For example, the first dielectric layer 110 and the second dielectric layer 120 may be etched to form a patterned mask.

[0061] The material of the semiconductor layer 1100 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0062] The material of the first dielectric layer 110 may include an oxide such as silicon oxide. The material of the second dielectric layer 120 may include a nitride such as silicon nitride. In an exemplary embodiment, the first dielectric layer 110 and the second dielectric layer 120 may be deposited by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. In another exemplary embodiment, the first dielectric layer 110 may be formed by oxidizing the surface of the semiconductor layer 1100 by an oxidation process such as oxidation.

[0063] Figure 4 and Figure 5 are schematic diagrams of structures for forming an initial semiconductor column 1110 - 1 and an isolation column 1300 according to an exemplary embodiment of the present application, wherein: Figure 5 for Figure 4 Schematic diagram of the cross section along the AA direction. For example, Figure 4 and Figure 5 As shown, a plurality of initial semiconductor pillars 1110 - 1 extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1100 .

[0064] For example, a plurality of isolation columns 1300 extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1100, wherein the plurality of isolation columns 1300 may divide a portion of the semiconductor layer 1100 into a plurality of initial semiconductor columns 1110-1. The initial semiconductor columns 1110-1 and the isolation columns 1300 may be alternately arranged along the third direction Y. For example, a plurality of grooves (not shown) extending along the first direction X and the second direction Z may be formed in the semiconductor layer 1100; and the isolation columns 1300 may be formed in the grooves, wherein the semiconductor layer 1100 that is not removed forms the initial semiconductor columns 1110-1.

[0065] Exemplarily, the second dielectric layer 120, the first dielectric layer 110, and the semiconductor layer 1100 may be etched by an etching process to form a groove and an initial semiconductor pillar 1110-1. For example, the second dielectric layer 120 and the first dielectric layer 110 may be etched by a photolithography process to form a patterned mask, wherein the second dielectric layer 120 may be used as a bottom anti-reflective layer for photolithography, and the first dielectric layer 110 may be used as a hard mask; then, the semiconductor layer 1100 is etched by one or more dry etching and / or wet etching processes using the patterned mask as a mask to form a groove in the semiconductor layer 1100, wherein the semiconductor layer 1100 that is not removed may form an initial semiconductor pillar 1110-1.

[0066] By way of example, the material of the isolation column 1300 may include, but is not limited to, an insulating material such as oxide. By way of example, the isolation column 1300 may be formed by depositing an insulating material in the groove by, for example, a thin film deposition process, so that adjacent initial semiconductor columns 1110-1 are isolated by the isolation column 1300. In addition, a planarization process such as a mechanical grinding process may be performed to remove the insulating material on the surface of the second dielectric layer 120.

[0067] Figure 6 and Figure 7 are schematic diagrams of structures for forming an initial first trench 210' and a second trench 220 according to an exemplary embodiment of the present application, wherein: Figure 7 for Figure 6 A schematic cross-sectional view along the BB direction. For example, Figure 6 and Figure 7 As shown, initial first trenches 210 ′ and second trenches 200 that pass through the initial semiconductor pillar 1110 - 1 and extend along the third direction Y and are alternately arranged along the first direction X may be formed in the semiconductor layer 1100 .

[0068] For example, one or more dry etching and / or wet etching processes may be used to form the initial first trench 210 ′ and the second trench 200 . The initial first trench 210 ′ and the second trench 200 may separate the initial semiconductor pillar 1110 - 1 into a plurality of semiconductor pillars 1110 .

[0069] A plurality of semiconductor pillars 1110 may extend along a second direction Z and be arrayed in a distribution along a first direction X and a third direction Y, where the first direction X, the second direction Z, and the third direction Y may intersect pairwise. For example, the first direction X and the third direction Y intersect, and the second direction Z may be perpendicular to the first direction X and the third direction Y. Also for example, the first direction X, the second direction Z, and the third direction Y may intersect pairwise. Exemplarily, a plurality of semiconductor pillars 1110 may be formed by removing a portion of the semiconductor layer 1100. In other words, the non-removed portion of the semiconductor layer 1100 may include a plurality of semiconductor pillars 1110. Therefore, the semiconductor pillars 1110 may be made of the same material as the non-removed portion of the semiconductor layer 1100, such as single crystal silicon or the like.

[0070] Exemplarily, a plurality of semiconductor pillars 1110 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1110. For example, the semiconductor pillars 1110 may have a cubic shape to expose four of their sidewalls. It should be understood that the semiconductor pillars 1110 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1110 in a plan view (e.g., in the X-Y plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular (or an elliptical shape), or any other suitable shape.

[0071] Figure 8 and Fig. 9 are schematic structural diagrams of forming a first sacrificial layer 310 and a second sacrificial layer 320 according to an exemplary embodiment of the present application, where Fig. 9 is Figure 8 a cross-sectional schematic diagram along the B-B direction. Exemplarily, as Figure 8 and Fig. 9 shown, the first sacrificial layer 310 and the second sacrificial layer 320 may be respectively formed in an initial first trench 210' and a second trench 200. For example, the first sacrificial layer 310 and the second sacrificial layer 320 may be formed by depositing a dielectric material such as silicon oxide, carbon material, etc. through one or more thin film deposition processes.

[0072] Fig.10 and Fig.11 are schematic structural diagrams of forming an isolation structure 1200 according to an exemplary embodiment of the present application, where Fig.11 is Fig.10 a cross-sectional schematic diagram along the B-B direction. Exemplarily, as Fig.10 and Fig.11 shown, the second sacrificial layer 320 may be removed along the second direction Z, and an isolation structure 1200 may be formed in the removed space. Exemplarily, the isolation structure 1200 may extend along the third direction Y.

[0073] For example, the second sacrificial layer 320 may be removed by using a photolithography process, one or more dry etching and / or wet etching processes, etc.; and then one or more thin film deposition processes may be used to form the isolation structure 1200 in the removed space.

[0074] By way of example, the isolation structure 1200 may include an isolation conductive layer 1210 and an isolation dielectric layer 1220 surrounding the isolation conductive layer 1210. The material of the isolation conductive layer 1210 may include but is not limited to metal materials such as tungsten and copper. The material of the isolation dielectric layer 1220 may include but is not limited to silicon oxide.

[0075] Fig.12 and Fig.13 is a schematic diagram of a structure for forming a first trench 210 according to an exemplary embodiment of the present application, wherein: Fig.13 for Fig.12 A schematic cross-sectional view along the BB direction. For example, Fig.12 and Fig.13 As shown, the first sacrificial layer 310 may be removed, and the width and depth of the initial first trench 210 ′ may be increased to form the first trench 210 .

[0076] For example, the first sacrificial layer 310 may be removed by photolithography, one or more dry etching and / or wet etching processes, etc. For example, during the removal of the first sacrificial layer 310, the initial first trench 210' may be enlarged and deepened to form a first trench 210 having a greater width and depth than the initial first trench 210'.

[0077] Fig.14 and Fig.15 is a schematic diagram of a structure for forming a sacrificial structure 1400 according to an exemplary embodiment of the present application, wherein: Fig.15 for Fig.14 A schematic cross-sectional view along the BB direction. For example, Fig.14 and Fig.15 As shown, a sacrificial structure 1400 may be formed in the first trench 210. For example, the sacrificial structure 1400 may be formed by depositing a dielectric material such as a carbon material by one or more thin film deposition processes. The sacrificial structure 1400 may extend along the third direction Y. The sacrificial structure 1400 and the isolation structure 1200 may be arranged along the first direction X. The sacrificial structure 1400 and the isolation structure 1200 may be respectively located on two sidewalls of the semiconductor pillar 1110 along the first direction X.

[0078] For example, Fig.16As shown, a portion of the sacrificial structure 1400 may be removed along the second direction Z to form a sacrificial gap 400. The semiconductor pillar 1110 may include a first end 1111 and a second end 1112 that are oppositely disposed along the second direction Z. Exemplarily, a portion of the sacrificial structure 1400 near the second end 1112 of the semiconductor pillar 1110 may be removed by an etch-back process, and a portion of the sacrificial structure 1400 near the first end 1111 of the semiconductor pillar 1110 may be retained.

[0079] For example, Figures 17 to 19 As shown, the remaining sacrificial structure 1400 may be replaced with a semiconductor doping layer 1600. For example, a barrier layer 1510 ( Fig.17 ); removing the remaining sacrificial structure 1400 to form a gap 500 ( Fig.18 ); and forming a semiconductor doping layer 1600 ( Fig.19 ).

[0080] Exemplarily, the barrier layer 1510 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. The barrier layer 1510 may be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. For example, a dielectric material may be deposited in the sacrificial gap 400, wherein the surface of the remaining sacrificial structure 1400 may be used as a starting surface for depositing the dielectric material, that is, the dielectric material is located on the surface of the remaining sacrificial structure 1400; then, a portion of the dielectric material is removed, and the dielectric material located on the sidewall of the sacrificial gap 400 is retained to form the barrier layer 1510. It should be understood that, as Fig.17 As shown, the formed barrier layer 1510 may extend along the second direction to the surface of the remaining sacrificial structure 1400. In other words, the remaining sacrificial structure 1400 may serve as a formation stop layer for the barrier layer 1510.

[0081] For example, Fig.18 As shown, after forming the barrier layer 1510, the remaining sacrificial structure 1400 may be removed by photolithography, one or more dry etching and / or wet etching processes, etc., to form a gap 500. One or more thin film deposition processes, including but not limited to CVD, PVD, ALD or any combination thereof, may be used to deposit and form the semiconductor doping layer 1600 ( Fig.19 ). The semiconductor doping layer 1600 may include doping ions, for example, may include N-type doping ions. For example, the N-type doping ions may be doping ions such as phosphorus (P), arsenic (Ar), or antimony (Sb).

[0082] For example, Fig.19As shown, a doped portion 1113 may be formed at the first end 1111, wherein the doped portion 1113 may be connected to a gate structure 1500 ( Fig.21 ) overlap with the projections of the semiconductor doping layer 1600 along the first direction X. Exemplarily, the doping portion 1113 may be formed by diffusing doping ions in the semiconductor doping layer 1600 to the first end 1111, wherein the doping ions may be diffused to the first end 1111 along the direction C. For example, an annealing process may be performed on the semiconductor doping layer 1600 to diffuse doping ions such as N-type doping ions to the first end 1111 to form the doping portion 1113.

[0083] By setting a semiconductor doping layer 1600, the present application can not only diffuse the doped ions in the semiconductor doping layer 1600 to the first end 1111 to form a doped portion 1113, but also control the position of the subsequently formed gate structure 1500 (including the blocking layer 1510), such as the gate structure 1500 is located above the semiconductor doping layer 1600, which is beneficial to control the relative position relationship between the doped portion 1113 and the gate structure 1500, and reduce the coupling phenomenon between the gate structure 1500 and the doped portion 1113.

[0084] like Fig. 20 and Fig.21 As shown, the present application provides a process step diagram for forming a gate structure 1500. It should be understood that the process for forming the gate structure 1500 provided in the present application is only an example and is not a specific limitation. In the actual process, the process for forming the gate structure 1500 can be reasonably set according to actual needs. In addition, although the present application records that the isolation structure 1200 has been formed when the gate structure 1500 is formed, it should be understood that there is no order of formation between the isolation structure 1200 and the gate structure 1500, and the present application does not specifically limit the order of the formation process of the isolation structure 1200 and the gate structure 1500.

[0085] In the exemplary embodiment of the present application, Fig.21 As shown, a gate structure 1500 may be formed in the sacrificial gap 400, wherein the gate structure 1500 may be distributed adjacent to the semiconductor doping layer 1600 along the second direction Z. Exemplarily, forming the gate structure 1500 in the sacrificial gap 400 may include: forming a dielectric layer 1520 on the sidewall of the barrier layer 1510 and the surface of the semiconductor doping layer 1600; and forming a gate conductive layer 1530 on the surface of the dielectric layer 1520.

[0086] For example, Fig. 20 As shown, a dielectric layer 1520 may be formed on the sidewall of the barrier layer 1510 and the surface of the semiconductor doping layer 1600; and a gate conductive layer 1530 may be formed on the surface of the dielectric layer 1520. The gate conductive layer 1530 and the semiconductor doping layer 1600 may be separated by the dielectric layer 1520.

[0087] Exemplarily, the dielectric layer 1520 and the gate conductive layer 1530 may be deposited sequentially by one or more thin film deposition processes including but not limited to CVD, PVD, ALD or any combination thereof. The dielectric layer 1520 may include any suitable dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride or a high-k dielectric. For example, the dielectric layer 1520 may include silicon oxide. The gate conductive layer 1530 may include one or more conductive materials such as metals and / or metal compounds such as metal tungsten W and / or titanium nitride TiN. Exemplarily, a planarization process such as a chemical mechanical polishing process may be performed to remove excess conductive material and dielectric material on the surface of the second dielectric layer 120.

[0088] For example, Fig.21 As shown, a gap 600 may be formed along the second direction Z through the gate conductive layer 1530 and the dielectric layer 1520 to extend to the semiconductor doping layer 1400. Exemplarily, the gap 600 may be formed by an etching process such as punch-down etching, dry etching and / or wet etching to form two disconnected gate structures 1500 in the sacrificial gap 400. Exemplarily, a bottom punch-down etching process may be used to disconnect the gate structure 1500 at the bottom of the sacrificial gap 400 to expose the semiconductor doping layer 1600. The barrier layer 1510, the dielectric layer 1520 and the gate conductive layer 1530 that is not removed may be used to form the gate structure 1500. The gate structure 1500 may be located on the sidewall of the semiconductor pillar 1110 and may extend along the third direction Y.

[0089] Exemplarily, a back-etching process may be used to remove part of the gate conductive layer 1530 along the second direction Z, so that the upper end of the gate conductive layer 1530 is below the top surface of the semiconductor column 1110. In addition, since the barrier layer 1510 and the dielectric layer 1520 are not back-etched, the upper end of the gate conductive layer 1530 is below the upper ends of the barrier layer 1510 and the dielectric layer 1520. In this way, the back-etched gate conductive layer 1530 may extend along the third direction Y, and its portion corresponding to the semiconductor column 1110 may serve as a gate electrode. The gate structure 1500 may be connected to a peripheral circuit to achieve transmission of electrical signals between the gate electrode and the peripheral circuit.

[0090] Exemplarily, the semiconductor pillar 1110 and the gate structure 1500 may be used together to form a vertical transistor, wherein the semiconductor pillar 1110 may be used to form an active region of multiple channels in the vertical transistor. Exemplarily, the gate structure 1500 may be located on at least one sidewall of the semiconductor pillar 1110, that is, the semiconductor pillar 1110 may be at least partially surrounded by the gate structure 1500. For example, the semiconductor pillar 1110, the barrier layer 1510, the dielectric layer 1520, and the gate conductive layer 1530 may be radially arranged in this order from the center of the vertical transistor. Exemplarily, the barrier layer 1510 may surround and contact the semiconductor pillar 1110. The dielectric layer 1520 may surround and contact the barrier layer 1510. The gate conductive layer 1530 may surround and contact the dielectric layer 1520.

[0091] It should be understood that Fig.21 The situation in which the gate structure 1500 is located on one sidewall of the semiconductor pillar 1110 is only an example and is not specifically limited.

[0092] In one embodiment of the present application, the gate structure 1500 may be located on multiple sidewalls of the semiconductor column 1110, in which case the semiconductor column 1110 and the gate structure 1500 may be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, better speed (saturated drain current) / leakage current performance may be achieved using a multi-gate transistor.

[0093] In another embodiment of the present application, the gate structure 1500 may be located on a side wall of the semiconductor column 1110, and the semiconductor column 1110 and the gate structure 1500 may be used together to form a single-gate transistor. For example, the single-gate transistors adjacent to each other along the first direction X may be arranged symmetrically. By providing a single-gate transistor, the present application can significantly increase the density of the semiconductor column 1110 in the first direction X and reduce the difficulty of the manufacturing process. In addition, the mirror-symmetrical single-gate transistor may have a larger process window, which is conducive to reducing the spacing between the bit lines, word lines and transistors formed subsequently.

[0094] Fig. 22 and Fig.23 is a schematic diagram of a structure for forming a dielectric layer and a separation structure according to an exemplary embodiment of the present application, wherein: Fig.23 for Fig. 22 A schematic cross-sectional view along the BB direction. For example, Fig. 22 and Fig.23As shown, a filling dielectric layer 1540 may be formed along the second direction Z through the gate conductive layer 1530 and the dielectric layer 1520 and extending to the semiconductor doping layer 1600 . In other words, the filling dielectric layer 1540 may be formed in the gap 600 .

[0095] For example, one or more thin film deposition processes may be used to deposit and form a filling dielectric layer 1540 in the gap 600. The material of the filling dielectric layer 1540 includes, but is not limited to, silicon oxide. In addition, a planarization process such as a mechanical grinding process may be performed to remove the filling dielectric layer 1540, the second dielectric layer 120, and the first dielectric layer 110 on the surface of the semiconductor pillar 1110.

[0096] For example, Fig. 22 As shown, a separation structure 700 may be formed to penetrate the barrier layer 1510, the dielectric layer 1520, and the gate conductive layer 1530 along the second direction Z to separate the annular gate structure 1500 in the sacrificial gap 400 into at least two parts. For example, two separation structures 700 with a certain interval may be formed in each annular gate structure 1500 to separate the annular gate structure 1500 into two parts. In other words, the two separation structures 700 separate the annular barrier layer 1510 into two parts, separate the dielectric layer 1520 into two parts, and separate the gate conductive layer 1530 into two parts.

[0097] It should be understood that the present application does not specifically limit the size and / or position of the separation structure 700 , and the size and / or position of the separation structure 700 may be arbitrarily set according to the actual process to separate the gate structure 1500 in the sacrificial gap 400 into two parts.

[0098] Exemplarily, a doped region (not shown) may be formed at the second end 1112 of the semiconductor column 1110. The doped portion 1113 and the doped region may be the drain and source of the semiconductor column 1110, respectively. The source and the drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). When the gate voltage applied to the gate conductive layer 1530 of the gate structure 1500 is higher than the threshold voltage of the vertical transistor (including the gate structure 1500 and the semiconductor column 1110), one or more channels of the vertical transistor may be formed vertically in the semiconductor column 1110 between the source and the drain.

[0099] In the exemplary embodiment of the present application, Fig.24As shown, a capacitor 1700 connected to the second end 1112 of the semiconductor pillar 1110 may be formed. The capacitor 1700 may include a first electrode (not shown) connected to the doped region (located at the second end 1112), a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1700 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. Exemplarily, the capacitor 1700 may be a vertical capacitor in which the first electrode, the capacitor dielectric, and the second electrode are stacked along the second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0100] Fig.25 For the general Fig.24 A schematic diagram of a structure in which the structure is flipped 180° and then thinned. In an exemplary embodiment of the present application, Fig.25 As shown, a bit line 1800 contacting the doped portion 1113 and extending along the first direction X may be formed on a side close to the semiconductor doped layer 1600 .

[0101] For example, a portion of the semiconductor layer 1100 may be removed from a side close to the semiconductor doping layer 1600 to expose the doped portion 1113 located at the first end 1111 of the semiconductor column 1110; then, a bit line 1800 may be formed on a side close to the semiconductor doping layer 1600 to contact the doped portion 1113 (such as a drain) and extend along the first direction X.

[0102] For example, a chemical mechanical polishing process may be used to remove a portion of the semiconductor layer 1100 to expose the doped portion 1113. One or more deposition processes may be used to deposit and form the bit line 1800. In the present application, a word line) may be coupled to the gate electrode of the transistor to turn the transistor on or off. The bit line 1800 may be coupled to the doped portion 1113 (e.g., drain) of the transistor and serve as a path for charging or discharging the capacitor 1700.

[0103] For example, a lead structure (not shown) connected to the isolation structure 1200 may be formed on one side close to the semiconductor doping layer 1600. In the present application, the lead structure may be grounded or a certain fixed potential may be applied to the lead structure, so that the isolation structure 1200 can electrically insulate adjacent semiconductor pillars 1110 and reduce coupling between adjacent semiconductor pillars 1110.

[0104] Fig.25 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment of the present application.

[0105] The semiconductor structure may include a plurality of semiconductor pillars 1110 , a gate structure 1500 , and a semiconductor doping layer 1600 .

[0106] The plurality of semiconductor pillars 1110 may extend along the second direction Z and be distributed in an array along the first direction X and the third direction Y, wherein the first direction X, the second direction Z, and the third direction Y intersect each other. For example, the first direction X and the third direction Y intersect, and the second direction Z may be perpendicular to the first direction X and the third direction Y. For another example, the first direction X, the second direction Z, and the third direction Y are perpendicular to each other.

[0107] Exemplarily, a plurality of semiconductor pillars 1110 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1110. For example, the semiconductor pillars 1110 may have a cubic shape to expose four sidewalls thereof. It should be understood that the semiconductor pillars 1110 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1110 in a plan view (e.g., in an XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0108] The material of the semiconductor pillar 1110 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0109] The gate structure 1500 may be located on at least one side of the semiconductor pillar 1110 along the first direction X. For example, the gate structure 1500 may be located on at least one sidewall of the semiconductor pillar 1110 along the first direction X and may extend along the third direction Y. For example, semiconductor pillars 1110 adjacent to each other along the first direction X may be isolated by the gate structure 1500 .

[0110] The semiconductor doping layer 1600 may include doping ions, and may be located at one side of the gate structure 1500 along the second direction Z. The doping ions may include, for example, N-type doping ions.

[0111] In an exemplary embodiment of the present application, the semiconductor pillar 1110 may include a first end 1111 and a second end 1112 disposed opposite to each other along the second direction Z. The semiconductor pillar 1110 further includes a doping portion 1113 located at the first end 1111. The doping portion 1113 may overlap with a projection portion of the gate structure 1500 along the first direction X. Exemplarily, the doping portion 1113 may be formed by diffusing doping ions in the semiconductor doping layer 1600 to the first end 1111. For example, an annealing process may be performed on the semiconductor doping layer 1600 to diffuse doping ions such as N-type doping ions to the first end 1111 to form the doping portion 1113.

[0112] By setting a semiconductor doping layer 1600, the present application can diffuse the doped ions in the semiconductor doping layer 1600 to the first end 1111 to form a doped portion 1113, and can also control the position of the gate structure 1500, such as the gate structure 1500 is located above the semiconductor doping layer 1600, which is beneficial to control the relative position relationship between the doped portion 1113 and the gate structure 1500 and reduce the coupling phenomenon between the gate structure 1500 and the doped portion 1113.

[0113] By way of example, the gate structure 1500 may include a gate conductive layer 1530 and a gate dielectric layer. The gate conductive layer 1530 may be located on at least one side of the semiconductor pillar 1110 along the first direction X, wherein the semiconductor doping layer 1600 may be located on one side of the gate conductive layer 1530 along the second direction Z. The gate dielectric layer may be located between the gate conductive layer 1530 and the semiconductor pillar 1110 and between the gate conductive layer 1530 and the semiconductor doping layer 1600. By way of example, the gate dielectric layer may include a barrier layer 1510 and a dielectric layer 1520. The barrier layer 1510 may be located between the gate conductive layer 1530 and the semiconductor pillar 1110, that is, the barrier layer 1510 may be located on at least one side wall of the semiconductor pillar 1110 along the first direction X and extend to the surface of the semiconductor doping layer 1600 along the second direction Z. The dielectric layer 1520 may be located between the gate conductive layer 1530 and the barrier layer 1510 and between the gate conductive layer 1530 and the semiconductor doping layer 1600. The gate conductive layer 1530 and the semiconductor doping layer 1600 may be separated by the dielectric layer 1520.

[0114] The barrier layer 1510 and the dielectric layer 1520 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the barrier layer 1510 and the dielectric layer 1520 may include silicon oxide. The gate conductive layer 1530 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide.

[0115] The upper end of the gate conductive layer 1530 may be below the top surface of the semiconductor pillar 1110 and below the upper ends of the barrier layer 1510 and the dielectric layer 1520. The gate conductive layer 1530 may extend along the third direction Y, and a portion thereof corresponding to the semiconductor pillar 1110 may serve as a gate electrode. The gate structure 1500 may be connected to a peripheral circuit to transmit electrical signals between the gate electrode and the peripheral circuit.

[0116] Exemplarily, the semiconductor pillar 1110 and the gate structure 1500 may be used together to form a vertical transistor, wherein the semiconductor pillar 1110 may be used to form an active region of multiple channels in the vertical transistor. Exemplarily, the gate structure 1500 may be located on at least one sidewall of the semiconductor pillar 1110, that is, the semiconductor pillar 1110 may be at least partially surrounded by the gate structure 1500. For example, the semiconductor pillar 1110, the barrier layer 1510, the dielectric layer 1520, and the gate conductive layer 1530 may be radially arranged in this order from the center of the vertical transistor. Exemplarily, the barrier layer 1510 may surround and contact the semiconductor pillar 1110. The dielectric layer 1520 may surround and contact the barrier layer 1510. The gate conductive layer 1530 may surround and contact the dielectric layer 1520.

[0117] It should be understood that Fig.25 The situation in which the gate structure 1500 is located on one sidewall of the semiconductor pillar 1110 is only an example and is not specifically limited.

[0118] In one embodiment of the present application, the gate structure 1500 may be located on multiple sidewalls of the semiconductor column 1110, in which case the semiconductor column 1110 and the gate structure 1500 may be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). The multi-gate transistor may have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the cut-off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, better speed (saturated drain current) / leakage current performance may be achieved using a multi-gate transistor.

[0119] In another embodiment of the present application, the gate structure 1500 may be located on a side wall of the semiconductor column 1110, and the semiconductor column 1110 and the gate structure 1500 may be used together to form a single-gate transistor. For example, the single-gate transistors adjacent to each other along the first direction X may be arranged symmetrically. By providing a single-gate transistor, the present application can significantly increase the density of the semiconductor column 1110 in the first direction X and reduce the difficulty of the manufacturing process. In addition, the mirror-symmetrical single-gate transistor may have a larger process window, which is conducive to reducing the spacing between the bit lines, word lines and transistors formed subsequently.

[0120] In the exemplary embodiment of the present application, the semiconductor structure may further include an isolation structure 1200. The gate structure 1500 may be located at a first sidewall of the semiconductor pillar 1110 along the first direction X, and the isolation structure 1200 may be located at a second sidewall of the semiconductor pillar 1110 opposite to the first sidewall and extend along the third direction Y. In other words, the isolation structure 1200 and the gate structure 1500 may be located at both sidewalls of the semiconductor pillar 1110 along the first direction X, respectively.

[0121] The isolation structure 1200 may include an isolation conductive layer 1210 and an isolation dielectric layer 1220 surrounding the isolation conductive layer 1210. The material of the isolation conductive layer 1210 may include but is not limited to metal materials such as tungsten and copper. The material of the isolation dielectric layer 1220 may include but is not limited to silicon oxide.

[0122] Exemplarily, the semiconductor structure may further include a lead-out structure (not shown) connected to the isolation structure 1200. In the present application, the lead-out structure may be grounded or a certain fixed potential may be applied to the lead-out structure, so that the isolation structure 1200 can electrically insulate adjacent semiconductor pillars 1110 and reduce coupling between adjacent semiconductor pillars 1110.

[0123] In the exemplary embodiment of the present application, the semiconductor structure may further include a filling dielectric layer 1540. The filling dielectric layer 1540 may pass through the gate conductive layer 1530 and the dielectric layer 1520 along the second direction Z and extend to the semiconductor doping layer 1600. The material of the filling dielectric layer 1540 includes, but is not limited to, silicon oxide.

[0124] Exemplarily, the semiconductor structure may further include a doped region (not shown) located at the second end 1112 of the semiconductor column 1110. The doped portion 1113 and the doped region may be the drain and source of the semiconductor column 1110, respectively. The source and the drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)) or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). When the gate voltage applied to the gate conductive layer 1530 of the gate structure 1500 is higher than the threshold voltage of the vertical transistor (including the gate structure 1500 and the semiconductor column 1110), one or more channels of the vertical transistor may be formed vertically in the semiconductor column 1110 between the source and the drain.

[0125] Exemplarily, the semiconductor structure may further include a capacitor 1700 connected to the second end 1112 of the semiconductor column 1110. The capacitor 1700 may include a first electrode (not shown) connected to the doped region (located at the second end 1112), a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1700 may include, but is not limited to, a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. Exemplarily, the capacitor 1700 may be a vertical capacitor, in which the first electrode, the capacitor dielectric, and the second electrode are stacked along the second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0126] Exemplarily, the semiconductor structure may further include a bit line 1800 located near one side of the semiconductor doping layer 1600 and in contact with the doping portion 1113. The bit line 1800 may extend along the first direction X. In the present application, the word line may be coupled to the gate electrode of the transistor to turn the transistor on or off. The bit line 1800 may be coupled to the doping portion 1113 (e.g., the drain) of the transistor and serve as a path for charging or discharging the capacitor 1700.

[0127] Since the contents and structures involved in the method 1000 for manufacturing a semiconductor structure described above may be fully or partially applicable to the semiconductor structure described herein, the contents related or similar thereto will not be described in detail herein.

[0128] Although the exemplary structure and method of making the semiconductor structure are described herein, it is understood that one or more features may be omitted, replaced or added from the method of making the semiconductor structure. In addition, the illustrated layers and materials thereof are merely exemplary.

[0129] Fig.26 is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of the present application.

[0130] The system 10 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device having the storage system 12 located therein). Fig.26As shown, the system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0131] The three-dimensional memory 14 may include a semiconductor structure described in any embodiment of the present application. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate function may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0132] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig.27AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Fig.26 The host 18 in the memory card connector 24 is coupled. Fig.27B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Fig.26 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0133] The above description is only a preferred embodiment of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept. For example, the above features are replaced with the technical features with similar functions disclosed in this application (but not limited to) by each other.

Claims

1. A method for manufacturing a semiconductor structure, It is characterized in that The semiconductor layer includes a plurality of initial semiconductor pillars extending along a first direction and a second direction, and the method includes: Forming a plurality of sacrificial structures that pass through the initial semiconductor column and extend along a third direction and are arranged along the first direction, wherein the first direction, the second direction, and the third direction intersect each other, and the plurality of sacrificial structures divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction; removing part of the sacrificial structure along the second direction to form a sacrificial gap; replacing the remaining sacrificial structure with a semiconductor doped layer; and A gate structure is formed in the sacrificial gap, wherein the gate structure and the semiconductor doping layer are adjacently distributed along the second direction.

2. The method according to claim 1, It is characterized in that The semiconductor column comprises a first end and a second end disposed opposite to each other along the second direction, wherein the first end is closer to the semiconductor doping layer than the second end, and the method further comprises: A doped portion is formed at the first end, wherein the doped portion partially overlaps with a projection of the gate structure along the first direction.

3. The method according to claim 2, It is characterized in that The method comprises: The doping portion is formed by diffusing doping ions in the semiconductor doping layer to the first end.

4. The method according to claim 1, It is characterized in that A plurality of sacrificial structures are formed which pass through the initial semiconductor column, extend along a third direction and are arranged along the first direction, comprising: The sacrificial structures and the isolation structures are formed to pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction, wherein the sacrificial structures and the isolation structures divide the initial semiconductor column into a plurality of semiconductor columns extending along the second direction.

5. The method according to claim 1, It is characterized in that Replacing the remaining sacrificial structure with a semiconductor doping layer comprises: forming a barrier layer on a sidewall of the sacrificial gap; removing the remaining sacrificial structure to form a gap; and The semiconductor doping layer is formed in the gap.

6. The method according to claim 5, It is characterized in that A gate structure is formed in the sacrificial gap, comprising: forming a dielectric layer on the sidewall of the barrier layer and the surface of the semiconductor doping layer; and A gate conductive layer is formed on the surface of the dielectric layer.

7. The method according to claim 3, It is characterized in that The doping ions include N-type doping ions, and the method includes: An annealing process is performed on the semiconductor doping layer to diffuse the N-type doping ions to the first end.

8. The method according to claim 2, It is characterized in that The method further comprises: A capacitor is formed connected to the second end.

9. The method according to claim 4, It is characterized in that The sacrificial structure and the isolation structure are formed to pass through the initial semiconductor column and extend along the third direction and to be alternately arranged along the first direction, comprising: forming a plurality of the initial semiconductor pillars extending along the first direction and the second direction in the semiconductor layer; forming first trenches and second trenches that pass through the initial semiconductor pillars and extend along the third direction and are alternately arranged along the first direction; and The sacrificial structure and the isolation structure are formed in the first trench and the second trench, respectively.

10. The method according to claim 9, It is characterized in that Forming a first trench and a second trench that pass through the initial semiconductor column and extend along the third direction and are alternately arranged along the first direction, comprising: forming, in the semiconductor layer, initial first trenches and second trenches that pass through the initial semiconductor pillars and extend along the third direction and are alternately arranged along the first direction; forming a first sacrificial layer and a second sacrificial layer in the initial first trench and the second trench, respectively; removing the second sacrificial layer along a second direction, and forming the isolation structure in the removed space; and The first sacrificial layer is removed, and the width and depth of the initial first trench are increased to form the first trench.

11. The method according to claim 4, It is characterized in that The method further comprises: A lead-out structure connected to the isolation structure is formed on a side close to the semiconductor doping layer.

12. The method according to claim 2 or 3, It is characterized in that The method further comprises: A bit line is formed on a side close to the semiconductor doping layer, contacting the doping portion and extending along the first direction.

13. A semiconductor structure, It is characterized in that include: Semiconductor columns; A gate structure, located on at least one side of the semiconductor column along the first direction; as well as The semiconductor doping layer is located on one side of the gate structure along a second direction, wherein the second direction intersects with the first direction.

14. The semiconductor structure according to claim 13, It is characterized in that The semiconductor column includes a first end and a second end opposite to each other along the second direction, wherein the semiconductor column further includes a doped portion located at the first end, and the doped portion partially overlaps with a projection of the gate structure along the first direction.

15. The semiconductor structure according to claim 13, It is characterized in that The gate structure is located at the first side wall of the semiconductor column and extends along a third direction intersecting with the second direction, and the semiconductor structure further includes: The isolation structure is located at a second sidewall of the semiconductor column opposite to the first sidewall and extends along the third direction.

16. The semiconductor structure according to claim 13, It is characterized in that The gate structure comprises: a gate conductive layer, located on at least one side of the semiconductor column along the first direction, wherein the semiconductor doping layer is located on one side of the gate conductive layer along the second direction; and A gate dielectric layer is located between the gate conductive layer and the semiconductor pillar and between the gate conductive layer and the semiconductor doping layer.

17. The semiconductor structure according to claim 16, It is characterized in that The gate dielectric layer comprises: a barrier layer, located on at least one side wall of the semiconductor column along the first direction and extending to a surface of the semiconductor doping layer along the second direction; and The dielectric layer is located between the gate conductive layer and the barrier layer and between the gate conductive layer and the semiconductor doping layer.

18. The semiconductor structure according to claim 14, It is characterized in that The semiconductor structure further comprises: A capacitor is connected to the second end.

19. The semiconductor structure according to claim 15, It is characterized in that The semiconductor structure further comprises: The lead-out structure is located at a side close to the semiconductor doping layer and connected to the isolation structure.

20. The semiconductor structure according to claim 14, It is characterized in that The semiconductor structure further comprises: The bit line is located at a side close to the semiconductor doping layer and is in contact with the doping portion.

21. A storage system, It is characterized in that include: At least one three-dimensional memory, each of the three-dimensional memory comprising a semiconductor structure as claimed in any one of claims 13 to 20; as well as The controller is coupled to the semiconductor structure and is used for controlling the three-dimensional memory to store data.

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