Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the steps that a substrate is provided, a suspension gate layer is formed on the top of the substrate, and a control gate layer is arranged on the top of the suspension gate layer in a protruding mode; forming a first side wall layer on the side wall of the control gate layer; after the first side wall layer is formed, a second side wall layer covering the side wall of the first side wall layer is formed on the top of the substrate; and taking the first side wall layer and the second side wall layer as masks, performing graphical processing on the suspension gate layer, and removing the suspension gate layer at the side part of the control gate layer. The side wall of the first side wall layer and the side wall of the second side wall layer are smooth, the probability that the first side wall layer is in an L shape is reduced, the morphology of the side wall of the patterned suspended gate layer can be flat and smooth, the probability that the side wall of the suspended gate layer is uneven is reduced, and therefore the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be divided into three main types: analog circuits, digital circuits, and mixed analog / digital circuits. Among them, memory devices are an important type of digital circuits. In recent years, among memory devices, flash memory has developed particularly rapidly. The main feature of flash memory is that it can retain stored information for a long time without power; it also has the advantages of high integration, fast access speed, easy erasure and rewriting, etc., so it has been widely used in many fields such as microcomputers and automation control.

[0003] However, the performance of flash memory still needs to be improved. Summary of the invention

[0004] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure, thereby improving the performance of the semiconductor device.

[0005] To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, a floating gate layer is formed on the top of the substrate, and a control gate layer is protruded on the top of the floating gate layer; a first sidewall layer is formed on the sidewall of the control gate layer; after the first sidewall layer is formed, a second sidewall layer is formed on the top of the substrate to cover the sidewall of the first sidewall layer; using the first sidewall layer and the second sidewall layer as masks, the floating gate layer is patterned to remove the floating gate layer on the side of the control gate layer.

[0006] Optionally, the step of forming the control gate layer includes: forming a control gate material layer on top of the floating gate layer; forming a patterned hard mask layer on top of the control gate material layer; using the patterned hard mask layer as a mask, patterning the control gate material layer to form a protruding control gate layer on top of the floating gate layer.

[0007] Optionally, the first spacer layer includes a first sub-spacer layer covering a sidewall of the control gate layer, and a second sub-spacer layer covering a sidewall of the first sub-spacer layer.

[0008] Optionally, the step of forming the first sidewall layer includes: forming a first sub-sidewall material layer on the top of the floating gate layer exposed by the control gate layer, and on the top and sidewall of the control gate layer; forming a second sub-sidewall material layer covering the first sub-sidewall material layer; removing the second sub-sidewall material layer on the top of the floating gate layer and the second sub-sidewall material layer on the top of the control gate layer, and using the first sub-sidewall material layer located on the sidewall of the control gate layer and the remaining second sub-sidewall material layer as the first sidewall layer; in the step of forming the second sidewall layer, the first sub-sidewall material layer on the top of the floating gate layer and the first sub-sidewall material layer on the top of the floating gate layer are also removed.

[0009] Optionally, the process of removing the second sub-spacer material layer on the top of the floating gate layer and the second sub-spacer material layer on the top of the control gate layer includes a dry etching process.

[0010] Optionally, process parameters of the dry etching process include: process gases include argon, oxygen and fluoromethane; and the chamber pressure ranges from 60 mTorr to 90 mTorr.

[0011] Optionally, in the process of removing the second sub-spacer material layer on the top of the floating gate layer and the second sub-spacer material layer on the top of the control gate layer, an etching selectivity ratio of the second sub-spacer material layer to the first sub-spacer material layer is greater than 10:1.

[0012] Optionally, in the step of forming the first spacer layer, the thickness of the first spacer layer is 13 nanometers to 17 nanometers.

[0013] Optionally, the step of forming the second sidewall layer includes: forming a second sidewall material layer on the top of the floating gate layer exposed by the control gate layer, on the sidewall of the first sidewall layer and on the top of the control gate layer; removing the second sidewall material layer on the top of the floating gate layer and the second sidewall material layer on the top of the control gate layer, and using the remaining second sidewall material layer located on the sidewall of the control gate layer as the second sidewall layer.

[0014] Optionally, the process of removing the second spacer material layer on the top of the floating gate layer and the second spacer material layer on the top of the control gate layer includes a dry etching process.

[0015] Optionally, process parameters of the dry etching process include: process gases include argon, oxygen and fluoromethane; and the chamber pressure ranges from 10 mTorr to 20 mTorr.

[0016] Optionally, in the step of forming the second spacer layer, the thickness of the second spacer layer is 33 nanometers to 40 nanometers.

[0017] Optionally, the process of patterning the floating gate layer by using the first spacer layer and the second spacer layer as masks comprises a dry etching process.

[0018] Optionally, in the step of providing a substrate, a gate oxide layer is also formed on the top of the substrate, and the gate oxide layer is located between the substrate and the floating gate layer; after removing the floating gate layer on the side of the control gate layer, the method for forming the semiconductor structure also includes: forming a third sidewall layer covering the sidewalls of the second sidewall layer and the sidewalls of the floating gate layer on the top of the substrate; forming an erase gate layer covering the gate oxide layer and the third sidewall layer between adjacent control gate layers and between adjacent floating gate layers, and forming a word line structure covering the gate oxide layer and the third sidewall layer on the side opposite to each other of the adjacent control gate layers and on the side opposite to each other of the adjacent floating gate layers.

[0019] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0020] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first spacer layer is formed on the side wall of the control gate layer; after the first spacer layer is formed, a second spacer layer covering the side wall of the first spacer layer is formed on the top of the substrate; the first spacer layer and the second spacer layer are used as masks to perform patterning on the floating gate layer, and the floating gate layer on the side of the control gate layer is removed. Compared with the solution in which the first spacer layer and the second spacer layer are formed in the same step, the first spacer layer and the second spacer layer are formed in different steps in the embodiment of the present invention. In the process of forming the first spacer layer, the process of forming the first spacer layer consumes part of the side wall of the first spacer layer, so that the second spacer layer is not formed. The side wall of one side wall layer becomes smooth, which reduces the probability that the first side wall layer is L-shaped. Correspondingly, in the process of forming the second side wall layer, the process of forming the second side wall layer will consume part of the side wall of the second side wall layer, so that the side wall of the second side wall layer also becomes smooth. In the subsequent process of patterning the floating gate layer using the first side wall layer and the second side wall layer as masks, since the first side wall layer and the second side wall layer are used as etching masks and the side walls of the first side wall layer and the second side wall layer are relatively smooth, the morphology of the side wall of the patterned floating gate layer can also be relatively flat and smooth, which reduces the probability of unevenness on the side wall of the floating gate layer, thereby improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1 to 3 is a structural schematic diagram corresponding to a method for forming a semiconductor structure;

[0022] Figures 4 to 11 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0023] At present, the performance of semiconductor structures still needs to be improved. The reasons why the performance of semiconductor structures needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0024] Figures 1 to 3 The present invention is a structural schematic diagram corresponding to a method for forming a semiconductor structure.

[0025] refer to Figure 1 A substrate 10 is provided, a floating gate layer 12 is formed on the top of the substrate 10, a control gate layer 14 is protruded on the top of the floating gate layer 12, a first spacer material layer 16 covering the floating gate layer 12 and the control gate layer 14, and a second spacer material layer 17 covering the first spacer material layer 16 are formed on the top of the substrate 10.

[0026] refer to Figure 2 , remove the first spacer material layer 16 and the second spacer material layer 17 on the top of the floating gate layer 12 exposed by the control gate layer 14, as well as the first spacer material layer 16 and the second spacer material layer 17 on the top of the control gate layer 14, and the remaining first spacer material layer 16 serves as the first spacer layer 20, and the remaining second spacer material layer 17 serves as the second spacer layer 18.

[0027] refer to Figure 3 , using the first spacer layer 20 and the second spacer layer 18 as masks, the floating gate layer 12 on the side of the control gate layer 14 is patterned to remove the floating gate layer 12 on the side of the control gate layer 14 .

[0028] Through research, it is found that the first sidewall layer and the second sidewall layer are formed by a dry etching process, and the first sidewall layer and the second sidewall layer are formed in the same step. In the process of forming the first sidewall layer and the second sidewall layer by the dry etching process, the first sidewall layer is L-shaped, that is, it is easy to cause the part protruding from the side wall of the first sidewall layer to remain (such as Figure 2 As shown in the dotted circle in the middle, accordingly, in the subsequent process of patterning the floating gate layer 12 on the side of the control gate layer 14, it is easy to cause the side wall morphology of the second side wall layer to be uneven. Accordingly, in the subsequent process of patterning the floating gate layer 12 on the side of the control gate layer 14 using the first side wall layer and the second side wall layer as masks, it is easy to cause the side wall morphology of the patterned floating gate layer 12 to be uneven. In the subsequent process of reliability testing of the semiconductor structure, electrons are easy to escape from the uneven side wall morphology of the floating gate layer 12, thereby affecting the performance of the semiconductor structure.

[0029] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a floating gate layer is formed on the top of the substrate, and a control gate layer is protruded on the top of the floating gate layer; forming a first sidewall layer on the sidewall of the control gate layer; after forming the first sidewall layer, forming a second sidewall layer on the top of the substrate to cover the sidewall of the first sidewall layer; using the first sidewall layer and the second sidewall layer as masks, patterning the floating gate layer to remove the floating gate layer on the side of the control gate layer.

[0030] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first spacer layer is formed on the side wall of the control gate layer; after the first spacer layer is formed, a second spacer layer covering the side wall of the first spacer layer is formed on the top of the substrate; the first spacer layer and the second spacer layer are used as masks to perform patterning on the floating gate layer, and the floating gate layer on the side of the control gate layer is removed. Compared with the solution in which the first spacer layer and the second spacer layer are formed in the same step, the first spacer layer and the second spacer layer are formed in different steps in the embodiment of the present invention. In the process of forming the first spacer layer, the process of forming the first spacer layer consumes part of the side wall of the first spacer layer, so that the second spacer layer is not formed. The side wall of one side wall layer becomes smooth, which reduces the probability that the first side wall layer is L-shaped. Correspondingly, in the process of forming the second side wall layer, the process of forming the second side wall layer will consume part of the side wall of the second side wall layer, so that the side wall of the second side wall layer also becomes smooth. In the subsequent process of patterning the floating gate layer using the first side wall layer and the second side wall layer as masks, since the first side wall layer and the second side wall layer are used as etching masks and the side walls of the first side wall layer and the second side wall layer are relatively smooth, the morphology of the side wall of the patterned floating gate layer can also be relatively flat and smooth, which reduces the probability of unevenness on the side wall of the floating gate layer, thereby improving the performance of the semiconductor structure.

[0031] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0032] refer to Figures 4 to 11 , showing a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0033] refer to Figure 4 , a substrate 100 is provided, a floating gate layer 102 is formed on the top of the substrate 100 , and a control gate layer 104 is protruded on the top of the floating gate layer 102 .

[0034] The substrate 100 provides a process platform for forming a Flash memory.

[0035] In this embodiment, the substrate 100 includes a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0036] The floating gate layer 102 is used to store electrons during the operation of the Flash memory, so that the Flash memory can perform the function of data storage.

[0037] In this embodiment, the material of the floating gate layer 102 is polysilicon.

[0038] Polysilicon is a commonly used material for the suspended gate layer 102 in a Flash memory, and thus has the characteristic of low process cost.

[0039] As an example, in the step of providing the substrate 100 , a gate oxide layer 101 is further formed on the top of the substrate 100 , and the gate oxide layer 101 is located between the substrate 100 and the suspended gate layer 102 .

[0040] Specifically, the gate oxide layer 101 is a tunnel oxide layer (Tunnel Oxide) of the Flash memory, which is used as an isolation insulating layer between the floating gate layer 102 and the substrate 100, so that when the flash memory is working, the tunneling effect is used to allow electrons to enter the floating gate layer 102 through the gate oxide layer 101. Moreover, during the data storage process, the electrons stored in the floating gate layer 102 are prevented from entering the silicon substrate, thereby reducing the loss of electrons. That is, the gate oxide layer 101 is suitable for preventing the data stored in the floating gate layer 102 from being lost.

[0041] As an example, the material of the gate oxide layer 101 is silicon oxide. In other embodiments, the material of the gate oxide layer may also be silicon oxynitride.

[0042] It should be noted that the thickness of the gate oxide layer 101 should not be too large or too small. If the thickness of the gate oxide layer 101 is too large, after the control gate layer 104 is formed, it is easy to cause the overall height of the Flash memory to be too high, which is not conducive to further shrinking the semiconductor structure; if the thickness of the gate oxide layer 101 is too small, during the data storage process, the probability of the electrons stored in the floating gate layer 102 entering the substrate 100 is increased, thereby increasing the probability of electron loss, and further affecting the storage performance of the Flash memory. For this reason, in this embodiment, the thickness of the gate oxide layer 101 is 7 nanometers to 11 nanometers.

[0043] Specifically, the control gate layer 104 is used to be electrically connected to an external circuit structure to control the longitudinal electric field of the floating gate layer 102 .

[0044] As an example, the steps of forming the control gate layer 104 include: forming a control gate material layer (not shown) on the top of the floating gate layer 102; forming a patterned hard mask layer 105 on the top of the control gate material layer; using the patterned hard mask layer 105 as a mask, patterning the control gate material layer to form a protruding control gate layer 104 on the top of the floating gate layer 102.

[0045] As an example, the process of patterning the control gate material layer using the patterned hard mask layer 105 as a mask includes a dry etching process.

[0046] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has anisotropic dry etching characteristics, and its longitudinal etching rate is greater than the lateral etching rate. The process controllability is relatively high. The dry etching process is used to perform patterning on the control gate material layer, which can ensure the morphology quality of the side wall of the control gate layer 104 and make the morphology of the side wall of the control gate layer 104 relatively flat and smooth. Accordingly, in the subsequent process of forming the first side wall layer and the second side wall layer, the process difficulty of depositing the film layer on the side wall of the control gate layer 104 is reduced, and the uniformity of the film layer thickness can be improved.

[0047] In this embodiment, the material of the control gate layer 104 is polysilicon.

[0048] Polysilicon is a commonly used material for the suspended gate layer 102 in a Flash memory, and thus has the characteristic of low process cost.

[0049] In this embodiment, in the step of providing the substrate 100 , a gate insulating layer 103 is further formed between the floating gate layer 102 and the control gate layer 104 .

[0050] The gate insulating layer 103 is used to electrically isolate the floating gate layer 102 and the control gate layer 104 .

[0051] As an example, the gate insulating layer 103 is a silicon oxide layer-silicon nitride layer-silicon oxide layer (Oxide-Nitride-Oxide, ONO) structure.

[0052] The ONO structure can reduce the thickness of the gate insulating layer 103 of the Flash memory and further increase the dielectric constant of the gate insulating layer 103, thereby making the Flash memory have a higher breakdown electric field and lower leakage characteristics.

[0053] In other embodiments, the gate insulating layer may also be a single-layer structure, and the gate insulating layer is a silicon oxide layer or a silicon nitride layer.

[0054] refer to Figures 5 and 6, a first spacer layer 112 is formed on the sidewall of the control gate layer 104 .

[0055] It should be noted that, compared with the solution in which the first spacer layer 112 and the second spacer layer are formed in the same step, in this embodiment, the first spacer layer 112 and the subsequently formed second spacer layer are formed in different steps respectively. In the process of forming the first spacer layer 112, the process of forming the first spacer layer 112 consumes part of the sidewall of the first spacer layer 112, so that the sidewall of the first spacer layer 112 becomes smooth, thereby reducing the probability that the first spacer layer is L-shaped. Correspondingly, in the process of forming the second spacer layer, the process of forming the second spacer layer consumes part of the sidewall of the second spacer layer. Part of the sidewall of the spacer layer makes the sidewall of the second spacer layer smooth. In the subsequent process of patterning the floating gate layer 102 with the first spacer layer 112 and the second spacer layer as masks, since the first spacer layer 112 and the second spacer layer are used as etching masks and the sidewalls of the first spacer layer 112 and the second spacer layer are relatively smooth, the morphology of the sidewall of the patterned floating gate layer 102 can also be relatively flat and smooth, which reduces the probability of unevenness on the sidewall of the floating gate layer 102, thereby improving the performance of the semiconductor structure.

[0056] It should also be noted that the first spacer layer 112 is also used to electrically isolate the floating gate layer 102 from the subsequently formed erase gate layer and word line structure, and the control gate layer 104 from the subsequently formed erase gate layer and word line structure.

[0057] In this embodiment, the first spacer layer 112 includes a first sub-spacer layer 110 covering the sidewall of the control gate layer 104 , and a second sub-spacer layer 108 covering the sidewall of the first sub-spacer layer 110 .

[0058] Specifically, the first sub-spacer layer 110 acts as an etching stop layer. In the process of forming the second sub-spacer layer 108, the material forming the first sub-spacer layer 110 protects the side walls and top of the floating gate layer 102, as well as the side walls and top of the control gate layer 104, thereby reducing the probability of the process of forming the second sub-spacer layer 108 causing damage to the floating gate layer 102 and the control gate layer 104, thereby improving the performance of the semiconductor structure.

[0059] In this embodiment, the step of forming the first spacer layer 112 includes: forming a first sub-spacer material layer 106 on the top of the floating gate layer 102 exposed by the control gate layer 104, and on the top and sidewall of the control gate layer 104; forming a second sub-spacer material layer 107 covering the first sub-spacer material layer 106; removing the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104, and using the first sub-spacer material layer 106 located on the side wall of the control gate layer 104 as the first sub-spacer layer 110, and using the remaining second sub-spacer material layer 107 as the second sub-spacer layer 108, and the first sub-spacer layer 110 and the second sub-spacer layer 108 constitute the first spacer layer 112.

[0060] The first sub-spacer material layer 106 is used as a material layer for forming the first sub-spacer layer 110 .

[0061] In the process of removing the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104, the first sub-spacer material layer 106 acts as an etching stop layer. The first sub-spacer material layer 106 protects the sidewall and top of the floating gate layer 102 and the sidewall and top of the control gate layer 104, reducing the probability of damage to the floating gate layer 102 and the control gate layer 104, thereby improving the performance of the semiconductor structure.

[0062] In this embodiment, the process of removing the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104 includes a dry etching process.

[0063] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has anisotropic dry etching characteristics, and its longitudinal etching rate is greater than the lateral etching rate. The process controllability is high. The dry etching process is used to remove the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104, so that the first sub-spacer material layer 106 can protect the side wall and top of the floating gate layer 102 and the side wall and top of the control gate layer 104. When the dry etching process is used to remove the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104, the dry etching process will also consume part of the side wall of the second sub-spacer layer 108. Since the longitudinal etching rate of the dry etching process is greater than the lateral etching rate, the side wall morphology of the second sub-spacer layer 108 becomes smooth, which correspondingly means that the side wall morphology of the first spacer layer 112 becomes smooth, thereby improving the side wall morphology quality of the first spacer layer 112.

[0064] In this embodiment, in the dry etching process, the process gas includes argon, oxygen and fluoromethane.

[0065] In the dry etching process, oxygen is used as an auxiliary gas to promote the etching reaction. Argon is used as a functional auxiliary gas in the dry etching process to increase the etching rate of the etching process. Fluoromethane is used as an etching gas in the dry etching process.

[0066] It should be noted that in the dry etching process, the chamber pressure range should not be too large or too small. If the chamber pressure in the dry etching process is too large, it is easy to cause the concentration of the reaction gas per unit volume to be too high, and the probability of collision between electrons and ions in the plasma will be higher, thereby causing energy loss of charged reaction particles, thereby reducing the bombardment ability of ions in the dry etching process; if the chamber pressure in the dry etching process is too small, it is easy to cause the plasma mean free path to be longer, thereby affecting the etching rate of the dry etching process. For this reason, in this embodiment, in the dry etching process, the chamber pressure range is 60mTorr to 90mTorr.

[0067] It should also be noted that in the process of removing the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104, the etching selectivity ratio of the second sub-spacer material layer 107 and the first sub-spacer material layer 106 should not be too small. If the etching selectivity ratio of the second sub-spacer material layer 107 and the first sub-spacer material layer 106 is too small, the first sub-spacer material layer 106 may be easily removed during the process of removing the second sub-spacer material layer 107, thereby increasing the probability of the floating gate layer 102 and the control gate layer 104 being damaged. At the same time, the probability of the surface of the first sub-spacer material layer 106 being damaged is also increased, resulting in poor surface flatness of the first sub-spacer material layer 106. In the subsequent process of forming the second spacer layer, the probability of the second spacer layer having uneven thickness is increased, thereby affecting the subsequent patterned floating gate layer 102, causing the sidewall morphology of the floating gate layer 102 to be uneven, thereby affecting the performance of the semiconductor structure. To this end, in this embodiment, in the process of removing the second sub-spacer material layer 107 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second sub-spacer material layer 107 on the top of the control gate layer 104, the etching selectivity ratio of the second sub-spacer material layer 107 and the first sub-spacer material layer 106 is greater than 10:1.

[0068] Specifically, the thickness of the first sidewall layer 112 should not be too large or too small. If the thickness of the first sidewall layer 112 is too large, it is easy to affect the size of the semiconductor device; in the process of forming the first sidewall layer 112 by a dry etching process, the dry etching process will also consume part of the sidewall of the first sidewall layer 112. If the thickness of the first sidewall layer 112 is too small, it is easy to cause the first sidewall layer 112 to be completely consumed or the remaining thickness of the first sidewall layer 112 to be smaller, which cannot meet the thickness requirements and dielectric constant requirements of the Flash memory for the first sidewall layer 112, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the first sidewall layer 112 is 13 nanometers to 17 nanometers.

[0069] refer to Figures 7 and 8 After forming the first spacer layer 112 , a second spacer layer 122 is formed on the top of the substrate 100 to cover the sidewalls of the first spacer layer 112 .

[0070] It should be noted that in the process of forming the second sidewall layer 122, the process of forming the second sidewall layer 122 will consume part of the sidewall of the second sidewall layer 122, so that the sidewall of the second sidewall layer 122 also becomes smooth. In the subsequent process of patterning the floating gate layer 102 using the first sidewall layer 112 and the second sidewall layer 122 as masks, since the first sidewall layer 112 and the second sidewall layer 122 are used as etching masks and the sidewalls of the first sidewall layer 112 and the second sidewall layer 122 are relatively smooth, the morphology of the sidewall of the patterned floating gate layer 102 can also be relatively flat and smooth, which reduces the probability of unevenness on the sidewall of the floating gate layer 102 and improves the flatness of the sidewall of the floating gate layer 102, thereby improving the performance of the semiconductor structure.

[0071] In this embodiment, the step of forming the second spacer layer 122 includes: forming a second spacer material layer 123 on the top of the floating gate layer 102 exposed by the control gate layer 104, the side wall of the first spacer layer 112 and the top of the control gate layer 104; removing the second spacer material layer 123 on the top of the floating gate layer 102 and the second spacer material layer 123 on the top of the control gate layer 104, and using the remaining second spacer material layer 123 located on the side wall of the control gate layer 104 as the second spacer layer 122.

[0072] In this embodiment, the process of removing the second spacer material layer 123 on the top of the floating gate layer 102 and the second spacer material layer 123 on the top of the control gate layer 104 includes a dry etching process.

[0073] Specifically, the dry etching process is an anisotropic dry etching process, and the anisotropic dry etching process has anisotropic dry etching characteristics, and its longitudinal etching rate is greater than the lateral etching rate, and the process controllability is high. The second sidewall material layer 123 on the top of the floating gate layer 102 and the second sidewall material layer 123 on the top of the control gate layer 104 are removed by the dry etching process, and the second sidewall material layer 123 on the top of the floating gate layer 102 and the second sidewall material layer 123 on the top of the control gate layer 104 exposed by the control gate layer 104 can be removed cleanly, and the second sidewall material layer 123 on the side wall of the control gate layer 104 is retained. As the second spacer layer 122, at the same time, in the process of using a dry etching process to remove the second spacer material layer 123 on the top of the floating gate layer 102 exposed by the control gate layer 104 and the second spacer material layer 123 on the top of the control gate layer 104, the dry etching process will also consume part of the sidewall of the second spacer layer 122. Since the longitudinal etching rate of the dry etching process is greater than the lateral etching rate, the sidewall morphology of the second spacer layer 122 becomes smooth. In the subsequent process of patterning the floating gate layer 102, the first spacer layer 112 and the second spacer layer 122 are used as etching masks, thereby improving the flatness of the sidewall of the floating gate layer 102.

[0074] In this embodiment, in the dry etching process, the process gas includes argon, oxygen and fluoromethane.

[0075] In the dry etching process, oxygen is used as an auxiliary gas to promote the etching reaction. Argon is used as a functional auxiliary gas in the dry etching process to increase the etching rate of the etching process. Fluoromethane is used as an etching gas in the dry etching process.

[0076] It should be noted that in the dry etching process, the chamber pressure range should not be too large or too small. If the chamber pressure in the dry etching process is too large, it is easy to cause the concentration of the reaction gas per unit volume to be too high, and the probability of collision between electrons and ions in the plasma will be higher, thereby causing energy loss of charged reaction particles, thereby reducing the bombardment ability of ions in the dry etching process; if the chamber pressure in the dry etching process is too small, it is easy to cause the plasma mean free path to be longer, thereby affecting the etching rate of the dry etching process. For this reason, in this embodiment, in the dry etching process, the chamber pressure range is 60mTorr to 90mTorr.

[0077] It should also be noted that, during the process of forming the second spacer material layer 123 , the second spacer material layer 123 covers the first sub-spacer material layer 106 located on the top of the floating gate layer 102 and the first sub-spacer material layer 106 located on the top of the control gate layer 104 .

[0078] In this embodiment, in the step of forming the second spacer layer 122 , the first sub-spacer material layer 106 on the top of the floating gate layer 102 and the first sub-spacer material layer 106 on the top of the floating gate layer 102 are also removed.

[0079] Specifically, in the process of removing the second spacer material layer 123 on the top of the floating gate layer 102 and the second spacer material layer 123 on the top of the control gate layer 104, the first sub-spacer material layer 106 on the top of the floating gate layer 102 and the first sub-spacer material layer 106 on the top of the floating gate layer 102 are removed, which means that the second spacer material layer 123 and the first sub-spacer material layer 106 are removed in the same step, thereby reducing the process steps and lowering the process cost.

[0080] In other embodiments, after removing the second spacer material layer on the top of the floating gate layer and the second spacer material layer on the top of the control gate layer, the first sub-spacer material layer on the top of the floating gate layer and the first sub-spacer material layer on the top of the floating gate layer may be removed.

[0081] It should be noted that the thickness of the second spacer layer 122 should not be too large or too small. If the thickness of the second spacer layer 122 is too large, it is easy to affect the size of the semiconductor device; if the thickness of the second spacer layer 122 is too small, in the process of forming the second spacer layer 122 by the dry etching process, the dry etching process will also consume part of the sidewall of the second spacer layer 122, which is easy to cause the second spacer layer 122 to be completely consumed or make the remaining second spacer layer 122 thinner, which cannot meet the thickness requirements and dielectric constant requirements of the Flash memory for the second spacer layer 122, thereby affecting the performance of the semiconductor structure. For this reason, in this embodiment, the thickness of the second spacer layer 122 is 33 nanometers to 40 nanometers.

[0082] refer to Fig. 9 , using the first spacer layer 112 and the second spacer layer 122 as masks, the floating gate layer 102 is patterned to remove the floating gate layer 102 on the side of the control gate layer 104 .

[0083] Specifically, the floating gate layer 102 is patterned to remove the floating gate layer 102 at the side of the control gate layer 104, so as to provide a space for the erase gate layer and word line structure to be formed subsequently.

[0084] In this embodiment, the process of patterning the floating gate layer 102 by using the first spacer layer 112 and the second spacer layer 122 as masks includes a dry etching process.

[0085] Specifically, the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has anisotropic dry etching characteristics, and its longitudinal etching rate is greater than the lateral etching rate. The process controllability is relatively high. Since the first sidewall layer 112 and the second sidewall layer 122 are used as etching masks, and the sidewalls of the first sidewall layer 112 and the second sidewall layer 122 are relatively smooth, the morphology of the sidewalls of the patterned floating gate layer 102 can also be relatively flat and smooth, which reduces the probability of unevenness on the sidewalls of the floating gate layer 102 and improves the flatness of the sidewalls of the floating gate layer 102, thereby improving the performance of the semiconductor structure.

[0086] refer to Figure 10 to Figure 11The method for forming the semiconductor structure also includes: forming a third spacer layer 130 covering the sidewalls of the second spacer layer 122 and the sidewalls of the floating gate layer 102 on the top of the substrate 100; forming an erase gate layer 140 covering the gate oxide layer 101 and the third spacer layer 130 between adjacent control gate layers 104 and between adjacent floating gate layers 102, and forming a word line (WL) structure covering the gate oxide layer 101 and the third spacer layer 130 on the opposite side of the adjacent control gate layer 104 and the opposite side of the adjacent floating gate layer 102.

[0087] Specifically, the third spacer layer 130 is used to achieve electrical isolation between the erase gate layer 140 and the floating gate layer 102 , and electrical isolation between the word line structure 150 and the floating gate layer 102 .

[0088] In this embodiment, the material of the third spacer layer 130 includes one or more of silicon oxide, silicon nitride and silicon oxynitride.

[0089] The erase gate layer 140 is used to implement signal erasure of the Flash memory.

[0090] Specifically, by applying a high voltage to the erase gate layer 140, a potential difference is formed on the third sidewall layer 130 between the erase gate layer 140 and the floating gate layer 102 due to the coupling capacitance, which can pull the electrons in the floating gate layer 102 to the erase gate layer 140 through tunneling. As the electrons in the floating gate layer 102 are pulled out, the potential in the floating gate layer 102 increases, and the difference between its potential and that of the erase gate layer 140 is reduced, thereby weakening the potential difference of the gate insulating layer 103. Finally, the electrons in the floating gate layer 102 are completely pulled out, thereby realizing the signal erasure of the memory.

[0091] In this embodiment, the material of the erase gate layer 140 includes polysilicon.

[0092] The word line structure 150 is used to control channel electrons.

[0093] Specifically, a high voltage is applied to the word line structure 150 to open the channel, and a high voltage is applied to the control gate layer 104 to create a strong vertical electric field between the floating gate layer 102 and the control gate layer 104. The strong vertical electric field accelerates the channel electrons in the vertical direction, and a portion of the electrons are injected into the floating gate layer 102, thereby achieving electron injection and signal writing.

[0094] As an example, the material of the word line structure 150 is polysilicon.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, comprising: providing a substrate, on the top of which a floating gate layer is formed, and a control gate layer protrudes on the top of the floating gate layer; forming a first sidewall layer on the sidewalls of the control gate layer; after forming the first sidewall layer, forming a second sidewall layer on the top of the substrate to cover the sidewalls of the first sidewall layer; using the first sidewall layer and the second sidewall layer as masks to pattern the floating gate layer and removing the floating gate layer on the side of the control gate layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, the step of forming the control gate layer includes: forming a control gate material layer on the top of the floating gate layer; forming a patterned hard mask layer on the top of the control gate material layer; using the patterned hard mask layer as a mask to pattern the control gate material layer and forming a protruding control gate layer on the top of the floating gate layer.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, the first sidewall layer includes a first sub-sidewall layer covering the sidewalls of the control gate layer and a second sub-sidewall layer covering the sidewalls of the first sub-sidewall layer.

4. The method for forming a semiconductor structure according to claim 3, characterized in that, the step of forming the first sidewall layer includes: forming a first sub-sidewall material layer on the top of the floating gate layer exposed by the control gate layer, on the top and sidewalls of the control gate layer; forming a second sub-sidewall material layer covering the first sub-sidewall material layer; removing the second sub-sidewall material layer on the top of the floating gate layer exposed by the control gate layer and the second sub-sidewall material layer on the top of the control gate layer, using the first sub-sidewall material layer located on the sidewalls of the control gate layer as the first sub-sidewall layer, and using the remaining second sub-sidewall material layer as the second sub-sidewall layer, and the first sub-sidewall layer and the second sub-sidewall layer constitute the first sidewall layer; in the step of forming the second sidewall layer, the first sub-sidewall material layer on the top of the floating gate layer and the first sub-sidewall material layer on the top of the floating gate layer are also removed.

5. The method for forming a semiconductor structure according to claim 4, characterized in that, the process of removing the second sub-sidewall material layer on the top of the floating gate layer exposed by the control gate layer and the second sub-sidewall material layer on the top of the control gate layer includes a dry etching process.

6. The method for forming a semiconductor structure according to claim 5, characterized in that, the process parameters of the dry etching process include: the process gas includes argon, oxygen and fluoromethane; the chamber pressure range is 60 mTorr to 90 mTorr.

7. The method for forming a semiconductor structure according to claim 4, characterized in that, during the process of removing the second sub-sidewall material layer on the top of the floating gate layer exposed by the control gate layer and the second sub-sidewall material layer on the top of the control gate layer, the etching selectivity between the second sub-sidewall material layer and the first sub-sidewall material layer is greater than 10:

1.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, in the step of forming the first sidewall layer, the thickness of the first sidewall layer is 13 nanometers to 17 nanometers.

9. The method for forming a semiconductor structure according to claim 1, It is characterized in that The step of forming the second spacer layer includes: forming a second spacer material layer on the top of the floating gate layer exposed by the control gate layer, the side wall of the first spacer layer and the top of the control gate layer; removing the second spacer material layer on the top of the floating gate layer and the second spacer material layer on the top of the control gate layer, and using the remaining second spacer material layer located on the side wall of the control gate layer as the second spacer layer.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The process of removing the second spacer material layer on the top of the floating gate layer and the second spacer material layer on the top of the control gate layer includes a dry etching process.

11. The method for forming a semiconductor structure according to claim 10, It is characterized in that The process parameters of the dry etching process include: the process gas includes argon, oxygen and fluoromethane; the chamber pressure ranges from 10mTorr to 20mTorr.

12. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of forming the second spacer layer, the thickness of the second spacer layer is 33 nanometers to 40 nanometers.

13. The method for forming a semiconductor structure according to claim 1, It is characterized in that The process of patterning the floating gate layer by using the first spacer layer and the second spacer layer as masks includes a dry etching process.

14. The method for forming a semiconductor structure according to claim 1, It is characterized in that In the step of providing a substrate, a gate oxide layer is also formed on the top of the substrate, and the gate oxide layer is located between the substrate and the suspended gate layer; After removing the floating gate layer on the side of the control gate layer, the method for forming the semiconductor structure further includes: forming a third spacer layer covering the sidewalls of the second spacer layer and the sidewalls of the floating gate layer on the top of the substrate; An erase gate layer covering the gate oxide layer and the third sidewall layer is formed between adjacent control gate layers and between adjacent floating gate layers, and a word line structure covering the gate oxide layer and the third sidewall layer is formed on the opposite sides of adjacent control gate layers and the opposite sides of adjacent floating gate layers.

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