Hybrid gate high electron mobility transistor, preparation method and testing method thereof

Abstract

The present invention discloses a hybrid gate high electron mobility transistor, a preparation method and a test method thereof. The transistor can be configured in depletion mode or enhancement mode, and the gate structure is composed of p-GaN semiconductor layers in different proportions. Inductively coupled plasma reactive ion etching technology is used in the preparation process to protect the gate structure and reduce defects. When the device is working, by applying a driving voltage to the gate, the built-in electric field of the p-GaN / AlGaN / GaN heterojunction is regulated under the source and drain bias, and the two-dimensional electron gas under the gate is depleted, and the degree of depletion varies with the p-GaN ratio. Applying a positive bias can restore the two-dimensional electron gas. The entire preparation process strictly follows the standard gallium nitride technical process and does not require additional modification. This design can effectively reduce gate leakage, provide a stable and adjustable threshold voltage, and achieve flexible control of the device's normally on and normally off states by adjusting the p-GaN ratio.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor preparation, and in particular to a hybrid gate high electron mobility transistor, a preparation method and a testing method thereof. Background Art

[0002] Currently, direct bandgap gallium nitride semiconductors are one of the most promising candidate materials in the field of power electronics. GaN has excellent material properties, including a high bandgap of up to 2.5×10 7 GaN boasts a high electron saturation drift velocity of cm / s, a wide bandgap of 3.4 eV, excellent thermal stability, strong radiation resistance, and a high breakdown field strength of up to 2.2 MV / cm. Furthermore, spontaneous and piezoelectric polarization effects at the GaN / GaN heterojunction interface can form a high-mobility and high-concentration two-dimensional electron gas (2DEG). Furthermore, GaN is compatible with low-cost, highly mature silicon-based semiconductor integrated circuit technology. GaN-based devices have been widely used in next-generation high-power, small-size lasers, radio frequency (RF) and microwave devices, power converters, semiconductor lighting, and other applications.

[0003] In a gallium nitride (GaN)-based high electron mobility transistor (HEMT), when a drain-source voltage (VDS) is applied between the drain and source, the two-dimensional electron gas (2DEG) is driven by a lateral electric field and directed along the AlGaN (aluminum gallium nitride) / GaN (gallium nitride) heterojunction interface, generating an on-state current. By adjusting the applied gate voltage, the 2DEG channel can be effectively controlled to open and close, thereby achieving device switching. However, in traditional AlGaN / GaN HEMT structures, the inherent presence of 2DEG due to polarization effects causes the device to operate in a normally-on mode. This means that the device is always on at zero gate bias and requires a negative gate bias to turn it off.

[0004] In practical circuit applications, such as startup circuits, depletion-mode (D-mode) devices with negative threshold voltages are often required to clamp a specific potential to achieve biasing. However, while existing metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) can achieve threshold voltage (Vth) control to a certain extent by adjusting the thickness of the dielectric layer, this approach has significant limitations. Specifically, to obtain MIS-HEMT devices with different Vths, dielectric layers of varying thicknesses must be designed and an additional mask layer must be introduced to define specific Vth regions. This not only increases process complexity and cost but also makes mask alignment and process control more difficult. Furthermore, the interface states formed during dielectric layer deposition significantly impact device performance, further reducing Vth uniformity across the wafer and making device reliability difficult to guarantee. This limits the widespread adoption of MIS-HEMTs in high-reliability and large-scale integration applications. Summary of the Invention

[0005] The object of the present invention is to provide a hybrid gate high electron mobility transistor, a preparation method and a testing method thereof, so as to achieve flexible regulation of the normally-on and normally-off states of the device.

[0006] In order to solve the above technical problems, the present invention provides a hybrid gate high electron mobility transistor, comprising: a substrate;

[0007] An N-type channel layer, a barrier layer, and a P-type semiconductor layer are sequentially stacked along a first direction, wherein the first direction is a direction from the substrate to the P-type semiconductor layer;

[0008] The P-type semiconductor layer includes a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; the second direction is a direction perpendicular to the source and pointing to the drain.

[0009] When the occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%, the sub-P-type semiconductor layer includes a plurality of sub-P-type semiconductor layer islands equidistantly arranged along the second direction; when the occupancy ratio of the sub-P-type semiconductor layer is 100%, the sub-P-type semiconductor layer includes one sub-P-type semiconductor layer island;

[0010] Passivation dielectric layer and Schottky metal layer;

[0011] The passivation dielectric layer is provided on the surface of the barrier layer in an area not covered by the P-type semiconductor layer;

[0012] The Schottky metal layer is provided on the surface of the P-type semiconductor layer to simultaneously form a metal / semiconductor Schottky contact and a MIS gate;

[0013] The occupancy ratio is:

[0014] P p-GaN = W p-GaN / W total ;

[0015] Among them, P p-GaN is the occupancy ratio, W total is the width of a sub-P-type semiconductor layer, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layer islands in a corresponding sub-P-type semiconductor layer.

[0016] Furthermore, the sub-P-type semiconductor layer includes a plurality of sub-P-type semiconductor layer islands equidistantly arranged along the second direction, wherein an occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%.

[0017] Furthermore, the P-type semiconductor layer includes a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; and the second direction is the direction from the source to the drain.

[0018] Furthermore, the P-type semiconductor layer includes a sub-P-type semiconductor layer with an occupancy ratio of 0%, a sub-P-type semiconductor layer with an occupancy ratio of 75%, a sub-P-type semiconductor layer with an occupancy ratio of 50% and / or a sub-P-type semiconductor layer with an occupancy ratio of 100%.

[0019] On the other hand, the present invention further discloses a method for preparing a hybrid gate high electron mobility transistor, the method comprising:

[0020] providing a substrate;

[0021] An N-type channel layer, a barrier layer, and a P-type semiconductor layer are sequentially stacked on the substrate;

[0022] Marking formation areas of each sub-P-type semiconductor layer on the P-type semiconductor layer;

[0023] marking an etching region of the sub-P-type semiconductor layer on the formation region;

[0024] Plasma etching is performed on the etched area to form a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction and having different occupancy ratios on the surface of the barrier layer; wherein the second direction is a direction perpendicular to the source and pointing to the drain; the occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%.

[0025] Further, performing plasma etching on the etching area includes:

[0026] Introducing an etching gas into the reaction chamber; wherein the etching gas comprises boron trichloride and chlorine; and the gas flow ratio of the boron trichloride to the chlorine is in the range of 1:1-3:1;

[0027] Applying radio frequency power into the reaction chamber, the radio frequency power is used to ionize the etching gas to form plasma, and the plasma is used to perform plasma etching on the etching area; wherein the radio frequency power ranges from 10W to 15W.

[0028] Furthermore, the method further comprises:

[0029] Depositing a passivation dielectric layer on the surface of the P-type semiconductor layer and the barrier layer by an evaporation method;

[0030] The passivation dielectric layer on the surface of the P-type semiconductor layer is etched.

[0031] Furthermore, the method further comprises:

[0032] Depositing a Schottky metal layer on the P-type semiconductor layer by an electron beam evaporation deposition method, and performing a uniform temperature-raising annealing process on the Schottky metal layer;

[0033] The growth areas of the source and drain are marked on the passivation dielectric layer, the growth areas are plasma etched to form empty areas, and a metal layer is deposited in the empty areas to form the source and drain.

[0034] On the other hand, the present invention further discloses a method for testing a hybrid gate high electron mobility transistor, the method comprising:

[0035] Probe operation on HEMT;

[0036] collecting an electrical signal from the HEMT;

[0037] Analyzing and processing the electrical signal to obtain electrical test curves of different high electron mobility transistors;

[0038] It is determined whether the HEMT can realize gate controllability between a normally-off state and a normally-on state according to the electrical test curve.

[0039] Compared with the prior art, the present invention has at least the following beneficial effects:

[0040] By designing the P-type semiconductor layer as multiple sub-P-type semiconductor layers with different duty ratios arranged horizontally (the second direction), the threshold voltage (Vth) of each device region can be flexibly controlled, enabling the integration of enhancement-mode (E-mode) and depletion-mode (D-mode) HEMTs on the same GaN device. This design requires no additional processing steps and is compatible with existing GaN platforms. It offers a simple process and highly precise Vth control, effectively reducing gate leakage current and improving device reliability and high-voltage withstand capability. It is particularly suitable for high-power, high-frequency, and highly integrated applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic cross-sectional view of a HEMT in Example 1 of the present invention;

[0042] Figure 2 4 is a top view of a HEMT with a P-type semiconductor layer occupancy ratio of 75% in Example 1 of the present invention;

[0043] Figure 3 4 is a top view of a HEMT in which the occupancy ratio of the P-type semiconductor layer is 50% in Example 1 of the present invention;

[0044] Figure 4 4 is a top view of a HEMT in which the occupancy ratio of the P-type semiconductor layer is 100% in Example 1 of the present invention;

[0045] Figure 5 Schematic diagram of the preparation process of the hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0046] Figure 6 Schematic diagram of the preparation process of a hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0047] Figure 7 Schematic diagram of another preparation process of a hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0048] Figure 8 Schematic diagram of another preparation process of a hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0049] Figure 9 Schematic diagram of another preparation process of a hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0050] Figure 10 Schematic diagram of another preparation process of a hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0051] Figure 11 Schematic diagram of another preparation process of a hybrid gate high electron mobility transistor in the second embodiment of the present invention;

[0052] Figure 12 Graph showing transmission curves of the first sub-P-type semiconductor, the second sub-P-type semiconductor, and the third sub-P-type semiconductor in the third embodiment of the present invention;

[0053] Figure 13 This is an output curve diagram of the first sub-P-type semiconductor, the second sub-P-type semiconductor, and the third sub-P-type semiconductor in the third embodiment of the present invention;

[0054] Figure 14 This is a breakdown curve diagram of the first sub-P-type semiconductor in the third embodiment of the present invention;

[0055] Figure 15 This is a breakdown curve diagram of the second sub-P-type semiconductor in the third embodiment of the present invention;

[0056] Figure 16 This is a breakdown curve diagram of the third sub-P-type semiconductor in the third embodiment of the present invention. DETAILED DESCRIPTION

[0057] The hybrid-gate high electron mobility transistor, its fabrication method, and its testing method of the present invention are described below with reference to schematic diagrams. Preferred embodiments of the present invention are shown. It should be understood that those skilled in the art may modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a general guide for those skilled in the art and not as a limitation of the present invention.

[0058] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact scale, and are provided solely for the purpose of assisting in the description of the embodiments of the present invention.

[0059] Example 1

[0060] The inventors discovered that in gallium nitride-based devices, when a driving voltage is applied to the gate and the device is under source-drain bias stress conditions, the p-GaN layer located in the gate region generates hot electrons due to carrier acceleration. These hot electrons can be effectively compensated by the hole channels provided in the gate structure, thereby significantly reducing gate leakage current under gate / drain voltage stress conditions and effectively maintaining the stability of the device threshold voltage (Vth). In addition, the inventors further discovered that by adjusting the coverage ratio of the p-GaN (P-type doped gallium nitride) layer in the gate structure of the gallium nitride device, the device threshold voltage can be precisely controlled, giving the device adjustable characteristics from normally-off to normally-on, thereby enhancing the device's flexibility and applicability.

[0061] Please refer to Figure 1 Based on the above findings, this embodiment discloses a hybrid gate high electron mobility transistor (HG-HEMT), comprising:

[0062] A substrate 1; an N-type channel layer 2, a barrier layer 3, a P-type semiconductor layer 4, and a Schottky metal layer sequentially stacked along a first direction, wherein the first direction is from the substrate 1 toward the P-type semiconductor layer 4. The P-type semiconductor layer 4 includes a plurality of sub-P-type semiconductor layers sequentially arranged along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; the second direction is perpendicular to the source and toward the drain.

[0063] In this embodiment, after the introduction of the N-type channel layer 2, a heterostructure is formed consisting of the N-type channel layer 2, the barrier layer 3, and the P-type peninsular bulk layer 4. These three layers form an electrically equivalent PIN junction (P-type-barrier layer-N-type). The built-in electric field of the PIN structure effectively raises the potential at the heterojunction interface above the Fermi level, thereby depleting the 2DEG beneath the gate, thereby achieving the device's normally-off characteristic. Applying a positive gate bias overcomes the built-in electric field, allowing the 2DEG to re-accumulate and restore conduction. Furthermore, by designing the P-type semiconductor layer 4 as multiple sub-P-type semiconductor layers with different duty ratios arranged horizontally (in the second direction), the Vth of each device region can be flexibly controlled, enabling the integration of enhancement-mode (E-mode) and depletion-mode (D-mode) HEMTs (high electron mobility transistors) on the same semiconductor device. This design requires no additional processing steps and is compatible with existing GaN platforms. It offers a simple process and high Vth control precision, effectively reducing gate leakage current and improving device reliability and high-voltage withstand capability.

[0064] It should be understood that Vth in this embodiment refers to the gate voltage at which the two-dimensional electron gas (2DEG) in the channel below the gate is completely depleted. When the gate voltage is lower than Vth, the 2DEG in the channel is completely depleted, leaving only minimal leakage current. At this point, the device is in the off state.

[0065] The N-type channel layer 2 prepared in this embodiment is composed of GaN material and includes a buffer layer. The buffer layer has a thickness of 5 μm, and the overall thickness of the N-type channel layer 2 is 200 nm. It is understood that those skilled in the art can introduce a buffer layer and / or a transition layer between the N-type channel layer 2 and the substrate 1 according to actual conditions.

[0066] The barrier layer 3 prepared in this embodiment is made of AlGaN material. The specific thickness of the barrier layer 3 is 15 nm. The aluminum content in the AlGaN material is between 10% and 30%.

[0067] The P-type semiconductor layer 4 prepared in this embodiment is composed of p-GaN doped with Mg (magnesium).

[0068] A p-type semiconductor layer 4 (p-GaN) is introduced between the gate and the AlGaN / GaN heterojunction to form a p-GaN / AlGaN / GaN heterostructure. The Schottky metal layer and the p-type semiconductor layer 4 form a metal-semiconductor (MS) heterojunction, while the p-type semiconductor layer 4 and the AlGaN / GaN layer form an electrically equivalent PIN (P-type-functional barrier layer 3-N-type) heterojunction structure. Both GaN and AlGaN are Group III nitride semiconductor materials, and the polarization effect generates a polarization-induced electrostatic field at their heterojunction interface. This electrostatic field modulates the band structure and carrier distribution, prompting a large number of electrons to transfer to the lower-energy AlGaN / GaN interface, forming a 2DEG channel extending along the first direction.

[0069] The built-in electric field of the PIN structure can effectively increase the potential at the heterojunction interface, raising it above the Fermi level of the 2DEG, thereby depleting the 2DEG below the gate and achieving the normally-off characteristic of the device. When a positive gate bias is applied, the built-in electric field can be overcome, causing the depleted 2DEG to reaccumulate and resume conduction, forming a current path. After applying a drain-source bias voltage (VDS), the 2DEG is directed along the heterojunction interface under the action of the lateral electric field, completing current conduction. The gate acts as a control terminal, and by adjusting the applied gate voltage, it can effectively control the switching state of the 2DEG channel, thereby realizing the switching function of the device.

[0070] In this embodiment, the occupancy ratio is calculated as follows:

[0071] P p-GaN = W p-GaN / W total ;

[0072] Among them, P p-GaN is the occupancy ratio, W total is the width of a sub-P-type semiconductor layer, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layer islands in a corresponding sub-P-type semiconductor layer.

[0073] With P p-GaNWith the change of (p-GaN proportion), the electrical connection method of the gate will also be different. E-mode HEMT (enhancement mode high electron mobility transistor) uses 100% p-GaN islands. Its gate is composed entirely of p-GaN, and the opening of the 2DEG channel is controlled by the gate voltage. D-mode HEMT (depletion mode high electron mobility transistor) uses 0% p-GaN. Its gate structure does not include p-GaN. The gate voltage is applied negatively to control the closing of the 2DEG. HG-HEMT (hybrid high electron mobility transistor) uses different proportions of p-GaN islands in the gate design. These islands are filled with other materials to control the effect of the gate voltage on the two-dimensional electron gas.

[0074] Please refer to Figure 2-Figure 3 Furthermore, the plurality of sub-P-type semiconductor layers include a plurality of sub-P-type semiconductor layer islands arranged equidistantly along the second direction, wherein the occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%.

[0075] In this embodiment, to achieve uniform electric field distribution and enhance device reliability and controllability, the multiple sub-P-type semiconductor layer islands are preferably arranged equidistantly along the second direction. This equidistant arrangement effectively avoids problems with excessively strong or weak local electric fields, reduces the risk of breakdown, and ensures a uniform distribution of the 2DEG depletion region, thereby achieving stable and adjustable Vth. Furthermore, this equidistant arrangement facilitates precise control of processes such as lithography and etching, improving manufacturing consistency and mass production yield, further enhancing device performance and application reliability.

[0076] Please refer to Figure 4 Furthermore, the P-type semiconductor layer 4 also includes a sub-P-type semiconductor layer with an occupancy ratio of 100%.

[0077] When the occupancy ratio of the sub-P-type semiconductor layer is equal to 100%, the sub-P-type semiconductor layer achieves full coverage in the gate region, which can completely deplete the 2DEG in the N-type channel layer 2, so that the device is in the off state under zero gate-source bias, thereby making the device exhibit E-mode transistor characteristics with Vth greater than 0V.

[0078] Please refer to Figure 5 Furthermore, the P-type semiconductor layer 4 may also include a sub-P-type semiconductor layer with an occupancy ratio of 0%.

[0079] When the P-type semiconductor layer accounts for 0%, the device's gate structure contains no P-type semiconductor layer at all, which usually causes the device to operate in D-mode. In this mode, the device is in the on state when no gate voltage is applied, and only when a sufficiently negative gate voltage is applied will the 2DEG be depleted and the device will be turned off.

[0080] In a specific embodiment, the P-type semiconductor layer 4 includes three sequentially arranged sub-P-type semiconductor layers, with occupancy rates of 100%, 75% and 50% respectively.

[0081] The 100% occupancy region enables the GaN device to be completely turned off at zero gate bias, improving the stability of the normally-off device. The 75% and 50% occupancy regions provide progressive 2DEG compensation, enabling Vth to be continuously adjustable between positive and negative values, thereby optimizing the device's performance in different operating modes.

[0082] It is understood that those skilled in the art can select sub-P-type semiconductor layers with different duty ratios according to actual conditions to form a desired gate structure. The number of sub-P-type semiconductor layers can also be selected according to actual conditions to enhance 2DEG compensation or adjust Vth to achieve desired switching characteristics and electrical performance.

[0083] Furthermore, in this embodiment, a passivation dielectric layer is further included between each of the sub-P-type semiconductor layer islands, and on the surface of the sub-P-type semiconductor layer islands.

[0084] In a specific embodiment, the P-type semiconductor layer 4 is generally formed of magnesium-doped P-type GaN, and the passivation dielectric layer 5 is composed of AlN. The thickness of the two layers is generally 50-100 nm.

[0085] Furthermore, in this embodiment, a Schottky metal layer 6 is stacked on the surface of the P-type semiconductor layer 4 to form a Schottky contact and an MIS (metal-insulator-semiconductor) gate.

[0086] In a specific embodiment, the thickness of the Schottky metal layer 6 is 5-10 mm.

[0087] Furthermore, in this embodiment, a source electrode 8 and a drain electrode 7 are further included, which are located at two ends of the HEMT and serve as the input and output ends of the current, respectively.

[0088] In a specific embodiment, the source electrode 8 and the drain electrode 7 are formed by sequentially stacking TiN (titanium nitride), Al (aluminum), Ti (titanium), and TiN (titanium nitride).

[0089] Example 2

[0090] Based on the same inventive concept, this embodiment discloses a method for preparing a hybrid gate HEMT, for preparing the hybrid gate HEMT disclosed in the first embodiment, the method comprising:

[0091] S1. Providing a substrate 1;

[0092] S2. An N-type channel layer 2, a barrier layer 3 and a P-type semiconductor layer 4 are sequentially stacked on the substrate 1;

[0093] S3. Marking the formation region of each sub-P-type semiconductor layer on the P-type semiconductor layer 4;

[0094] S4. Marking the etching region of the sub-P-type semiconductor layer on the formation region;

[0095] S5. Plasma etching is performed on the etched area to form a plurality of sub-P-type semiconductor layers arranged in sequence along the second direction and having different occupancy ratios on the surface of the barrier layer 3; wherein the second direction is a direction perpendicular to the source and pointing to the drain; the occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%.

[0096] Through the above process flow, etching of gate structures with different proportions is organically integrated with the device preparation process. The prepared HEMT structure can be configured as D-mode or E-mode according to design requirements, and has high voltage tolerance. Its gate structure is composed of P-type semiconductor layers 4 with different proportions, and the threshold voltage Vth is precisely adjusted by the occupancy ratio of the P-type semiconductor layer. Specifically, under source-drain bias stress conditions, when a driving voltage is applied to the gate, the design of different occupancy ratios can effectively enhance the electric field in the depletion region, improve the carrier depletion efficiency, and then regulate Vth, so that the HEMT can flexibly switch between D-mode and normally-off E-mode working states. In addition, under the action of gate / drain voltage stress, the design can effectively reduce gate leakage current and stabilize the Vth of the device, thereby improving the reliability and voltage resistance of the device. In summary, the present invention helps to form gallium nitride devices with stable physical and chemical properties, facilitates subsequent applications and performance testing, and has good application prospects.

[0097] Please refer to Figure 6 In a specific embodiment of step S2, a P-type silicon substrate 1 is used as a base. An N-type channel layer 2 composed of GaN, a barrier layer 3 composed of AlGaN, and a P-type semiconductor layer 4 composed of p-GaN are epitaxially grown in sequence by MOCVD (metal organic chemical vapor deposition), forming a p-GaN / AlGaN / GaN heterostructure.

[0098] Furthermore, in this embodiment, a mask is applied to the surface of the P-type semiconductor layer 4 and plasma etching is performed to form sub-P-type semiconductor layer islands of different types of devices (for an E-mode HEMT with a duty cycle of 100%, a continuous gate structure is formed).

[0099] In step S4, the distances between the etching regions in the same formation region are set to be equal, so as to form a plurality of sub-P-type semiconductor layer islands equidistantly distributed along the second direction.

[0100] It should be noted that for an E-mode HEMT with a duty cycle of 100%, a continuous gate structure is formed, and steps S3 to S5 are not required for this structure.

[0101] It should be further explained that for a D-mode HEMT with a 0% ratio, the structure does not require a P-type semiconductor layer 4. In this case, the HEMT is formed by sequentially stacking an N-type channel layer 2, a barrier layer 3, and a passivation layer on a substrate.

[0102] Furthermore, during the preparation of step S5, an etching gas is introduced into the reaction chamber.

[0103] Those skilled in the art may select different etching gases based on actual conditions. Preferably, the etching gas comprises boron trichloride and chlorine; the gas flow ratio of the boron trichloride to the chlorine is in the range of 1:1 to 3:1. Specifically, a boron trichloride to chlorine gas flow ratio in the range of 1:1 to 3:1 is advantageous in that it provides good etching selectivity and controllability. Within this flow ratio range, boron trichloride provides effective etching power, while chlorine helps increase the etching rate and reduce damage to other materials during the etching process.

[0104] Furthermore, during the preparation step S5, radio frequency power is applied to the reaction chamber to ionize the etching gas to form a plasma, which is used to perform plasma etching on the etched area. Those skilled in the art can select different radio frequency power ranges according to actual conditions. Preferably, the radio frequency power range is 10-15 W.

[0105] Under the plasma power condition in the above preferred range, the etching selectivity of the P-type semiconductor layer 4 exceeds 20. This means that during the etching process of p-GaN, the p-GaN is removed with minimal etching damage to the GaN device.

[0106] Please refer to Figure 7 Furthermore, after completing step S5 and preparing the P-type semiconductor layer 4 , a passivation dielectric layer 5 is deposited on the surface of the P-type semiconductor layer 4 and the surface of the barrier layer 3 by using an evaporation method.

[0107] Please refer to Figure 8Furthermore, after the passivation dielectric layer 5 is deposited, the passivation dielectric layer 5 located above the sub-P-type semiconductor layer island is etched away, so that the subsequently provided Schottky metal layer 6 can directly contact the P-type semiconductor, forming a stable Schottky contact and MIS gate electrode.

[0108] Please refer to Figure 9 Furthermore, after completing the above preparation steps, a Schottky metal layer 6 is deposited on the P-type semiconductor layer 4 by electron beam evaporation, and then the Schottky metal layer 6 is annealed.

[0109] Specifically, the Schottky metal layer 6 needs to be deposited over the entire gate to simultaneously form a metal / semiconductor Schottky contact and a MIS gate.

[0110] In a specific embodiment, nitrogen is used as the inert gas during the annealing process. Of course, those skilled in the art can also select different inert gases for annealing according to actual conditions, and no specific limitation is made here.

[0111] In another specific embodiment, annealing is performed using a uniform temperature ramp annealing method. Specifically, the temperature of the inert gas atmosphere is uniformly increased over a predetermined period of time. For example, the nitrogen temperature is uniformly increased from 350°C to 400°C over 5 minutes. It will be appreciated that those skilled in the art may set different annealing times, annealing temperatures, and inert gas atmosphere heating rates based on actual conditions, and no specific limitations are imposed herein.

[0112] The uniform temperature rise annealing method improves the stability of the physical, chemical and electrical properties of the Schottky metal layer 6, making it very suitable for subsequent preparation processes.

[0113] Please refer to Figure 10-11 Furthermore, after the annealing operation is completed, the growth areas of the source 8 and the drain 7 are marked on the passivation dielectric layer, and the growth areas are plasma etched to form empty areas, and metal layers are sequentially deposited in the empty areas.

[0114] In a specific embodiment, chlorine-based ICP-RIE (inductively coupled plasma-reactive ion etching) is used on the passivation dielectric layer 5 and is etched down into the N-type channel layer 2 to form a rectangular trench, and the Schottky metal layer 6 is sequentially deposited in the rectangular trench.

[0115] In another specific embodiment, metals such as TiN (titanium nitride), Al (aluminum), Ti (titanium), and TiN (titanium nitride) are sequentially deposited and annealed in a nitrogen environment to form a source electrode 8 and a drain electrode 7 with ohmic contact. Of course, those skilled in the art can also select different metals to form the metal layer according to actual conditions, thereby forming different contact types.

[0116] Example 3

[0117] Based on the same inventive concept, this embodiment discloses a testing method for an HG-HEMT with an adjustable Vth function, which is intended to evaluate the performance of the HEMT disclosed in Examples 1 and 2. The specific method is as follows:

[0118] S1. Perform probe operation on HEMT device;

[0119] S2. Collecting the electrical signal of the HEMT;

[0120] S3 analyzes and processes the electrical signal to obtain electrical test curves of different high electron mobility transistors;

[0121] S4. Determine whether the high electron mobility transistor can achieve gate controllability between a normally-off state and a normally-on state based on the electrical test curve.

[0122] It can be understood that probing involves physically contacting a probe with a specific test point (such as the source, drain, or gate) on a HEMT device using a microscope or probe station, thereby forming a test circuit. Collecting electrical signals, on the other hand, involves measuring and recording changes in electrical signals (such as voltage and current) after probing to obtain the device's electrical characteristics.

[0123] In a specific embodiment of step S1, a microscope is used to perform a probe operation on the HEMT device.

[0124] In a specific embodiment of step S2, a high-power probe station is used to perform electrical testing.

[0125] In a specific embodiment of step S3, a power device analyzer is used to analyze and process the electrical signal of the HEMT device.

[0126] In a specific embodiment of step S4, by evaluating the performance of the device under different temperatures, different gate voltages, and different drain voltage stress conditions, it is determined whether the HEMT can effectively reduce gate leakage and maintain a stable Vth, thereby achieving the gate controllable function of the HEMT between the normally-off state and the normally-on state.

[0127] In one specific embodiment, the gate structure of the tested GaN device includes, from top to bottom, a Schottky metal layer 6, a P-type semiconductor layer 4 (composed of p-GaN), a barrier layer 3 (composed of AlGaN), and an N-type channel layer 2 (composed of GaN). These four layers together form a double junction structure, including a metal / semiconductor Schottky junction and a p-GaN / AlGaN / GaN heterojunction. Furthermore, the P-type semiconductor layer 4 includes a first sub-P-type semiconductor layer, a second sub-P-type semiconductor layer, and a third sub-P-type semiconductor layer, arranged sequentially along the second direction. The occupancy ratios of the first sub-P-type semiconductor layer, the second sub-P-type semiconductor layer, and the third sub-P-type semiconductor layer are 100%, 75%, and 50%, respectively. Under the stress conditions of applying the drain bias voltage and the gate drive voltage, the P-type semiconductor layer 4 with different occupancy ratios can enhance the electric field in the depletion region, further intensifying the depletion degree of carriers, thereby modulating the Vth of the gallium nitride-based device, realizing the gate adjustable capability of the device between the normally-off state and the normally-on state, while effectively reducing the gate leakage and providing a stable Vth under the gate / drain voltage stress conditions.

[0128] In one embodiment, see Figure 12 Under the condition of a drain current ID = 1μA / mm, the Vth values of the three devices (curve A for the first P-type semiconductor layer, curve B for the second P-type semiconductor layer, and curve C for the third P-type semiconductor layer) were +1.5V, -13.6V, and -52.9V, respectively. These test results demonstrate that by adjusting the coverage of the P-type GaN (p-GaN) layer in the gate structure (from 100% to 50%), the device Vth can be adjusted from positive to negative values, thus achieving the Vth tunability characteristic of GaN HEMT devices.

[0129] In another embodiment, see Figure 13 , a gate voltage V is applied to the first sub-P-type semiconductor layer with an occupancy ratio of 100%. GS = +6V, and apply gate voltage V to the second and third sub-P-type semiconductor layers with duty ratios of 75% and 50% respectively. GS = 0V, under the above test conditions, the on-resistance (Ron) of the three devices (the first sub-P-type semiconductor layer is curve A, the second sub-P-type semiconductor layer is curve B, and the third sub-P-type semiconductor layer is curve C) are 10.9Ωmm, 18.0Ωmm, and 15.1Ωmm, respectively. The test results show that the HEMT device in the embodiment of the present invention has excellent conduction performance and low on-resistance. For further information, see Figure 14-16The breakdown voltages (BV) of the three devices (curve A for the first sub-P-type semiconductor layer, curve B for the second sub-P-type semiconductor layer, and curve C for the third sub-P-type semiconductor layer) were 920V, 915V, and 913V, respectively. These results demonstrate that the GaN-based devices of the present invention have a high withstand voltage rating and good voltage blocking reliability, thus possessing excellent performance in high-voltage applications.

[0130] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A hybrid gate high electron mobility transistor, characterized in that include: substrate; An N-type channel layer, a barrier layer, and a P-type semiconductor layer are sequentially stacked along a first direction, wherein the first direction is a direction from the substrate to the P-type semiconductor layer; The P-type semiconductor layer includes a plurality of sub-P-type semiconductor layers sequentially arranged along a second direction, wherein the plurality of sub-P-type semiconductor layers have different occupancy ratios; the second direction is a direction perpendicular to the source and pointing to the drain; When the occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%, the sub-P-type semiconductor layer includes a plurality of sub-P-type semiconductor layer islands equidistantly arranged along the second direction; when the occupancy ratio of the sub-P-type semiconductor layer is 100%, the sub-P-type semiconductor layer includes one sub-P-type semiconductor layer island; Passivation dielectric layer and Schottky metal layer; The passivation dielectric layer is provided on the surface of the barrier layer in an area not covered by the P-type semiconductor layer; The Schottky metal layer is provided on the surface of the P-type semiconductor layer to simultaneously form a metal / semiconductor Schottky contact and a MIS gate; The occupancy ratio is: P p-GaN =W p-GaN / W total ; Among them, P p-GaN is the occupancy ratio, W total is the width of a sub-P-type semiconductor layer, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layer islands in a corresponding sub-P-type semiconductor layer.

2. The gate-coupled high electron mobility transistor according to claim 1, wherein: The P-type semiconductor layer includes a sub-P-type semiconductor layer with an occupancy ratio of 0%, a sub-P-type semiconductor layer with an occupancy ratio of 75%, a sub-P-type semiconductor layer with an occupancy ratio of 50% and / or a sub-P-type semiconductor layer with an occupancy ratio of 100%.

3. A method for preparing a hybrid gate high electron mobility transistor, comprising preparing the hybrid gate high electron mobility transistor according to any one of claims 1 and 2, wherein: The method comprises: providing a substrate; An N-type channel layer, a barrier layer, and a P-type semiconductor layer are sequentially stacked on the substrate; marking formation areas of each sub-P-type semiconductor layer on the P-type semiconductor layer; marking an etching region of the sub-P-type semiconductor layer on the formation region; Plasma etching is performed on the etched area to form a plurality of sub-P-type semiconductor layers arranged in sequence along a second direction and having different occupancy ratios on the surface of the barrier layer; wherein the second direction is a direction from the source to the drain, and the occupancy ratio of the sub-P-type semiconductor layer is greater than 0% and less than 100%; The occupancy ratio is: P p-GaN =W p-GaN / W total ; Among them, P p-GaN is the occupancy ratio, W total is the width of a sub-P-type semiconductor layer, W p-GaN It is the sum of the widths of all sub-P-type semiconductor layer islands in a corresponding sub-P-type semiconductor layer.

4. The method for preparing a hybrid gate high electron mobility transistor according to claim 3, wherein: Plasma etching the etched area includes: Introducing an etching gas into the reaction chamber; wherein the etching gas comprises boron trichloride and chlorine; and the gas flow ratio of the boron trichloride to the chlorine is in the range of 1:1-3:1; Applying radio frequency power into the reaction chamber, the radio frequency power is used to ionize the etching gas to form plasma, and the plasma is used to perform plasma etching on the etching area; wherein the radio frequency power ranges from 10W to 15W.

5. The method for preparing a hybrid gate high electron mobility transistor according to claim 4, wherein: The method further comprises: Depositing a passivation dielectric layer on the surface of the P-type semiconductor layer and the barrier layer by an evaporation method; The passivation dielectric layer on the surface of the P-type semiconductor layer is etched.

6. The method for preparing a hybrid gate high electron mobility transistor according to claim 5, wherein: The method further comprises: Depositing a Schottky metal layer on the P-type semiconductor layer by an electron beam evaporation deposition method, and performing a uniform temperature-raising annealing process on the Schottky metal layer; The growth areas of the source and drain are marked on the passivation dielectric layer, the growth areas are plasma etched to form empty areas, and a metal layer is deposited in the empty areas to form the source and drain.

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