A Shallow Trench Insulated Terminal Structure and Preparation Method for a Silicon Carbide VDMOS Device

Abstract

The present invention provides a shallow trench isolation terminal structure and a preparation method for a silicon carbide VDMOS device. The method includes: epitaxially growing on a silicon carbide substrate to form a drift layer; forming a blocking layer, etching, ion implanting to form a first left P+ doped region and a second left P+ doped region; reforming the blocking layer, etching, ion implanting to form a P+ well region and a cutoff ring contact region; reforming the blocking layer, etching, depositing, and forming a second right P+ doped region and a first right P+ doped region through thermal diffusion; reforming the blocking layer, etching, depositing to form a second insulating dielectric region and a first insulating dielectric region; reforming the blocking layer, etching, depositing metal to form a source metal layer and a cutoff ring metal layer; reforming the blocking layer, etching the blocking layer to form a via hole, depositing, forming an insulating layer, and removing the blocking layer, saving the width of the terminal structure while ensuring the terminal breakdown voltage capability.

Description

Technical Field

[0001] The present invention relates to a shallow trench insulation terminal structure and a preparation method of a silicon carbide VDMOS device. Background Art

[0002] Silicon carbide VDMOS is a typical representative of silicon carbide power devices and has wide applications in fields such as electric vehicles, aerospace, and power conversion. Based on the device structure design, due to the lateral distribution of the electric field at the edge of the repeating cell, electric field concentration occurs in the transverse direction, resulting in breakdown at the device edge. The traditional cell uses a field limiting ring structure with the same doping concentration to suppress electric field concentration. Since the doping concentration and spacing distribution of the field limiting ring are equal, the electric field intensity distribution gradually decreases, and there are still high and low differences in the electric field distribution. The risk of breakdown is still relatively high in the area near the P+ well region, and a relatively large number of field limiting rings are required to achieve the breakdown voltage of the device terminal, and it is necessary to sacrifice area to obtain the breakdown voltage. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a shallow trench insulation terminal structure and a preparation method of a silicon carbide VDMOS device. By adopting the shallow trench insulation terminal, the problem of great process difficulty in realizing the deep trench terminal is avoided, and at the same time, the breakdown voltage within 1200V of the terminal is achieved, and the breakdown voltage ability of the average unit width terminal is improved, that is, while ensuring the breakdown voltage ability of the terminal, the width of the terminal structure is saved.

[0004] In the first aspect, the present invention provides a preparation method of a shallow trench insulation terminal structure of a silicon carbide VDMOS device, including the following steps:

[0005] Step 1: Epitaxially grow on a silicon carbide substrate to form a drift layer;

[0006] Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a first left P+ doping region;

[0007] Step 3: Remove the blocking layer, re-form a blocking layer above the N-type drift layer, etch the blocking layer to form a through hole, and perform ion implantation to form a second left P+ doping region;

[0008] Step 4: Remove the blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, and perform ion implantation to form a P+ well region and a cut-off ring contact region;

[0009] Step 5: Remove the blocking layer, re-form a blocking layer, etch the blocking layer to form a through hole, deposit, and form a second right P+ doping region through thermal diffusion. The second P+ doping region includes the second left P+ doping region and the second right P+ doping region;

[0010] Step 6: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit, and form a first right P+ doped region by thermal diffusion. The first P+ doped region includes a first left P+ doped region and a first right P+ doped region;

[0011] Step 7: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the second P+ doped region to form a second trench, deposit, and form a second insulating dielectric region;

[0012] Step 8: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, etch the first P+ doped region to form a first trench, deposit, and form a first insulating dielectric region;

[0013] Step 9: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit metal, and form a source electrode metal layer and a cutoff ring metal layer;

[0014] Step 10: Remove the blocking layer, reform the blocking layer, etch the blocking layer to form a through hole, deposit, form an insulating layer, and remove the blocking layer.

[0015] In a second aspect, the present invention provides a shallow trench isolation terminal structure for a silicon carbide VDMOS device, and the silicon carbide VDMOS is prepared by using the preparation method of the shallow trench isolation terminal structure for a silicon carbide VDMOS device described in the first aspect.

[0016] The advantages of the present invention are as follows:

[0017] First, in the terminal structure beside the P+ well region of the device, the present invention provides a first insulating dielectric region wrapped by a first P+ doped region to effectively truncate the electric field at the edge of the P+ well region, and suppress the electric field strength in the terminal region;

[0018] Second, the present invention provides a second insulating dielectric region wrapped by a second P+ doped region to achieve secondary truncation and gradual change suppression of the strong electric field, and this double-layer structure can meet the device requirements within 1200V. Description of the Drawings

[0019] The following further describes the present invention with reference to the drawings in conjunction with embodiments.

[0020] Figure 1 It is a schematic diagram of a shallow trench isolation terminal structure for a silicon carbide VDMOS device of the present invention.

[0021] Figure 2 It is a process cross-section of a shallow trench isolation terminal structure for a silicon carbide VDMOS device of the present invention Figure 1 。

[0022] Figure 3 It is a process cross-section of a shallow trench isolation terminal structure for a silicon carbide VDMOS device of the present inventionFigure 2 。

[0023] Figure 4 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 3 。

[0024] Figure 5 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 4 。

[0025] Figure 6 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 5 。

[0026] Figure 7 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 6 。

[0027] Figure 8 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 7 。

[0028] Figure 9 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 8 。

[0029] Figure 10 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 9 。

[0030] Figure 11 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 10 。

[0031] Figure 12 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 10 I.

[0032] Figure 13 Process cross-section of a shallow trench insulation terminal structure of a silicon carbide VDMOS device according to the present invention Figure 10 II. Detailed implementation manners

[0033] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used herein in the specification of this application are for the purpose of describing particular embodiments only and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.

[0036] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation depicted in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may also assume other orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0037] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0038] As Figures 1 to 13 shown, the embodiment of the present application provides a method for preparing a shallow trench isolation terminal structure of a silicon carbide VDMOS device, including the following steps:

[0039] Step 1: Epitaxially grow on a silicon carbide substrate 1 to form a drift layer 2;

[0040] Step 2: Form a barrier layer 7 above the drift layer 2, etch the barrier layer 7 to form a through hole, and perform ion implantation to form a first left P+ doping region 231;

[0041] Step 3: Remove the barrier layer 7, reform the barrier layer 7 above the N-type drift layer 2, etch the barrier layer 7 to form a through hole, and perform ion implantation to form a second left P+ doping region 2521;

[0042] Step 4: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a through hole, and perform ion implantation to form a P+ well region 21 and a cutoff ring contact region 24;

[0043] Step 5: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a through hole, deposit a high P-type doped silicon carbide material, and form a second right P+ doping region 2522 by thermal diffusion. The second P+ doping region 252 includes the second left P+ doping region 2521 and the second right P+ doping region 2522; Since thermal diffusion requires a concentration gradient, it will not affect the doping concentration of the second left P+ doping region 2521 formed in the previous process steps;

[0044] Step 6: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a through hole, deposit a high P-type doped silicon carbide material, and form a first right P+ doping region 232 by thermal diffusion. The first P+ doping region 23 includes the first left P+ doping region 231 and the first right P+ doping region 232;

[0045] Step 7: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a through hole, etch the second P+ doping region 252 to form a second trench 2523, and deposit to form a second insulating dielectric region 251;

[0046] Step 8: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a through hole, etch the first P+ doping region 23 to form a first trench 233, and deposit to form a first insulating dielectric region 22;

[0047] Step 9: Remove the barrier layer 7, reform the barrier layer 7, etch the barrier layer 7 to form a through hole, deposit metal to form a source metal layer 5 and a cutoff ring metal layer 4;

[0048] Step 10: Remove the blocking layer 7, reform the blocking layer 7, etch the blocking layer 7 to form a through hole, deposit, form the insulating layer 3, and remove the blocking layer 7.

[0049] In this embodiment, preferably, at least one field limiting ring 25 is provided in the drift layer 2. Each field limiting ring 25 includes a second insulating dielectric region 251 and a second P+ doped region 252. The second insulating dielectric region 251 is provided in the second P+ doped region 252, and the second P+ doped region 252 is located between the first P+ doped region 23 and the cutoff ring contact region 24. The lower side of the insulating layer 3 is connected to the upper side of the second insulating dielectric region 251 and the upper side of the second P+ doped region 252.

[0050] In this embodiment, preferably, the depth of the first insulating dielectric region 22 is less than the depth of the second insulating dielectric region 251; the depth of the first P+ doped region 23 is less than the depth of the second P+ doped region 252.

[0051] In this embodiment, preferably, the width of the second P+ doped region 252 on the left side of the second insulating dielectric region 251 is less than the width of the second P+ doped region 252 on the right side of the second insulating dielectric region 251.

[0052] In this embodiment, preferably, the width of the first P+ doped region 23 on the left side of the first insulating dielectric region 22 is less than the width of the first P+ doped region 23 on the right side of the first insulating dielectric region 22.

[0053] As Figure 1 shown, the terminal structure obtained by the above manufacturing method includes:

[0054] Silicon carbide substrate 1,

[0055] Drift layer 2, the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a P+ well region 21, a first insulating dielectric region 22, a first P+ doped region 23, and a cutoff ring contact region 24 are provided on the drift layer 2; one side of the P+ well region 21 is connected to one side of the first insulating dielectric region 22, the lower side of the P+ well region 21 is connected to the first P+ doped region 23, the first insulating dielectric region 22 is provided in the first P+ doped region 23, and the cutoff ring contact region 24 is located on one side of the first P+ doped region 23;

[0056] Insulating layer 3, the lower side of the insulating layer 3 is connected to the upper side of the first insulating dielectric region 22, the upper side of the first P+ doped region 23, and the upper side of the drift layer 2;

[0057] Cutoff ring metal layer 4, the lower side of the cutoff ring metal layer 4 is connected to the upper side of the cutoff ring contact region 24;

[0058] The source metal layer 5, the lower side of the source metal layer 5 is connected to the P+ well region 21;

[0059] The drain metal layer 6, the drain metal layer 6 is connected to the lower side of the silicon carbide substrate 1.

[0060] In another embodiment of the present invention, the terminal structure is applied to the terminal of a planar gate silicon carbide VDMOS device. Taking the terminal structure on one side of the device as an example for illustration, the terminal structure on the other side is in a mirror image relationship with the structure of this embodiment. Among them, the doping concentration of the N-type silicon carbide substrate 1 is 2 - 8e18 cm -3 , the doping concentration of the N-type drift layer 2 is 5 - 9e16 cm -3 , the doping concentrations of the first P+ doped region 23 and the second P+ doped region 252 are both 1 - 5e18 cm -3 , the doping concentration of the P+ well region 21 is 5 - 8e18 cm -3 , the doping concentration of the cutoff ring contact region 24 is 5 - 8e18 cm -3 , the material of the insulating layer 3 can be silicon dioxide, and the materials of the first insulating dielectric region 22 and the second insulating dielectric region 251 can be one of SiN and diamond;

[0061] The doping concentrations of the N-type silicon carbide substrate 1, the N-type drift layer 2, and the P+ well region 21 are considered in the traditional design structure of the planar gate silicon carbide VDMOS device. The doping concentrations of the first P+ doped region 23 and the second P+ doped region 252 are to realize the lateral sharing of the main electric field in the first insulating dielectric region 22 and the second insulating dielectric region 251 and then diffuse the electric field distribution of the P+ well region 21 downward, reduce the electric field strength, and improve the device reliability;

[0062] In the terminal structure, the width d1 of the first P+ doped region 23 on the right side of the first insulating dielectric region 22 is 1 μm, and the width w of the first insulating dielectric region 22 is 1 μm; the width w1 of the first P+ doped region 23 on the left side of the first insulating dielectric region 22 is 300 nm, and the maximum depth of the first P+ doped region 23 is 1.3 μm; in the terminal structure, the width d2 of the second P+ doped region 252 on the right side of the second insulating dielectric region 251 is 1.5 μm, the width w of the second insulating dielectric region 251 is 1 μm, the width w2 of the second P+ doped region 252 on the left side of the second insulating dielectric region 251 is 200 nm, the maximum depth of the second P+ doped region 252 is 1.7 μm, and the minimum distance between the first insulating dielectric region 22 and the second insulating dielectric region 251 is 2 μm; the thicknesses of the insulating layer 3, the source metal layer 5, and the cutoff ring metal layer 4 are all 300 nm. The thickness of the insulating layer 3 is to ensure that after the electric field is staged, the influence on the device top interconnect structure during device breakdown voltage is avoided;

[0063] By arranging a first insulating dielectric region 22 wrapped by a first P+ doping region 23 in the terminal structure beside the P+ well region 21 of the device, the electric field at the edge of the P+ well region 21 is effectively truncated; the suppression of the electric field intensity in the terminal region is realized; a second insulating dielectric region 251 wrapped by a second P+ doping region 252 is arranged to realize the secondary truncation and gradual change suppression of the strong electric field, and this double-layer structure can meet the device requirements within 1200V.

[0064] The device terminal structure has scalability. When the breakdown voltage of the device is higher, more structure designs can be carried out according to the electric field distribution, but the terminal structure parameters need to be optimized according to the electric field distribution.

[0065] Although the specific embodiments of the present invention have been described above, those skilled in the art of this technology should understand that the specific embodiments we described are illustrative only and not used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered by the scope protected by the claims of the present invention.

Claims

1. A preparation method for a shallow trench isolation terminal structure of a silicon carbide VDMOS device, characterized in that: It includes the following steps: Step 1: Epitaxially grow on a silicon carbide substrate to form a drift layer; Step 2: Form a blocking layer above the drift layer, etch the blocking layer to form a through hole, perform ion implantation to form a first left P+ doped region; Step 3: Remove the blocking layer in Step 2, reform a blocking layer above the N-type drift layer, etch the blocking layer to form a through hole, perform ion implantation to form a second left P+ doped region; Step 4: Remove the blocking layer in Step 3, reform a blocking layer, etch the blocking layer to form a through hole, perform ion implantation to form a P+ well region and a cutoff ring contact region; Step 5: Remove the blocking layer in Step 4, reform a blocking layer, etch the blocking layer to form a through hole, deposit, and form a second right P+ doped region through thermal diffusion. The second P+ doped region includes the second left P+ doped region and the second right P+ doped region; Step 6: Remove the blocking layer in Step 5, reform a blocking layer, etch the blocking layer to form a through hole, deposit, and form a first right P+ doped region through thermal diffusion. The first P+ doped region includes the first left P+ doped region and the first right P+ doped region; Step 7: Remove the blocking layer in Step 6, reform a blocking layer, etch the blocking layer to form a through hole, etch the second P+ doped region to form a second trench, deposit, and form a second insulating dielectric region; Step 8: Remove the blocking layer in Step 7, reform a blocking layer, etch the blocking layer to form a through hole, etch the first P+ doped region to form a first trench, deposit, and form a first insulating dielectric region; Step 9: Remove the blocking layer in Step 8, reform a blocking layer, etch the blocking layer to form a through hole, deposit metal, and form a source metal layer and a cutoff ring metal layer; Step 10: Remove the blocking layer in Step 9, reform a blocking layer, etch the blocking layer to form a through hole, deposit, form an insulating layer, and remove the blocking layer; The lower side of the drift layer is connected to the upper side of the silicon carbide substrate; the drift layer is provided with a P+ well region, a first insulating dielectric region, a first P+ doped region, and a cutoff ring contact region; One side of the P+ well region is connected to one side of the first insulating dielectric region, the lower side of the P+ well region is connected to the first P+ doped region, the first insulating dielectric region is disposed in the first P+ doped region, and the cutoff ring contact region is located on one side of the first P+ doped region; The lower side of the insulating layer is connected to the upper side of the first insulating dielectric region, the upper side of the first P+ doped region, and the upper side of the drift layer; The lower side of the cutoff ring metal layer is connected to the upper side of the cutoff ring contact region; The lower side of the source metal layer is connected to the P+ well region; The second insulating dielectric region is disposed in the second P+ doped region, and the second P+ doped region is located between the first P+ doped region and the cutoff ring contact region; the lower side of the insulating layer is connected to the upper side of the second insulating dielectric region and the upper side of the second P+ doped region.

2. The manufacturing method of a shallow trench isolation terminal structure of a silicon carbide VDMOS device as described in claim 1, characterized in that: The depth of the first insulating dielectric region is less than the depth of the second insulating dielectric region; the depth of the first P+ doped region is less than the depth of the second P+ doped region.

3. The manufacturing method of a shallow trench isolation terminal structure of a silicon carbide VDMOS device as described in claim 1, characterized in that: The width of the second P+ doped region on the left side of the second insulating dielectric region is less than the width of the second P+ doped region on the right side of the second insulating dielectric region.

4. The preparation method of a shallow trench isolation terminal structure of a silicon carbide VDMOS device according to claim 1, characterized in that: The width of the first P+ doped region on the left side of the first insulating dielectric region is smaller than the width of the first P+ doped region on the right side of the first insulating dielectric region.

5. A shallow trench isolation terminal structure for a silicon carbide VDMOS device, characterized in that, The terminal structure is obtained by the preparation method described in any one of claims 1 to 4.

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