Gallium oxide solar-blind ultraviolet detector, preparation method thereof and imaging array

Abstract

The invention provides a gallium oxide solar-blind ultraviolet detector, a preparation method thereof and an imaging array, and belongs to the technical field of semiconductor devices. The gallium oxide solar-blind ultraviolet detector comprises a substrate, a gate electrode, a first dielectric layer, an n-Ga2O3 layer, a second dielectric layer, a third dielectric layer and a first semiconductor layer from bottom to top, and further comprises a source electrode, a drain electrode, an anode, a cathode and a second semiconductor layer. The gate electrode is covered by the first dielectric layer. The source electrode and the drain electrode are located on the side, away from the first dielectric layer, of the n-Ga2O3 layer. The anode is located on the surface, away from the n-Ga2O3 layer, of the source electrode. The cathode and the n-Ga2O3 layer are located at the two ends of the surface of the side, away from the substrate, of the first dielectric layer respectively. The cathode is in direct contact with the first semiconductor layer. The anode is in direct contact with the second semiconductor layer. The first semiconductor layer and the second semiconductor layer form a pn junction. The gallium oxide solar blind ultraviolet detector has the characteristics of high withstand voltage, small dark current and high detection efficiency.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices, and in particular relates to a gallium oxide solar-blind ultraviolet detector and a preparation method thereof, and an imaging array composed of the gallium oxide solar-blind ultraviolet detector. Background Art

[0002] As an indispensable part of spectral detection, photodetectors play an important role in many scenarios such as biosensing, fire warning and deep space exploration. When used in unique scenarios, photodetectors will inevitably face extremely harsh environments (such as high temperature, high electric field and high radiation). However, traditional silicon-based photodetectors have high sensitivity to some light sources (such as ultraviolet light) and poor thermal stability, which makes it difficult to meet the needs of high sensitivity in harsh environments. Gallium oxide, as an emerging ultra-wide bandgap semiconductor material, has the advantages of good thermal stability, large bandgap width, large ultraviolet absorption coefficient, and easy material processing. Its corresponding light wavelength is 254~270nm, which corresponds to the day-blind ultraviolet band of 200~280nm. Therefore, gallium oxide material is an ideal candidate material for day-blind ultraviolet photodetectors. At the same time, since gallium oxide is an ultra-wide bandgap semiconductor material, its intrinsic carrier concentration is very low. Therefore, in the day-blind ultraviolet photodetector devices with the same structural design, the leakage current of gallium oxide day-blind ultraviolet photodetectors is smaller (that is, dark current is smaller), which further indicates that the noise of its detector is better.

[0003] In the prior art, when gallium oxide materials are used to design and prepare day-blind ultraviolet photodetectors, the most basic Schottky structure or metal-semiconductor-metal (MSM) structure is mainly used. Among them, the disadvantage of Schottky-type day-blind ultraviolet photodetectors is that the depletion region of the Schottky structure is thinner and the reverse barrier is lower, which leads to a larger leakage current (i.e., dark current) and a lower reverse bias voltage, making it more suitable for low-voltage occasions. Once the reverse bias voltage is higher, it cannot meet the use requirements. In addition, too many interface defects of the Schottky junction seriously affect the response speed of the device. The MSM structure is composed of two back-to-back Schottky barrier structures, which is essentially based on the Schottky junction and also has the disadvantages of the Schottky-type day-blind ultraviolet photodetector. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a gallium oxide solar-blind ultraviolet detector and a preparation method thereof. The gallium oxide solar-blind ultraviolet detector integrates a thin film transistor as a solar-blind ultraviolet detection unit and a light-emitting diode as a display unit, and the obtained integrated device has the characteristics of high withstand voltage and fast response speed.

[0005] Specifically, in order to achieve the above purpose, the present invention adopts the following technical solutions: A gallium oxide solar-blind ultraviolet detector, comprising from bottom to top a substrate, a gate electrode, a first dielectric layer, an n-Ga2 O 3 layer, a second dielectric layer, a third dielectric layer, a first semiconductor layer, and also includes a source electrode, a drain electrode, an anode, a cathode, and a second semiconductor layer; the gate electrode is covered by the first dielectric layer; the source electrode and the drain electrode are both located on the n-Ga 2 O 3 The anode is located on the side of the source electrode away from the n-Ga 2 O 3 on the surface of the layer; the cathode and the n-Ga 2 O 3 The layers are respectively located at two ends of the surface of the first dielectric layer away from the substrate; the cathode is in direct contact with the first semiconductor layer; the anode is in direct contact with the second semiconductor layer; and the first semiconductor layer and the second semiconductor layer form a pn junction.

[0006] In a preferred embodiment, the substrate is a transparent substrate.

[0007] In a preferred solution, the first medium layer is a transparent structure.

[0008] In a preferred embodiment, the n-Ga 2 O 3 A p-type doped region is arranged in or on the surface of a side of the layer close to the second dielectric layer, an n+ doped region is arranged in or on the surface of the p-type doped region away from the first dielectric layer; the n+ doped region is in direct contact with the source electrode; and a base is arranged on the surface of the p-type doped region away from the first dielectric layer.

[0009] In a further preferred solution, the doping element of the p-type doping region is N.

[0010] In a further preferred embodiment, the doping element of the n+ doping region is Si.

[0011] In a preferred embodiment, the substrate is at least one of a gallium oxide substrate, a sapphire substrate, a silicon carbide substrate, and a silicon nitride substrate.

[0012] In a preferred embodiment, the material of the gate electrode is molybdenum.

[0013] In a preferred embodiment, the material of the first dielectric layer is SiN, SiO 2 、Al 2 O 3 At least one of .

[0014] In a preferred embodiment, the material of the second dielectric layer is SiN, SiO 2 、Al 2 O3 At least one of .

[0015] In a preferred embodiment, the material of the third dielectric layer is SiN, SiO 2 、Al 2 O 3 At least one of .

[0016] In a preferred embodiment, the material of the first semiconductor layer is SiC, GaN, GaAs, Ga 2 O 3 , AlN, GaP, and diamond.

[0017] In a preferred embodiment, the material of the second semiconductor layer is SiC, GaN, GaAs, Ga 2 O 3 , AlN, GaP, and diamond.

[0018] The preparation method of the gallium oxide solar-blind ultraviolet detector comprises the following steps: S1. Prepare a thin film transistor and a light emitting diode; wherein the method for preparing the thin film transistor comprises the following steps: S11-1, forming a gate electrode on a substrate; S11-2, depositing a first dielectric layer on the substrate so that the first dielectric layer covers the gate electrode; S11-3, depositing n-Ga on the surface of the first dielectric layer away from the substrate 2 O 3 layer, etching away part of the n-Ga 2 O 3 layer, retaining the n-Ga 2 O 3 layer; S11-4, depositing metal on the upper surface of the structure obtained in step S11-3, etching the metal layer to obtain a source electrode, a drain electrode and a first cathode respectively; annealing; S11-5, depositing a second dielectric layer on the upper surface of the structure obtained in step S11-4, and etching the second dielectric layer to expose the upper surface of the source electrode and the upper surface of the first cathode; The method for preparing the light emitting diode comprises the following steps: S12-1, manufacturing a semiconductor layer, wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer; the first semiconductor layer and the second semiconductor layer have opposite doping types; and depositing a third dielectric layer on a surface of the semiconductor layer that needs to be combined with the second dielectric layer; S12-2, etching the third dielectric layer to obtain a first through hole and a second through hole penetrating the third dielectric layer respectively; S12-3, depositing metal on the surface of the third dielectric layer away from the semiconductor layer, etching, retaining the metal layer located in the first through hole and the metal layer located in the second through hole, and obtaining the anode and the second cathode of the light-emitting diode respectively; S2. Combine the second dielectric layer with the third dielectric layer, make the anode directly contact the source electrode, and integrate the thin film transistor and the light-emitting diode; the first cathode directly contact the second cathode to form a whole as the cathode of the light-emitting diode.

[0019] In a preferred embodiment, in step S11-3, the n-Ga 2 O 3 A p-type doped region is formed in the surface layer on one side of the layer close to the second dielectric layer, and an n+ doped region is formed in the p-type doped region; a base is also obtained when etching the metal layer in step S11-4; and an ohmic contact is formed between the base and the p-type doped region.

[0020] Arranging the multiple gallium oxide solar-blind ultraviolet detectors provided by the present invention in an array can realize array imaging display.

[0021] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: (1) In the present invention, a gallium oxide thin film transistor is used as a high-voltage solar-blind ultraviolet detection unit to convert optical signals into electrical signals; a light-emitting diode is used as a display unit to convert electrical signals into optical signals; and by utilizing the large bandgap width of gallium oxide materials and the characteristics of being sensitive to ultraviolet light absorption and the ability of light-emitting diodes to increase the carrier recombination rate, a gallium oxide solar-blind ultraviolet detector with the characteristics of high voltage resistance, small dark current, high detection efficiency, and fast response speed is obtained.

[0022] (2) Furthermore, when there are one or more transparent structures in the device integrating the gallium oxide thin film transistor and the light emitting diode, light detection in multiple directions can be achieved.

[0023] (3) Furthermore, the integrated device also includes an APD. When the intensity of ultraviolet light irradiation is low and the resulting photogenerated carriers are small, the APD can increase the concentration of photogenerated carriers, thereby increasing the intensity of the current signal, thereby enabling the light-emitting diode to emit light even when the original photogenerated carrier concentration is very small. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1A schematic diagram of the structure of a gallium oxide solar-blind ultraviolet detector provided in Example 1 of the present invention; and also a schematic diagram of the structure of a gallium oxide solar-blind ultraviolet detector prepared in Example 2 of the present invention; Figure 2 A schematic structural diagram of another gallium oxide solar-blind ultraviolet detector provided in Example 1 of the present invention; Figure 3 A schematic structural diagram of another gallium oxide solar-blind ultraviolet detector provided in Example 1 of the present invention; Figure 4 A schematic structural diagram of another gallium oxide solar-blind ultraviolet detector provided in Example 1 of the present invention; Figures 5 to 12 A schematic diagram of a process for preparing a gallium oxide solar-blind ultraviolet detector provided in Example 2 of the present invention; Fig.13 A schematic diagram of the structure obtained in step S11-3 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Example 2 of the present invention; Fig.14 A schematic diagram of the structure obtained in step S11-4 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Example 2 of the present invention; Fig.15 A schematic diagram of the structure obtained in step S12-1 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Example 2 of the present invention; Fig.16 A schematic diagram of the structure obtained in step S12-1 of another method for preparing a gallium oxide solar-blind ultraviolet detector provided in Example 2 of the present invention; Fig.17 A schematic diagram of the distribution of gallium oxide solar-blind ultraviolet detectors in a gallium oxide solar-blind ultraviolet detector array provided by the present invention.

[0025] 1. Substrate; 2. Gate electrode; 3. First dielectric layer; 4. n-Ga 2 O 3 Layer; 5, source electrode; 6, drain electrode; 7, cathode; 701, first cathode; 702, second cathode; 8, second dielectric layer; 9, first semiconductor layer; 10, second semiconductor layer; 11, third dielectric layer; 12, first through hole; 13, second through hole; 14, anode; 15, p-type doped region; 16, n+ doped region; 17, base; 18, groove; 100, gallium oxide solar-blind ultraviolet detector. DETAILED DESCRIPTION

[0026] The following content is combined with the embodiments to clearly and completely describe the technical solution of the present application so that those skilled in the art can fully understand the present application. Obviously, the described embodiments are only some preferred embodiments of the present application, rather than all embodiments. Any equivalent transformation or substitution made to the following implementation modes by those of ordinary skill in the art without creative work belongs to the protection scope of the present application.

[0027] Directional terms described in this application, such as "upper", "lower", "inner", "outer", "bottom", "upper surface", etc., indicate directions or positional relationships based on directions or positional relationships in the drawings of the specification, or directions or positional relationships in which the products of this application are usually placed when in use, and are only for the convenience of describing and understanding the product structure of this application. Therefore, directional terms cannot be understood as limiting this application. In this application, unless otherwise clearly defined, expressions such as "upper", "above", "above", and "upper surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly above or obliquely above the second feature, or simply indicate that the first feature is higher in level than the second feature. Expressions such as "lower", "below", "below", and "lower surface" of a first feature on a second feature indicate that the first feature and the second feature may be in direct contact or indirect contact through an intermediate medium; the first feature may be directly below or obliquely below the second feature, or simply indicate that the first feature is lower in level than the second feature. Ordinal numbers used in this application, such as "first", "second", etc., are only used for descriptive purposes to distinguish similar objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. The methods not described in detail in the following embodiments are all conventional methods well known to those skilled in the art.

[0028] Example 1 Reference Figure 1 A gallium oxide solar-blind ultraviolet detector comprises a substrate 1, a gate electrode 2 and a first dielectric layer 3 located on the upper surface of the substrate 1, and an n-Ga 2 O 3 Layer 4, a second dielectric layer 8 located on the first dielectric layer 3, a third dielectric layer 11 located on the upper surface of the second dielectric layer 8, a first semiconductor layer 9 located on the upper surface of the third dielectric layer 11, as well as a source electrode 5, a drain electrode 6, a cathode 7, an anode 14 and a second semiconductor layer 10.

[0029] The gate electrode 2 is covered by the first dielectric layer 3. The direction from the substrate 1 to the first semiconductor layer 9 (or the direction from the first semiconductor layer to the substrate 1) is defined as the first direction, the direction perpendicular to the paper surface is defined as the second direction, and the direction perpendicular to both the first direction and the second direction is defined as the third direction. In the third direction, n-Ga 2 O 3 One end of the layer 4 is aligned with the side surface of the first dielectric layer 3, and the other end is located near the middle of the upper surface of the first dielectric layer 3 (that is, along the third direction, there is a part of the upper surface of the first dielectric layer 3 without n-Ga 2 O 3 Layer 4). The source electrode 5 and the drain electrode 6 are located on the n-Ga 2 O 3 The second dielectric layer 8 is wrapped around the n-Ga 2 O 3 Layer 4, source electrode 5 and drain electrode 6. n-Ga 2 O 3 The side of the layer 4 aligned with the first dielectric layer 3 is exposed. The cathode 7 is located on the upper surface of the first dielectric layer 3 and has no n-Ga 2 O 3 The anode 14 is located on the upper surface of the source electrode 5. The upper surface of the anode 14 is in direct contact with the lower surface of the second semiconductor layer 10. The second semiconductor layer 10 and the first semiconductor layer 9 have different doping types, and the two form a pn junction. Specifically, the doping type of the first semiconductor layer 9 is n-type, and the doping type of the second semiconductor layer 10 is p-type.

[0030] The above-mentioned gallium oxide solar-blind ultraviolet detector is integrated with a bottom-gate thin film transistor (TFT) and a light-emitting diode. The TFT is used as a detection unit and the light-emitting diode is used as a display unit. In the detection unit, the gate electrode 2 controls the n-Ga 2 O 3 Layer 4 (n-Ga 2 O 3 The anode 14 of the light-emitting diode is in direct contact with the source electrode 5 of the thin-film transistor, and the cathode 7 is located on one side of the entire integrated device. The working process of the entire integrated device is as follows: the drain electrode 6 of the thin-film transistor is connected to a high voltage, and when a negative voltage is applied to the gate electrode 2, the n-Ga 2 O 3 After the carriers in the channel of layer 4 are removed, the TFT is turned off and only a very small dark current passes. When there is external light, such as solar-blind ultraviolet light shining on the depletion region, the n-Ga 2 O 3The gallium oxide material of layer 4 can absorb the solar-blind ultraviolet light with high efficiency and generate photogenerated carriers. After a large number of electron-hole pairs are generated, under the action of the high voltage and strong electric field of the drain electrode 6, the electron holes quickly drift to both ends, forming a strong photocurrent (the current path is as follows Figure 1 , Figure 2 When the photocurrent passes through the light emitting diode, light of the corresponding color will be generated. A plurality of the above-mentioned gallium oxide solar-blind ultraviolet detectors 100 are packaged together and arranged in an array (such as Fig.17 As shown), array imaging display can be realized. When the materials of the light-emitting diodes in the structures of the gallium oxide day-blind ultraviolet detectors 100 located at different positions in the array are different, the colors of the light emitted by the gallium oxide day-blind ultraviolet detectors 100 at different positions are different, and different information can be displayed according to different combinations of light colors. For example, when the light-emitting diode is a gallium arsenide (GaAs) diode, red light is emitted; when the light-emitting diode is a gallium phosphide (GaP) diode, green light is emitted; when the light-emitting diode is a silicon carbide (SiC) diode, yellow light is emitted; when the light-emitting diode is a gallium nitride (GaN) diode, blue light is emitted; the gallium oxide day-blind ultraviolet detectors 100 integrated with these light-emitting diodes are distributed at different positions in the array as needed, and different information can be displayed.

[0031] Further, refer to Figure 4 In some specific gallium oxide solar-blind UV detector structures, n-Ga 2 O 3 A p-type doping region 15 is provided in the upper surface layer or on the upper surface of the layer 4, and an n+ doping region 16 is provided in the upper surface layer or on the upper surface of the p-type doping region 15. The source electrode 5 is located on the upper surface of the n+ doping region 16. The area of ​​the n+ doping region 16 is larger than that of the source electrode 5 on the n-Ga 2 O 3 The area of ​​the projection on the upper surface of layer 4. n-Ga 2 O 3 Layer 4 , p-type doped region 15 , and n+ doped region 16 form an avalanche photodiode (APD). A base 17 is disposed on the surface of the p-type doped region 15 away from the first dielectric layer 3 , and the base 17 is located on the side of the source electrode 5 away from the drain electrode 6 .

[0032] As an example, Figure 4 As shown, the upper surface of the p-type doped region 15 and the upper surface of the n+ doped region 16 are both connected to the n-Ga 2 O 3 The upper surface of the layer 4 is flush. The n+ doping region 16 is located below the source electrode 5 (the source electrode 5 is located on the upper surface of the n+ doping region 16 ) and is in direct contact with the source electrode 5 . The base 17 is arranged on the upper surface of the p-type doping region 15 .

[0033] As an example, the upper surface of the p-type doping region 15 and the upper surface of the n+ doping region 16 are both adjacent to the n-Ga 2 O 3 The upper surface of layer 4 is flush. The bottom of source electrode 5 extends into the interior of n+ doping region 16 and is surrounded by n+ doping region 16, and the top protrudes out of the upper surface of n+ doping region 16. The bottom of base 17 extends into the interior of p-type doping region 15 and is surrounded by p-type doping region 15, and the top protrudes out of the upper surface of p-type doping region 15.

[0034] As an example, the upper surface of the n+ doping region 16 protrudes beyond the upper surface of the p-type doping region 15, the source electrode 5 extends deep into the n+ doping region 16, its bottom is surrounded by the n+ doping region 16 (that is, the source electrode 5 does not contact the p-type doping region 15), and the top protrudes beyond the upper surface of the n+ doping region 16. Alternatively, the source electrode 5 is located on the upper surface of the n+ doping region 16.

[0035] As an example, the upper surface of the p-type doped region 15 protrudes above the n-Ga 2 O 3 The base 17 extends beyond the upper surface of the layer 4 into the p-type doping region 15, with its bottom surrounded by the p-type doping region 15 and its top protruding beyond the upper surface of the p-type doping region 15. Alternatively, the base 17 is located on the upper surface of the p-type doping region 15.

[0036] When the intensity of ultraviolet light received by the gallium oxide solar-blind ultraviolet detector is low, the concentration of photogenerated carriers is low, resulting in a small photogenerated current, which may cause the light-emitting diode to be unable to conduct and display, thereby failing to achieve the functions of ultraviolet detection and display. Therefore, APD is further integrated in the above-mentioned integrated device. When ultraviolet light irradiates the integrated device to form photogenerated carriers, APD can increase the concentration of photogenerated carriers. Therefore, even when the concentration of photogenerated carriers is very small, the light-emitting diode can emit light and display.

[0037] Furthermore, the substrate 1 is a transparent substrate. When there is no transparent structure in the structure of the gallium oxide solar-blind ultraviolet detector, the solar-blind ultraviolet light can be transmitted from the n-Ga 2 O 3 When the substrate 1 is a transparent substrate, the solar-blind ultraviolet light is incident on the side of the layer 4 exposed to the outside. 2 O 3 The incident light can be incident from the exposed side of layer 4, or from the surface of substrate 1 away from first dielectric layer 3. Similarly, when there are other transparent structures in the structure of gallium oxide solar-blind UV detector, solar-blind UV light can also be incident from the exposed surface of other transparent structures.

[0038] Furthermore, the first medium layer 3 is a transparent structure.

[0039] As an example, the substrate 1 is any one of a gallium oxide substrate, a sapphire substrate, a silicon carbide substrate, and a silicon nitride substrate, or a combination of several of them.

[0040] As an example, the material of the gate electrode 2 is metal molybdenum (Mo).

[0041] As an example, the material of the first dielectric layer 3 is SiN, SiO 2 、Al 2 O 3 Any one or a combination of the following.

[0042] As an example, n-Ga 2 O 3 The carrier concentration of layer 4 is 10 16 cm -3 Order of magnitude.

[0043] As an example, the source electrode 5 is composed of a titanium layer and a gold (Ti / Au) layer.

[0044] As an example, the drain electrode 6 is composed of a titanium layer and a gold (Ti / Au) layer.

[0045] As an example, the cathode 7 consists of a titanium layer and a gold (Ti / Au) layer.

[0046] As an example, the material of the second dielectric layer 8 is SiN, SiO 2 、Al 2 O 3 Any one or a combination of the following.

[0047] As an example, the material of the first semiconductor layer 9 is SiC, GaN, GaAs, Ga 2 O 3 , AlN, GaP, diamond, any one or a combination of them.

[0048] As an example, the material of the second semiconductor layer 10 is SiC, GaN, GaAs, Ga 2 O 3 , AlN, GaP, diamond, any one or a combination of them.

[0049] As an example, the upper surface of the second semiconductor layer 10 is flush with the upper surface of the third dielectric layer 11 (eg Figure 1 That is, the lower surface of the first semiconductor layer 9 is in direct contact with the upper surface of the second semiconductor layer 10 to form a pn junction, and the second semiconductor layer 10 is surrounded by the third dielectric layer 11. Or, the second semiconductor layer 10 is arranged inside the first semiconductor layer 9, and the lower surface of the second semiconductor layer 10 is flush with the lower surface of the first semiconductor layer 9 (as shown in FIG. Figure 2Or, the second semiconductor layer 10 is disposed inside the first semiconductor layer 9 and is surrounded by the first semiconductor layer 9, the anode 14 penetrates into the first semiconductor layer 9 and contacts the lower surface of the second semiconductor layer 10, and the portion of the anode 14 that penetrates into the first semiconductor layer 9 is surrounded by the third dielectric layer 11 (as shown in FIG. Figure 3 as shown).

[0050] As an example, the material of the third dielectric layer 11 is SiN, SiO 2 、Al 2 O 3 Any one or a combination of the following.

[0051] As an example, the anode 14 is composed of a titanium layer and a gold (Ti / Au) layer.

[0052] As an example, the doping element of the p-type doping region 15 is N.

[0053] As an example, the doping concentration of the p-type doping region 15 is 1×10 18 cm -3 .

[0054] As an example, the doping element of the n+ doping region 16 is Si.

[0055] As an example, the doping concentration of the n+ doping region 16 is 1×10 19 cm -3 ~1×10 20 cm -3 For example, the doping concentration of the n+ doping region 16 is 1×10 19 cm -3 , 1.1×10 19 cm -3 , 1.2×10 19 cm -3 , 1.5×10 19 cm -3 , 2×10 19 cm -3 , 2.5×10 19 cm -3 , 3×10 19 cm -3 , 3.5×10 19 cm -3 ……1×10 19 cm -3 .

[0056] Example 2 Reference Figure 1 , Figures 5 to 12 , a method for preparing a gallium oxide solar-blind ultraviolet detector, comprising the following steps: S1. Prepare a thin film transistor and a light emitting diode, wherein the method for preparing the thin film transistor comprises the following steps: S11-1, forming a gate electrode 2 (such as Figure 5 as shown).

[0057] S11-2, fabricate a first dielectric layer 3 (such as Figure 6 If the upper surface of the first dielectric layer 3 has a large curvature, a chemical mechanical polishing (CMP) process may be used to make the sample surface flat.

[0058] S11-3, depositing n-Ga on the upper surface of the first dielectric layer 3 2 O 3 (n-type gallium oxide) layer, etching away part of the n-Ga 2 O 3 layer, exposing the upper surface of the first dielectric layer 3 and retaining the n-Ga 2 O 3 Layer 4 (such as Figure 7 as shown).

[0059] S11-4, depositing metal on the upper surface of the structure obtained in step S11-3, etching the metal layer, and obtaining the source electrode 5 and the drain electrode 6 of the thin film transistor and the first cathode 701 of the light emitting diode (such as Figure 8 ) annealing, so that the source electrode 5 and the drain electrode 6 are respectively connected to the n-Ga 2 O 3 Layer 4 forms the ohmic contact.

[0060] S11-5, depositing a second dielectric layer 8 on the upper surface of the structure obtained in step S11-4, and etching the second dielectric layer 8 to expose the upper surface of the source electrode 5 and the upper surface of the first cathode 701 (eg, Fig. 9 as shown).

[0061] The preparation of light emitting diodes includes the following steps: S12-1, a semiconductor layer is produced, the semiconductor layer comprising a first semiconductor layer 9 and a second semiconductor layer 10; the first semiconductor layer 9 is doped with an n-type, and the second semiconductor layer 10 is doped with a p-type. A third dielectric layer 11 (such as Fig.10 as shown).

[0062] S12-2, etching the third dielectric layer 11 to obtain a first through hole 12 and a second through hole 13 penetrating the third dielectric layer (such as Fig.11 as shown).

[0063] S12-3, depositing metal on the upper surface of the structure obtained in step S12-2, etching, retaining the metal layer in the first through hole 12 and the metal layer in the second through hole 13 to obtain the anode 14 and the second cathode 702 of the light emitting diode (such as Fig.12 as shown).

[0064] S2, integrating the thin film transistor and the light emitting diode, combining the third dielectric layer of the light emitting diode with the second dielectric layer of the thin film transistor, making the anode 14 directly contact with the source electrode 5, and the second cathode 702 directly contact with the first cathode 701 to form a whole as the cathode 7 of the light emitting diode (such as Figure 1 as shown).

[0065] Furthermore, step S11-3 further includes the following steps: 2 O 3 A p-type doping region 15 is formed in the layer 4, and an n+ doping region 16 (such as Fig.13 When etching the metal layer in step S11-4, a base electrode 17 (as shown) is also obtained. Fig.14 The source electrode 5 is located above the n+ doped region 16. 2 O 3 The layer 4 forms an ohmic contact, the drain electrode 6 forms an ohmic contact with the n+ doped region 16 , and the base 17 forms an ohmic contact with the p-type doped region 15 .

[0066] Furthermore, after the anode 14 and the second cathode 702 are etched out in step S12 - 3 , annealing is performed.

[0067] As an example, the method of manufacturing the gate electrode on the substrate in step S11 - 1 is implemented by a lift-off process (ie, a Lift-Off process).

[0068] As an example, in step S11-3, n-Ga is deposited 2 O 3 The process of the layer is any one of molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), and gallium oxide ceramic sputtering.

[0069] As an example, in step S11 - 3 , the p-type doping region 15 is formed by nitrogen (N) ion implantation.

[0070] As an example, in step S11 - 3 , the n+ doped region 16 is formed by silicon (Si) ion implantation.

[0071] As an example, the method of depositing the metal in step S11 - 4 is electron beam evaporation (EBE).

[0072] As an example, the annealing condition in step S11 - 4 is: 470° C. for 1 minute in a nitrogen atmosphere.

[0073] As an example, the method for making the semiconductor layer in step S12-1 is: epitaxially grow a p-type second semiconductor layer 10 on the surface of the n-type first semiconductor layer 9, and the epitaxial growth method is homoepitaxial growth or heteroepitaxial growth. After the epitaxial growth is completed, the second semiconductor layer 10 is etched to remove the parts at both ends of the second semiconductor layer 10.

[0074] As an example, the method for making the semiconductor layer in step S12-1 is: forming a p-type second semiconductor layer 10 (such as Fig.15 as shown).

[0075] As an example, the method for making the semiconductor layer in step S12-1 is: etching the n-type first semiconductor layer 9 to obtain the groove 18, and then obtaining the p-type second semiconductor layer 10 (such as Fig.16 as shown).

[0076] As an example, the method of depositing metal in step S12 - 3 is electron beam evaporation.

[0077] As an example, the annealing condition in step S12-3 is: 470°C for 1 minute in a nitrogen atmosphere.

[0078] As an example, in step S2, the thin film transistor and the light emitting diode are integrated by bonding.

[0079] The above-described embodiments are only preferred embodiments of the present application and are not intended to limit the scope of protection of the present application. For any person skilled in the art, the present application may have various changes and modifications. Any simple equivalent changes and modifications made based on the scope of protection of the present application and the contents of the specification should be included in the scope of protection of the present application.

Claims

1. A gallium oxide solar-blind ultraviolet detector, characterized in that: From bottom to top, it includes a substrate, a gate electrode, a first dielectric layer, an n-Ga2O3 layer, a second dielectric layer, a third dielectric layer, a first semiconductor layer, and also includes a source electrode, a drain electrode, an anode, a cathode, and a second semiconductor layer; the gate electrode is covered by the first dielectric layer; the source electrode and the drain electrode are both located on the side of the n-Ga2O3 layer away from the first dielectric layer; the anode is located on the surface of the source electrode away from the n-Ga2O3 layer; the cathode and the n-Ga2O3 layer are respectively located at two ends of the surface of the first dielectric layer away from the substrate; the cathode is in direct contact with the first semiconductor layer; the anode is in direct contact with the second semiconductor layer; the first semiconductor layer and the second semiconductor layer form a pn junction.

2. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that: The substrate is a transparent substrate; or / and the first medium layer is a transparent structure.

3. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that: A p-type doped region is arranged in the surface layer or on the surface of the n-Ga2O3 layer on the side close to the second dielectric layer, and an n+ doped region is arranged in the surface layer or on the surface of the p-type doped region away from the first dielectric layer; the n+ doped region is in direct contact with the source electrode; and a base is arranged on the surface of the p-type doped region away from the first dielectric layer.

4. The gallium oxide solar-blind ultraviolet detector according to claim 3, characterized in that: The doping element of the p-type doping region is N; or / and the doping element of the n+ doping region is Si.

5. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that: The substrate is at least one of a gallium oxide substrate, a sapphire substrate, a silicon carbide substrate, and a silicon nitride substrate; or / and the material of the gate electrode is molybdenum.

6. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that: The material of the first dielectric layer is at least one of SiN, SiO2, and Al2O3; or / and the material of the second dielectric layer is at least one of SiN, SiO2, and Al2O3; or / and the material of the third dielectric layer is at least one of SiN, SiO2, and Al2O3.

7. The gallium oxide solar-blind ultraviolet detector according to claim 1, characterized in that: The material of the first semiconductor layer is at least one of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond; or / and the material of the second semiconductor layer is at least one of SiC, GaN, GaAs, Ga2O3, AlN, GaP, and diamond.

8. The method for preparing the gallium oxide solar-blind ultraviolet detector according to any one of claims 1 to 7, characterized in that: The following steps are involved: S1. Prepare a thin film transistor and a light emitting diode; wherein the method for preparing the thin film transistor comprises the following steps: S11-1, forming a gate electrode on a substrate; S11-2, depositing a first dielectric layer on the substrate so that the first dielectric layer covers the gate electrode; S11-3, depositing an n-Ga2O3 layer on the surface of the first dielectric layer facing away from the substrate, etching away a portion of the n-Ga2O3 layer, and retaining the n-Ga2O3 layer located above the gate electrode; S11-4, depositing metal on the upper surface of the structure obtained in step S11-3, etching the metal layer to obtain a source electrode, a drain electrode and a first cathode respectively; annealing; S11-5, depositing a second dielectric layer on the upper surface of the structure obtained in step S11-4, and etching the second dielectric layer to expose the upper surface of the source electrode and the upper surface of the first cathode; The method for preparing the light emitting diode comprises the following steps: S12-1, manufacturing a semiconductor layer, wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer; the first semiconductor layer and the second semiconductor layer have opposite doping types; and depositing a third dielectric layer on a surface of the semiconductor layer that needs to be combined with the second dielectric layer; S12-2, etching the third dielectric layer to obtain a first through hole and a second through hole penetrating the third dielectric layer respectively; S12-3, depositing metal on the surface of the third dielectric layer away from the semiconductor layer, etching, retaining the metal layer located in the first through hole and the metal layer located in the second through hole, and obtaining the anode and the second cathode of the light-emitting diode respectively; S2. Combine the second dielectric layer with the third dielectric layer, make the anode directly contact the source electrode, and integrate the thin film transistor and the light-emitting diode; the first cathode directly contact the second cathode to form a whole as the cathode of the light-emitting diode.

9. The preparation method according to claim 8, characterized in that: In step S11-3, a p-type doped region is formed in the surface layer of the retained n-Ga2O3 layer on one side close to the second dielectric layer, and an n+ doped region is formed in the p-type doped region; in step S11-4, a base is also obtained when etching the metal layer; the base forms an ohmic contact with the p-type doped region.

10. A gallium oxide solar-blind ultraviolet detector array, characterized in that: The array comprises a plurality of gallium oxide solar-blind ultraviolet detectors as described in any one of claims 1 to 7.

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