Preparation method of semi-insulating bicrystal gallium arsenide wafer, wafer and electrode plate

Abstract

The invention provides a preparation method of a semi-insulating bicrystal gallium arsenide wafer, the wafer and an electrode plate. The preparation method comprises the following steps: S1, providing a first seed crystal and a second seed crystal with different crystal faces; s2, welding the first seed crystal and the second seed crystal with gallium arsenide; s3, growing gallium arsenide crystals on the first seed crystal and the second seed crystal to obtain a gallium arsenide bicrystal crystal; and S4, cutting the gallium arsenide bicrystal crystal to obtain the semi-insulating bicrystal gallium arsenide wafer. Separation of carriers in carrier transmission time is realized by utilizing drift rate difference of the carriers on different crystal faces, so that the problem of carrier recombination is avoided. A weak energy level difference exists between the two crystal orientation regions, so that a certain separation effect exists between electron transmission and hole transmission in space. On the basis, compared with a conventional semiconductor material at the present stage, the semiconductor material has the remarkable advantages of being capable of remarkably reducing carrier recombination, wide in application range, good in imaging effect and the like.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and specifically refers to a preparation method of a semi-insulating double-crystal gallium arsenide wafer, a wafer and an electrode sheet. Background Art

[0002] In many fields of modern science and technology, semiconductor photoelectric detection, as a key technology for detecting weak optical signals, plays a crucial role. Its core component is a photodetector. When the photodetector receives incident photons, charges in the photoelectric material will be separated, and the electrons released by the photocathode will drift to the anode under the drive of an electric field, thereby realizing the preliminary detection of optical signals. In the above process, weak incident optical signals usually appear as a kind of photon stream that is discretely distributed in time, and this characteristic results in relatively weak signal resolution. Therefore, in order to effectively obtain the required information, it is necessary to perform signal amplification processing on this weak optical signal.

[0003] Gallium arsenide detectors have quickly become a research hotspot material in the fields of photoelectric energy spectrum detection and imaging due to their high sensitivity and excellent energy resolution exhibited at room temperature. In many conventional application scenarios, gallium arsenide detectors can work stably and efficiently, providing reliable detection and imaging support for related fields. However, in some special application scenarios, such as environmental monitoring in the nuclear industry, space exploration under extreme conditions, etc., gallium arsenide detectors face severe challenges.

[0004] Excessively high-energy and intense incident light will cause a large number of electron-hole pairs to be generated inside the detector, which makes the space charge increase sharply; the harsh environmental temperature will affect the electrical properties of the material, thereby interfering with the normal operation of the detector; too high a bias voltage will exacerbate the drift and recombination processes of carriers. The combined effect of these factors causes the space charge to accumulate inside the detector. As the space charge concentration continues to accumulate, a built-in electric field opposite to the direction of the applied electric field will be generated. The emergence of the built-in electric field will exacerbate the recombination of carriers, thus seriously affecting the performance stability of the detector. The existence of the built-in electric field will significantly reduce the intensity of the net electric field. In extreme cases, it will even cause the applied electric field to completely fail, resulting in a polarization effect. Once the polarization effect occurs, it will cause the counting rate of the detector to decrease significantly, and a severe polarization effect will even cause the detector to be completely unable to detect signals, which undoubtedly greatly limits the application of gallium arsenide detectors in special scenarios.

[0005] In summary, how to effectively avoid the problem of carrier recombination in gallium arsenide detectors in special application scenarios has become a key technical problem that needs to be overcome urgently, and it has important practical significance for expanding its application scope and improving the detection and imaging level in related fields. Summary of the Invention

[0006] To this end, the technical problem to be solved by the present invention is to overcome the carrier recombination problem in gallium arsenide detectors in the prior art, and to provide a preparation method, a wafer and an electrode sheet of a semi-insulating double-crystal gallium arsenide wafer.

[0007] To solve the above technical problem, the present invention provides a preparation method of a semi-insulating double-crystal gallium arsenide wafer, which includes: Step S1, providing a first seed crystal and a second seed crystal with different crystal planes; Step S2, welding the first seed crystal and the second seed crystal to gallium arsenide; Step S3, growing gallium arsenide crystals on the first seed crystal and the second seed crystal to obtain a gallium arsenide double-crystal crystal; Step S4, cutting the gallium arsenide double-crystal crystal to obtain the semi-insulating double-crystal gallium arsenide wafer.

[0008] In an embodiment of the present invention, the crystal planes of the first seed crystal and the second seed crystal are one of (100), (111), (110), (311), and (511).

[0009] In an embodiment of the present invention, in Step S1, both the first seed crystal and the second seed crystal are configured as semi-cylindrical structures.

[0010] In an embodiment of the present invention, Step S2 is specifically: Step S21, heating gallium arsenide to a first preset temperature to obtain a gallium arsenide melt, and at the same time maintaining the solid parts of the first seed crystal and the second seed crystal at a second preset temperature through a temperature difference process; Step S22, connecting the solid parts of the first seed crystal and the second seed crystal to the gallium arsenide melt.

[0011] In an embodiment of the present invention, the first preset temperature is not lower than 1250 °C, and the second preset temperature is not higher than 1230 °C.

[0012] In an embodiment of the present invention, in Step S3, gallium arsenide crystal growth is carried out on the first seed crystal and the second seed crystal by the vertical gradient solidification method to obtain a gallium arsenide double-crystal crystal.

[0013] In an embodiment of the present invention, Step S4 is specifically: cutting along the crystal plane dividing line of the gallium arsenide double-crystal crystal as the central axis to obtain a semi-insulating double-crystal gallium arsenide wafer with two crystal planes.

[0014] The present invention also provides a wafer prepared by using the above preparation method of the semi-insulating double-crystal gallium arsenide wafer.

[0015] The present invention also provides an electrode sheet, which includes a semi-insulating double-crystal gallium arsenide wafer prepared by using the above preparation method of the semi-insulating double-crystal gallium arsenide wafer and an electrode array layer, and the electrode array layer is coated on the surface of the semi-insulating double-crystal gallium arsenide wafer.

[0016] In one embodiment of the present invention, the substrate of the electrode array layer is one or more of Au, Pt, Ti, and Ni, and its thickness is 50 nm to 300 nm.

[0017] The above technical solution of the present invention has the following advantages compared with the prior art: The preparation method, wafer and electrode sheet of the semi-insulating double-crystal gallium arsenide wafer of the present invention utilize the difference in the drift rate of carriers on different crystal planes to achieve the separation of carriers in terms of carrier transport time, thereby avoiding the problem of carrier recombination. At the same time, the weak energy level difference between the two crystal orientation regions also results in a certain separation effect of the electron transport and hole transport in space, thereby further improving the transport and separation efficiency of electrons and holes, and achieving the purpose of optimizing the imaging effect of gallium arsenide detectors. Based on this, this application has significant advantages such as significantly reducing carrier recombination, wide application range, and good imaging effect compared with conventional semiconductor materials at the present stage, providing new ideas for the research and development of detection and imaging technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to specific embodiments of the present invention in conjunction with the drawings.

[0019] Figure 1 It is a partial structural schematic diagram of a gallium arsenide double-crystal in a preferred embodiment of the present invention; Figure 2 It is a structural schematic diagram of a semi-insulating double-crystal gallium arsenide wafer and an enlarged structural schematic diagram of different crystal planes at the same magnification in a preferred embodiment of the present invention; Figure 3 It is an image test imaging diagram of an electrode sheet in another embodiment of the present invention; Figure 4 It is an image test imaging diagram in Comparative Example 1 of the present invention; Figure 5 It is an image test imaging diagram in Comparative Example 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The present invention will be further described below in conjunction with the drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the examples given are not intended to limit the present invention. Example 1

[0021] This embodiment provides a preparation method of a semi-insulating double-crystal gallium arsenide wafer, which is used to prepare wafers with different crystal planes, and specifically includes: Step S1: Provide a first seed crystal and a second seed crystal with different crystal planes. In this embodiment, a first seed crystal with a crystal plane of (100) and a second seed crystal with a crystal plane of (111) are provided. It should be noted that carriers are more likely to recombine when they aggregate in the same time and the same region. Therefore, in this application, the possibility of such aggregation is primarily reduced by separating the carrier transport time. Specifically, in this embodiment, there are differences in the drift rates of carriers on these two crystal planes. Therefore, within the same time, the distances they move on different seed crystals are correspondingly different, thereby achieving the effect of separating different carriers.

[0022] Further, in different embodiments, the crystal planes of the first seed crystal and the second seed crystal can be configured as one of (100), (111), (110), (311), (511), as long as it is ensured that the crystal planes of the first seed crystal and the second seed crystal are different. The present invention does not make specific limitations on this.

[0023] Further, both the first seed crystal and the second seed crystal in this embodiment are configured as semi-cylindrical structures. First, the semi-cylindrical structure is beneficial for capturing and scattering incident light. At the same time, it can increase the propagation path length of light in the seed crystal, enabling more interaction opportunities between light and the material, thereby improving the light absorption efficiency and further enhancing the photoelectric conversion efficiency of the device. Second, the curved surface of the semi-cylinder can also make light incident and exit at a more inclined angle, thereby reducing the reflectivity and enabling more light to enter the interior of the seed crystal for utilization. In addition, during the material growth process, the semi-cylindrical structure may have better growth stability. Compared with some sharp shapes or complex polyhedral structures, the curved surface of the semi-cylinder is relatively smooth. During the crystal growth process, atoms are more likely to be regularly arranged along the curved surface, reducing the situation of lattice defects and stress concentration, which is beneficial for growing high-quality crystal structures and thus ensuring the performance and quality of the seed crystal.

[0024] Step S2: Weld the first seed crystal and the second seed crystal to gallium arsenide. In this embodiment, step S2 is specifically: Step S21: Heat gallium arsenide to a first preset temperature to obtain a gallium arsenide melt, and at the same time, maintain the solid portions of the first seed crystal and the second seed crystal at a second preset temperature through a temperature difference process. It should be noted that the melting point of gallium arsenide is about 1250 °C. The seed crystal usually maintains good thermal stability below 1230 °C, and its crystal structure will not undergo serious distortion or damage due to overheating. If the processing temperature is too high and exceeds the tolerance range of the seed crystal, defects and dislocations may occur in the lattice of the seed crystal, thus affecting the entire crystal growth process and the performance of the final product. Therefore, in this embodiment, the first preset temperature is not lower than 1250 °C to ensure that gallium arsenide can be maintained in a molten state. At the same time, the second preset temperature is not higher than 1230 °C, so that the seed crystal can maintain a stable crystal structure to provide a good template and starting point for the subsequent growth of gallium arsenide crystals.

[0025] Step S22: Connect the solid portions of the first seed crystal and the second seed crystal to the gallium arsenide melt, thereby realizing the process of welding the first seed crystal and the second seed crystal to the gallium arsenide. Further, this welding method can form a good interfacial bond between the seed crystal and the growing gallium arsenide, reduce the stress and defects at the interface, facilitate the transport of carriers at the interface, reduce the scattering and recombination probability of carriers, and thus improve the performance and stability of gallium arsenide devices.

[0026] Step S3: Grow gallium arsenide crystals on the first seed crystal and the second seed crystal to obtain a gallium arsenide bicrystal; specifically, in step S3 of this embodiment, gallium arsenide crystal growth is carried out on the first seed crystal and the second seed crystal by the vertical gradient solidification method to obtain a gallium arsenide bicrystal. In this embodiment, due to the existence of a temperature gradient, the gallium arsenide melt in the region near the seed crystal will first reach a supercooled state, that is, a state where the temperature is lower than its theoretical solidification temperature but has not yet solidified. The seed crystal provides a crystallization core for the gallium arsenide melt, and the gallium arsenide atoms in the melt will start to arrange and crystallize on the surface of the seed crystal according to the crystal structure and orientation of the seed crystal, gradually forming a crystal layer. Further, as heat is continuously dissipated from the bottom, the temperature gradient causes the solidification interface to gradually advance from the seed crystal end to the other end of the melt, thereby achieving the purpose of continuous growth of gallium arsenide crystals on the seed crystal, and finally obtaining a bicrystal composed of two gallium arsenide single crystal parts with different orientations. For its specific structure, see Figure 1 as shown.

[0027] Step S4: Cut the gallium arsenide bicrystal to obtain the semi-insulating bicrystal gallium arsenide wafer. Further, step S4 in this embodiment is specifically: Cut along the crystal plane dividing line of the gallium arsenide bicrystal as the central axis to obtain a semi-insulating bicrystal gallium arsenide wafer with two crystal planes. See Figure 2 as shown, Figure 2shows the schematic diagram of the structure of the semi-insulating double-crystal gallium arsenide wafer in this embodiment and the enlarged schematic diagrams of different crystal planes at the same magnification. From Figure 2 it can be seen that at the same magnification, the crystal plane spacing of the gallium arsenide crystal grown on the (100) crystal plane side is 0.282 nm, while the crystal plane spacing of the gallium arsenide crystal grown on the (111) crystal plane side is 0.326 nm. Thus, it can be proved that the target semi-insulating double-crystal gallium arsenide wafer is obtained by using the method described in this embodiment.

[0028] For the wafer prepared by the above method, the difference in the drift rates of carriers on different crystal planes can be utilized to achieve the separation of carriers in the dimension of transmission time, effectively avoiding the problem of carrier recombination. At the same time, due to the weak energy level difference between the two crystal orientation regions, the transmission of electrons and holes shows a certain degree of spatial separation, further improving the transmission efficiency and separation efficiency of electrons and holes, and finally achieving the goal of optimizing the gallium arsenide detection imaging effect. Embodiment 2

[0029] This embodiment provides a wafer, which is prepared by using the preparation method of the semi-insulating double-crystal gallium arsenide wafer described in Embodiment 1. Embodiment 3

[0030] This embodiment provides an electrode sheet, which includes a semi-insulating double-crystal gallium arsenide wafer prepared by the preparation method of the semi-insulating double-crystal gallium arsenide wafer described in Embodiment 1 and an electrode array layer, and the electrode array layer is coated on the surface of the semi-insulating double-crystal gallium arsenide wafer.

[0031] Furthermore, in this embodiment, using the semi-insulating double-crystal gallium arsenide wafer as the electrode original sheet, metal Au is plated on the surface of the electrode original sheet by a double-sided sputtering gold plating process. In different embodiments, the substrate of the electrode array layer can also be configured as one or more of Pt, Ti, Ni, and its thickness can also be configured as 50 nm to 300 nm according to actual usage requirements, and the present invention does not make specific limitations on this.

[0032] Furthermore, the imaging diagram of the electrode sheet in this embodiment under image testing is shown in Figure 3 as follows. Comparative Example 1

[0033] In this comparative example, gallium arsenide single crystal (100) is used to replace the semi-insulating double-crystal gallium arsenide wafer in Embodiment 3, and the imaging of the same object is shown in Figure 4 as follows. Comparative Example 2

[0034] In this comparative example, gallium arsenide single crystal (111) is used to replace the semi-insulating double-crystal gallium arsenide wafer in Embodiment 3, and the imaging of the same object is shown in Figure 5 as follows. FromFigures 3 to 5 It can be seen that the imaging quality is higher when using semi-insulating double-crystal gallium arsenide wafers.

[0035] In summary, for the preparation method, wafer and electrode sheet of the semi-insulating double-crystal gallium arsenide wafer of the present invention, the difference in the drift rate of carriers on different crystal planes is utilized to achieve the separation of carrier transport time, thereby avoiding the problem of carrier recombination. At the same time, the weak energy level difference existing between the two crystal orientation regions also enables a certain separation effect in space between the transport of electrons and the transport of holes, thereby further improving the transport and separation efficiency of electrons and holes, and achieving the purpose of optimizing the imaging effect of gallium arsenide detectors. Based on this, compared with conventional semiconductor materials at the present stage, this application has significant advantages such as significantly reducing carrier recombination, wide application range and good imaging effect, providing new ideas for the research and development of detection and imaging technologies.

[0036] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to enumerate all the implementation manners here. And the obvious changes or modifications derived therefrom still fall within the protection scope of the present invention.

Claims

1. A method for preparing a semi-insulating twin-crystal gallium arsenide wafer, characterized in that: include: Step S1, providing a first seed crystal and a second seed crystal having different crystal planes; Step S2, welding the first seed crystal and the second seed crystal to gallium arsenide; Step S3, growing gallium arsenide crystals on the first seed crystal and the second seed crystal to obtain gallium arsenide twin crystals; Step S4, cutting the GaAs twin crystal to obtain the semi-insulating twin GaAs wafer.

2. The method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to claim 1, characterized in that: The crystal planes of the first seed crystal and the second seed crystal are one of (100), (111), (110), (311), and (511).

3. The method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to claim 1, characterized in that: In step S1 , the first seed crystal and the second seed crystal are both configured as a semi-cylindrical structure.

4. The method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to claim 1, characterized in that: Step S2 is specifically as follows: Step S21, heating gallium arsenide to a first preset temperature to obtain a gallium arsenide melt, while maintaining the solid parts of the first seed crystal and the second seed crystal at a second preset temperature through a temperature difference process; Step S22: connecting the solid parts of the first seed crystal and the second seed crystal to the gallium arsenide melt.

5. The method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to claim 4, characterized in that: The first preset temperature is not lower than 1250°C, and the second preset temperature is not higher than 1230°C.

6. The method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to claim 1, characterized in that: In step S3, gallium arsenide crystals are grown on the first seed crystal and the second seed crystal by vertical gradient solidification method to obtain gallium arsenide twin crystals.

7. The method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to claim 1, characterized in that: Step S4 specifically includes: cutting the GaAs wafer with the crystal plane boundary line of the GaAs twin crystal as the central axis to obtain a semi-insulating twin GaAs wafer with two crystal planes.

8. A wafer, characterized in that: The semi-insulating twin-crystal gallium arsenide wafer is prepared by the method for preparing the semi-insulating twin-crystal gallium arsenide wafer according to any one of claims 1 to 7.

9. An electrode sheet, characterized in that: It comprises a semi-insulating twin-crystal gallium arsenide wafer prepared by the method for preparing a semi-insulating twin-crystal gallium arsenide wafer according to any one of claims 1 to 7 and an electrode array layer, wherein the electrode array layer is coated on the surface of the semi-insulating twin-crystal gallium arsenide wafer.

10. The electrode sheet according to claim 9, characterized in that: The electrode array layer substrate is one or more of Au, Pt, Ti, and Ni, and has a thickness of 50 nm to 300 nm.

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