Temperature sensor
By designing a temperature sensor containing multiple circuit units, the problem of high power consumption of temperature sensors in the prior art is solved, and higher measurement accuracy and lower power consumption are achieved.
Patent Information
- Application Number
- CN202510057717.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-14
- Publication Date
- 2025-05-27
AI Technical Summary
Existing temperature sensors based on BJT temperature sensing have problems with high power consumption, which affects their measurement accuracy and energy efficiency.
A temperature sensor including a temperature-current conversion unit, a current-frequency conversion unit and a frequency-digital conversion unit is designed to achieve a smaller current value and a high slope by stacking field effect tube circuits, voltage-current conversion circuits, bias circuits, double clamp circuits, bandgap reference circuits and current subtractor circuits, thereby improving measurement accuracy and reducing power consumption.
It achieves the measurement accuracy of temperature sensors while reducing power consumption, and is suitable for smart homes, smart cities and industrial automation fields.
Smart Images
Figure CN120043648A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of electronic circuits, and particularly to a temperature sensor. Background Art
[0002] With the rapid development of the Internet of Things, temperature sensors have become an important part of various intelligent devices. In the fields of smart home, smart city, industrial automation, etc., real-time temperature monitoring can improve energy efficiency, optimize resource utilization, and enhance the user experience. However, in related technologies, temperature sensors based on BJT temperature sensing generally have the problem of high power consumption. Therefore, there are still technical problems to be solved in related technologies. Summary of the Invention
[0003] An object of this application is to solve at least to some extent one of the technical problems existing in the prior art.
[0004] To this end, an object of an embodiment of this application is to provide a temperature sensor, which can reduce its own power consumption and improve its measurement accuracy at the same time.
[0005] To achieve the above technical object, the technical solution adopted by the embodiment of this application includes: a temperature sensor, including a temperature-current conversion unit, a current-frequency conversion unit, and a frequency-digital conversion unit; the current-frequency conversion unit is connected to the temperature-current conversion unit; the current-frequency conversion unit is connected to the frequency-digital conversion unit;
[0006] Wherein the temperature-current conversion unit includes a stacked field-effect transistor circuit, a voltage-current conversion circuit, a bias circuit, a double-clamping circuit, a bandgap reference circuit, and a current subtractor circuit; the voltage-current conversion circuit and the double-clamping circuit are connected to the stacked field-effect transistor circuit; the bias circuit and the current subtractor circuit are connected to the double-clamping circuit; the bandgap reference circuit is connected to the current subtractor circuit.
[0007] In addition, for a temperature sensor according to the above embodiment of the present invention, the following additional technical features may further exist:
[0008] Further, in the embodiment of this application, the stacked field-effect transistor circuit includes a plurality of field-effect transistors connected in series; any one of the field-effect transistors is used to generate a reference voltage.
[0009] Further, in the embodiment of this application, the voltage-current conversion circuit includes a first amplifier, a second amplifier, a first field-effect transistor, a second field-effect transistor, a third field-effect transistor, a fourth field-effect transistor, a fifth field-effect transistor, and a first resistor;
[0010] The inverting input terminal of the first amplifier is connected to the stacked field effect transistor circuit; the non-inverting input terminal of the first amplifier and the drain of the second field effect transistor are connected to one end of the first resistor;
[0011] The output terminal of the first amplifier is connected to the gate of the second field effect transistor;
[0012] The gate of the first field effect transistor, the drain of the first field effect transistor, and the source of the second field effect transistor are connected to the gate of the fifth field effect transistor; the source of the first field effect transistor is connected to the first power supply; the drain of the fifth field effect transistor is connected to the current-frequency conversion unit;
[0013] The inverting input terminal of the second amplifier is connected to the stacked field effect transistor circuit; the non-inverting input terminal of the second amplifier and the drain of the third field effect transistor are connected to the other end of the first resistor;
[0014] The output terminal of the second amplifier is connected to the gate of the third field effect transistor;
[0015] The source of the third field effect transistor, the drain of the fourth field effect transistor, and the gate of the fourth field effect transistor are connected; the source of the fourth field effect transistor is grounded.
[0016] Further, in the embodiment of the present application, the bias circuit includes a first triode, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor, and a thirteenth field effect transistor;
[0017] The source of the sixth field effect transistor, the source of the seventh field effect transistor, and the source of the eighth field effect transistor are connected to the first power supply;
[0018] The gate of the sixth field effect transistor, the gate of the seventh field effect transistor, the gate of the eighth field effect transistor, and the drain of the seventh field effect transistor are connected to the drain of the tenth field effect transistor;
[0019] The drain of the sixth field effect transistor, the drain of the ninth field effect transistor, the gate of the ninth field effect transistor, and the gate of the twelfth field effect transistor are connected to the gate of the thirteenth field effect transistor;
[0020] The source of the tenth field effect transistor and the source of the ninth field effect transistor are connected to the drain of the twelfth field effect transistor;
[0021] The source of the eleventh field effect transistor and the source of the twelfth field effect transistor are connected to the drain of the thirteenth field effect transistor; the source of the thirteenth field effect transistor is grounded;
[0022] The drain of the eighth field effect transistor, the drain of the eleventh field effect transistor, and the gate of the eleventh field effect transistor are connected to the gate of the tenth field effect transistor;
[0023] The drain of the sixth field effect transistor and the emitter of the first triode are connected to the dual clamping circuit;
[0024] The collector and the base of the first triode are both grounded.
[0025] Further, in the embodiment of the present application, the dual clamping circuit includes
[0026] a third amplifier, a fourth amplifier, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor, and a second resistor;
[0027] The inverting input terminal of the third amplifier is connected to the bias circuit, and the non-inverting input terminal of the third amplifier and the drain of the sixteenth field effect transistor are connected to one end of the second resistor
[0028] The output terminal of the third amplifier is connected to the gate of the sixteenth field effect transistor;
[0029] The gate, the drain of the fifteenth field effect transistor, and the source of the sixteenth field effect transistor are connected to the gate of the fourteenth field effect transistor; the source of the fifteenth field effect transistor is connected to the first power supply; the drain of the fourteenth field effect transistor is connected to the current-frequency conversion unit;
[0030] The inverting input terminal of the fourth amplifier is connected to the stacked field effect transistor circuit; the non-inverting input terminal of the fourth amplifier and the drain of the seventeenth field effect transistor are connected to the other end of the second resistor;
[0031] The output terminal of the fourth amplifier is connected to the gate of the seventeenth field effect transistor;
[0032] The source of the seventeenth field effect transistor is grounded.
[0033] Further, in the embodiment of the present application, the bandgap reference circuit includes a third resistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a fifth amplifier, a second triode, and a third triode;
[0034] The source of the eighteenth field effect transistor and the source of the nineteenth field effect transistor are connected to the first power supply;
[0035] The gate of the eighteenth field effect transistor and the gate of the nineteenth field effect transistor are connected to the output terminal of the fifth amplifier; the output terminal of the fifth amplifier is connected to the current subtractor circuit;
[0036] The drain of the eighteenth field effect transistor and one end of the third resistor are connected to the non-inverting input terminal of the fifth amplifier;
[0037] The drain of the nineteenth field effect transistor and the emitter of the second triode are connected to the inverting input terminal of the fifth amplifier;
[0038] The other end of the third resistor is connected to the source of the third triode;
[0039] The base of the third triode, the collector of the third triode, the base of the second triode, and the collector of the second triode are grounded.
[0040] Further, in the embodiment of the present application, the current subtractor circuit includes a twentieth field effect transistor, a twenty-first field effect transistor, a twenty-second field effect transistor, a twenty-third field effect transistor, a twenty-fourth field effect transistor, a twenty-fifth field effect transistor, a twenty-sixth field effect transistor, a twenty-seventh field effect transistor, a twenty-eighth field effect transistor, and a twenty-ninth field effect transistor;
[0041] The source of the twentieth field effect transistor, the source of the twenty-first field effect transistor, the source of the twenty-fifth field effect transistor, and the source of the twenty-eighth field effect transistor are connected to the first power supply;
[0042] The gate of the twentieth field effect transistor is connected to the double clamping circuit; the gate of the twenty-first field effect transistor is connected to the bandgap reference circuit;
[0043] The drain of the twentieth field effect transistor, the drain of the twenty-second field effect transistor, the gate of the twenty-second field effect transistor are connected to the gate of the twenty-third field effect transistor;
[0044] The source of the twenty-second field effect transistor, the source of the twenty-third field effect transistor, the source of the twenty-fourth field effect transistor, and the source of the twenty-seventh field effect transistor are all grounded;
[0045] The drain of the twenty-first field effect transistor, the drain of the twenty-third field effect transistor, the drain of the twenty-fourth field effect transistor, and the gate of the twenty-fourth field effect transistor are connected to the gate of the twenty-seventh field effect transistor;
[0046] The drain of the twenty-fifth field effect transistor, the gate of the twenty-fifth field effect transistor, and the source of the twenty-sixth field effect transistor are connected to the gate of the twenty-eighth field effect transistor;
[0047] The drain of the twenty-sixth field effect transistor, the gate of the twenty-sixth field effect transistor, and the drain of the twenty-seventh field effect transistor are connected to the gate of the twenty-ninth field effect transistor;
[0048] The drain of the twenty-eighth field effect transistor is connected to the source of the twenty-ninth field effect transistor; the drain of the twenty-ninth field effect transistor is connected to the current-frequency conversion unit.
[0049] Further, in the embodiment of the present application, the current-frequency conversion unit includes a first frequency reading unit and a second frequency reading unit; wherein, the first frequency reading unit and the second frequency reading unit have the same structure, and the first frequency reading unit or the second frequency reading unit includes a first capacitor, a thirty-first field effect transistor, a first comparator, a first inverter module, a first delay unit, a first latch, and an edge detector;
[0050] The positive input terminal of the first comparator, one end of the first capacitor, and the drain of the thirty-first field effect transistor are connected to the voltage-current conversion circuit; the negative input terminal of the first comparator is connected to the stacked field effect transistor circuit;
[0051] The output terminal of the first comparator is connected to the input terminal of the first inverter module; the input terminal of the first delay unit and the first input terminal of the first latch are connected to the output terminal of the first inverter module; the output terminal of the first delay unit is connected to the second input terminal of the first latch; the first output terminal of the first latch is connected to the input terminal of the edge detector; the output terminal of the edge detector is connected to the frequency-digital conversion unit;
[0052] The second output terminal of the first latch is connected to the gate of the thirty-first field effect transistor; the source of the thirty-first field effect transistor and the other end of the first capacitor are connected.
[0053] Further, in the embodiment of the present application, the current-frequency conversion unit further includes a third frequency reading unit; the third frequency reading unit includes a second capacitor, a thirty-second field effect transistor, a second comparator, a second inverter module, a second delay unit, and a second latch;
[0054] The positive input terminal of the second comparator, one end of the second capacitor, and the drain of the thirty-second field effect transistor are connected to the voltage-current conversion circuit; the negative input terminal of the second comparator is connected to the stacked field effect transistor circuit;
[0055] The output terminal of the second comparator is connected to the input terminal of the second inverter module; the input terminal of the second delay unit and the first input terminal of the second latch are connected to the output terminal of the second inverter module; the output terminal of the second delay unit is connected to the second input terminal of the second latch; the first output terminal of the second latch is connected to the frequency-digital conversion unit;
[0056] The second output terminal of the second latch is connected to the gate of the thirty-first field effect transistor; the source of the thirty-first field effect transistor and the other end of the second capacitor are connected.
[0057] Further, in the embodiment of the present application, the frequency-digital conversion unit includes a first AND gate, a second AND gate, a third AND gate, a first inverter, a first counter, a second counter, and a third counter;
[0058] The first input terminal of the first AND gate, the first input terminal of the second AND gate, and the first input terminal of the third AND gate are connected to the output terminal of the first inverter;
[0059] The second input terminal of the first AND gate, the second input terminal of the second AND gate, and the second input terminal of the third AND gate are connected to the current-frequency conversion unit;
[0060] The output terminal of the first AND gate is connected to the first input terminal of the first counter; the output terminal of the second AND gate is connected to the first input terminal of the second counter; the output terminal of the third AND gate is connected to the first input terminal of the third counter;
[0061] The second input terminals of the first counter, the second counter, and the third counter are connected to the start signal;
[0062] The output terminal of the first counter is connected to the input terminal of the first inverter; the output signals after subtraction operations of the output terminals of the second counter and the third counter are used as the output signals of the frequency-digital conversion unit.
[0063] The advantages and beneficial effects of the present application will be partially given in the following description, partially will become obvious from the following description, or can be understood through the practice of the present application:
[0064] The temperature sensor of the present application may include a temperature-current conversion unit, a current-frequency conversion unit, and a frequency-digital conversion unit; the current-frequency conversion unit is connected to the temperature-current conversion unit; the current-frequency conversion unit is connected to the frequency-digital conversion unit; wherein the temperature-current conversion unit includes a stacked field effect transistor circuit, a voltage-current conversion circuit, a bias circuit, a double clamping circuit, a bandgap reference circuit, and a current subtractor circuit; the voltage-current conversion circuit and the double clamping circuit are connected to the stacked field effect transistor circuit; the bias circuit and the current subtractor circuit are connected to the double clamping circuit; the bandgap reference circuit is connected to the current subtractor circuit. By using the double clamping circuit and the current subtractor in the present application, a small current value is generated at the temperature sensing front end while maintaining a high slope, thereby improving the accuracy. Since a small current value is generated in the present application, the self-power consumption can be reduced, and at the same time, the self-measurement accuracy can be improved. Description of the Drawings
[0065] Figure 1 It is a schematic diagram of a module of a temperature sensor in a specific embodiment of the present invention;
[0066] Figure 2 It is a schematic diagram of the circuit structure of a stacked field - effect transistor circuit and a voltage - current conversion circuit in a specific embodiment of the present invention;
[0067] Figure 3 It is a schematic diagram of the circuit structure of a bias circuit in a specific embodiment of the present invention;
[0068] Figure 4 It is a schematic diagram of the circuit structure of a double - clamping circuit in a specific embodiment of the present invention;
[0069] Figure 5 It is a schematic diagram of the circuit structure of a band - gap reference circuit in a specific embodiment of the present invention;
[0070] Figure 6 It is a schematic diagram of the circuit structure of a current subtractor circuit in a specific embodiment of the present invention;
[0071] Figure 7 It is a schematic diagram of the circuit structure of a first frequency reading unit and a second frequency reading unit in a specific embodiment of the present invention;
[0072] Figure 8 It is a schematic diagram of the circuit structure of a frequency - to - digital conversion unit in a specific embodiment of the present invention. Detailed Embodiments
[0073] The following describes in detail the embodiments of the present invention. The principles and processes of the temperature sensor, system, device, and storage medium in the embodiments of the present invention are described as follows.
[0074] Referring to Figure 1 , the present application provides a temperature sensor. In Figure 1 , the sensor may include a temperature - to - current conversion unit 2, a current - to - frequency conversion unit 1, and a frequency - to - digital conversion unit 3; the current - to - frequency conversion unit 1 is connected to the temperature - to - current conversion unit 2; the current - to - frequency conversion unit 1 is connected to the frequency - to - digital conversion unit 3;
[0075] Among them, the degree-current conversion unit 2 includes a stacked field effect transistor circuit 21, a voltage-current conversion circuit 22, a bias circuit 23, a double clamping circuit 24, a bandgap reference circuit 25, and a current subtractor circuit 26; the voltage-current conversion circuit 22 and the double clamping circuit 24 are connected to the stacked field effect transistor circuit 21; the bias circuit 23 and the current subtractor circuit 26 are connected to the double clamping circuit 24; the bandgap reference circuit 25 is connected to the current subtractor circuit 26.
[0076] The temperature sensor of the present application may include a temperature-current conversion unit, a current-frequency conversion unit, and a frequency-digital conversion unit; the current-frequency conversion unit is connected to the temperature-current conversion unit; the current-frequency conversion unit is connected to the frequency-digital conversion unit; wherein the current-frequency conversion unit includes a stacked field effect transistor circuit, a voltage-current conversion circuit, a bias circuit, a double clamping circuit, a bandgap reference circuit, and a current subtractor circuit; the voltage-current conversion circuit and the double clamping circuit are connected to the stacked field effect transistor circuit; the bias circuit and the current subtractor circuit are connected to the double clamping circuit; the bandgap reference circuit is connected to the current subtractor circuit. By using the double clamping circuit and the current subtractor in the present application, a small current value is generated at the temperature-sensing front end while maintaining a high slope, thereby improving the accuracy. Since a small current value is generated in the present application, the self-power consumption can be reduced while the measurement accuracy of the present application is improved.
[0077] Further, in the embodiment of the present application, the stacked field effect transistor circuit 21 includes a plurality of field effect transistors PMOS connected in series; any one of the field effect transistors is used to generate a reference voltage. Specifically, referring to Figure 2 , the stacked field effect transistor circuit 21 may include at least 4 field effect transistors PMOS connected in series, wherein the source and gate of the first field effect transistor PMOS are connected to the first power supply V a ; the drain of the last field effect transistor PMOS is grounded, and starting from the second field effect transistor PMOS, the source and gate of the subsequent field effect transistor PMOS are connected to the drain of the previous field effect transistor PMOS.
[0078] Further, in the embodiment of the present application, referring to Figure 2 , the voltage-current conversion circuit 22 includes a first amplifier AMP 4 , a second amplifier AMP 5 , a first field effect transistor M 13 , a second field effect transistor M 14 , a third field effect transistor M 15 , a fourth field effect transistor M 16 , a fifth field effect transistor M 5 , and a first resistor R 4 ;
[0079] The first amplifier AMP4 The inverting input terminal is connected to the stacked field effect transistor circuit 21; the first amplifier AMP 4 's non-inverting input terminal and the second field effect transistor M 14 's drain is connected to one end of the first resistor R 4 ;
[0080] The output terminal of the first amplifier AMP 4 is connected to the gate of the second field effect transistor M 14 ;
[0081] The gate of the first field effect transistor M 13 , the drain of the first field effect transistor M 13 and the source of the second field effect transistor M 14 are connected to the gate of the fifth field effect transistor M 5 ; the source of the first field effect transistor M 13 is connected to the first power supply V a ; the drain of the fifth field effect transistor M 5 is connected to the current-frequency conversion unit 1;
[0082] The inverting input terminal of the second amplifier AMP 5 is connected to the stacked field effect transistor circuit 21; the non-inverting input terminal of the second amplifier AMP 5 and the drain of the third field effect transistor M 15 are connected to the other end of the first resistor R 4 ;
[0083] The output terminal of the second amplifier AMP 5 is connected to the gate of the third field effect transistor M 15 ;
[0084] The source of the third field effect transistor M 15 , the drain of the fourth field effect transistor M 16 are connected to the gate of the fourth field effect transistor M 16 ; the source of the fourth field effect transistor M 16 is grounded.
[0085] Furthermore, in the embodiment of the present application, referring to Figure 3 and Figure 4 , the bias circuit 23 includes the first triode Q 3 , the sixth field effect transistor M b1 , the seventh field effect transistor M b2 , the eighth field effect transistor M b3 , the ninth field effect transistor M b4 , the tenth field effect transistor M b5 , the eleventh field effect transistor M b6 , the twelfth field effect transistor M b7 and the thirteenth field effect transistor Mb8 ; The source electrode of the sixth field effect transistor M b1 , the source electrode of the seventh field effect transistor M b2 , the source electrode of the eighth field effect transistor M b3 are connected to the first power supply V a ; The gate electrode of the sixth field effect transistor M b1 , the gate electrode of the seventh field effect transistor M b2 , the gate electrode of the eighth field effect transistor M b3 and the drain electrode of the seventh field effect transistor M b2 are connected to the drain electrode of the tenth field effect transistor M b5 ; The drain electrode of the sixth field effect transistor M b1 , the drain electrode of the ninth field effect transistor M b4 , the gate electrode of the ninth field effect transistor M b4 and the gate electrode of the twelfth field effect transistor M b7 are connected to the gate electrode of the thirteenth field effect transistor M b8 ; The source electrode of the tenth field effect transistor M b5 and the source electrode of the ninth field effect transistor M b4 are connected to the drain electrode of the twelfth field effect transistor M b7 ; The source electrode of the eleventh field effect transistor M b6 and the source electrode of the twelfth field effect transistor M b7 are connected to the drain electrode of the thirteenth field effect transistor M b8 ; The source electrode of the thirteenth field effect transistor M b8 is grounded; The drain electrode of the eighth field effect transistor M b3 , the drain electrode of the eleventh field effect transistor M b6 and the gate electrode of the eleventh field effect transistor M b6 are connected to the gate electrode of the tenth field effect transistor M b5 ; The drain electrode of the sixth field effect transistor M b1 and the emitter of the first triode Q 3 are connected to the double clamping circuit 24; The collector of the first triode Q 3 and the base of the first triode Q 3 are both grounded.
[0086] Further, in the embodiment of the present application, referring to Figure 4 , the double clamping circuit 24 includes a third amplifier AMP 1 , a fourth amplifier AMP 2 , a fourteenth field effect transistor M 24 , a fifteenth field effect transistor M 34 , a sixteenth field effect transistor M 1 , a seventeenth field effect transistor M 2 and a second resistor R 1 ; The third amplifier AMP 1The inverting input terminal is connected to the bias circuit 23, and the third amplifier AMP 1 The non-inverting input terminal and the sixteenth field effect transistor M 1 The drain of is connected to the second resistor R 1 One end of is connected to the output terminal of the third amplifier AMP 1 The output terminal of is connected to the gate of the sixteenth field effect transistor M 1 The gate of the fifteenth field effect transistor M 34 The gate of the fifteenth field effect transistor M 34 The drain of and the sixteenth field effect transistor M 1 The source of is connected to the gate of the fourteenth field effect transistor M 24 The gate of the fifteenth field effect transistor M 34 The source of is connected to the first power supply V a Connected; the drain of the fourteenth field effect transistor M 24 Is connected to the current-frequency conversion unit 1; the fourth amplifier AMP 2 The inverting input terminal is connected to the stacked field effect transistor circuit 21; the fourth amplifier AMP 2 The non-inverting input terminal and the seventeenth field effect transistor M 2 The drain of is connected to the other end of the second resistor R 1 The output terminal of the fourth amplifier AMP 2 Is connected to the gate of the seventeenth field effect transistor M 2 The gate of the seventeenth field effect transistor M 2 The source of is grounded.
[0087] Furthermore, in the embodiment of the present application, referring to Figure 5 , the bandgap reference circuit 25 includes a third resistor R 2 , the eighteenth field effect transistor M 3 , the nineteenth field effect transistor M 4 , the fifth amplifier AMP 3 , the second triode Q 1 And the third triode Q 2 ; the source of the eighteenth field effect transistor M 3 And the source of the nineteenth field effect transistor M 4 Are connected to the first power supply V a Connected; the gate of the eighteenth field effect transistor M 3 And the gate of the nineteenth field effect transistor M 4 Are connected to the output terminal of the fifth amplifier AMP 3 The output terminal of the fifth amplifier AMP 3 Is connected to the current subtractor circuit 26; the drain of the eighteenth field effect transistor M 3 And one end of the third resistor R 2 Are connected to the non-inverting input terminal of the fifth amplifier AMP 3 The gate of the nineteenth field effect transistor M4 the drain of 1 and the emitter of the second triode Q 3 are connected to the inverting input terminal of the fifth amplifier AMP 2 ; the other end of the third resistor R 2 is connected to the source of the third triode Q 2 ; the base of the third triode Q 2 and the collector of the third triode Q 1 and the base of the second triode Q 1 and the collector of the second triode Q are grounded.
[0088] Furthermore, in the embodiment of the present application, referring to Figure 6 , the current subtractor circuit 26 includes the twentieth field effect transistor M 5 , the twenty - first field effect transistor M 6 , the twenty - second field effect transistor M 7 , the twenty - third field effect transistor M 8 , the twenty - fourth field effect transistor M 12 , the twenty - fifth field effect transistor M 9 , the twenty - sixth field effect transistor M 10 , the twenty - seventh field effect transistor M 11 , the twenty - eighth field effect transistor M 44 and the twenty - ninth field effect transistor M 54 ; the source of the twentieth field effect transistor M 5 , the source of the twenty - first field effect transistor M 6 , the source of the twenty - fifth field effect transistor M 9 and the source of the twenty - eighth field effect transistor M 44 are connected to the first power supply V a ; the gate of the twentieth field effect transistor M5 is connected to the double - clamping circuit 24; the gate of the twenty - first field effect transistor M 6 is connected to the bandgap reference circuit 25; the drain of the twentieth field effect transistor M 5 , the drain of the twenty - second field effect transistor M 7 and the gate of the twenty - second field effect transistor M 7 are connected to the gate of the twenty - third field effect transistor M 8 ; the source of the twenty - second field effect transistor M 7 , the source of the twenty - third field effect transistor M 8 , the source of the twenty - fourth field effect transistor M 12 and the source of the twenty - seventh field effect transistor M 11 are all grounded; the drain of the twenty - first field effect transistor M 6 , the drain of the twenty - third field effect transistor M 8 , the drain of the twenty - fourth field effect transistor M 12 and the drain of the twenty - fourth field effect transistor M12 The gate of is connected to the gate of the twenty-seventh field effect transistor M 11 ; The drain of the twenty-fifth field effect transistor M 9 The gate of the twenty-fifth field effect transistor M 9 And the source of the twenty-sixth field effect transistor M are connected to the gate of the twenty-eighth field effect transistor M 10 ; The drain of the twenty-sixth field effect transistor M 44 The gate of the twenty-sixth field effect transistor M 10 And the drain of the twenty-seventh field effect transistor M are connected to the gate of the twenty-ninth field effect transistor M 10 ; The drain of the twenty-eighth field effect transistor M 11 The gate of the twenty-eighth field effect transistor M 54 And the drain of the twenty-seventh field effect transistor M are connected to the gate of the twenty-ninth field effect transistor M 44 ; The drain of the twenty-eighth field effect transistor M 54 Is connected to the source of the twenty-ninth field effect transistor M; The drain of the twenty-ninth field effect transistor M 54 Is connected to the current-frequency conversion unit 1.
[0089] Furthermore, in the embodiment of the present application, referring to Figure 7 , the current-frequency conversion unit 1 includes a first frequency reading unit and a second frequency reading unit; wherein, the first frequency reading unit and the second frequency reading unit have the same structure, and the first frequency reading unit or the second frequency reading unit includes a first capacitor C1, a thirtieth field effect transistor M64, a first comparator A4, a first inverter module INV4, a first delay unit D4, a first latch SR1, and an edge detector SCK1. The first inverter module INV4 can be composed of several inverters connected in series.
[0090] The positive input terminal of the first comparator A4, one end of the first capacitor C1, and the drain of the thirtieth field effect transistor M64 are connected to the voltage-current conversion circuit 22; the negative input terminal of the first comparator A4 is connected to the stacked field effect transistor circuit 21;
[0091] The output terminal of the first comparator A4 is connected to the input terminal of the first inverter module INV4; the input terminal of the first delay unit D4 and the first input terminal of the first latch SR1 are connected to the output terminal of the first inverter module INV4; the output terminal of the first delay unit D4 is connected to the second input terminal of the first latch SR1; the first output terminal of the first latch SR1 is connected to the input terminal of the edge detector SCK1; the output terminal of the edge detector SCK1 is connected to the frequency-digital conversion unit 3;
[0092] The second output terminal of the first latch SR1 is connected to the gate of the thirtieth field effect transistor M64; the source of the thirtieth field effect transistor M64 and the other end of the first capacitor C1 are connected.
[0093] Further, in the embodiment of the present application, the current-frequency conversion unit 1 further includes a third frequency reading unit; the third frequency reading unit includes a second capacitor, a thirty-first field effect transistor, a second comparator, a second inverter module, a second delay unit, and a second latch; the positive input terminal of the second comparator, one end of the second capacitor, and the drain of the thirty-first field effect transistor are connected to the voltage-current conversion circuit 22; the negative input terminal of the second comparator is connected to the stacked field effect transistor circuit 21; the output terminal of the second comparator is connected to the input terminal of the second inverter module; the input terminal of the second delay unit and the first input terminal of the second latch are connected to the output terminal of the second inverter module; the output terminal of the second delay unit is connected to the second input terminal of the second latch; the first output terminal of the second latch is connected to the frequency-digital conversion unit 3; the second output terminal of the second latch is connected to the gate of the thirty-first field effect transistor; the source of the thirty-first field effect transistor and the other end of the second capacitor are connected.
[0094] It can be understood that the structure of the third frequency reading unit differs from that of the first frequency reading unit and the second frequency reading unit by an edge detector.
[0095] Further, in the embodiment of the present application, referring to Figure 8 , the frequency-digital conversion unit 3 includes a first AND gate A 1 , a second AND gate A 2 , a third AND gate A 3 , a first inverter INV, a first counter D 1 , a second counter D 2 , and a third counter D 3 ;
[0096] The first input terminal of the first AND gate A 1 , the first input terminal of the second AND gate A 2 , and the first input terminal of the third AND gate A 3 are connected to the output terminal of the first inverter INV;
[0097] The second input terminal of the first AND gate A 1 , the second input terminal of the second AND gate A 2 , and the second input terminal of the third AND gate A 3 are connected to the current-frequency conversion unit 1;
[0098] The output terminal of the first AND gate A 1 is connected to the first input terminal of the first counter D 1 ; the output terminal of the second AND gate A 2 is connected to the first input terminal of the second counter D 2 ; the output terminal of the third AND gate A 3 is connected to the first input terminal of the third counter D 3 ;
[0099] The first counter D 1 The second input terminal of, the second counter D 2 The second input terminal of, the third counter D 3 The second input terminals are connected to the start signal;
[0100] The first counter D 1 The output terminal of is connected to the input terminal of the first inverter INV; The output terminal of the second counter D 2 The output terminal of and the output terminal of the third counter D 3 The output signal after subtraction operation is used as the output signal of the frequency - digital conversion unit 3.
[0101] The following combines the accompanying drawings to illustrate the specific implementation principle of this application:
[0102] The current generated by the all - CMOS bias circuit is used to bias the temperature - sensing element BJT, so that the base - emitter voltage (V BE ) exhibits a good linearity to reduce the error of the system.
[0103] The double - clamping circuit makes the voltage at one end of the resistor not GND but have a voltage value. Doing so will achieve that the relative magnitude range of the current remains unchanged, but the ratio between the maximum value and the minimum value effectively increases, thus effectively improving the resolution of the temperature sensor. And in order to reduce the power consumption of this structure, the value of the resistor is crucial. This circuit can also reduce the resistor value required to reduce power consumption and reduce the circuit area. The relevant formula is as follows:
[0104]
[0105] In the formula, V T is the thermal voltage drop, I B is the base current, I S is the saturation current, V BE is the temperature - sensing voltage with negative temperature coefficient, V ref is the lower clamping voltage.
[0106] The bandgap reference itself can generate ΔV BE by clamping through the V BE of different numbers of BJTs. ΔV BE exhibits a positive temperature coefficient characteristic. However, the positive temperature - coefficient temperature - sensing current generated by the bandgap reference itself has too low sensitivity, which will make the resolution of the system not good enough. The use of the current subtractor avoids increasing the current sensitivity by increasing the number m of BJTs at one end, thus avoiding the problems of too high power consumption and too large area. Using a current mirror to mirror, subtract the current generated by the bandgap reference from the above I CTAT to obtain a high - sensitivity positive temperature - coefficient current. The formula is as follows:
[0107]
[0108] I PTAT I = F * I P - K * E * I CTAT
[0109] Wherein, I P is the current generated by the bandgap reference, k is the Boltzmann constant, T is the absolute temperature, and q is the electron migration rate. I PTAT is I P and I CTAT after subtraction, and F, K, and E are the mirror ratios of the current mirror.
[0110] The relevant important node voltages of the current - frequency converter have been given in Figure 3 . Using a latch to limit the discharge time of the capacitor to the delay time of the delay unit, which is the reset signal. This time is very small, making the clock period of V 2 almost determined by the charging time of the capacitor. The output frequency formula is as follows:
[0111]
[0112] Wherein, t charge is the capacitor charging time, t delay is the delay time, and C is the capacitance value. The first term of the formula is the ideal term, and the second term is the error term. t dclay << t charge , so the second term can be almost ignored.
[0113] To further reduce the influence of t delay , the use of an edge detector enables capturing two edge signals when a clock signal of V 2 is input, thereby outputting two pulses. The time error of one clock is averaged into the two outputs, and the system resolution is improved.
[0114] In the frequency - digital converter, STR is the start signal. When the high level comes, the converter starts to work. A 4 - bit counter inputs a reference frequency, and its output is used to control the operation of the entire temperature sensor. When the 4 - bit counter counts to 11, it outputs a DONE signal to stop the operation of the other two 12 - bit counters, thus completing the conversion. The other two 12 - bit counters respectively input f CTAT and f PTAT , and the output digital codes are subtracted to further reduce the time error in the current - frequency converter and improve the system resolution. The formula for the output digital code is as follows:
[0115] DCTAT = T cv * f CTAT
[0116] D PTAT = T cv * f PTAT
[0117] T cv = a * f STATIC
[0118]
[0119] Wherein, D CTAT and D PTAT are digital codes output by two 12-bit counters, T cv is the conversion time controlled by a 4-bit counter, a is a preset count value, f STATIC is the input reference frequency. Among them, since the error term D error is very small relative to the previous term, it can be almost ignored, and the output digital code can be approximated as:
[0120]
[0121] Wherein, A and B are the derivatives of the currents I comb and I CTAT , and B is a negative value, which is expressed as a constant term according to the above. Therefore, the output digital code is uniquely represented by the temperature.
[0122] Finally, a power consumption of 1.12 μW, an inaccuracy of +0.62 / -0.78 °C, a resolution of 40 mk, a conversion energy consumption of 2.46 nJ, and a resolution quality factor of 3.9 pJ.K are achieved in the temperature range of -60 to 110 °C and a conversion time of 2.2 ms. 2 Resolution quality factor.
[0123] In the above description of this specification, the descriptions with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0124] Although embodiments of the present application have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present application. The scope of the present application is defined by the claims and their equivalents.
[0125] The above has specifically described the preferred embodiments of the present application, but the present application is not limited to the described embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present application, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present application.
Claims
1. A temperature sensor, characterized in that: include: A temperature-current conversion unit, a current-frequency conversion unit and a frequency-digital conversion unit; the current-frequency conversion unit is connected to the temperature-current conversion unit; the current-frequency conversion unit is connected to the frequency-digital conversion unit; The temperature-current conversion unit includes a stacked field effect transistor circuit, a voltage-current conversion circuit, a bias circuit, a double clamp circuit, a bandgap reference circuit and a current subtractor circuit; the voltage-current conversion circuit and the double clamp circuit are connected to the stacked field effect transistor circuit; the bias circuit and the current subtractor circuit are connected to the double clamp circuit; the bandgap reference circuit is connected to the current subtractor circuit.
2. A temperature sensor according to claim 1, characterized in that: The stacked field effect tube circuit includes a plurality of field effect tubes connected in series; any one of the field effect tubes is used to generate a reference voltage.
3. A temperature sensor according to claim 1, characterized in that: The voltage-current conversion circuit includes a first amplifier, a second amplifier, a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor and a first resistor; The inverting input terminal of the first amplifier is connected to the stacked field effect tube circuit; the non-inverting input terminal of the first amplifier and the drain of the second field effect tube are connected to one end of the first resistor; The output end of the first amplifier is connected to the gate of the second field effect transistor; The gate of the first field effect tube, the drain of the first field effect tube and the source of the second field effect tube are connected to the gate of the fifth field effect tube; the source of the first field effect tube is connected to the first power supply; the drain of the fifth field effect tube is connected to the current-frequency conversion unit; The inverting input terminal of the second amplifier is connected to the stacked field effect tube circuit; the non-inverting input terminal of the second amplifier and the drain of the third field effect tube are connected to the other end of the first resistor; The output end of the second amplifier is connected to the gate of the third field effect transistor; The source of the third field effect tube, the drain of the fourth field effect tube and the gate of the fourth field effect tube are connected; the source of the fourth field effect tube is grounded.
4. A temperature sensor according to claim 1, characterized in that: The bias circuit includes a first triode, a sixth field effect transistor, a seventh field effect transistor, an eighth field effect transistor, a ninth field effect transistor, a tenth field effect transistor, an eleventh field effect transistor, a twelfth field effect transistor and a thirteenth field effect transistor; The source of the sixth field effect transistor, the source of the seventh field effect transistor, and the source of the eighth field effect transistor are connected to the first power supply; The gate of the sixth field effect transistor, the gate of the seventh field effect transistor, the gate of the eighth field effect transistor and the drain of the seventh field effect transistor are connected to the drain of the tenth field effect transistor; The drain of the sixth field effect transistor, the drain of the ninth field effect transistor, the gate of the ninth field effect transistor and the gate of the twelfth field effect transistor are connected to the gate of the thirteenth field effect transistor; The source of the tenth field effect transistor and the source of the ninth field effect transistor are connected to the drain of the twelfth field effect transistor; The source of the eleventh field effect transistor and the source of the twelfth field effect transistor are connected to the drain of the thirteenth field effect transistor; the source of the thirteenth field effect transistor is grounded; The drain of the eighth field effect transistor, the drain of the eleventh field effect transistor, and the gate of the eleventh field effect transistor are connected to the gate of the tenth field effect transistor; The drain of the sixth field effect transistor and the emitter of the first transistor are connected to the double clamp circuit; The collector of the first transistor and the base of the first transistor are both grounded.
5. A temperature sensor according to claim 1, characterized in that: The double clamp circuit includes a third amplifier, a fourth amplifier, a fourteenth field effect transistor, a fifteenth field effect transistor, a sixteenth field effect transistor, a seventeenth field effect transistor and a second resistor; The inverting input terminal of the third amplifier is connected to the bias circuit, and the non-inverting input terminal of the third amplifier and the drain of the sixteenth field effect transistor are connected to one end of the second resistor. The output end of the third amplifier is connected to the gate of the sixteenth field effect transistor; The gate of the fifteenth field effect transistor, the drain of the fifteenth field effect transistor and the source of the sixteenth field effect transistor are connected to the gate of the fourteenth field effect transistor; the source of the fifteenth field effect transistor is connected to the first power supply; the drain of the fourteenth field effect transistor is connected to the current-frequency conversion unit; The inverting input terminal of the fourth amplifier is connected to the stacked field effect tube circuit; the non-inverting input terminal of the fourth amplifier and the drain of the seventeenth field effect tube are connected to the other end of the second resistor; The output end of the fourth amplifier is connected to the gate of the seventeenth field effect transistor; The source of the seventeenth field effect transistor is grounded.
6. A temperature sensor according to claim 1, characterized in that: The bandgap reference circuit includes a third resistor, an eighteenth field effect transistor, a nineteenth field effect transistor, a fifth amplifier, a second triode and a third triode; The source of the eighteenth field effect transistor and the source of the nineteenth field effect transistor are connected to the first power supply; The gate of the eighteenth field effect transistor and the gate of the nineteenth field effect transistor are connected to the output end of the fifth amplifier; the output end of the fifth amplifier is connected to the current subtractor circuit; The drain of the eighteenth field effect transistor and one end of the third resistor are connected to the non-inverting input end of the fifth amplifier; The drain of the nineteenth field effect transistor and the emitter of the second transistor are connected to the inverting input terminal of the fifth amplifier; The other end of the third resistor is connected to the source of the third transistor; The base of the third transistor, the collector of the third transistor, the base of the second transistor, and the collector of the second transistor are grounded.
7. A temperature sensor according to claim 1, characterized in that: The current subtractor circuit includes a 20th field effect transistor, a 21st field effect transistor, a 22nd field effect transistor, a 23rd field effect transistor, a 24th field effect transistor, a 25th field effect transistor, a 26th field effect transistor, a 27th field effect transistor, a 28th field effect transistor and a 29th field effect transistor; The source of the 20th field effect transistor, the source of the 21st field effect transistor, the source of the 25th field effect transistor, and the source of the 28th field effect transistor are connected to the first power supply; The gate of the 20th field effect transistor is connected to the double clamp circuit; the gate of the 21st field effect transistor is connected to the bandgap reference circuit; The drain of the 20th field effect transistor, the drain of the 22nd field effect transistor, the gate of the 22nd field effect transistor and the gate of the 23rd field effect transistor are connected; The source of the 22nd field effect transistor, the source of the 23rd field effect transistor, the source of the 24th field effect transistor and the source of the 27th field effect transistor are all grounded; The drain of the twenty-first field effect transistor, the drain of the twenty-third field effect transistor, the drain of the twenty-fourth field effect transistor, and the gate of the twenty-fourth field effect transistor are connected to the gate of the twenty-seventh field effect transistor; The drain of the twenty-fifth field effect transistor, the gate of the twenty-fifth field effect transistor, and the source of the twenty-sixth field effect transistor are connected to the gate of the twenty-eighth field effect transistor; The drain of the twenty-sixth field effect transistor, the gate of the twenty-sixth field effect transistor, and the drain of the twenty-seventh field effect transistor are connected to the gate of the twenty-ninth field effect transistor; The drain of the 28th field effect transistor is connected to the source of the 29th field effect transistor; the drain of the 29th field effect transistor is connected to the current-frequency conversion unit.
8. A temperature sensor according to claim 1, characterized in that: The current-frequency conversion unit includes a first frequency readout unit and a second frequency readout unit; wherein the first frequency readout unit and the second frequency readout unit have the same structure, and the first frequency readout unit or the second frequency readout unit includes a first capacitor, a thirtieth field effect transistor, a first comparator, a first inverter module, a first delay unit, a first latch and an edge detector; The non-inverting input terminal of the first comparator, one end of the first capacitor and the drain of the thirtieth field effect transistor are connected to the voltage-current conversion circuit; the inverting input terminal of the first comparator is connected to the stacked field effect transistor circuit; The output end of the first comparator is connected to the input end of the first inverter module; the input end of the first delay unit and the first input end of the first latch are connected to the output end of the first inverter module; the output end of the first delay unit is connected to the second input end of the first latch; the first output end of the first latch is connected to the input end of the edge detector; the output end of the edge detector is connected to the frequency-to-digital conversion unit; The second output end of the first latch is connected to the gate of the thirtieth field effect transistor; the source of the thirtieth field effect transistor and the other end of the first capacitor are connected.
9. A temperature sensor according to claim 8, characterized in that: The current-frequency conversion unit further includes a third frequency readout unit; the third frequency readout unit includes a second capacitor, a thirty-first field effect transistor, a second comparator, a second inverter module, a second delay unit and a second latch; The non-inverting input terminal of the second comparator, one end of the second capacitor and the drain of the thirty-first field effect transistor are connected to the voltage-current conversion circuit; the inverting input terminal of the second comparator is connected to the stacked field effect transistor circuit; The output end of the second comparator is connected to the input end of the second inverter module; the input end of the second delay unit and the first input end of the second latch are connected to the output end of the second inverter module; the output end of the second delay unit is connected to the second input end of the second latch; the first output end of the second latch is connected to the frequency-to-digital conversion unit; The second output end of the second latch is connected to the gate of the thirty-first field effect transistor; the source of the thirty-first field effect transistor and the other end of the second capacitor are connected.
10. A temperature sensor according to claim 1, characterized in that: The frequency-to-digital conversion unit includes a first AND gate, a second AND gate, a third AND gate, a first inverter, a first counter, a second counter and a third counter; The first input terminal of the first AND gate, the first input terminal of the second AND gate, and the first input terminal of the third AND gate are connected to the output terminal of the first inverter; The second input terminal of the first AND gate, the second input terminal of the second AND gate, and the second input terminal of the third AND gate are connected to the current-frequency conversion unit; The output end of the first AND gate is connected to the first input end of the first counter; the output end of the second AND gate is connected to the first input end of the second counter; the output end of the third AND gate is connected to the first input end of the third counter; The second input end of the first counter, the second input end of the second counter, and the second input end of the third counter are connected to the start signal; The output end of the first counter is connected to the input end of the first inverter; the output signal of the output end of the second counter and the output end of the third counter after subtraction operation is used as the output signal of the frequency-to-digital conversion unit.