Probe card

Abstract

The invention provides a probe card which is used for testing the electrical property of an object to be tested. The probe card comprises an adapter plate, a guide plate, a plurality of probes, at least one capacitor and a conductive layer. The adapter plate comprises at least one power supply connecting pad and at least one grounding connecting pad. The guide plate is arranged between the adapter plate and the to-be-tested object. The probe penetrates through the guide plate and is electrically connected to the adapter plate. The probes comprise at least one power supply probe and at least one grounding probe. The power probe is electrically connected to the power pad, and the ground probe is electrically connected to the ground pad. The capacitor is located on at least a portion of the power probe. The conductive layer connects the guide plate. The capacitor connects the power probe and the grounding probe in series through the conductive layer to form a current loop. According to the probe card, the integrity of a test signal can be improved.

Description

Technical Field

[0001] The present invention relates to a test device, and more particularly to a probe card. Background Art

[0002] Generally, when a probe card is used for testing, a test machine provides voltage / current to the device under test (DUT). When the current extraction speed of an integrated circuit (IC) is too fast or too large, it will cause an instantaneous voltage drop (AC Voltage Drop) of the power supply easily. At this time, the machine end will provide a compensation current. Due to the large parasitic inductance between the machine end and the device under test, the compensation current cannot reach the device under test in time. Therefore, a de-coupling capacitor is usually placed close to the device under test, such as on a backplane or a printed circuit board. However, this will cause difficulties in the wiring design of the probe card, and the inductance of the probe path can only be improved by selecting short needles. Therefore, how to reduce the parasitic effect of the probe between the device under test and the path of the de-coupling capacitor is the main topic for improving power integrity (PI) at the present stage. Summary of the Invention

[0003] The present invention is directed to a probe card that can improve the integrity of test signals.

[0004] According to an embodiment of the present invention, a probe card is used to test the electrical properties of a device under test. The probe card includes a backplane, a guide plate, a plurality of probes, at least one capacitor, and a conductive layer. The backplane includes at least one power supply pad and at least one ground pad. The guide plate is disposed between the backplane and the device under test. The probes penetrate the guide plate and are electrically connected to the backplane. The probes include at least one power supply probe and at least one ground probe. At least one power supply probe is electrically connected to at least one power supply pad. At least one ground probe is electrically connected to at least one ground pad. At least one capacitor is located on at least a part of at least one power supply probe. At least one power supply probe, a dielectric layer, and a metal layer define at least one capacitor. The conductive layer is connected to the guide plate, and at least one capacitor forms a current loop by connecting at least one power supply probe and at least one ground probe in series through the conductive layer.

[0005] In a probe card according to an embodiment of the present invention, the probe card further includes a dielectric layer and at least one metal layer. The dielectric layer is located on at least a part of at least one power probe. At least one metal layer is disposed on the dielectric layer. When the at least one metal layer is a metal layer, the dielectric layer and the metal layer are sequentially stacked on at least a part of at least one power probe, and at least a part of at least one power probe, the dielectric layer, and the metal layer define at least one capacitor. Or, when the at least one metal layer is two metal layers, the dielectric layer is located between the two metal layers, and the two metal layers and the dielectric layer define at least one capacitor.

[0006] In a probe card according to an embodiment of the present invention, the above-mentioned guide plate includes a first guide plate portion and a second guide plate portion. The first guide plate portion and the second guide plate portion are arranged at intervals to form a hollow ring shape. The second guide plate portion is located between the first guide plate portion and the object to be measured. At least one power probe includes at least one fixed end and at least one detection end. At least one fixed end is connected to at least one power pad, and at least one detection end is used to contact the object to be measured.

[0007] In a probe card according to an embodiment of the present invention, the above-mentioned conductive layer is disposed on the outer surface of the first guide plate portion relatively close to the adapter board, and at least one capacitor penetrates the first guide plate portion and is adjacent to at least one fixed end.

[0008] In a probe card according to an embodiment of the present invention, the above-mentioned conductive layer is disposed on the outer surface of the second guide plate portion relatively far from the adapter board, and at least one capacitor penetrates the second guide plate portion and is adjacent to at least one detection end.

[0009] In a probe card according to an embodiment of the present invention, the probe card further includes another conductive layer. The conductive layer is connected inside the first guide plate portion, and the other conductive layer is connected inside the second guide plate portion, and at least one capacitor penetrates the other conductive layer.

[0010] In a probe card according to an embodiment of the present invention, the above-mentioned at least one capacitor includes at least one first capacitor and at least one second capacitor. At least one first capacitor penetrates the conductive layer, and at least one second capacitor penetrates the other conductive layer.

[0011] In a probe card according to an embodiment of the present invention, the above-mentioned at least one first capacitor further penetrates the first guide plate portion and extends adjacent to at least one power pad.

[0012] In a probe card according to an embodiment of the present invention, the above-mentioned second guide plate portion has at least one first opening. The conductive layer is disposed on an outer surface of the second guide plate portion relatively far from the adapter board and extends into at least one first opening. At least one capacitor is located in at least one first opening and is arranged at intervals with the conductive layer.

[0013] In the probe card according to an embodiment of the present invention, the probe card further includes another conductive layer. The guide plate further includes a third guide plate portion. The third guide plate portion has at least one second opening. At least one second opening is arranged corresponding to at least one first opening. The diameter of at least one second opening is larger than that of at least one first opening. The another conductive layer is disposed on the surface of the third guide plate portion relatively far from the adapter board and extends into at least one second opening. At least one capacitor also extends into at least one second opening and is arranged at intervals with the another conductive layer.

[0014] In the probe card according to an embodiment of the present invention, the probe card further includes an insulating layer disposed on a part of each probe.

[0015] Based on the above, in the present invention, the capacitor on the power probe forms a current loop by connecting the conductive layer of the guide plate in series with the power probe and the ground probe, and the capacitor can supply power instantaneously during the test process of the probe card. Compared with the prior art in which the decoupling capacitor is placed on the adapter board or the printed circuit board, the probe card design of the present invention can greatly shorten the distance between the power supply and the device under test, not only can supply power instantaneously, but also can reduce the parasitic inductance, so that the high test voltage (VIH) can be effectively identified, the test signal ambiguity can be avoided, and the test signal integrity can be improved. Description of the Drawings

[0016] Figure 1 is a schematic diagram of a probe card according to an embodiment of the present invention;

[0017] Figure 2 is a schematic diagram of a probe card according to another embodiment of the present invention;

[0018] Figure 3 is a schematic diagram of a probe card according to another embodiment of the present invention;

[0019] Figure 4 is a schematic diagram of a probe card according to another embodiment of the present invention;

[0020] Figure 5 is a schematic diagram of a probe card according to another embodiment of the present invention;

[0021] Figure 6 is a schematic diagram of a probe card according to another embodiment of the present invention;

[0022] Figure 7A is a schematic diagram of a probe card according to another embodiment of the present invention;

[0023] Figure 7B is Figure 7A a top view schematic diagram of;

[0024] Figure 8ASchematic diagram of a probe card according to another embodiment of the present invention;

[0025] Figure 8B is Figure 8A top view schematic diagram.

[0026] Description of reference numerals

[0027] 10: Object to be measured;

[0028] 100a, 100b, 100c, 100d, 100e, 100f, 100g, 100h: Probe card;

[0029] 110: Adapter board;

[0030] 112: Power supply pad;

[0031] 114: Ground pad;

[0032] 116: Signal pad;

[0033] 120a, 120g, 120h: Guide plate;

[0034] 122, 122g, 122h: First guide plate part;

[0035] 121, 125: Outer surface;

[0036] 124, 124g, 124h: Second guide plate part;

[0037] 126h: Third guide plate part;

[0038] 127g, 127h, 128h, 129g, 129h: Opening;

[0039] 130a, 130b, 130c, 130d, 130e, 130f, 130g, 130h: Probe;

[0040] 131b: Groove;

[0041] 132a, 132b, 132c, 132d, 132e, 132f, 132g, 132h: Power supply probe;

[0042] 133a: Fixed end;

[0043] 134: Ground probe;

[0044] 135a, 135c: Detection end;

[0045] 134: Signal probe;

[0046] 140, 140g, 140h1, 140h2: Dielectric layer;

[0047] 150, 150g, 150h1, 150h2: Metal layers;

[0048] 160a, 160c, 160d, 160e, 160f, 160g, 160h: Conductive layers;

[0049] 170: Insulating layer;

[0050] 180d, 180e, 180f, 180h: Another conductive layer;

[0051] C1, C2, C3, C4, C51, C52, C61, C62, C7, C8: Capacitors;

[0052] S: Surface. Detailed implementation manners

[0053] Now, reference will be made in detail to the exemplary embodiments of the present invention, and examples of the exemplary embodiments are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to represent the same or similar parts.

[0054] The present invention can be understood by referring to the following detailed description and in conjunction with the accompanying drawings. It should be noted that, for the convenience of the reader's understanding and for the simplicity of the drawings, the elements in the drawings are not drawn to actual scale. In addition, the number and size of each element in the drawings are only for illustration and are not used to limit the scope of the present invention.

[0055] Figure 1 is a schematic diagram of a probe card according to an embodiment of the present invention. Please first refer to Figure 1 , in this embodiment, the probe card 100a is used to test the electrical properties of the device under test 10. The probe card 100a includes an adapter board 110, a guide board 120a, a plurality of probes 130a, at least one capacitor (a plurality of capacitors C1 are schematically shown), and a conductive layer 160a. The adapter board 110 includes at least one power supply pad (a plurality of power supply pads 112 are schematically shown) and at least one ground pad (a plurality of ground pads 114 are schematically shown). The guide board 120a is disposed between the adapter board 110 and the device under test 10. The probes 130a penetrate through the guide board 120a and are electrically connected to the adapter board 110. The probes 130a include at least one power supply probe (a plurality of power supply probes 132a are schematically shown) and at least one ground probe (a plurality of ground probes 134 are schematically shown). The power supply probes 132a are respectively electrically connected to the power supply pads 112. The ground probes 134 are respectively electrically connected to the ground pads 114. Each capacitor C1 is located on at least a part of each power supply probe 132a. The conductive layer 160a is connected to the guide board 120a to connect the power supply probes 132a and the ground probes 134 in series to form a current loop.

[0056] More specifically, in the present embodiment, the guide plate 120a includes a first guide plate portion 122 and a second guide plate portion 124. The shapes of the first guide plate portion 122 and the second guide plate portion 124 are both U-shaped and the two are in a mirror pattern, wherein the first guide plate portion 122 and the second guide plate portion 124 are arranged at intervals to form a hollow ring. The second guide plate portion 124 is located between the first guide plate portion 122 and the object under test 10. In one embodiment, the guide plate 120a is, for example, a ceramic guide plate, but is not limited thereto.

[0057] Each power supply probe 132a of the present embodiment includes a fixed end 133a and a detection end 135a. The fixed end 133a is connected to the power supply pad 112, and the detection end 135a is used to contact the object under test 10. Furthermore, in the present embodiment, the probe card 100a further includes a dielectric layer 140 and at least one metal layer (one metal layer 150 is schematically shown). The dielectric layer 140 is disposed on at least a part of each power supply probe 132a, and the metal layer 150 is disposed on the dielectric layer 140. That is to say, the dielectric layer 140 and the metal layer 150 are sequentially stacked on at least a part of each power supply probe 132a. Herein, at least a part of each power supply probe 132a, the dielectric layer 140, and the metal layer 150 define a capacitor C1, and this capacitor C1 is embodied as a parallel plate capacitor. In one embodiment, the dielectric layer 140 is, for example, made of a material with a high dielectric constant (high Dk) and is formed on at least a part of each power supply probe 132a by a deposition method, but is not limited thereto. The metal layer 150 is, for example, formed on the dielectric layer 140 by a deposition method, but is not limited thereto.

[0058] Please refer again to Figure 1 , in the present embodiment, the conductive layer 160a is specifically disposed on the outer surface 121 of the first guide plate portion 122 relatively close to the adapter plate 110, and the capacitor C1 penetrates the first guide plate portion 122 and the conductive layer 160a and is adjacent to the fixed end 133a. In addition, the probe card 100a of the present embodiment further includes an insulating layer 170 disposed on a part of each probe 130a.

[0059] In short, in the present embodiment, the capacitor C1 on the power supply probe 132a forms a current loop by connecting the conductive layer 160a of the guide plate 120a in series with the power supply probe 132a and the ground probe 134, wherein the capacitor C1 can supply power instantaneously during the test process of the probe card 100a. Compared with the prior art in which the decoupling capacitor is placed on the adapter plate or the printed circuit board, the design of the probe card 100a in the present embodiment can greatly shorten the distance between the power supply and the object under test 10, not only can supply power instantaneously, but also can reduce the parasitic inductance, enable the effective identification of the test high voltage (VIH), avoid misjudgment caused by fuzzy test signals, and improve the integrity of the test signals.

[0060] It should be noted here that in the following embodiments, the component numbers and some content of the foregoing embodiments are adopted, where the same numbers are used to represent the same or similar components, and the description of the same technical content is omitted. For the description of the omitted parts, reference can be made to the foregoing embodiments, and the following embodiments will not be repeated.

[0061] Figure 2 It is a schematic diagram of a probe card according to another embodiment of the present invention. Please also refer to Figure 1 and Figure 2 , the probe card 100b of this embodiment is similar to the Figure 1 probe card 100a. The difference between the two is that in this embodiment, each power probe 132b of the probe 130b has a groove 131b, and the dielectric layer 140 and the metal layer 150 disposed on the dielectric layer 140 are both located within the groove 131b. At least a part of each power probe 132b, the dielectric layer 140, and the metal layer 150 define a capacitor C2. Here, the groove 131b can be formed on the power probe 132b by means of microelectromechanical technology, laser engraving technology, etching method, etc., but not limited thereto.

[0062] It should be noted that in another embodiment not shown, the metal layer can be two metal layers, the dielectric layer is located between the two metal layers, and the two metal layers and the dielectric layer define a capacitor located on the power probe, which still belongs to the scope of protection of the present invention.

[0063] Figure 3 It is a schematic diagram of a probe card according to another embodiment of the present invention. Please also refer to Figure 1 and Figure 3 , the probe card 100c of this embodiment is similar to the Figure 1 probe card 100a. The difference between the two is that in this embodiment, the conductive layer 160c is disposed on the outer surface 125 of the second guide plate portion 124 relatively far from the adapter plate 110, and at least a part of each power probe 132c of the probe 130c, the dielectric layer 140, and the capacitor C3 defined by the metal layer 150 penetrate through the second guide plate portion 124 and the conductive layer 160c and are adjacent to the detection end 135c. The setting of this capacitor C3 can be greatly close to the object under test 10, can reduce the inductance, and improve the test signal integrity and test quality of the probe card 100c.

[0064] Figure 4 It is a schematic diagram of a probe card according to another embodiment of the present invention. Please also refer to Figure 1 and Figure 4 , the probe card 100d of this embodiment is similar to the Figure 1Similar to the probe card 100a, the difference between the two is that: in this embodiment, the probe card 100d further includes another conductive layer 180d. The conductive layer 160d is connected within the first guide portion 122, while the other conductive layer 180d is connected within the second guide portion 124. At least a portion of each power probe 132d of the probe 130d, the dielectric layer 140, and the metal layer 150 define a capacitor C4 that penetrates through the other conductive layer 180d. The setting of this capacitor C4 can be significantly closer to the device under test 10, reducing the inductance to improve the test signal integrity and test quality of the probe card 100d.

[0065] Figure 5 is a schematic diagram of a probe card according to another embodiment of the present invention. Please also refer to Figure 4 and Figure 5 , the probe card 100e of this embodiment is similar to Figure 4 the probe card 100d, and the difference between the two is that: in this embodiment, at least a portion of each power probe 132e of the probe 130e, the dielectric layer 140, and the metal layer 150 can define at least one first capacitor (schematically showing a first capacitor C51) and at least one second capacitor (schematically showing a second capacitor C52). The first capacitor C51 penetrates through the conductive layer 160e, while the second capacitor C52 penetrates through the other conductive layer 180e. The setting of this second capacitor C52 can be significantly closer to the device under test 10, reducing the inductance to improve the test signal integrity and test quality of the probe card 100e, and the setting of the first capacitor C51 can increase the capacitance value.

[0066] Figure 6 is a schematic diagram of a probe card according to another embodiment of the present invention. Please also refer to Figure 4 and Figure 6 , the probe card 100f of this embodiment is similar to Figure 4 the probe card 100d, and the difference between the two is that: in this embodiment, at least a portion of each power probe 132f of the probe 130f, the dielectric layer 140, and the metal layer 150 can define at least one first capacitor (schematically showing a first capacitor C61) and at least one second capacitor (schematically showing a second capacitor C62). The first capacitor C61 penetrates through the conductive layer 160f and the first guide portion 122 and extends adjacent to the power pad 112, while the second capacitor C62 penetrates through the other conductive layer 180f. The setting of this second capacitor C62 can be significantly closer to the device under test 10, reducing the inductance to improve the test signal integrity and test quality of the probe card 100f, and the setting of the first capacitor C61 can increase the capacitance value.

[0067] Figure 7A is a schematic diagram of a probe card according to another embodiment of the present invention. Figure 7B is Figure 7ATop view schematic diagram. Please also refer to Figure 1 and Figure 7A The probe card 100g of this embodiment is similar to the probe card 100a of Figure 1 . The difference between the two is that in this embodiment, the first guide plate portion 122g of the guide plate 120g has at least one opening (a plurality of openings 127g are schematically shown), and the second guide plate portion 124g has at least one opening (a plurality of openings 129g, i.e., the first opening, are schematically shown). The probe 130g further includes a signal probe 136 connected to the signal pad 116 of the adapter board 110. The power probe 132g, the ground probe 134, and the signal probe 136 of the probe 130g all pass through the opening 127g and the opening 129g. The conductive layer 160g is disposed on the outer surface 125 of the second guide plate portion 124g relatively far from the adapter board 110 and extends into the opening 129g. At least a part of each power probe 132g of the probe 130g, the dielectric layer 140g, and the capacitance C7 defined by the metal layer 150g are located in the opening 129g and are arranged at intervals with the conductive layer 160g. As Figure 7B shown, the dielectric layer 140g of this embodiment surrounds the periphery of the power probe 132g, and the metal layer 150g surrounds the periphery of the dielectric layer 140g, wherein both the dielectric layer 140g and the metal layer 150g are arranged in a ring shape. In short, in this embodiment, the position of the conductive layer 160g is directly defined on the guide plate 120g by techniques such as lithography or Chemical Vapor Deposition (CVD). The conductive layer 160g on the guide plate 120g is used to connect the capacitive probe (i.e., the power probe 132g) and the non-capacitive probe (i.e., the ground probe 134) in series. The setting of this capacitance C7 can be greatly close to the object under test 10, reduce the inductance, and improve the test signal integrity and test quality of the probe card 100g.

[0068] Figure 8A is a schematic diagram of a probe card according to another embodiment of the present invention. Figure 8B is Figure 8A Top view schematic diagram. Please also refer to Figure 1 and Figure 8A The probe card 100h of this embodiment is similar to the probe card of Figure 1is similar to the probe card 100a. The difference between the two is that in this embodiment, the probe card 100h further includes another conductive layer 180h, and the guide plate 120h further includes a third guide plate portion 126h. Specifically, the first guide plate portion 122h of the guide plate 120h has at least one opening (a plurality of openings 127h are schematically shown), the second guide plate portion 124h has at least one opening (a plurality of openings 129h, i.e., the first opening, are schematically shown), and the third guide plate portion 126h has at least one opening (a plurality of openings 128h, i.e., the second opening, are schematically shown). The probe 130h further includes a signal probe 136 connected to the signal pad 116 of the adapter board 110. The power probe 132h, the ground probe 134, and the signal probe 136 of the probe 130h all pass through the opening 127h, the opening 128h, and the opening 129h. Herein, the opening 127h, the opening 128h, and the opening 129h are arranged corresponding to each other, and the diameter of the opening 128h is larger than that of the opening 129h. The conductive layer 160h is disposed on the outer surface 125 of the second guide plate portion 124h relatively far from the adapter board 110 and extends into the opening 129h. Another conductive layer 180h is disposed on the surface S of the third guide plate portion 126h relatively far from the adapter board 110 and extends into the opening 128h. At least a part of each power probe 132h of the probe 130h, the dielectric layer 140h1, and the metal layer 150h1 are located in the opening 129h and the opening 128h, and the dielectric layer 140h2 and the metal layer 150h2 are disposed on the metal layer 150h1 located in the opening 128h. Wherein, at least a part of each power probe 132h, the dielectric layer 140h1, the metal layer 150h1, the dielectric layer 140h2, and the metal layer 150h2 define a double-layer capacitance C8, and this capacitance C8 is arranged at intervals with the conductive layer 160h and another conductive layer 180h. As Figure 8B shown, in this embodiment, the dielectric layer 140h1 surrounds the periphery of the power probe 132h, the metal layer 150h1 surrounds the periphery of the dielectric layer 140h1, the dielectric layer 140h2 surrounds the periphery of the metal layer 150h1, and the metal layer 150h2 surrounds the periphery of the dielectric layer 140h2. Herein, the dielectric layer 140h1, the metal layer 150h1, the dielectric layer 140h2, and the metal layer 150h2 are all arranged in a ring shape.

[0069] Briefly speaking, in this embodiment, the positions of the conductive layer 160h and another conductive layer 180h are directly defined on the guide plate 120h through techniques such as lithography or Chemical Vapor Deposition (CVD). A capacitive probe (i.e., the power supply probe 132h) and a non-capacitive probe (i.e., the ground probe 134) are connected in series through the conductive layer 160h and another conductive layer 180h on the guide plate 120h. The setting of this capacitor C8 can be greatly close to the object under test 10, reducing the inductance to improve the test signal integrity and test quality of the probe card 100h. In addition, the double-layer capacitor C8 structure setting can also increase the capacitance value.

[0070] In summary, in the present invention, the capacitor on the power supply probe forms a current loop by connecting the conductive layers of the guide plate in series with the power supply probe and the ground probe, where the capacitor can supply power instantaneously during the test process of the probe card. Compared with the prior art where the decoupling capacitor is placed on the adapter board or printed circuit board, the probe card design of the present invention can greatly shorten the distance between the power supply and the object under test, not only supply power instantaneously, but also reduce the parasitic inductance, enabling the effective identification of the high test voltage (VIH), avoiding misjudgment caused by fuzzy test signals, and improving the test signal integrity.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A probe card for testing the electrical properties of a device under test, characterized in that, the probe card comprises: a carrier board including at least one power pad and at least one ground pad; a guide plate disposed between the carrier board and the device under test; a plurality of probes passing through the guide plate and electrically connected to the carrier board, the plurality of probes including at least one power probe and at least one ground probe, the at least one power probe being electrically connected to the at least one power pad, and the at least one ground probe being electrically connected to the at least one ground pad; at least one capacitor located on at least a part of the at least one power probe; and a conductive layer connecting the guide plate, wherein the at least one capacitor forms a current loop by connecting the at least one power probe and the at least one ground probe in series through the conductive layer.

2. The probe card according to claim 1, characterized in that, it further comprises: a dielectric layer located on at least a part of the at least one power probe; and at least one metal layer disposed on the dielectric layer, wherein when the at least one metal layer is a single metal layer, the dielectric layer and the metal layer are stacked in sequence on at least a part of the at least one power probe, and at least a part of the at least one power probe, the dielectric layer and the metal layer define the at least one capacitor, or when the at least one metal layer is two metal layers, the dielectric layer is located between the two metal layers, and the two metal layers and the dielectric layer define the at least one capacitor.

3. The probe card according to claim 1, characterized in that, the guide plate includes a first guide plate portion and a second guide plate portion, the first guide plate portion and the second guide plate portion are arranged at intervals to form a hollow ring shape, the second guide plate portion is located between the first guide plate portion and the device under test, the at least one power probe includes at least one fixed end and at least one detection end, the at least one fixed end is connected to the at least one power pad, and the at least one detection end is used for contacting the device under test.

4. The probe card according to claim 3, characterized in that, the conductive layer is disposed on an outer surface of the first guide plate portion relatively close to the carrier board, and the at least one capacitor penetrates through the first guide plate portion and is adjacent to the at least one fixed end.

5. The probe card according to claim 3, characterized in that, the conductive layer is disposed on an outer surface of the second guide plate portion relatively far from the carrier board, and the at least one capacitor penetrates through the second guide plate portion and is adjacent to the at least one detection end.

6. The probe card according to claim 3, characterized in that, it further comprises: another conductive layer, the conductive layer is connected inside the first guide plate portion, and the another conductive layer is connected inside the second guide plate portion, and the at least one capacitor penetrates through the another conductive layer.

7. The probe card according to claim 6, characterized in that, the at least one capacitor includes at least one first capacitor and at least one second capacitor, the at least one first capacitor penetrates through the conductive layer, and the at least one second capacitor penetrates through the another conductive layer.

8. The probe card according to claim 7, characterized in that, The at least one first capacitor also passes through the first guide portion and extends adjacent to the at least one power pad.

9. The probe card according to claim 3, wherein, the second guide portion has at least one first opening, the conductive layer is disposed on an outer surface of the second guide portion relatively far from the adapter board and extends into the at least one first opening, and the at least one capacitor is located in the at least one first opening and is arranged at intervals with the conductive layer.

10. The probe card according to claim 9, wherein, further comprising: another conductive layer, the guide further includes a third guide portion, the third guide portion has at least one second opening, the at least one second opening is disposed corresponding to the at least one first opening, and a diameter of the at least one second opening is larger than a diameter of the at least one first opening, the another conductive layer is disposed on a surface of the third guide portion relatively far from the adapter board and extends into the at least one second opening, and the at least one capacitor further extends and is located in the at least one second opening and is arranged at intervals with the another conductive layer.

11. The probe card according to claim 1, wherein, further comprising: an insulating layer disposed on a part of each of the plurality of probes.

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