DFT test mode control circuit, method and chip

Abstract

The invention provides a DFT test mode control circuit and method and a chip, and relates to the technical field of integrated circuit testing, and the circuit comprises a time sequence verification module which accesses a test clock signal and is used for recording a rising edge count value and comparing the rising edge count value with a pre-designed value to obtain a time sequence comparison result; the signal verification module is connected with a test data signal and is used for recording an actual sampling value and comparing the actual sampling value with a preset sampling value to obtain a signal comparison result; the test control module outputs a preset logic level signal to control the circuit to be tested to enter a DFT test mode when the rising edge count value is equal to a pre-designed value and the actual sampling value is equal to a preset sampling value. According to the circuit, signal resources output by existing ports are utilized to form a multi-verification mechanism for triggering a test mode, the reliability of the to-be-tested circuit entering the test mode is improved, ports do not need to be independently arranged, the number of the ports is reduced, the chip cost is reduced, and DFT test can be carried out when a chip does not have all test ports.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and particularly to a DFT test mode control circuit, method, and chip. Background Art

[0002] In the field of integrated circuit design, DFT (Design for Testability) technology can effectively improve the testability of a chip by inserting specific logic structures, such as scan chains, boundary scans, etc. Thereby, potential problems in the chip can be detected at an early stage to improve product quality and reduce production costs. Considering that the core of DFT technology lies in inserting test logic structures into the chip, usually six key ports are required to ensure the realization of its functions, namely a test mode selection port, a test clock port, a test data input port, a test data output port, a test reset port, and a test enable port. Different ports are used to implement different functions, from switching working modes to transmitting test instructions or data, etc., which is crucial for ensuring the effective operation of the DFT circuit.

[0003] However, considering that in some chip designs, the number of ports is limited and it is impossible to allocate independent physical connections for all DFT - required ports, resulting in the inability to meet the DFT design. For example, some chips only have four ports, which will inevitably lead to the lack of some functional ports for DFT testing, and thus the DFT technology cannot be effectively applied for testing. Summary of the Invention

[0004] Aiming at the deficiencies of the above - mentioned existing technologies, the present invention provides a DFT test mode control circuit, method, and chip, which solve the technical problem that DFT testing cannot be performed when the number of chip ports is insufficient in the prior art.

[0005] In the first aspect of the present invention, a DFT test mode control circuit is provided, including a timing verification module, a signal verification module, and a test control module. Among them, the output ends of the timing verification module and the signal verification module are respectively connected to the input end of the test control module, and the output end of the test control module is connected to the circuit under test; The input end of the timing verification module is connected to a test clock signal, which is used to incrementally count the rising edge of the test clock signal, record the rising - edge count value, compare the rising - edge count value with a pre - designed value, obtain a timing comparison result, and output it to the test control module; The input end of the signal verification module is connected to a test data signal, which is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value, compare the actual sampling value with a preset sampling value, obtain a signal comparison result and output it to the test control module, where the value of the preset period is equal to the preset value; The test control module is configured to output a preset logic level signal to control the circuit under test to enter the DFT test mode when the timing comparison result indicates that the rising edge count value is equal to the preset value and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value.

[0006] Optionally, the timing verification module includes a rising edge counter and a first comparator, where the output end of the rising edge counter is connected to the input end of the first comparator, and the output end of the first comparator is connected to the input end of the test control module; the input end of the rising edge counter is connected to the test clock signal, which is used to incrementally count the rising edge of the test clock signal, record the rising edge count value and output it to the first comparator, where when the rising edge count value reaches the preset value, the rising edge count value stops incrementing and remains at the preset value; the first comparator compares the rising edge count value with the preset value, obtains a timing comparison result and outputs it to the test control module.

[0007] Optionally, the signal verification module includes a register unit and a comparator unit, where the output end of the register unit is connected to the input end of the comparator unit, and the output end of the comparator unit is connected to the input end of the test control module; the register unit is connected to the test data signal, which is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value and output it to the comparator unit; the comparator unit compares the actual sampling value with the preset value, obtains a signal comparison result and outputs it to the test control module.

[0008] Optionally, the test data signal includes a test data input signal and a test enable signal, the register unit includes a first register and a second register, and the comparator unit includes a second comparator and a third comparator. Among them, the output terminal of the first register is connected to the input terminal of the second comparator, the output terminal of the second register is connected to the input terminal of the third comparator, and the output terminals of the second comparator and the third comparator are respectively connected to the input terminal of the test control module; the input terminal of the first register accesses the test data input signal, and is used to sample the test data input signal at the rising edge of the test clock signal within a preset period, record the first sampled value and output it to the second comparator, and the second comparator compares the first sampled value with a first preset sampled value to obtain a first signal comparison result and output it to the test control module; the input terminal of the second register accesses the test enable signal, and is used to sample the test enable signal at the rising edge of the test clock signal within a preset period, record the second sampled value and output it to the third comparator, and the third comparator compares the second sampled value with a second preset sampled value to obtain a second signal comparison result and output it to the test control module; when the timing comparison result indicates that the rising edge count value is equal to the preset value, the first signal comparison result indicates that the first sampled value is equal to the first preset sampled value, and the second signal comparison result indicates that the second sampled value is equal to the second preset sampled value, the test control module outputs a high-level signal to control the circuit under test to enter the DFT test mode.

[0009] Optionally, the DFT test mode control circuit further includes a system reset module, and the system reset module is respectively connected to the timing verification module, the signal verification module, the test control module and the circuit under test; the system reset module is configured to generate a global reset signal in response to a system reset instruction to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit under test.

[0010] Optionally, the DFT test mode control circuit further includes a test reset port; the test reset port is any output port in the circuit under test, and the test reset port is connected to a test device for receiving a test reset signal sent by the test device, where the signal output by the test reset port maintains an invalid level state.

[0011] Optionally, the signal output by the test reset port is set to an invalid level state based on a DFT test script through a preset connection operation.

[0012] The second aspect of the present invention provides a DFT test mode control method, which is applied to the DFT test mode control circuit described in any one of the above. The method includes: Using the timing verification module to access the test clock signal, incrementally count the rising edge of the test clock signal, record the rising edge count value, compare the rising edge count value with a pre-set value, obtain a timing comparison result and output it to the test control module; Using the signal verification module to access the test data signal, sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value, compare the actual sampling value with a preset sampling value, obtain a signal comparison result and output it to the test control module, where the value of the preset period is equal to the pre-set value; When the timing comparison result indicates that the rising edge count value is equal to the pre-set value and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.

[0013] Optionally, the DFT test mode control circuit further includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module and the circuit under test; before using the timing verification module to access the test clock signal, the method further includes: in response to a system reset instruction, the system reset module generates a global reset signal to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit under test.

[0014] The third aspect of the present invention provides a chip, including the DFT test port simulation circuit described in any one of the above and at least one circuit under test.

[0015] The DFT test mode control circuit, method and chip provided by the present invention respectively use the timing verification module to count the rising edge of the test clock signal and the signal verification module to sample the test data signal. Only when the rising edge count value and the actual sampling value simultaneously meet the preset standard values for entering the test, the test control module can output a preset logic level signal to control the circuit under test to enter the DFT test mode; the above circuit effectively utilizes the signal resources output by the existing ports to form a multiple verification mechanism triggered by the test mode selection port, improving the reliability of the circuit under test entering the DFT test mode. There is no need to separately set a dedicated port for test mode selection, significantly reducing the number of ports, lowering the chip design cost, making the chip have stronger applicability and versatility, and being able to meet the basic requirements of DFT testing without having all test ports.

[0016] Other features and advantages of the present invention will be set forth in the following description, and in part will be obvious from the description, or may be learned by practice of the present invention. The objectives and other advantages of the present invention may be realized and attained by the structure particularly pointed out in the written description, claims, as well as the appended drawings.

[0017] The technical solution of the present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0018] The drawings are provided to further understand the present invention, and constitute a part of the description. Together with the embodiments of the present invention, they are used to explain the present invention, but do not constitute a limitation to the present invention. In the drawings: Figure 1 It is a schematic diagram of the overall structure of the DFT test mode control circuit in an embodiment provided by the present application; Figure 2 It is a schematic diagram of the overall structure of the DFT test mode control circuit in another embodiment provided by the present application; Figure 3 It is a specific circuit diagram of the DFT test mode control circuit in another embodiment provided by the present application; Figure 4 It is a signal waveform diagram of the DFT test mode control circuit in another embodiment provided by the present application; Figure 5 It is a schematic flowchart of the DFT test mode control method in an embodiment provided by the present application; Figure 6 It is a schematic flowchart of the DFT test mode control method in another embodiment provided by the present application.

[0019] In the figures: PIN1, test clock port; PIN2, test data input port; PIN3, test enable port; init_reg[7:0], the first sampling value; init_reg1[7:0], the second sampling value; test_mode_cnt[3:0], the rising edge count value; test_mode, the signal output by the test control module. Detailed Embodiments

[0020] The present application will be described in detail below with reference to the drawings and in combination with embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments may be combined with each other.

[0021] In one embodiment, as Figure 1As shown, a DFT test mode control circuit is provided, including a timing verification module, a signal verification module, and a test control module. Among them, the output terminals of the timing verification module and the signal verification module are respectively connected to the input terminal of the test control module, and the output terminal of the test control module is connected to the circuit under test; the input terminal of the timing verification module receives a test clock signal, which is used to incrementally count the rising edge of the test clock signal, record the rising edge count value, compare the rising edge count value with a pre-designed value, obtain a timing comparison result and output it to the test control module; the input terminal of the signal verification module receives a test data signal, which is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampled value, compare the actual sampled value with a preset sampled value, obtain a signal comparison result and output it to the test control module, where the value of the preset period is equal to the pre-designed value; the test control module is used to output a preset logic level signal when the timing comparison result indicates that the rising edge count value is equal to the pre-designed value and the signal comparison result indicates that the actual sampled value is equal to the preset sampled value, so as to control the circuit under test to enter the DFT test mode.

[0022] For the DFT test mode control circuit provided in this embodiment, the rising edge of the test clock signal is counted by the timing verification module, and the test data signal is sampled by the signal verification module. Only when the rising edge count value and the actual sampled value both meet the preset standard values for entering the test, can the test control module output a preset logic level signal, thereby controlling the circuit under test to enter the DFT test mode; the above circuit effectively utilizes the signal resources output by the existing ports to form a multiple verification mechanism triggered by the test mode selection port, improving the reliability of the circuit under test to enter the DFT test mode, without the need to separately set a dedicated port for test mode selection, significantly reducing the number of ports, reducing the chip design cost, making the chip have stronger applicability and versatility, and being able to meet the basic requirements of DFT testing without having all test ports.

[0023] Among them, the preset logic level signal is a high level signal.

[0024] In one embodiment, as Figure 2 shown, the timing verification module includes a rising edge counter and a first comparator. Among them, the output terminal of the rising edge counter is connected to the input terminal of the first comparator, and the output terminal of the first comparator is connected to the input terminal of the test control module; the input terminal of the rising edge counter receives a test clock signal, which is used to incrementally count the rising edge of the test clock signal, record the rising edge count value and output it to the first comparator. Among them, when the rising edge count value reaches the pre-designed value, the rising edge count value stops incrementing and remains at the pre-designed value; the first comparator compares the rising edge count value with the pre-designed value, obtains a timing comparison result and outputs it to the test control module.

[0025] In this embodiment, the rising-edge counter can accurately record the number of rising edges of the test clock signal, ensuring the accuracy of timing verification. The preset value can also be adjusted according to specific test requirements, making the timing verification module highly flexible and versatile, capable of adapting to different test scenarios. Moreover, the timing verification module and the signal verification module together constitute a multiple verification mechanism triggered by the test mode selection port. Only when all conditions are met will the test mode be triggered, improving the reliability of entering the DFT test mode.

[0026] In one embodiment, as Figure 2 shown, the signal verification module includes a register unit and a comparator unit. Among them, the output end of the register unit is connected to the input end of the comparator unit, and the output end of the comparator unit is connected to the input end of the test control module; the register unit accesses the test data signal, samples the test data signal at the rising edge of the test clock signal within a preset period, records the actual sampled value and outputs it to the comparator unit; the comparator unit compares the actual sampled value with the preset sampled value, obtains the signal comparison result and outputs it to the test control module.

[0027] In this embodiment, at least one register is provided in the register unit, and at least one comparator is provided in the comparator unit. The register and the comparator are in a one-to-one correspondence connection relationship. The register is used to access the signal output by a port and sample it to obtain the sampled value, and the corresponding comparator is used to compare the sampled value with the preset sampled value to obtain the comparison result. Finally, all the obtained comparison results are output to the test control module. In cooperation with the timing verification module, on the basis that the rising-edge count value reaches the preset value, only when all the comparison results show that all the sampled values meet the preset sampled values can the signal test_mode output by the test control module be controlled to be high level, and then control the circuit under test to enter the DFT test mode; using the register unit for redundant sampling enhances the fault tolerance of the signal verification module. Multiple registers in the register unit work in parallel to process different types of test data signals respectively, improving the parallel processing ability of the signal verification module. The modular structure design and flexible configuration of the signal verification module can be expanded or trimmed according to actual needs, enhancing the versatility and adaptability of the signal verification module.

[0028] Specifically, as Figure 2 and Figure 3As shown, the test data signal includes a test data input signal and a test enable signal. The register unit includes a first register and a second register. The comparator unit includes a second comparator and a third comparator. Among them, the output end of the first register is connected to the input end of the second comparator, and the output end of the second register is connected to the input end of the third comparator. The output ends of the second comparator and the third comparator are respectively connected to the input end of the test control module. The input end of the first register accesses the test data input signal, which is used to sample the test data input signal at the rising edge of the test clock signal within a preset period, record the first sampled value and output it to the second comparator. The second comparator compares the first sampled value with the first preset sampled value, obtains the first signal comparison result and outputs it to the test control module. The input end of the second register accesses the test enable signal, which is used to sample the test enable signal at the rising edge of the test clock signal within a preset period, record the second sampled value and output it to the third comparator. The third comparator compares the second sampled value with the second preset sampled value, obtains the second signal comparison result and outputs it to the test control module. When the timing comparison result indicates that the rising edge count value is equal to the preset value, the first signal comparison result indicates that the first sampled value is equal to the first preset sampled value, and the second signal comparison result indicates that the second sampled value is equal to the second preset sampled value, the test control module outputs a high-level signal to control the circuit under test to enter the DFT test mode.

[0029] In this embodiment, taking the RTC circuit of the IIC interface as an example, there are only four available ports, specifically including: PIN1 is the test clock port, PIN2 is the test data input port, PIN3 is the test enable port, and PIN4 is the test data output port. Based on this, this circuit lacks a test reset port and a test mode selection port. Here, specifically analyze how this application simulates and implements the test mode selection port based on the existing ports. The test reset port will be analyzed in the following content.

[0030] Among them, the implementation principle of the test mode selection port is generated based on the specific input timing of the output signals of the three ports PIN1, PIN2, and PIN3. The waveform diagram of the signal is specifically as Figure 4As shown, the initial value of the test data input signal output from the test data input port PIN2 is 0, and it is sequentially sampled at the rising edge of the test clock signal output from the test clock port PIN1 to obtain the first sampled value 8’b00000111, which becomes 0 at the 9th rising edge of the test clock signal and then remains 0; the initial value of the test enable signal output from the test enable port PIN3 is 0, and it is sequentially sampled at the rising edge of the test clock port PIN1 to obtain the second sampled value 8’b00101001 and then remains 1; meanwhile, the initial value of the rising edge count value test_mode_cnt[3:0] recorded by the rising edge counter in the circuit is 0, and it is incremented by 1 at the rising edge of each test clock signal output from the test clock port PIN1 and remains unchanged after reaching the pre-set value, and the pre-set value is specifically 8; the first register in the circuit is used to record the first sampled value init_reg[7:0] of 8 cycles of the test data input signal output from the test data input port PIN2, and the second register in the circuit is used to record the second sampled value init_reg1[7:0] of 8 cycles of the test enable signal output from the test enable port PIN3. Among them, the first preset sampled value 8’h07 is pre-stored in the second comparator, and the second preset sampled value 8’h29 is pre-stored in the third comparator. When the pre-set value is 8, if the first sampled value init_reg[7:0] is 8’h07, the second sampled value init_reg1[7:0] is 8’h29, and the rising edge count value test_mode_cnt[3:0] is 8, the test control module outputs a high-level signal test_mode, thereby controlling the circuit under test to enter the test mode.

[0031] It should be noted that since the test control module outputs a high-level signal test_mode and the three ports PIN1, PIN2, and PIN3 are all in the normal mode of operation and are not used as signals for the test mode, specific excitations can be output through the three ports PIN1, PIN2, and PIN3 to control the circuit under test to enter the DFT test mode, saving a commonly used test mode selection port. At the same time, the rising edge counter counts the rising edges of the test clock signal, ensuring that the high-level signal test_mode will only be generated in the first 8 cycles when just powered on; when the circuit in the chip operates in the normal mode, even if the signals output from the PIN2 port and the PIN3 port are abnormal, it can effectively prevent the test control module from outputting a high-level signal test_mode, avoiding controlling the circuit under test to enter the DFT test mode during normal mode operation and disturbing the normal operation of the circuit.

[0032] In one embodiment, the DFT test mode control circuit further includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module, and the circuit under test; the system reset module is configured to generate a global reset signal in response to a system reset instruction, so as to perform a reset operation on the timing verification module, the signal verification module, and the test control module, and initialize the circuit under test.

[0033] Specifically, the DFT test mode control circuit further includes a test reset port; the test reset port is any output port in the circuit under test, and the test reset port is connected to a test device for receiving a test reset signal sent by the test device, wherein the signal output by the test reset port remains in an invalid level state.

[0034] Further, the signal output by the test reset port is set to an invalid level state based on a DFT test script through a preset connection operation.

[0035] Wherein, the invalid level state refers to a state in which a signal does not trigger any specific function or operation. In digital circuit design, a signal usually has two basic level states, namely the high level state of logic 1 and the low level state of logic 0. According to specific design requirements, one of the levels may be defined as the valid level state, and the other as the invalid level state. When the signal is in the valid level state, it will trigger a specific operation or function; when the signal is in the invalid level state, it will not trigger any specific operation or function; taking the test reset signal as an example, if the high level is the valid level state, then the low level is the invalid level state, which means that the signal will not trigger the reset operation.

[0036] In this embodiment, for the test reset port, its basic function is to perform a reset operation when the circuit under test enters the test mode. Considering that the generation logic of the high-level signal test_mode output by the test control module can be reset by the system reset module, the test reset port cannot share the system reset module. Otherwise, after entering the test mode, executing the function of the test reset port will directly exit the test mode. Based on this, in the DFT script of this application, an output port in the circuit under test is directly set as the test reset port through the hookup method, and the signal output by this port is set to an invalid level state inside the circuit, so that the test reset port cannot trigger any reset operation. Since all registers have been reset when the chip is powered on using the system reset module, and the test mode is entered by sending a sequence in a non-power-down manner, that is, the test control module outputs a high-level signal test_mode, all registers have been reset, and the internal state of the circuit under test has been initialized, there is no need to use the test reset port for resetting. Therefore, on the basis of saving a test mode selection port, a test reset port can also be saved, and only four ports are required to implement all the functions of DFT testing.

[0037] In one embodiment, as Figure 5 shown, a DFT test mode control method is provided. This method can be applied to the DFT test mode control circuit in any of the above embodiments. Among them, the execution subject of this method can be a signal detection device, a computer device, etc. This method includes the following steps: Step 101: Use the timing verification module to access the test clock signal, incrementally count the rising edge of the test clock signal, record the rising edge count value, compare the rising edge count value with the pre-designed value, obtain the timing comparison result, and output it to the test control module.

[0038] Step 102: Use the signal verification module to access the test data signal, sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value, compare the actual sampling value with the preset sampling value, obtain the signal comparison result, and output it to the test control module, where the value of the preset period is equal to the pre-designed value; Step 103: When the timing comparison result indicates that the rising edge count value is equal to the pre-designed value and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.

[0039] In this embodiment, the provided DFT test mode control method accurately counts and samples the test clock signal and the test data signal through the timing verification module and the signal verification module respectively, and performs a strict comparison operation. Only when both the timing comparison result and the signal comparison result meet the conditions, the circuit under test will be triggered to enter the DFT test mode. The dual verification mechanism greatly improves the reliability of entering the test mode and reduces the possibility of misjudgment. The timing verification module and the signal verification module respectively output the comparison results to the test control module, which improves the system integration through centralized processing. Moreover, each functional module is independent and works collaboratively, enhancing the flexibility and maintainability of the circuit.

[0040] Further, as Figure 6 shown, before step 101, the DFT test mode control method further includes: Step 104, in response to the system reset instruction, the system reset module generates a global reset signal to perform a reset operation on the timing verification module, the signal verification module, and the test control module, and initialize the circuit under test.

[0041] In this embodiment, by generating a global reset signal through the system reset module, it is ensured that all relevant modules and the circuit under test are in the initial state, providing a stable environment for subsequent tests, reducing the influence of external interference on the test results, and eliminating the need to design separate reset logics for each module. The overall system reset is the reset before the circuit under test enters the DFT test mode. After the overall system reset, the timing verification module, the signal verification module, and the test control module directly enter the working state, and the test control module can output a high-level signal test_mode within the shortest time period to control the circuit under test to enter the DFT test mode, further reducing the setting of test reset ports and compressing the number of ports.

[0042] In one embodiment, a chip is provided, including the DFT test mode control circuit according to any of the above embodiments and at least one circuit under test.

[0043] In this embodiment, the chip can enable the circuit under test to enter the test state by utilizing the signal resources output from the existing ports, effectively reducing the number of ports required to be set on the chip, reducing the chip size, and lowering the chip cost.

[0044] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity in description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0045] The above embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A DFT test mode control circuit, characterized in that: It includes a timing verification module, a signal verification module and a test control module, wherein the output end of the timing verification module and the output end of the signal verification module are respectively connected to the input end of the test control module, and the output end of the test control module is connected to the circuit to be tested; The input end of the timing verification module is connected to the test clock signal, which is used to count the rising edge of the test clock signal, record the rising edge count value, compare the rising edge count value with the pre-designed value, obtain the timing comparison result and output it to the test control module; The input end of the signal verification module is connected to the test data signal, which is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampling value, compare the actual sampling value with the preset sampling value, obtain the signal comparison result and output it to the test control module, wherein the value of the preset period is equal to the pre-designed value; The test control module is used to output a preset logic level signal to control the circuit under test to enter a DFT test mode when the timing comparison result indicates that the rising edge count value is equal to the pre-designed value and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value.

2. The DFT test mode control circuit according to claim 1, characterized in that: The timing verification module includes a rising edge counter and a first comparator, wherein the output end of the rising edge counter is connected to the input end of the first comparator, and the output end of the first comparator is connected to the input end of the test control module; The input end of the rising edge counter is connected to the test clock signal, and is used to count the rising edges of the test clock signal, record the rising edge count value and output it to the first comparator, wherein when the rising edge count value reaches a pre-designed value, the rising edge count value stops increasing and is maintained at the pre-designed value; The first comparator compares the rising edge count value with a pre-designed value to obtain a timing comparison result and outputs it to the test control module.

3. The DFT test mode control circuit according to claim 1, characterized in that: The signal verification module includes a register unit and a comparator unit, wherein the output end of the register unit is connected to the input end of the comparator unit, and the output end of the comparator unit is connected to the input end of the test control module; The register unit is connected to the test data signal, and is used to sample the test data signal at the rising edge of the test clock signal within a preset period, record the actual sampled value and output it to the comparator unit; The comparator unit compares the actual sampling value with the preset sampling value, obtains a signal comparison result and outputs it to the test control module.

4. The DFT test mode control circuit according to claim 3, characterized in that: The test data signal includes a test data input signal and a test enable signal, the register unit includes a first register and a second register, and the comparator unit includes a second comparator and a third comparator, wherein the output end of the first register is connected to the input end of the second comparator, the output end of the second register is connected to the input end of the third comparator, and the output end of the second comparator and the output end of the third comparator are respectively connected to the input end of the test control module; The input end of the first register is connected to the test data input signal, and is used to sample the test data input signal at the rising edge of the test clock signal within a preset period, record a first sampling value and output it to the second comparator, and the second comparator compares the first sampling value with a first preset sampling value to obtain a first signal comparison result and output it to the test control module; The input end of the second register is connected to the test enable signal, and is used to sample the test enable signal at the rising edge of the test clock signal within a preset period, record a second sampled value and output it to the third comparator, and the third comparator compares the second sampled value with a second preset sampled value to obtain a second signal comparison result and output it to the test control module; When the timing comparison result indicates that the rising edge count value is equal to the pre-designed value, and the first signal comparison result indicates that the first sampling value is equal to the first preset sampling value, and the second signal comparison result indicates that the second sampling value is equal to the second preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.

5. The DFT test mode control circuit according to claim 1, characterized in that: The DFT test mode control circuit further includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module and the circuit to be tested; The system reset module is used to generate a global reset signal in response to a system reset instruction to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit to be tested.

6. The DFT test mode control circuit according to claim 1 or 5, characterized in that: The DFT test mode control circuit also includes a test reset port; The test reset port is any output port in the circuit to be tested, and the test reset port is connected to a test device and is used to receive a test reset signal sent by the test device, wherein the signal output by the test reset port maintains an invalid level state.

7. The DFT test mode control circuit according to claim 6, characterized in that: The signal output by the test reset port is set to an invalid level state through a preset connection operation based on a DFT test script.

8. A DFT test mode control method, characterized in that: The method is applied to the DFT test mode control circuit according to any one of claims 1 to 7, and the method comprises: The timing verification module is used to access the test clock signal, the rising edge of the test clock signal is counted incrementally, the rising edge count value is recorded, the rising edge count value is compared with the pre-designed value, the timing comparison result is obtained and output to the test control module; The signal verification module is used to access the test data signal, the test data signal is sampled at the rising edge of the test clock signal within a preset period, the actual sampling value is recorded, the actual sampling value is compared with the preset sampling value, and the signal comparison result is obtained and output to the test control module, wherein the value of the preset period is equal to the pre-designed value; When the timing comparison result indicates that the rising edge count value is equal to the pre-designed value, and the signal comparison result indicates that the actual sampling value is equal to the preset sampling value, the test control module outputs a preset logic level signal to control the circuit under test to enter the DFT test mode.

9. The DFT test mode control method according to claim 8, characterized in that: The DFT test mode control circuit further includes a system reset module, which is respectively connected to the timing verification module, the signal verification module, the test control module and the circuit to be tested; before the timing verification module is used to access the test clock signal, the method further includes: In response to a system reset instruction, the system reset module generates a global reset signal to perform a reset operation on the timing verification module, the signal verification module and the test control module, and initialize the circuit under test.

10. A chip, characterized in that: The method comprises the DFT test port simulation circuit according to any one of claims 1 to 7 and at least one circuit to be tested.

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