Model verification file generation method and device, medium and product

Abstract

The invention discloses a model verification file generation method and device, a medium and a product, and relates to the technical field of semiconductor integrated circuits. The model verification file generation method comprises the following steps: obtaining a layout measurement area of a to-be-tested layout; a target feature point in the layout measurement area is used as a center, the layout measurement area is segmented according to the multiple area sizes, multiple first layout segmentation areas of different sizes are obtained, and the target feature point is any one of the feature points of the layout measurement area; for each first layout segmentation region, respectively shifting the first layout segmentation regions in the to-be-tested layout, so that no overlapping region exists between the shifted first layout segmentation regions, and determining the shifted first layout segmentation regions as second layout segmentation regions; and generating a model verification file according to the area features and the offset features of the second layout segmentation areas.

Description

Technical Field

[0001] This application belongs to the technical field of semiconductor integrated circuits, and particularly relates to a method, device, medium, and product for generating a model verification file. Background Art

[0002] Optical Proximity Correction (OPC) is a technology to enhance lithography effects. In current semiconductor manufacturing, OPC mostly uses model-based dynamic simulation to obtain mask patterns and contour lines. To obtain an accurate model, proximity effect verification is often required, and a large amount of measurement data needs to be prepared to form a model verification file.

[0003] In the existing method, in each layout measurement area of the layout to be tested, a measurement sub-layout is cut out according to the corresponding area size respectively, so as to form a model verification file.

[0004] However, in the case of a huge amount of measurement data required, more layout measurement areas and corresponding area sizes need to be set. This leads to a cumbersome data preparation process and a low generation efficiency of the model verification file. Summary of the Invention

[0005] Embodiments of this application provide a method, device, medium, and product for generating a model verification file, which can improve the generation efficiency of the model verification file.

[0006] On the one hand, an embodiment of this application provides a method for generating a model verification file, including:

[0007] Obtain the layout measurement area of the layout to be tested;

[0008] Centering on the target feature point in the layout measurement area, the layout measurement area is cut according to multiple area sizes respectively to obtain multiple first layout cut areas with different sizes, and the target feature point is any one of the feature points of the layout measurement area;

[0009] For each first layout cut area, perform an offset in the layout to be tested so that there is no overlapping area between the offset first layout cut areas, and determine the offset first layout cut areas as second layout cut areas;

[0010] Generate a model verification file according to the area features and offset features of each second layout cut area.

[0011] On the one hand, an embodiment of this application provides a device for generating a model verification file, including:

[0012] An area acquisition module, configured to acquire a layout measurement area of a layout to be tested;

[0013] An area splitting module, configured to split the layout measurement area according to multiple area sizes respectively with a target feature point in the layout measurement area as the center, to obtain a plurality of first layout split areas with different sizes, where the target feature point is any one of the feature points of the layout measurement area;

[0014] An area offset module, configured to offset each first layout split area in the layout to be tested respectively, so that there is no overlapping area between the offset first layout split areas, and determine the offset first layout split areas as second layout split areas;

[0015] A file generation module, configured to generate a model verification file according to the area features and offset features of the second layout split areas.

[0016] In one aspect of the embodiments of the present application, an electronic device is provided, and the device includes: a memory and a program or instruction stored on the memory and executable on a processor, and when the program or instruction is executed by the processor, it implements the method for generating a model verification file provided in any aspect of the embodiments of the present application as described above.

[0017] In one aspect of the embodiments of the present application, a readable storage medium is provided, and a program or instruction is stored on the readable storage medium, and when the program or instruction is executed by the processor, it implements the method for generating a model verification file provided in any aspect of the embodiments of the present application as described above.

[0018] In one aspect of the embodiments of the present application, a computer program product is provided, and when the instructions in the computer program product are executed by the processor of the electronic device, the electronic device is enabled to execute the method for generating a model verification file provided in any aspect of the embodiments of the present application as described above.

[0019] In the method for generating a model verification file provided by an embodiment of the present application, multiple region sizes are preset in advance, and then the layout measurement region is segmented according to the set region sizes to obtain multiple first layout segmentation regions. Then, each first layout segmentation region is offset so that there is no overlapping region between the second layout segmentation regions obtained after the offset, thereby generating a model verification file. In this way, in the case where the amount of measurement data required is huge, multiple layout segmentation regions are divided in one layout measurement region. Compared with the solution in the existing method where only one layout segmentation region can be divided in one layout measurement region, the number of layout measurement regions that need to be set can be reduced; at the same time, multiple region sizes are preset in advance, and each layout measurement region is segmented according to these multiple region sizes, without setting a region size for each layout measurement region separately. In the case where the number of set layout measurement regions is large, the number of set region sizes can be significantly reduced. In this way, the number of layout measurement regions and the corresponding region sizes that need to be set can be reduced, thereby improving the generation efficiency of the model verification file. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0021] Figure 1 is a flowchart of a method for generating a model verification file provided by an embodiment of the present application;

[0022] Figure 2 is a schematic diagram of a first layout segmentation region provided by an embodiment of the present application;

[0023] Figure 3 is a schematic diagram of a second layout segmentation region provided by an embodiment of the present application;

[0024] Figure 4 is a schematic diagram of the structure of a model verification file generation device provided by an embodiment of the present application;

[0025] Figure 5 is a schematic diagram of the structure of a model verification file generation device provided by an embodiment of the present application. Detailed Embodiments

[0026] The features and exemplary embodiments of various aspects of the present application will be described in detail below. To make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by showing examples of the present application.

[0027] It should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, elements defined by the statement "including..." do not exclude the existence of additional identical elements in the process, method, article or device including the said elements.

[0028] It should be noted that the acquisition, storage, use, processing, etc. of data in the technical solution of the present application all comply with the relevant provisions of national laws and regulations.

[0029] It should be noted that in the embodiments of the present application, some existing industry solutions such as certain software, components, models, etc. may be mentioned. They should be regarded as exemplary, and their purpose is only to illustrate the feasibility in the implementation of the technical solution of the present application, but it does not mean that the applicant has already or necessarily used this solution.

[0030] Optical proximity correction is a technology to enhance the lithography effect, which is used to reduce the image edge distortion phenomenon caused by diffraction effects. In current semiconductor manufacturing technologies, optical proximity correction mostly uses model-based dynamic simulation to obtain the mask pattern and contour line. As the manufacturing node technology becomes more difficult, the requirement for the model accuracy is also higher. Therefore, it is crucial to verify the optical proximity effect of the model. When verifying the optical proximity effect of the model, a large amount of measurement data needs to be prepared to form a model verification file for optical proximity effect.

[0031] In the existing method, in a to-be-tested layout pre-determined for optical proximity effect verification, multiple layout measurement regions for dynamic simulation of optical proximity effect verification are selected. Then, a measurement sub-layout is cut out according to the corresponding region size in the layout measurement region, and a model verification file is formed based on the measurement data of the measurement sub-layout.

[0032] However, in the case where the amount of measurement data required is huge, more layout measurement regions and corresponding region sizes need to be set, resulting in a cumbersome data preparation process and a low generation efficiency of the model verification file.

[0033] The purpose of this application is to provide a method, device, medium and product for generating a model verification file. In the model verification file generation method provided by the embodiments of this application, multiple region sizes are preset, and then the layout measurement region is cut according to the set region sizes to obtain multiple first layout cut regions. Then, each first layout cut region is offset so that there is no overlapping region between the second layout cut regions obtained after offset, thereby generating a model verification file. In this way, in the case where the amount of measurement data required is huge, multiple layout cut regions are divided in one layout measurement region. Compared with the solution in the existing method where only one layout cut region can be divided in one layout measurement region, the number of layout measurement regions that need to be set can be reduced; at the same time, multiple region sizes are preset, and each layout measurement region is cut according to the multiple region sizes, without setting a region size for each layout measurement region separately. In the case where the number of set layout measurement regions is large, the number of set region sizes can be significantly reduced. In this way, the number of layout measurement regions and corresponding region sizes that need to be set can be reduced, thereby improving the generation efficiency of the model verification file.

[0034] The following introduces the specific embodiments of the method, device, medium and product for generating a model verification file provided by the embodiments of this application. First, the method for generating a model verification file is introduced below.

[0035] Figure 1 A flowchart of a method for generating a model verification file is provided. This method for generating a model verification file can be applied to a server, and this method for generating a model verification file may include the following S101 to S104.

[0036] S101, obtain the layout measurement region of the to-be-tested layout.

[0037] In this embodiment, the to-be-tested layout is used to represent a layout pre-determined for optical proximity effect verification.

[0038] The layout measurement region is used to characterize the region in the layout to be tested for dynamic simulation of optical proximity effect verification. Among them, the layout to be tested can be a binary format file or a database format file.

[0039] As an example, the server first imports the layout to be tested from a design tool or a database. Then, using layout editing software or a script, the layout measurement region to be measured is selected from the entire layout to be tested; specifically, it can be manually selected by the user or automatically determined by a selection algorithm. Finally, preprocessing is performed on the selected layout measurement region, such as removing unnecessary graphic elements, to ensure the accuracy of subsequent processing.

[0040] S102: Centering on the target feature point in the layout measurement region, the layout measurement region is divided according to multiple region sizes respectively to obtain multiple first layout division regions with different sizes. The target feature point is any one of the feature points in the layout measurement region.

[0041] In this embodiment, the feature point is used to characterize the position point at a critical position or with significant features in the layout measurement region. For example, the feature point can include the center point and each vertex of the layout measurement region.

[0042] Among them, the target feature point is any one of the feature points. For example, the target feature point can be the center point of the layout measurement region, or any one of the vertices of the layout measurement region.

[0043] The region size is used to characterize the size of the first layout division region obtained after dividing the layout measurement region. Among them, the region shape of the first layout division region is not limited. For example, the first layout division region can be a rectangular region, a square region or a circular region.

[0044] The region size can be the side length, radius or perimeter of the first layout division region. For example, when the first layout division region is a square region, the region size is used to characterize the side length of the square region; when the first layout division region is a circular region, the region size is used to characterize the radius of the circular region.

[0045] As an example, as Figure 2 shown, a schematic diagram of a first layout division region is provided. Among them, the layout to be tested includes two layout measurement regions, namely layout measurement region 201 and layout measurement region 202.

[0046] The server first identifies the corresponding target feature point A and target feature point B in the layout measurement area 201 and the layout measurement area 202 respectively. Then, according to requirements, multiple different area sizes are set. Centering on the target feature point A and the target feature point B respectively, the layout measurement area 201 and the layout measurement area 202 are segmented according to each area size, so as to obtain multiple first layout segmentation areas corresponding to the layout measurement area 201 and multiple first layout segmentation areas corresponding to the layout measurement area 202.

[0047] Among them, the layout measurement area 201 can be divided into three first layout segmentation areas, namely the first layout segmentation area 201a, the first layout segmentation area 201b, and the layout measurement area 201 itself can also be used as a first layout segmentation area; the layout measurement area 202 is divided into three first layout segmentation areas, namely the first layout segmentation area 202a, the first layout segmentation area 202b, and the layout measurement area 202 itself can also be used as a first layout segmentation area. In addition, the area shapes of the first layout segmentation areas corresponding to the layout measurement area 201 and the layout measurement area 202 can be the same or different. Figure 2 In it, the area shapes of the first layout segmentation area 201a and the first layout segmentation area 201b corresponding to the first layout measurement area 201 are square, and the area shapes of the first layout segmentation area 202a and the first layout segmentation area 202b corresponding to the second layout measurement area 202 are rectangular.

[0048] S103. For each first layout segmentation area, perform an offset in the layout to be tested respectively, so that there is no overlapping area between the offset first layout segmentation areas, and determine the offset first layout segmentation areas as the second layout segmentation areas.

[0049] In this embodiment, the second layout segmentation area is used to represent the layout segmentation area obtained by offsetting the first layout segmentation area and having no overlapping area with other first layout segmentation areas.

[0050] As an example, the server sets appropriate offset amounts for each first layout segmentation area to ensure that they do not overlap. Then, according to the offset amounts corresponding to each first layout segmentation area, the first layout segmentation areas are offset in the layout to be tested respectively, and the offset first layout segmentation areas are determined as the second layout segmentation areas.

[0051] Such as Figure 3As shown in the figure, a schematic diagram of the second layout segmentation region is provided. Among them, the layout measurement region 202 is offset to obtain the second layout segmentation region test1_3, the first layout segmentation region 202a is offset to obtain the second layout segmentation region test1_2, and the first layout segmentation region 202b is offset to obtain the second layout segmentation region test1_1; the layout measurement region 201 is offset to obtain the second layout segmentation region test2_3, the first layout segmentation region 201a is offset to obtain the second layout segmentation region test2_2, and the first layout segmentation region 201b is offset to obtain the second layout segmentation region test2_1.

[0052] S104. Generate a model verification file according to the region characteristics and offset characteristics of each second layout segmentation region.

[0053] In this embodiment, the model verification file is used to represent a data file that can be used for proximity effect verification generated according to the second layout segmentation region. Among them, the model verification file includes a layout file and a measurement data file. The layout file includes information on the layout regions for performing optical proximity effect verification, and the measurement data file includes the measurement data of each layout region for performing optical proximity effect verification.

[0054] Specifically, after obtaining the model verification file, each layout region included in the layout file can be input into the model to obtain the corresponding simulation measurement results; then, the simulation measurement results are compared with the real measurement results in the measurement data file to verify the accuracy of the model.

[0055] The region characteristics are used to represent the characteristics of the spatial range of the second layout segmentation region. Exemplarily, the region characteristics may include region shape, region size, etc.

[0056] The offset characteristics are used to represent the characteristics when the first layout segmentation region is offset to the second layout segmentation region. Exemplarily, the offset characteristics may include offset amount, offset direction, etc.

[0057] As an example, the server first extracts the corresponding region characteristics from each second layout segmentation region; then, records the offset characteristics of each second layout segmentation region. Finally, according to the region characteristics and offset characteristics of the second layout segmentation region, a model verification file is generated using a specific file format.

[0058] In the method for generating a model verification file provided in this embodiment, multiple region sizes are preset in advance, and then the layout measurement region is divided according to the set region sizes to obtain multiple first layout division regions. Then, each first layout division region is offset so that there are no overlapping regions between the second layout division regions obtained after the offset, thereby generating a model verification file. In this way, in the case where the amount of measurement data required is huge, in one layout measurement region, multiple layout division regions are obtained. Compared with the solution in the existing method where only one layout division region can be divided from one layout measurement region, the number of layout measurement regions that need to be set can be reduced; at the same time, multiple region sizes are preset in advance, and each layout measurement region is divided according to these multiple region sizes, without setting a region size for each layout measurement region separately. In the case where the number of layout measurement regions set is large, the number of region sizes set can be significantly reduced. In this way, the number of layout measurement regions and the corresponding region sizes that need to be set can be reduced, thereby improving the generation efficiency of the model verification file.

[0059] As an optional embodiment, S102 may specifically include:

[0060] Taking the target feature point in the layout measurement region as the center and using N times the preset length as the region size, the layout measurement region is divided to obtain the Nth first layout division region, and the initial value of N is 1;

[0061] In the case where (N + 1) times the preset length is less than or equal to the size length of the layout measurement region, update N to N + 1, and return to execute taking the target feature point in the layout measurement region as the center and using N times the preset length as the region division size to divide the layout measurement region to obtain the Nth first layout division region.

[0062] In this embodiment, the preset length is used to represent the length preset by the server for determining the region sizes of each first layout division region.

[0063] As an example, in the case where the first layout division region is a square region, the region size may represent the side length of the square region. At this time, the size length of the layout measurement region is the side length of the layout measurement region. At this time, the server uses N times the preset length as the side length of the current first layout division region, and the initial value of N is 1. For example, if the preset length is 10 units, when N = 1, the side length of the first layout division region is 10 units; when N = 2, the side length of the first layout division region is 20 units, and so on.

[0064] Then, centered on the target feature point, according to the side length of the currently corresponding first layout segmentation region, a square first layout segmentation region is cut out from the layout measurement region. Then, it is checked whether (N + 1) times the preset length is less than or equal to the side length of the layout measurement region. If so, it means that the segmentation region can be further expanded; if not, it means that the boundary of the layout measurement region has been reached and no further segmentation is possible.

[0065] Finally, if (N + 1) times the preset length is less than or equal to the side length of the layout measurement region, then N is updated to N + 1, and the process returns to re-segment the layout measurement region; if (N + 1) times the preset length is greater than the side length of the layout measurement region, the iterative process is stopped.

[0066] As another example, when the first layout segmentation region is a circular region, the region size can represent the radius of the circular region. At this time, the size length of the layout measurement region is the radius length of the layout measurement region. At this time, the server uses N times the preset length as the radius of the currently corresponding first layout segmentation region, and the initial value of N is 1. For example, if the preset length is 10 units, when N = 1, the radius of the first layout segmentation region is 10 units; when N = 2, the radius of the first layout segmentation region is 20 units, and so on.

[0067] Then, centered on the target feature point, according to the radius of the currently corresponding first layout segmentation region, a circular first layout segmentation region is cut out from the layout measurement region. Then, it is checked whether (N + 1) times the preset length is less than or equal to the radius of the layout measurement region. If so, it means that the segmentation region can be further expanded; if not, it means that the boundary of the layout measurement region has been reached and no further segmentation is possible.

[0068] Finally, if (N + 1) times the preset length is less than or equal to the radius of the layout measurement region, then N is updated to N + 1, and the process returns to re-segment the layout measurement region; if (N + 1) times the preset length is greater than the radius of the layout measurement region, the iterative process is stopped.

[0069] Through this embodiment, using N times the preset length as the region size, the segmentation region is gradually expanded until the entire layout measurement region is covered or no further segmentation is possible. In this way, it is possible to segment the layout measurement region as many times as possible, thereby reducing the number of layout measurement regions that need to be set and improving the generation efficiency of the model verification file.

[0070] As an alternative embodiment, the preset length is an integer multiple of the model recognition accuracy in the optical proximity effect correction model.

[0071] In this embodiment, the server determines the model recognition accuracy (ambit parameter) of the optical proximity effect correction model according to the performance and process requirements of the lithography machine.

[0072] Then, according to the determined model recognition accuracy, the aforementioned preset length is set. Among them, this preset length should be a positive integer multiple of the model recognition accuracy to ensure that the distortion of the lithography pattern can be accurately recognized and corrected during the model correction process. For example, if the model recognition accuracy of the optical proximity effect correction model is 1um, the preset length can be set to 1um, 2um, 3um, etc.

[0073] Through this embodiment, the preset length is determined according to the model recognition accuracy of the optical proximity effect correction model. In this way, it can be ensured that the first layout segmentation region divided according to the preset length can be accurately recognized by the optical proximity effect correction model, thereby improving the accuracy of model verification.

[0074] As an alternative embodiment, S103 may specifically include:

[0075] The following steps are repeatedly executed until all the first layout segmentation regions are traversed:

[0076] Select the first first layout segmentation region from each of the first layout segmentation regions in accordance with the preset selection order;

[0077] Move the first first layout segmentation region by the corresponding offset length along the offset direction.

[0078] In this embodiment, the preset selection order may be the order of the areas of the first layout segmentation regions from large to small, or the order of the areas of the first layout segmentation regions from small to large.

[0079] The offset direction may be the direction along the horizontal axis of the coordinate axis parallel to the layout coordinate system, or the direction along the vertical axis of the coordinate axis parallel to the layout coordinate system. Among them, the layout coordinate system is a plane rectangular coordinate system constructed with any feature point in the layout to be tested as the origin.

[0080] The offset length is a predefined value that determines the distance of region movement. Among them, the offset lengths between the first layout segmentation regions are different.

[0081] As an example, the server can set a loop structure (such as a for loop, a while loop, etc.) to iteratively process each first layout segmentation region, where the termination condition of the loop is that all the first layout segmentation regions have been processed.

[0082] In each iteration of the loop, the server determines the first first layout segmentation area to be processed currently according to the preset selection order. Then, along the preset offset direction, the first first layout segmentation area is moved by the corresponding offset length, so as to obtain the second layout segmentation area.

[0083] As Figure 3 shown, among them, test1_1, test1_2, and test1_3 belong to the second layout segmentation areas obtained after splitting the same layout measurement area; test2_1, test2_2, and test2_3 belong to the second layout segmentation areas obtained after splitting the same layout measurement area. Among the second layout segmentation areas obtained after splitting the same layout measurement area, they are arranged in the order of the area size of the second layout segmentation areas.

[0084] Through this embodiment, each first layout segmentation area in the layout measurement area is moved by the corresponding offset length along the offset direction to obtain the corresponding second layout segmentation area, thereby forming an array. In this way, there will be no overlap between the finally obtained second layout segmentation areas, so as to improve the accuracy of model verification.

[0085] As an optional embodiment, the offset length is equal to the product of the target difference and the reference movement length. The target difference is the difference between the total number of the first layout segmentation areas and the current movement ordinal number of the first layout segmentation areas, and the reference movement length is greater than or equal to the maximum size along the offset direction among the first layout segmentation areas.

[0086] In this embodiment, the reference movement length is set according to the maximum size along the offset direction among the first layout segmentation areas. Exemplarily, the sizes of the first layout segmentation areas along the offset direction are 1um, 2um, and 3um respectively. At this time, the reference movement length is set to any length value greater than or equal to 3um.

[0087] According to the difference between the total number of the first layout segmentation areas and the current movement ordinal number of the first layout segmentation areas, and the reference movement length, the offset length corresponding to the first layout segmentation area is determined. Exemplarily, there are a total of 5 first layout segmentation areas. Then, when moving for the first time, the offset length corresponding to the first layout segmentation area is 4 times the reference movement length; when moving for the second time, the offset length corresponding to the first layout segmentation area is 3 times the reference movement length, and so on.

[0088] In this embodiment, the offset length is set to the product of the target difference and the reference movement length. The target difference is the difference between the total number of the first layout segmentation regions and the current movement ordinal number of the first layout segmentation regions. The reference movement length is greater than or equal to the maximum dimension along the offset direction in each of the first layout segmentation regions. In this way, it can be ensured that there is no overlapping region between the first layout segmentation regions after offset, and the accuracy of model verification can be improved.

[0089] As an alternative embodiment, moving the first first layout segmentation region along the offset direction by the corresponding offset length includes any of the following methods:

[0090] In the plane rectangular coordinate system corresponding to the layout to be tested, move the first feature point in the first first layout segmentation region along the offset direction by the corresponding offset length;

[0091] In the polar coordinate system corresponding to the layout to be tested, based on the offset direction and the corresponding offset length, determine the offset angle and the change value of the radial distance; and move the second feature point in the first first layout segmentation region along the offset angle by the change value of the radial distance.

[0092] In this embodiment, the first feature point is used to represent the feature point position of the first layout segmentation region in the plane rectangular coordinate system corresponding to the layout to be tested.

[0093] The second feature point is used to represent the feature point position of the first layout segmentation region in the polar coordinate system corresponding to the layout to be tested.

[0094] As an example, in the plane rectangular coordinate system corresponding to the layout to be tested, each point is determined by its abscissa (x) and ordinate (y). To move the first layout segmentation region, only need to move each first feature point in the first layout segmentation region respectively.

[0095] Specifically, for the coordinates of the first feature point, according to the offset direction and the offset length, use the rotation and translation formulas in the two-dimensional plane to calculate the new coordinates after movement. Among them, if the offset direction is horizontal to the right or left, only the abscissa of the first feature point needs to be changed; if the offset direction is vertical up or down, only the ordinate of the first feature point needs to be changed.

[0096] As another example, in the polar coordinate system corresponding to the layout to be tested, each point is determined by its distance (r) from the origin and the angle (θ) between it and the positive x-axis. To move the first layout segmentation region, only need to move each second feature point in the first layout segmentation region respectively. Among them, the offset angle is the change value of the angle between the second feature point and the positive x-axis, and the change value of the radial distance is the change value of the distance between the second feature point and the origin.

[0097] Specifically, for the second feature point, according to the offset angle, the angle between the second feature point and the positive x-axis is updated; at the same time, according to the change value of the radial distance, the distance between the second feature point and the origin is updated, so as to obtain the new position after movement.

[0098] Through this embodiment, two ways of graphic offset, namely offset in the rectangular coordinate system and offset in the polar coordinate system, are provided. In this way, the server can select a suitable graphic offset method according to the actual situation of the layout to be tested, thereby improving the convenience of graphic offset.

[0099] As an alternative embodiment, S101 includes any of the following methods:

[0100] In response to the operation of the user inputting the range of the layout measurement area, based on the range of the layout measurement area, the layout measurement area is determined in the layout to be tested;

[0101] Boolean operations are performed between the historical measurement areas to obtain the layout measurement area of the layout to be tested.

[0102] In this embodiment, the Boolean operation, also known as the logical operation, is a logical mathematical calculation method for processing the relationship between two entities. It performs operations such as union, intersection, and subtraction on two or more objects through specific logical operation rules, so as to obtain new objects or results.

[0103] As an example, the server can provide a user interface that allows the user to input the range of the measurement area through a graphical interface or command line in the user interface. Among them, the user interface includes selection tools, input boxes, buttons, etc., for receiving the input instructions of the user.

[0104] Then, the server receives the range information of the layout measurement area input by the user, and the range information may include parameters such as coordinates, dimensions, and shapes. And the range information is parsed to determine the corresponding layout measurement area in the layout to be tested.

[0105] As another example, the server obtains the previously verified historical measurement areas from the database, and performs operations on the historical measurement areas according to the preset Boolean operation rules (such as union operation, intersection operation, difference operation, etc.). Thus, one or more new areas are obtained, and the new area is determined as the layout measurement area of the layout to be tested.

[0106] Through this embodiment, two ways of obtaining the layout measurement area, namely the user inputting the range of the layout measurement area and performing Boolean operations between the historical measurement areas, are provided. In this way, the server can select a suitable way to obtain the layout measurement area according to the actual situation of the layout to be tested, thereby improving the convenience of obtaining the layout measurement area.

[0107] As an alternative embodiment, the region feature includes a region position and a region size, the offset feature includes an offset direction and an offset length, and the model verification file includes a layout file and a measurement data file;

[0108] S104 may specifically include:

[0109] Generate a layout file based on the region positions of the second layout segmentation regions in the layout to be tested;

[0110] Update the measurement data of the layout measurement region based on the offset direction, offset length, and region size of each second layout segmentation region to obtain the measurement data of each second layout segmentation region;

[0111] Generate a measurement data file based on the measurement data of each second layout segmentation region.

[0112] In this embodiment, for each second layout segmentation region, the server extracts its region position in the layout to be tested. According to the extracted region position, a layout file is generated using a specific file format. Among them, the layout file contains the region position information of all second layout segmentation regions in the layout to be tested.

[0113] Then, for each second layout segmentation region, based on its offset direction, offset length, and region size, the measurement data of the layout measurement region in the layout to be tested is updated, so as to obtain the measurement data of each second layout segmentation region.

[0114] Finally, the measurement data of each second layout segmentation region is summarized to generate a measurement data file (GaugeFile). Among them, the measurement data file contains the measurement data of all second layout segmentation regions. Exemplarily, the measurement data file may include the starting point (startx, starty), ending point (endx, endy), center point (centerx, centery) of the second layout segmentation region, and the group name (groupname), etc.

[0115] Through this embodiment, a layout file is generated based on the region positions of the second layout segmentation regions in the layout to be tested; at the same time, based on the offset direction, offset length, and region size of each second layout segmentation region, the measurement data of the layout measurement region is updated, so as to generate a measurement data file. In this way, it is not necessary to measure the region positions and measurement data of each second layout segmentation region separately, and the model verification file can be generated quickly, improving the generation efficiency of the model verification file.

[0116] A method for generating a model verification file. Correspondingly, the present application also provides a specific embodiment of a device for generating a model verification file.

[0117] As shown Figure 4 in the figure, the model verification file generation device 400 provided by the embodiment of the present application includes a region acquisition module 410, a region segmentation module 420, a region offset module 430, and a file generation module 440.

[0118] The region acquisition module 410 is configured to acquire the layout measurement region of the layout to be tested.

[0119] The region segmentation module 420 is configured to take a target feature point in the layout measurement region as the center, and segment the layout measurement region according to a plurality of region sizes respectively to obtain a plurality of first layout segmentation regions with different sizes. The target feature point is any one of the feature points of the layout measurement region.

[0120] The region offset module 430 is configured to offset each first layout segmentation region in the layout to be tested respectively, so that there is no overlapping region between the offset first layout segmentation regions, and determine the offset first layout segmentation regions as the second layout segmentation regions.

[0121] The file generation module 440 is configured to generate a model verification file according to the region features and offset features of each second layout segmentation region.

[0122] In the model verification file generation device provided by this embodiment, a plurality of region sizes are preset in advance, and then the layout measurement region is segmented according to the set region sizes to obtain a plurality of first layout segmentation regions. Then, each first layout segmentation region is offset so that there is no overlapping region between the offset second layout segmentation regions, thereby generating a model verification file. In this way, in the case where the required measurement data volume is huge in the embodiment of the present application, a plurality of layout segmentation regions are divided in one layout measurement region. Compared with the solution in the existing method where only one layout segmentation region can be divided in one layout measurement region, the number of layout measurement regions that need to be set can be reduced; at the same time, a plurality of region sizes are preset in advance, and each layout measurement region is segmented according to the plurality of region sizes, without setting a region size for each layout measurement region respectively. In the case where the number of set layout measurement regions is large, the number of set region sizes can be significantly reduced. In this way, the number of layout measurement regions and the corresponding region sizes that need to be set can be reduced, thereby improving the generation efficiency of the model verification file.

[0123] As an optional embodiment, the region segmentation module 420 is specifically configured to:

[0124] Take a target feature point in the layout measurement region as the center, and use N times the preset length as the region size to segment the layout measurement region to obtain the Nth first layout segmentation region, where the initial value of N is 1;

[0125] When the N + 1 times of the preset length is less than or equal to the dimension length of the layout measurement area, update N to N + 1, and return to perform splitting the layout measurement area with the target feature point in the layout measurement area as the center and N times of the preset length as the area splitting dimension, so as to obtain the Nth first layout splitting area.

[0126] As an optional embodiment, the area offset module 430 is specifically configured to:

[0127] Loop to execute the following steps until all the first layout splitting areas are traversed:

[0128] Select the first first layout splitting area from each first layout splitting area according to the preset selection order;

[0129] Move the first first layout splitting area along the offset direction by the corresponding offset length.

[0130] As an optional embodiment, the area acquisition module 410 is specifically configured to:

[0131] In response to the operation of the user inputting the range of the layout measurement area, determine the layout measurement area in the layout to be tested based on the range of the layout measurement area;

[0132] Perform a Boolean operation between each historical measurement area to obtain the layout measurement area of the layout to be tested.

[0133] As an optional embodiment, the area feature includes the area position and the area dimension, the offset feature includes the offset direction and the offset length, and the model verification file includes the layout file and the measurement data file;

[0134] The file generation module 440 is specifically configured to:

[0135] Generate a layout file based on the area position of each second layout splitting area in the layout to be tested;

[0136] Update the measurement data of the layout measurement area based on the offset direction, the offset length and the area dimension of each second layout splitting area to obtain the measurement data of each second layout splitting area;

[0137] Generate a measurement data file based on the measurement data of each second layout splitting area.

[0138] The generation method of the model verification file. Correspondingly, the present application also provides a specific embodiment of the device for generating the model verification file.

[0139] Figure 5 Shows the hardware structure schematic diagram of the device for generating the model verification file provided by the embodiment of the present application.

[0140] The generating device of the model verification file may include a processor 501 and a memory 502 storing computer program instructions.

[0141] Specifically, the above-mentioned processor 501 may include a central processing unit (CPU), or an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application.

[0142] The memory 502 may include a mass storage for data or instructions. By way of example and not limitation, the memory 502 may include a hard disk drive (HDD), a floppy disk drive, a flash memory, an optical disk, a magneto-optical disk, a magnetic tape, or a universal serial bus (USB) drive, or a combination of two or more of these. In a suitable case, the memory 502 may include a removable or non-removable (or fixed) medium. In a suitable case, the memory 502 may be internal or external to the integrated gateway disaster recovery device. In a specific embodiment, the memory 502 is a non-volatile solid state memory.

[0143] The processor 501 reads and executes the computer program instructions stored in the memory 502 to implement any one of the model verification file generating methods in the above embodiments.

[0144] In one example, the generating device of the model verification file may further include a communication interface 503 and a bus 510. Among them, as Figure 5 shown, the processor 501, the memory 502, and the communication interface 503 are connected through the bus 510 and complete communication with each other.

[0145] The communication interface 503 is mainly used to implement communication between the various modules, devices, units, and / or devices in the embodiments of the present application.

[0146] The bus 510 includes hardware, software, or both, and couples components of the model verification file generation device to each other. By way of example and not limitation, the bus may include an Accelerated Graphics Port (AGP) or other graphics bus, an Extended Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an InfiniBand interconnect, a Low Pin Count (LPC) bus, a memory bus, a MicroChannel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or other suitable buses or a combination of two or more of these. Where appropriate, the bus 510 may include one or more buses. Although embodiments of the present application describe and illustrate specific buses, the present application contemplates any suitable bus or interconnect.

[0147] In addition, in combination with the model verification file generation method in the above embodiments, an embodiment of the present application can be implemented by providing a computer storage medium. Computer program instructions are stored on the computer storage medium; when the computer program instructions are executed by a processor, any one of the model verification file generation methods in the above embodiments is implemented.

[0148] In addition, in combination with the model verification file generation method in the above embodiments, an embodiment of the present application can be implemented by providing a computer program product. When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device is caused to execute the model verification file generation method provided in any aspect of the above embodiments of the present application.

[0149] It should be clear that the present application is not limited to the specific configurations and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known methods are omitted here. In the above embodiments, several specific steps are described and illustrated as examples. However, the method process of the present application is not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications, and additions, or change the order between steps after understanding the spirit of the present application.

[0150] The functional blocks shown in the above-described structural block diagrams can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it can be, for example, an electronic circuit, an application-specific integrated circuit (ASIC), appropriate firmware, a plug-in, a functional card, and so on. When implemented in software, the elements of the present application are programs or code segments used to perform the required tasks. The program or code segment can be stored in a machine-readable medium or transmitted via a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" can include any medium that can store or transmit information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical discs, hard disks, fiber optic media, radio frequency (RF) links, and so on. The code segment can be downloaded via a computer network such as the Internet, an intranet, and so on.

[0151] It should also be noted that the exemplary embodiments mentioned in the present application describe some methods or systems based on a series of steps or devices. However, the present application is not limited to the order of the above steps, that is, the steps can be executed in the order mentioned in the embodiments, can be different from the order in the embodiments, or several steps can be executed simultaneously.

[0152] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block in the flowcharts and / or block diagrams, and the combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in one or more blocks of the flowchart and / or block diagram. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It should also be understood that each block in the block diagram and / or flowchart, and the combinations of blocks in the block diagram and / or flowchart, can also be implemented by dedicated hardware that performs the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0153] As described above, this is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application.

Claims

1. A method for generating a model verification file, characterized in that: include: Obtaining a layout measurement area of ​​a layout to be tested; Taking the target feature point in the layout measurement area as the center, the layout measurement area is divided according to a plurality of area sizes to obtain a plurality of first layout division areas of different sizes, wherein the target feature point is any one of the feature points in the layout measurement area; For each of the first layout segmentation regions, offset them in the layout to be tested so that there is no overlapping area between the first layout segmentation regions after the offset, and determine the first layout segmentation regions after the offset as the second layout segmentation regions; A model verification file is generated according to the regional features and offset features of each of the second layout segmentation regions.

2. The method according to claim 1, characterized in that The target feature point in the layout measurement area is taken as the center, and the layout measurement area is divided according to multiple area sizes to obtain multiple first layout division areas of different sizes, including: Taking the target feature point in the layout measurement area as the center and N times the preset length as the area size, the layout measurement area is divided to obtain the Nth first layout division area, where the initial value of N is 1; When N+1 times the preset length is less than or equal to the size length of the layout measurement area, N is updated to N+1, and the execution returns to the target feature point in the layout measurement area as the center and N times the preset length as the area segmentation size, and the layout measurement area is segmented to obtain the Nth first layout segmentation area.

3. The method according to claim 2, characterized in that The preset length is equal to a positive integer multiple of the model recognition accuracy in the optical proximity effect correction model.

4. The method according to claim 1, characterized in that: The step of offsetting each of the first layout segmentation regions in the layout to be tested so that there is no overlapping area between the offset first layout segmentation regions comprises: The following steps are executed in a loop until all the first layout segmentation areas are traversed: Selecting the first first layout segmentation area from each of the first layout segmentation areas according to a preset selection order; The first region of the first layout is cut into pieces and moved along the offset direction by a corresponding offset length.

5. The method according to claim 4, characterized in that The offset length is equal to the product of the target difference and the reference movement length, the target difference is the difference between the total number of the first layout segmentation areas and the current movement sequence number of the first layout segmentation areas, and the reference movement length is greater than or equal to the maximum size of each of the first layout segmentation areas along the offset direction.

6. The method according to claim 4, characterized in that The first segmentation area of ​​the first layout is moved along the offset direction by a corresponding offset length, including any of the following methods: In the plane rectangular coordinate system corresponding to the layout to be tested, a first feature point in a first segmented area of ​​the first layout is moved along an offset direction by a corresponding offset length; In the polar coordinate system corresponding to the layout to be tested, based on the offset direction and the corresponding offset length, determine the offset angle and the radial distance change value; And move the first second feature point in the first layout segmentation area along the offset angle by the radial distance change value.

7. The method according to claim 1, characterized in that The method of obtaining the layout measurement area of ​​the layout to be tested includes any of the following methods: In response to an operation in which a user inputs a range of a layout measurement area, determining the layout measurement area in the layout to be tested based on the range of the layout measurement area; A Boolean operation is performed between each historical measurement area to obtain the layout measurement area of ​​the layout to be tested.

8. The method according to any one of claims 1 to 7, characterized in that: The region feature includes the region position and the region size, the offset feature includes the offset direction and the offset length, and the model verification file includes the layout file and the measurement data file; The step of generating a model verification file according to the regional features and offset features of each of the second layout segmentation regions includes: Generate a layout file based on the region position of each of the second layout segmentation regions in the layout to be tested; Based on the offset direction, the offset length and the area size of each second layout segmentation area, the measurement data of the layout measurement area is updated to obtain the measurement data of each second layout segmentation area; A measurement data file is generated based on the measurement data of each of the second layout segmentation areas.

9. An electronic device, characterized in that: The device comprises: a processor and a memory storing computer program instructions; When the processor executes the computer program instructions, the method for generating a model verification file according to any one of claims 1 to 8 is implemented.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer program instructions, and when the computer program instructions are executed by a processor, the method for generating a model verification file according to any one of claims 1 to 8 is implemented.

11. A computer program product, characterized in that When the instructions in the computer program product are executed by a processor of an electronic device, the electronic device executes the method for generating a model verification file according to any one of claims 1 to 8.

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