Power-on and power-off time sequence control circuit of GPU (Graphics Processing Unit) and intelligent computing card
By using Schmitt inverter module and delay control module in the GPU power-down timing control circuit, the area occupation and stability of the CPLD and MCU control methods is solved, and efficient and reliable power-down control of GPU power-down is achieved.
Patent Information
- Application Number
- CN202510209603.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-27
AI Technical Summary
The existing CPLD and MCU control methods have shortcomings in occupying the power-up circuit area, and the program burning process is complex and unstable, which affects the normal operation of the system.
The power-on and down timing control circuit of the GPU is adopted, and the Schmitt inverter module replaces the traditional CPLD or MCU, and the power-on and down timing control is realized using the delay control module and the trigger module, and it is directly operated through the external signal source control circuit.
It effectively controls the power-on and power-off timing of the GPU on a compact circuit board, reduces the area occupied by the circuit layout, improves the stability and reliability of the system, and avoids the complexity and risks in the program burning process.
Smart Images
Figure CN120044860A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of timing control circuits, and in particular to a GPU power-on and power-off timing control circuit and an intelligent computing card. Background Art
[0002] In the existing timing control field, the commonly used CPLD (Complex Programmable Logic Device) and MCU (Microcontroller Unit) control methods have some defects that are difficult to ignore. Specifically: Chip size and peripheral device issues: Conventional CPLD and MCU chips are relatively large in size. For example, the common MCU_48Pin model chip size reaches 7mm×9mm, the MCU_64Pin model chip size is 12mm×12mm, and the CPLD_48Pin model chip size is 9mm×9mm. Not only that, these devices also require peripheral devices such as crystal oscillators required by peripherals in actual use. This makes it difficult to ignore the occupied circuit board area during the overall layout. In some application scenarios that have strict and compact requirements for the motherboard size, this large occupied area has become a prominent problem, limiting the flexibility and compactness of circuit design.
[0003] Program burning and stability issues: Before CPLD and MCU are put into use, they need to be programmed by professional software engineers, and the factory needs to perform program burning during the production process. This process not only increases the complexity and cost of the production process, but also introduces the risk of program data loss. Once the medium storing the program fails or is interfered with by the outside world, the program data may be lost or damaged, thus affecting the normal operation of the entire system.
[0004] In summary, how to overcome the shortcomings of CPLD and MCU control methods in occupying the power-on circuit area, meet the demand for miniaturization of the motherboard, and improve the stability and reliability of the system is a technical problem that needs to be solved urgently. Summary of the invention
[0005] In order to overcome the shortcomings of the prior art, the present application provides a GPU power-on and power-off timing control circuit and an intelligent computing card to overcome the shortcomings of CPLD and MCU control methods in occupying the power-on circuit area, meet the demand for a compact motherboard size, and improve the stability and reliability of the system.
[0006] The technical solution adopted by this application to solve its technical problem is: In a first aspect, the present application provides a power-on and power-off timing control circuit for a GPU, including: a Schmitt inverter module with multiple paths; each output end of the Schmitt inverter module is respectively connected to different power-on pins of the target GPU; Each input end of the Schmitt inverter module is respectively connected to the first end of a delay control module; each of the delay control modules has different delay settings based on corresponding resistance value differences; The second ends of all the delay control modules are connected to the first end of the trigger module, the second end of the trigger module is connected to an external first signal source, and the third end of the trigger module is grounded; The third end of each of the delay control modules is connected to an external second signal source. When the first signal source sends a first enable signal to the trigger module, if the second signal source sends a second enable signal to all the delay control modules, then according to the delay settings corresponding to each of the delay control modules, the multiple output ends of the Schmitt inverter module are sequentially pulled high to achieve power-on timing control; The first end of the trigger module is also connected to an external third signal source. When the first signal source sends a first enable signal to the trigger module, if the third signal source sends a third enable signal to all the delay control modules, then according to the delay settings corresponding to each of the delay control modules, the multiple output ends of the Schmitt inverter module are sequentially pulled low to achieve power-off timing control.
[0007] Optionally, the trigger module includes a circuit trigger unit and an over-temperature protection unit; The first end of the circuit trigger unit is connected to the second ends of all the delay control modules, and the second end of the circuit trigger unit is connected to the first signal source; The third end of the circuit trigger unit is connected to the first end of the over-temperature protection unit, the second end of the over-temperature protection unit is connected to the overheat protection end of the target GPU, and the third end of the over-temperature protection unit is grounded; When the target CPU sends an overheat power-off protection signal to the over-temperature protection unit, the circuit trigger unit is used to prohibit each output end of the Schmitt inverter module from powering on the target GPU, thereby achieving overheat power-off protection.
[0008] Optionally, the Schmitt inverter module includes multiple Schmitt inverters; Each input end of the Schmitt inverter is respectively connected to the first end of a delay control module, and each output end of the Schmitt inverter is respectively connected to different power-on pins of the target GPU.
[0009] Optionally, the delay control module includes a first delay unit group, a second delay unit, and a third delay unit group; The first delay unit group includes one or more first delay units, and each of the first delay units is provided with a first resistor, a second resistor, a first capacitor, and a first diode; in each of the first delay units, the second signal source is connected to the input end of a Schmitt inverter and one end of the first resistor through the first capacitor, the other end of the first resistor is connected to the positive electrode of the first diode and one end of the second resistor, and the other end of the second resistor and the negative electrode of the first diode are both connected to the first end of the circuit trigger unit; The second delay unit is provided with a third resistor and a second capacitor; in the second delay unit, the second signal source is connected to one end of the third resistor and the input end of a Schmitt inverter through the second capacitor, and the other end of the third resistor is connected to the first end of the circuit trigger unit; The third delay unit group includes one or more third delay units, and each of the third delay units is provided with a fourth resistor, a fifth resistor, a third capacitor, and a second diode; in each of the second delay units, the second signal source is connected to one end of the fourth resistor and the input end of a Schmitt inverter through the third capacitor, the other end of the fourth resistor is connected to one end of the fifth resistor and the negative electrode of the second diode, and the other end of the fifth resistor and the positive electrode of the second diode are both connected to the first end of the circuit trigger unit; Wherein, the input end of each Schmitt inverter is connected to one of the first delay unit, the second delay unit, or the third delay unit.
[0010] Optionally, the circuit trigger unit includes a sixth resistor, a first MOS transistor, a seventh resistor, and an eighth resistor; The second ends of all the delay control modules are connected to the drain of the first MOS transistor and one end of the sixth resistor, and the other end of the sixth resistor is connected to the third signal source; The gate of the first MOS transistor is connected to the first signal source through the seventh resistor; the source of the first MOS transistor is connected to the first end of the over-temperature protection unit and is connected to the ground electrode through the eighth resistor.
[0011] Optionally, the over-temperature protection unit includes a second MOS transistor and a ninth resistor; The drain of the second MOS transistor is connected to the source of the first MOS transistor through the ninth resistor, the gate of the second MOS transistor is connected to the overheat protection terminal of the target GPU, and the source of the second MOS transistor is grounded.
[0012] Optionally, the timing control circuit is applied to the Zhikai 100 chip, the target GPU is the Zhikai 100 chip, and the model of the Schmidt inverter is RS6G14.
[0013] Optionally, the first delay unit group includes two first delay units; The resistance values of the first resistors in all the first delay units are different from each other, and the resistance values of the second resistors in all the first delay units are different from each other.
[0014] Optionally, the third delay unit group includes three third delay units; The resistance values of the fourth resistors in all the third delay units are different from each other, and the resistance values of the fifth resistors in all the third delay units are different from each other.
[0015] In a second aspect, the present application provides a computing card loaded with the above power-on and power-off timing control circuit.
[0016] The beneficial effects of the present application are as follows: This technical solution replaces the traditional complex programmable logic device (CPLD) or micro control unit (MCU) with a Schmidt inverter module, thereby realizing efficient power-on and power-off timing control of the GPU on a small circuit board. Specifically, this design reduces the area occupied by the circuit layout because the Schmidt inverter module has a smaller size than the CPLD and MCU; at the same time, it no longer depends on a complex programming process, and directly controls the power-on and power-off processes through an external signal source, thereby improving the stability and reliability of the system.
[0017] Specifically, its working process is as follows: When the external signal source sends a power-on control signal, the delay control module is activated in sequence, indirectly driving the Schmidt inverter module through the trigger module, so as to realize precise power-on timing control of the GPU; conversely, when the power-off control signal is generated, the delay control module will drive the Schmidt inverter module to discharge in sequence to complete the power-off process of the GPU. Such a design enables the control process of the entire system to be completed under a unified signal source, avoiding the risk of program loss that may occur during the programming process, and thus has high reliability and adaptability, especially suitable for application scenarios with strict requirements for the motherboard size. Description of the Drawings
[0018] Figure 1 is the module connection diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application; Figure 2 is the circuit schematic diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application; Figure 3 is the working logic diagram of the Schmidt inverter of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application; Figure 4 It is a schematic diagram of the power-on timing of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application; Figure 5 It is a schematic diagram of the power-off timing of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application; Figure 6 It is a circuit schematic diagram of the trigger module of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application.
[0019] Reference numerals: R1, the first resistor; R2, the second resistor; R3, the third resistor; R4, the fourth resistor; R5, the fifth resistor; R6, the sixth resistor; R7, the seventh resistor; R8, the eighth resistor; R9, the ninth resistor; C1, the first capacitor; C2, the second capacitor; C3, the third capacitor; Q1, the first MOS transistor; Q2, the second MOS transistor; D1, the first diode; D2, the second diode. Detailed implementation manners
[0020] The present application will be further described below in conjunction with the drawings and embodiments.
[0021] The concept, specific structure and technical effects generated by the present application will be clearly and completely described below in conjunction with the embodiments and the drawings to fully understand the purpose, features and effects of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of protection of the present application. In addition, all the connection / connection relationships involved in the patent do not refer to the direct connection of components alone, but refer to the more optimal connection structure that can be formed by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the creation of the present application can be combined with each other without conflicting with each other.
[0022] Refer to Figure 1 , Figure 1 It is a module connection diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application, including a Schmitt inverter module with multiple paths, a delay control module for implementing timing control, and a trigger module for starting the timing control module. Specific descriptions are as follows: It includes: a Schmitt inverter module with multiple paths; each output terminal of the Schmitt inverter module is respectively connected to different power-on pins of the target GPU.
[0023] Specifically, the Schmidt inverter module includes a Schmidt inverter. The Schmidt inverter is provided with multiple inputs and multiple outputs corresponding to the multiple inputs. The multiple outputs are respectively connected to multiple power-on pins of the target GPU. In the embodiment of the present application, when the timing control circuit provided in the present application is in the power-on mode, the multiple outputs of the Schmidt inverter are pulled high one by one according to a preset order, so as to meet the power-on timing requirements of the target GPU.
[0024] Further, each input end of the Schmidt inverter module is respectively connected to a first end of a delay control module; each of the delay control modules has different delay settings based on the corresponding resistance value differences.
[0025] Specifically, the Schmidt inverter in the Schmidt inverter module is provided with multiple inputs. Each output is connected to a delay control module. In each delay control module, different RC delay effects will be generated based on different resistance values set therein.
[0026] In this embodiment, if in the power-on mode, the external signal source controls all the delay control modules to start at the same time. Based on the different delay settings of each delay control module, all the input ends of the Schmidt inverter module are pulled low in sequence, so that all the output ends of the corresponding Schmidt inverter module are pulled high in sequence, realizing the power-on of the target GPU; if in the power-off mode, another external signal source controls all the delay control modules to start. Based on different diode connection methods and resistance value settings in each delay control module, all the input ends of the Schmidt inverter module are pulled high in sequence, so that all the output ends of the Schmidt inverter module are pulled low in sequence, realizing the timing power-off.
[0027] Further, the second ends of all the delay control modules are connected to the first end of the trigger module. The second end of the trigger module is connected to an external first signal source, and the third end of the trigger module is grounded.
[0028] Specifically, the trigger module is used to control the power-off of the delay control module, including two cases of active power-off and forced power-off. In the case of active power-off, the first signal source outputs a level signal, which causes the switch in the trigger module to turn off. The delay control module sends a high level to each input end of the Schmidt inverter module. Based on the delay setting, the input ends of the Schmidt inverter module are pulled high in sequence, thus realizing the power-off effect.
[0029] More specifically, the delay control module is connected to an external second signal source. When the first signal source sends a first enable signal to the trigger module, if the second signal source sends a second enable signal to all the delay control modules, then according to the corresponding delay setting of each delay control module, the multiple output ends of the Schmidt inverter module are pulled high in sequence, realizing the power-on timing control.
[0030] More specifically, the first end of the trigger module is also connected to an external third signal source. The third signal source can be an independent signal source or the same as the above-mentioned first signal source. When the first signal source sends a first enable signal to the trigger module, if the third signal source sends a third enable signal to all the delay control modules, the multiple output ends of the Schmitt inverter module are sequentially pulled low according to the delay settings corresponding to each delay control module, realizing the power-down timing control.
[0031] Furthermore, in order to implement the forced power-down function of the trigger module, the present application proposes that the trigger module consists of a circuit trigger unit and an over-temperature protection unit. Specifically: The first end of the circuit trigger unit is connected to the second ends of all the delay control modules, and the second end of the circuit trigger unit is connected to the first signal source; The third end of the circuit trigger unit is connected to the first end of the over-temperature protection unit. The second end of the over-temperature protection unit is connected to the overheat protection end of the target GPU, and the third end of the over-temperature protection unit is grounded.
[0032] Specifically, when the target CPU sends an overheat power-off protection signal to the over-temperature protection unit, the circuit trigger unit prohibits each output end of the Schmitt inverter module from powering on the target GPU, realizing the overheat power-off protection.
[0033] More specifically, when the target GPU has completed power-on and is in the running state, based on the real-time temperature detection of its chip interior by the target GPU, an overheat power-off protection signal will be output. When the chip temperature of the target GPU reaches the preset temperature threshold, the overheat protection end of the target GPU will send a corresponding overheat power-off protection signal, causing the over-temperature protection unit to forcibly turn off the entire trigger module, and all the output ends of the Schmitt inverter module are sequentially pulled low, thereby realizing the power-down protection function of forced power-down. The overheat power-off protection signal can be a kind of level signal, such as a low-level signal.
[0034] Furthermore, referring to Figure 2 , Figure 2 is the circuit schematic diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application, which provides a specific implementation manner of each of the above modules. The following will specifically describe each module in combination with Figure 2 respectively: The Schmitt inverter module includes multiple Schmitt inverters; Each input end of the Schmitt inverter is respectively connected to the first end of a delay control module, and each output end of the Schmitt inverter is respectively connected to different power-on pins of the target GPU.
[0035] Specifically, the multi-channel Schmitt inverter has multiple input terminals and multiple output terminals corresponding to the multiple input terminals. In the embodiment of the present application, taking the target GPU as the Zhikai 100 chip as an example, to meet the power-on and power-off requirements of the Zhikai 100 chip, a 6-channel Schmitt inverter of model RS6G14 is used.
[0036] Refer to Figure 3 , Figure 3 is the working logic diagram of the Schmitt inverter of the power-on and power-off timing control circuit of the GPU provided in the embodiment of the present application. Combining Figure 3 It can be seen from the left figure that the 6-channel Schmitt inverter is provided with 6 input terminals and corresponding 6 output terminals. Combining Figure 3 It can be seen from the right figure that when each input terminal is at a high level (H), the corresponding output terminal outputs a low level (L). In this case, multiple power-on pins of the target GPU are powered on one by one; conversely, when each input terminal is at a low level (L), the corresponding output terminal outputs a high level (H). In this case, multiple power-on pins of the target GPU are pulled low one by one to achieve timing power-off.
[0037] Furthermore, the delay control module includes a first delay unit group, a second delay unit, and a third delay unit group. Among them, the input terminal of each Schmitt inverter is connected to one of the first delay unit, the second delay unit, or the third delay unit. Specifically; The first delay unit group includes one or more first delay units. Each first delay unit is provided with a first resistor R1, a second resistor R2, a first capacitor C1, and a first diode D1; in each first delay unit, the second signal source is connected to the input terminal of one Schmitt inverter and one end of the first resistor R1 through the first capacitor C1. The other end of the first resistor R1 is connected to the positive electrode of the first diode D1 and one end of the second resistor R2. The other end of the second resistor R2 and the negative electrode of the first diode D1 are both connected to the first end of the circuit trigger unit.
[0038] Specifically, refer to Figure 2 , Figure 2 In the embodiment provided, the first delay unit group includes two first delay units. Taking one path (the first path) as an example, when in the power-on mode, the second signal source (P3VP) is sequentially output to the ground through the first capacitor C1, the first resistor R1, the first diode D1, and the trigger module, so that the input terminal of the Schmitt inverter is pulled low, thereby making the corresponding output terminal pulled high to complete the power-on of the corresponding pin of the output terminal; when in the power-off mode, the signal sent by the third signal source connected through the trigger module is used to pull high the input terminal of the Schmitt inverter through the second resistor R2 and the first resistor R1, thereby making the corresponding output terminal pulled low to complete the power-off of the corresponding pin of the output terminal.
[0039] The second delay unit is provided with a third resistor R3 and a second capacitor C2; in the second delay unit, the second signal source is connected to one end of the third resistor R3 and the input end of a Schmitt inverter through the second capacitor C2, and the other end of the third resistor R3 is connected to the first end of the circuit trigger unit.
[0040] Specifically, the second delay unit is the branch with the middle resistance value among all branches. For example, the 3rd or 4th branch of 6 branches (the 3rd branch of 6 branches in this embodiment), the 4th branch of 7 branches. To ensure stable timing, there is only one second delay unit. Compared with other branches, it does not need to be equipped with a diode or an additional resistor. It only needs to set the delay of its front and back branches reasonably, so as to reduce the use of components and achieve the effect of power-on and power-off timing control.
[0041] The third delay unit group includes one or more third delay units. Each third delay unit is provided with a fourth resistor R4, a fifth resistor R5, a third capacitor C3 and a second diode D2; in each second delay unit, the second signal source is connected to one end of the fourth resistor R4 and the input end of a Schmitt inverter through the third capacitor C3, the other end of the fourth resistor R4 is connected to one end of the fifth resistor R5 and the negative electrode of the second diode D2, and the other end of the fifth resistor R5 and the positive electrode of the second diode D2 are both connected to the first end of the circuit trigger unit.
[0042] Specifically, referring to Figure 2 , in the embodiment of the present application, it includes three third delay units. Taking one branch (the 4th branch) as an example, when in the power-on mode, the second signal source (P3VP) sequentially passes through the third capacitor C3, the fourth resistor R4, the fifth resistor R5, and the trigger module to the ground, so that the input level of the Schmitt inverter in this branch is pulled low, thereby pulling up the output end of the Schmitt inverter in this branch to realize the power-on of this path; when in the power-off mode, the signal sent by the third signal source connected through the trigger module, through the second diode D2 and the fourth resistor R4, pulls up the input level of the Schmitt inverter in this branch, so that the output end of the Schmitt inverter in this branch is pulled low to realize the power-off.
[0043] For intuitive display, the above descriptions about the power-on mode and the power-off mode can be combined, and referring to Figure 4 and Figure 5 can deepen the understanding of timing control, where Figure 4 is the power-on timing schematic diagram of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application; Figure 5It is a power-down timing schematic diagram of the power-up and power-down timing control circuit of the GPU provided by the embodiments of the present application.
[0044] The embodiments of the present application also provide parameter embodiments for the RC delay setting of the power-up part for reference:
[0045] Further, the circuit trigger unit includes a sixth resistor R6, a first MOS transistor Q1, a seventh resistor R7, and an eighth resistor R8; The second ends of all the delay control modules are connected to the drain of the first MOS transistor Q1 and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is connected to the third signal source; The gate of the first MOS transistor Q1 is connected to the first signal source through the seventh resistor R7; the source of the first MOS transistor Q1 is connected to the first end of the overtemperature protection unit and is connected to the ground electrode through the eighth resistor R8.
[0046] Specifically, referring to Figure 2 , in the present application, one ends of multiple delay control modules are all connected to the drain of the first MOS transistor Q1. If not in the overtemperature state (that is, when the overtemperature protection unit operates normally), when the first signal source sends a high level, it will pull up the gate of the first MOS transistor Q1 to turn on the first MOS transistor Q1. The turned-on first MOS transistor Q1 will make the drain of the first MOS transistor Q1 grounded through its source and the overtemperature protection unit, thereby pulling down the levels of the inputs of the Schmitt inverter.
[0047] If in the overtemperature state, in this case, the overtemperature protection unit is equivalent to being disconnected. In this case, regardless of the on-off state of the first MOS transistor Q1, the source of the first MOS transistor Q1 will be pulled up, and further, the levels of each input of the Schmitt inverter will be pulled up, achieving the power-down effect.
[0048] Further, the overtemperature protection unit includes a second MOS transistor Q2 and a ninth resistor R9; The drain of the second MOS transistor Q2 is connected to the source of the first MOS transistor Q1 through the ninth resistor R9, the gate of the second MOS transistor Q2 is connected to the overtemperature protection terminal of the target GPU, and the source of the second MOS transistor Q2 is grounded.
[0049] Specifically, referring to Figure 6 , Figure 6It is the circuit schematic diagram of the trigger module of the power-on and power-off timing control circuit of the GPU provided by the embodiment of the present application. The second position in the diagram is connected to the overheat protection terminal of the target GPU, and is at a high level when the chip temperature of the target GPU is within the normal range. This high level will pull up the gate of the second MOS transistor Q2, thereby turning on the second MOS transistor Q2 (that is, the over-temperature protection unit is in a normal state).
[0050] When the chip temperature of the target GPU reaches or exceeds the preset temperature threshold, in this case, the target GPU outputs an overheat power-off protection signal through its overheat protection terminal. Corresponding to the high level in the normal state, the overheat power-off protection signal is a low-level signal. At this time, the gate of the second MOS transistor Q2 is pulled down, and the second MOS transistor Q2 is turned off. In this case, even if the gate of the first MOS transistor Q1 is pulled up by the first signal source (position one), the gate of the first MOS transistor Q1 will also be pulled up due to the presence of the eighth resistor R8, resulting in the input terminal of the Schmitt inverter being pulled up and the output terminal of the Schmitt inverter being pulled down, disconnecting the power supply.
[0051] In a second aspect, the present application provides an intelligent computing card loaded with the above power-on and power-off timing control circuit.
[0052] The above is a specific description of the preferred embodiment of the present application, but the creation of the present application is not limited to the described embodiment. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present application. These equivalent deformations or substitutions are all included within the scope defined by the claims of the present application.
Claims
1. A GPU power-on and power-off timing control circuit, characterized in that: include: A multi-channel Schmidt inverter module is provided; each output end of the Schmidt inverter module is respectively connected to a different power-on pin of the target GPU; Each input end of the Schmidt inverter module is respectively connected to the first end of a delay control module; each of the delay control modules has different delay settings based on the corresponding resistance value difference; The second ends of all the delay control modules are connected to the first end of the trigger module, the second ends of the trigger module are connected to an external first signal source, and the third ends of the trigger module are grounded; The third end of each of the delay control modules is connected to an external second signal source. When the first signal source sends a first enable signal to the trigger module, if the second signal source sends a second enable signal to all of the delay control modules, then according to the delay setting corresponding to each of the delay control modules, the multi-channel output ends of the Schmitt inverter module are sequentially pulled up to realize power-on timing control; The first end of the trigger module is also connected to an external third signal source. When the first signal source sends a first enable signal to the trigger module, if the third signal source sends a third enable signal to all the delay control modules, then according to the delay setting corresponding to each of the delay control modules, the multi-channel output ends of the Schmitt inverter module are pulled down in turn to achieve power-off timing control.
2. The GPU power-on and power-off timing control circuit according to claim 1, characterized in that: The trigger module includes a circuit trigger unit and an over-temperature protection unit; The first end of the circuit trigger unit is connected to the second ends of all the delay control modules, and the second end of the circuit trigger unit is connected to the first signal source; The third end of the circuit trigger unit is connected to the first end of the over-temperature protection unit, the second end of the over-temperature protection unit is connected to the over-temperature protection end of the target GPU, and the third end of the over-temperature protection unit is grounded; When the target CPU sends an overheat power-off protection signal to the overheat protection unit, the circuit trigger unit prohibits each output end of the Schmidt inverter module from powering on the target GPU, thereby achieving overheat power-off protection.
3. The GPU power-on and power-off timing control circuit according to claim 2, characterized in that: The Schmidt inverter module includes a multi-channel Schmidt inverter; Each input end of the Schmidt inverter is respectively connected to a first end of the delay control module, and each output end of the Schmidt inverter is respectively connected to different power-on pins of the target GPU.
4. The GPU power-on and power-off timing control circuit according to claim 3, characterized in that: The delay control module comprises a first delay unit group, a second delay unit group and a third delay unit group; The first delay unit group includes one or more first delay units, each of which is provided with a first resistor, a second resistor, a first capacitor and a first diode; in each of the first delay units, the second signal source is connected to an input end of the Schmitt inverter and one end of the first resistor through the first capacitor, the other end of the first resistor is connected to the positive electrode of the first diode and one end of the second resistor, and the other end of the second resistor and the negative electrode of the first diode are both connected to the first end of the circuit trigger unit; The second delay unit is provided with a third resistor and a second capacitor; in the second delay unit, the second signal source is connected to one end of the third resistor and an input end of the Schmitt inverter through the second capacitor, and the other end of the third resistor is connected to the first end of the circuit trigger unit; The third delay unit group includes one or more third delay units, each of which is provided with a fourth resistor, a fifth resistor, a third capacitor and a second diode; in each of the second delay units, the second signal source is connected to one end of the fourth resistor and an input end of one Schmitt inverter through the third capacitor, the other end of the fourth resistor is connected to one end of the fifth resistor and the cathode of the second diode, and the other end of the fifth resistor and the anode of the second diode are both connected to the first end of the circuit trigger unit; Wherein, the input end of each Schmitt inverter is connected to one of the first delay unit, the second delay unit or the third delay unit.
5. The GPU power-on and power-off timing control circuit according to claim 2, characterized in that: The circuit trigger unit includes a sixth resistor, a first MOS tube, a seventh resistor and an eighth resistor; The second ends of all the delay control modules are connected to the drain of the first MOS tube and one end of the sixth resistor, and the other end of the sixth resistor is connected to the third signal source; The gate of the first MOS tube is connected to the first signal source through the seventh resistor; the source of the first MOS tube is connected to the first end of the over-temperature protection unit and is connected to the ground through the eighth resistor.
6. The GPU power-on and power-off timing control circuit according to claim 5, characterized in that: The over-temperature protection unit includes a second MOS tube and a ninth resistor; The drain of the second MOS tube is connected to the source of the first MOS tube through the ninth resistor, the gate of the second MOS tube is connected to the overheat protection terminal of the target GPU, and the source of the second MOS tube is grounded.
7. The GPU power-on and power-off timing control circuit according to claim 4, characterized in that: The timing control circuit is applied to the Zhikai 100 chip, the target GPU is the Zhikai 100 chip, and the model of the Schmidt inverter is RS6G14.
8. The power-on and power-off timing control circuit according to claim 7, characterized in that: The first delay unit group includes two first delay units; The resistance values of the first resistors in all the first delay units are different from each other, and the resistance values of the second resistors in all the first delay units are different from each other.
9. The power-on and power-off timing control circuit according to claim 7, characterized in that: The third delay unit group includes three third delay units; The resistance values of the fourth resistors in all the third delay units are different from each other, and the resistance values of the fifth resistors in all the third delay units are different from each other.
10. An intelligent computing card, characterized in that: The device is equipped with a power-on and power-off timing control circuit as described in any one of claims 1-9.