Self-adaptive voltage stabilizing source circuit

Abstract

The invention provides a self-adaptive voltage stabilizing source circuit, which comprises a grid end control circuit, a self-adaptive protection module and a voltage output module, and is characterized in that the self-adaptive protection module comprises a pair of PMOS (P-channel Metal Oxide Semiconductor) tube and NMOS (N-channel Metal Oxide Semiconductor) tube which are connected in parallel at a grid electrode, and a branch circuit where the NMOS tube is located is connected in series with a group of voltage dividing elements; one end of the grid end control circuit is connected to the grid electrode of the PMOS tube and the grid electrode of the NMOS tube; and the drain electrode of the PMOS tube and the source electrode of the NMOS tube are connected to one end of the voltage output module. According to the voltage stabilizing source circuit, a low-voltage mode and a high-voltage mode are adjusted and switched through a PMOS (P-channel Metal Oxide Semiconductor) tube and an NMOS (N-channel Metal Oxide Semiconductor) tube which are connected in parallel in a self-adaptive module, and the range of input voltage is adjusted and enlarged through several voltage dividing elements; and by adopting a common depletion type MOS (Metal Oxide Semiconductor) tube instead of a high-cost and high-complexity specific high-voltage-resistant device, not only is the circuit performance optimized, but also the economical efficiency of the circuit is improved, and an efficient and reliable solution is provided for the design of a voltage stabilizing source with a wide input voltage range.

Description

Technical Field

[0001] This application relates to the fields of electronic devices and industrial control, and particularly to an adaptive voltage regulator circuit. Background Art

[0002] In the fields of electronic devices and industrial control, the voltage regulator circuit plays a key role in ensuring the stable operation of electronic devices. Its core task is to convert the input unsteady voltage (such as a wide-range DC input voltage) into a stable output voltage to meet the requirements of the load for voltage accuracy and stability. Currently, the solutions for voltage regulator circuits mainly focus on two technical paths: low dropout linear regulator (LDO) and switching regulator circuit. For the typical structure of a traditional wide input voltage LDO, see Figure 1 shown. To meet the design requirements of a wide input voltage range, this circuit uses LDMOS transistors with high voltage tolerance in each branch. However, compared with conventional MOS transistors, the structure of LDMOS transistors is more complex, occupies a larger area, and the lateral diffusion charge layer of LDMOS transistors requires a larger current during operation, resulting in higher power losses. For the gallium nitride voltage regulator circuit with a wide power supply voltage range, see Figure 2 shown. By adding structural levels in the bias unit, the current stability under a wide voltage input range is effectively optimized, thus achieving a stable output voltage. However, under higher input voltage conditions, the voltage difference between the gate and drain of transistor M7, which mainly bears the output in this circuit, is relatively large, presenting a high breakdown risk and problems with circuit reliability. Although the low dropout linear regulator circuit has high voltage regulation accuracy and low output ripple, its output stability and conversion efficiency are insufficient under higher input voltages. The switching regulator circuit is suitable for the voltage regulation requirements of a wide input voltage range, but its output ripple is large, the circuit design is complex, and the chip area is large. Therefore, it is particularly important to develop a voltage regulator that can adapt to a wide range of input voltages and has high-precision output. Summary of the Invention

[0003] In view of the above situation, this application provides an adaptive voltage regulator circuit, which flexibly controls the high-voltage mode and low-voltage mode in the voltage regulator circuit to adapt to a wide range of input voltages, so as to achieve a voltage regulator with high-precision output.

[0004] The implementation solution of the present invention is as follows: An adaptive voltage regulator circuit includes a gate control circuit, an adaptive protection module, and a voltage output module. It is characterized in that the adaptive protection module includes a pair of PMOS and NMOS transistors connected in parallel at the gate, and a voltage dividing element group is connected in series in the branch where the NMOS transistor is located; one end of the gate control circuit is connected to the gates of the PMOS and NMOS transistors; the drain of the PMOS transistor and the source of the NMOS transistor are connected to one end of the voltage output module.

[0005] Furthermore, the voltage dividing element group includes several PMOS transistors.

[0006] Furthermore, the drain output terminal of the PMOS transistor in the gate control circuit that controls the gate voltage in the adaptive protection module is connected to the gates of the PMOS and NMOS transistors in the adaptive protection module.

[0007] Furthermore, one branch of the gate of the PMOS transistor in the gate control circuit that controls the gate voltage in the adaptive protection module is connected in series with a group of elements and grounded, and the other branch is connected to the input voltage; the group of elements includes several NMOS transistors.

[0008] Furthermore, the drain of the PMOS transistor in the adaptive protection module and the source of the NMOS transistor in the adaptive protection module are connected to the drain of the NMOS transistor that controls the output voltage in the voltage output module.

[0009] Furthermore, the output terminal in the voltage output module is connected to the source of the NMOS transistor that controls the output voltage in the voltage output module.

[0010] Furthermore, the gate control circuit and the adaptive protection module share the same input voltage.

[0011] Furthermore, the gate of the NMOS transistor that controls the output voltage in the voltage output module is connected in parallel with a Zener diode whose one end is connected to the input voltage and the other end is grounded; and both share the same ground wire.

[0012] Furthermore, when the input voltage is configured as a low voltage and the Zener diode is broken down, the output voltage value of the output terminal connected to the source of the NMOS transistor in the voltage output module is the breakdown voltage value of the Zener diode; when the input voltage is configured as a low voltage and the Zener diode is not broken down, the output voltage value of the output terminal connected to the source of the NMOS transistor in the voltage output module is the input voltage value.

[0013] Further, when the input voltage is set to a high voltage, the branch where the NMOS transistor in the adaptive protection module is turned on; when the input voltage is configured to be a low voltage, the branch where the PMOS transistor in the adaptive protection module is turned on.

[0014] The beneficial effects of this application are as follows: (1) The circuit structure is simple. Compared with traditional LDO and DCDC voltage regulators, the structure of the present invention is simple, saving energy and resources.

[0015] (2) Wide-range voltage input. The adaptive protection module provides a wider range of voltage input to prevent the depletion-type output transistor from being broken down at high voltages.

[0016] (3) More flexible. The voltage source input range and output voltage value are simple to adjust, making it more flexible to use.

[0017] Other features and advantages of this application will be described in the following specification, and part of them will become obvious from the specification, or will be understood by implementing this application. The objectives and other advantages of this application can be achieved and obtained through the structures specifically pointed out in the written specification, claims, and drawings. Brief Description of the Drawings

[0018] In order to more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the following will briefly introduce the drawings required to be used in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on the provided drawings.

[0019] Figure 1 It is a schematic diagram of the typical structure of a traditional wide-input voltage LDO; Figure 2 It is a gallium nitride voltage regulator circuit with a wide power supply voltage range; Figure 3 It is a schematic diagram of each module in an adaptive voltage regulator circuit provided by an embodiment of this application; Figure 4 It is a gate terminal control circuit provided in another embodiment of this application; Figure 5 It is an equivalent circuit diagram of the low-voltage mode of the voltage regulator provided by an embodiment of this application; Figure 6 It is an equivalent circuit diagram of the high-voltage mode of the voltage regulator provided by an embodiment of this application; Figure 7 It is a simulation waveform diagram of the voltage regulator provided by an embodiment of this application; Figure 8 It is a load step response diagram provided by an embodiment of this application. Detailed implementation manners

[0020] To make the objectives, technical solutions and advantages of the present application clearer and more understandable, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are only a part rather than all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts shall fall within the scope of protection of the present application.

[0021] The present application provides an adaptive voltage regulator circuit, which adopts an innovative design. Through a simple circuit structure, it meets the requirements of a wide input voltage range, without relying on specific high-voltage-resistant devices, complex operational amplifier circuits, and compensation networks, and provides a stable voltage output; significantly reduces the circuit complexity, reduces the difficulty of manufacturing design, saves chip area, and improves the reliability of the circuit. It not only optimizes the circuit performance but also improves its economy, providing an efficient and reliable solution for the design of voltage regulators with a wide input voltage range.

[0022] The design concept of the embodiments of the present application will be briefly introduced below.

[0023] As Figure 3 shown, an adaptive voltage regulator circuit includes a gate control circuit, an adaptive protection module, and a voltage output module. In the embodiment shown in Figure 3 the circuit is connected as follows. In the gate control circuit, transistor M4 is a high-voltage-resistant LDMOS transistor. Its source is connected to the input voltage Vin, one branch connected to its gate is connected to the input voltage Vin after series-connected with a resistor R5, and the other branch connected to its gate is connected to ground after series-connected with a resistor R6 and M NMOS transistors. One branch connected to its drain is connected to ground after series-connected with a resistor R4, and the other branch connected to its drain is connected to the gates V1 of a pair of PMOS and NMOS transistors in the adaptive module after series-connected with a resistor R3, serving as the control terminal of its gate voltage; a capacitor is connected in parallel at one end of the resistor R3 and then grounded to stabilize the voltage of the control terminal.

[0024] In another embodiment, as Figure 4 shown, a voltage-regulating diode D2 is series-connected on the branch of the gate of transistor M4 in the gate control circuit where a resistor R6 is series-connected to protect the stability of the gate voltage.

[0025] In the adaptive module, V1 controls two connecting branches. One branch is connected to the gate of PMOS transistor M2, and the source of PMOS transistor M2 is connected to the input voltage Vin. The other branch is connected to the gate of NMOS transistor M3. The drain of NMOS transistor M3 is connected in series with N PMOS transistors and connected to the input voltage Vin, and its source is connected to the drain of PMOS transistor M2 and connected to the drain of NMOS transistor M1 in the voltage output module. NMOS transistor M1 in the voltage output module is a depletion-type MOS transistor, whose gate is connected to another output terminal of the gate control circuit. One end of the Zener diode D1 on the branch connected to this output terminal is grounded, and the other end is connected in series with resistor R2 to the Vin input voltage. One branch of the source of NMOS transistor M1 is connected in series with resistor R1 and grounded, and the other branch outputs the voltage Vout.

[0026] In the implementation of this circuit, the resistor R6 and M NMOS transistors connected in series in the gate control circuit can increase the gate voltage of M4. When the input voltage is lower than M*Vgsn, the M NMOS transistor string is not yet turned on, and the voltage regulator operates in the low-voltage mode, and its equivalent circuit is Figure 5 as shown; at this time, M4 is in the off state, and the gate potentials V1 of PMOS transistor M2 and NMOS transistor M3 in the adaptive protection module controlled by it are at low level. At this time, PMOS transistor M2 is turned on and NMOS transistor M3 is turned off. When the input voltage Vin is lower than the breakdown voltage Vd of the Zener diode D1, VDD_DET = Vin; NMOS transistor M1 in the voltage output module is a depletion-type MOS transistor, and at this time the output voltage Vout = VDD_DET = Vin. When the input voltage Vin is higher than the breakdown voltage Vd of the Zener diode D1, VDD_DET = Vd, and the drain voltage of transistor M1 is pulled up to Vin through M2, making it operate in the saturation region or subthreshold region. The source voltage of M1 is equal to the gate voltage, and the output remains constant Vout = Vd.

[0027] As Vin increases, the gate-drain voltage Vdgl of M1 gradually increases, and when it reaches the breakdown voltage, it will cause M1 to break down and the circuit to fail. Therefore, when the power supply voltage reaches (V gsn is the gate-source voltage of a single NMOS transistor in the NMOS transistor string), M4 transistor is turned on, and M4 pulls up the gate voltage V1 of M2 and M3 to Vin. PMOS transistor M2 is turned off and NMOS transistor M3 is turned on. The voltage regulator enters the high-voltage operating mode. At this time, its equivalent circuit is as Figure 6 shown. Due to the presence of N series-connected PMOS transistors, the drain voltage of M1 becomes Vin - N*V gs , where V gs is the gate-source voltage of a single PMOS in the PMOS transistor string, which makes V dglIt also decreases by N gate-source voltages, increasing the input voltage range of the voltage regulator. Eventually, the highest input voltage is approximately V D +V B +N*V gs ; As shown in Figure 7 is the simulation result of the circuit shown in Figure 3 . When the power supply voltage is approximately 10V, the circuit switches to the high-voltage operating mode, and the highest output voltage range can reach 18V; As shown in Figure 8 , it shows the output change when the load jumps from 0 mA to 1 mA at a speed of 10 mA / μs. The overshoot voltages for upward and downward jumps are 2.86V and 0.75V respectively.

[0028] Therefore, the voltage range received by this adaptive voltage regulator is less than or equal to (V D +V B +N*V gs )V. If you want to adjust the highest input voltage of the voltage regulator, you need to increase the number of several voltage-dividing components connected in series to the drain of the NMOS transistor M3 in the adaptive protection module or increase its voltage-dividing value, which can increase its input voltage range.

[0029] Compared with the prior art, the technical effects of the adaptive voltage regulator circuit of this application are as follows: The circuit structure is simple. Compared with traditional LDO and DCDC voltage regulators, the structure of this invention is simple, saving energy consumption and resources.

[0030] Wide range of voltage input. The adaptive protection module provides a wider range of voltage input to prevent the depletion-mode output transistor from being broken down at high voltages.

[0031] More flexible. The voltage source input range and output voltage value are simple to adjust and more flexible to use.

[0032] As described above, the above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. An adaptive voltage-stabilizing source circuit, comprising a gate control circuit, an adaptive protection module, and a voltage output module, characterized in that: The adaptive protection module comprises a pair of PMOS tubes and NMOS tubes connected in parallel at the gate, and a group of voltage divider elements are connected in series to the branch where the NMOS tube is located; one end of the gate control circuit is connected to the gates of the PMOS tube and the NMOS tube; the drain of the PMOS tube and the source of the NMOS tube are connected to one end of the voltage output module.

2. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: The group of split components includes a plurality of PMOS tubes.

3. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: The drain output end of the PMOS tube in the gate terminal control circuit that controls the gate voltage in the adaptive protection module is connected to the gates of the PMOS tube and the NMOS tube in the adaptive protection module.

4. The adaptive voltage stabilizing source circuit as claimed in claim 3, characterized in that: A gate branch of the PMOS tube controlling the gate voltage in the adaptive protection module in the gate terminal control circuit is connected in series with a group of components and grounded, and another branch is connected to the input voltage; the group of components includes a plurality of NMOS tubes.

5. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: The drain of the PMOS tube in the adaptive protection module and the source of the NMOS tube in the adaptive protection module are connected to the drain of the depletion-type NMOS tube for controlling the output voltage in the voltage output module.

6. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: The output end of the voltage output module is connected to the source of the depletion-type NMOS tube for controlling the output voltage in the voltage output module.

7. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: The gate control circuit and the adaptive protection module share the same input voltage.

8. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: The gate of the depletion-type NMOS tube for controlling the output voltage in the voltage output module is connected in parallel with a Zener diode in the gate-end control circuit, one end of which is connected to the input voltage and the other end is grounded; and the two share the same ground line.

9. The adaptive voltage stabilizing source circuit according to claim 8, characterized in that: When the input voltage is configured as a low voltage and the Zener diode is broken down, the output voltage value of the output end connected to the source end of the depletion-type NMOS tube in the voltage output module is the breakdown voltage value of the Zener diode; when the input voltage is configured as a low voltage and the Zener diode is not broken down, the output voltage value of the output end connected to the source end of the depletion-type NMOS tube in the voltage output module is the input voltage value.

10. The adaptive voltage stabilizing source circuit according to claim 1, characterized in that: When the input voltage is set to a high voltage, the branch where the NMOS tube in the adaptive protection module is located is turned on; when the input voltage is configured as a low voltage, the branch where the PMOS tube in the adaptive protection module is located is turned on.

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