SSD main control chip low-power-consumption high-precision RTC counting method, device and equipment and medium
By waking up the crystal oscillator clock in the low-power mode of SSD to obtain the timing deviation and calibrating the OSC clock, the problem of degradation of clock accuracy in the low-power mode is solved, and high-precision time synchronization and low-power consumption are achieved.
Patent Information
- Application Number
- CN202510117563.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-24
- Publication Date
- 2025-05-27
AI Technical Summary
In the low-power PS4 mode of SSD, the clock accuracy drops sharply, resulting in the SSD being unable to meet the time synchronization requirements with the host, and timing errors occur.
In low power consumption mode, wake up the crystal oscillator clock, obtain the timing deviation of the OSC clock of the SSD master chip, update the error value of the RTC timing, and perform error calibration of the OSC clock based on the error value, and turn off the crystal oscillator clock.
By calibrating the OSC clock in low power consumption mode, the timing error is effectively reduced, the system's time synchronization requirements are met, while maintaining low power consumption.
Smart Images
Figure CN120045016A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solid-state drive RTC counting, and particularly to a method, device, equipment and medium for low-power and high-precision RTC counting of an SSD main control chip. Background Art
[0002] The SOC chip of an SSD (Solid State Drives) needs to maintain extremely low power consumption in the low-power PS4 mode to meet the long-time standby requirements of the whole machine. In the PS4 mode, all high-power IPs will be powered off, and at this time, the clock accuracy of the system will also drop sharply.
[0003] However, in the PS4 mode, the SSD needs to maintain high accuracy to meet the time synchronization requirements with the host. Because the sharp drop in clock accuracy caused by the PS4 mode increases the timing error of the SSD system, there is a problem that the SSD cannot meet the synchronization with the host. Summary of the Invention
[0004] Embodiments of the present invention provide a method, device, equipment and medium for low-power and high-precision RTC counting of an SSD main control chip, aiming to solve at least one technical problem in the above background art.
[0005] In a first aspect, embodiments of the present invention provide a method for low-power and high-precision RTC counting of an SSD main control chip, which includes:
[0006] In the low-power mode, wake up the crystal oscillator clock, and obtain the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock;
[0007] Update the error value of the RTC timing according to the timing deviation, perform error calibration on the OSC clock based on the error value, and at the same time turn off the crystal oscillator clock.
[0008] A further technical solution thereof is that the step of waking up the crystal oscillator clock in the low-power mode includes:
[0009] In the low-power mode, wake up the crystal oscillator clock at intervals of a preset cycle time.
[0010] A further technical solution thereof is that the step of obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock includes:
[0011] Perform counting for a preset fixed duration through the crystal oscillator clock to obtain a first count value;
[0012] Obtain a second count value of the OSC clock within the fixed duration;
[0013] Calculate the difference between the first count value and the second count value as the timing deviation.
[0014] A further technical solution thereof is that updating the error value of the RTC timing according to the timing deviation includes:
[0015] Configure the timing deviation into the error register of the RTC.
[0016] A further technical solution thereof is that performing error calibration on the OSC clock based on the error value includes:
[0017] Periodically calibrate the count value of the OSC clock based on the error value.
[0018] A further technical solution thereof is that the method further includes:
[0019] Before entering the low-power mode, execute the steps of obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock; updating the error value of the RTC timing according to the timing deviation, performing error calibration on the OSC clock based on the error value, and simultaneously turning off the crystal oscillator clock.
[0020] A further technical solution thereof is that the method further includes:
[0021] If exiting the low-power mode, switch the clock of the RTC back to the crystal oscillator clock for counting, and simultaneously modify the error value of the RTC timing to 0.
[0022] In a second aspect, an embodiment of the present invention further provides a low-power and high-precision RTC counting device for an SSD main control chip, which includes a unit for executing the above method.
[0023] In a third aspect, an embodiment of the present invention further provides a computer device, which includes a memory and a processor, where a computer program is stored on the memory, and when the processor executes the computer program, the above method is implemented.
[0024] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, where the storage medium stores a computer program, and when the computer program is executed by a processor, the above method can be implemented.
[0025] An embodiment of the present invention provides a method, device, equipment and medium for low-power and high-precision RTC counting of an SSD main control chip. Among them, the method includes: in the low-power mode, waking up the crystal oscillator clock, obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock; updating the error value of the RTC timing according to the timing deviation, and performing error calibration on the OSC clock based on the error value, and at the same time turning off the crystal oscillator clock; in the embodiment of the present invention, by waking up the crystal oscillator clock in the low-power mode to calibrate the OSC clock, the timing error in the low-power mode is calibrated, meeting the error requirements of the system, and at the same time the power consumption is also kept within the index range allowed by the low power consumption. Description of the Drawings
[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.
[0027] Figure 1 It is a schematic flowchart of a method for low-power and high-precision RTC counting of an SSD main control chip provided by an embodiment of the present invention;
[0028] Figure 2 It is a structural block diagram of high-precision RTC counting in the low-power mode in the embodiment of the present invention;
[0029] Figure 3 It is a schematic block diagram of a computer device provided by an embodiment of the present invention. Detailed Embodiments
[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.
[0031] It should be understood that when used in this specification and the appended claims, the terms "comprises" and "comprising" indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their combinations.
[0032] It should also be understood that the terms used in the description of the present invention herein are for the purpose of describing specific embodiments only and are not intended to limit the present invention. As used in the description of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include the plural forms.
[0033] It should be further understood that the term "and / or" used in the description of the present invention and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.
[0034] As used in this specification and the appended claims, the term "if" may be construed, depending on the context, as "when", "once", "in response to determining", or "in response to detecting". Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, as meaning "once determined", "in response to determining", "once [the described condition or event] is detected", or "in response to detecting [the described condition or event]".
[0035] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a low-power and high-precision RTC counting method for an SSD main control chip provided by an embodiment of the present invention. As Figure 1 shown, the method includes the following steps:
[0036] S1, in the low-power mode, wake up the crystal oscillator clock, and obtain the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock.
[0037] In specific implementation, the low-power mode of the SSD main control chip may specifically be the PS4 mode. Generally, in the low-power mode, in order to save power, the crystal oscillator clock is turned off. In the embodiment of the present invention, in order to accurately time, in the low-power mode, the crystal oscillator clock is briefly woken up, and the timing deviation of the OSC clock of the SSD main control chip is obtained based on the crystal oscillator clock.
[0038] Specifically, in some embodiments, such as this embodiment, the above step "in the low-power mode, wake up the crystal oscillator clock" specifically includes the following steps: in the low-power mode, wake up the crystal oscillator clock every preset cycle time.
[0039] In specific implementation, the cycle time can be set by those skilled in the art, and the present invention does not specifically limit this. By periodically waking up the crystal oscillator clock in the low-power mode and obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock, the timing accuracy in the low-power mode can be greatly improved.
[0040] In some embodiments, such as this embodiment, the above step of "obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock" specifically includes the following steps: counting for a preset fixed duration through the crystal oscillator clock to obtain a first count value; obtaining a second count value of the OSC clock within the fixed duration; calculating the difference between the first count value and the second count value as the timing deviation.
[0041] In specific implementation, the fixed duration can specifically be the duration corresponding to the preset count of the crystal oscillator clock, such as the duration corresponding to counting 1000. Further, obtain the second count value of the OSC clock within the fixed duration; calculate the difference between the first count value and the second count value as the timing deviation.
[0042] S2. Update the error value of the RTC timing according to the timing deviation, perform error calibration on the OSC clock based on the error value, and at the same time turn off the crystal oscillator clock.
[0043] In specific implementation, update the error value of the RTC timing according to the timing deviation. In some embodiments, the error value of the RTC timing is stored in the error register of the RTC. Therefore, configure the timing deviation into the error register of the RTC to achieve the update of the error value of the RTC timing.
[0044] Further, perform error calibration on the OSC clock based on the error value to achieve accurate timing in the low-power mode. At the same time, turn off the crystal oscillator clock and the calibration circuit to achieve power saving.
[0045] In some embodiments, the above step of "performing error calibration on the OSC clock based on the error value" includes: periodically calibrating the count value of the OSC clock based on the error value.
[0046] In specific implementation, in the low-power mode, the RTC uses the OSC clock for counting, and adjusts and compensates the RTC value periodically according to the configured error value. The period value of the periodic adjustment is configured by software, and this value is equal to the period range value corresponding to the configured error, that is, the fixed duration corresponding to calculating the error value in the above step S1.
[0047] See Figure 2 , Figure 2This is the structural block diagram of high-precision RTC counting in the low-power mode in the embodiments of the present invention. In this method, two modules, namely a wake-up control module and a calibration circuit module, are added on the basis of the original circuit. The calibration circuit is responsible for generating an indication of a fixed time length based on the timer value when counting with a high-precision clock timer, and counting (CNT) using the OSC clock within this indication window, and calculating the difference between the calculated CNT value of the OSC clock and the window length generated by the high-precision timer. This difference is the counting deviation of the OSC clock within this fixed window. Finally, this deviation is converted into the error of the OSC clock when counting the timer, and the timer is compensated.
[0048] The wake-up control is used to control the wake-up and shutdown of the high-precision clock in the low-power mode, ensuring that the accuracy can still meet the high-precision requirements when the temperature and voltage change in the low-power mode, and at the same time the overall power consumption is also below the low-power index.
[0049] Module description:
[0050] 1. Timer: RTC counter, used to count the absolute time of the system.
[0051] 2. Calibration circuit: used to calculate the precision deviation of the OSC clock using a high-precision clock.
[0052] 3. Wake-up control: used to control the turn-on and turn-off of the high-precision clock in the low-power mode.
[0053] CNT: Counter that uses the OSC clock during error calibration, counts within a fixed window, and calculates the error of the OSC clock based on the counting result of CNT.
[0054] Furthermore, in some embodiments, before entering the low-power mode, the steps of obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock, updating the error value of the RTC timing according to the timing deviation, and performing error calibration on the OSC clock based on the error value while turning off the crystal oscillator clock are executed, so that the OSC clock can be calibrated before entering the sleep state, improving the accuracy of timing in the sleep mode.
[0055] Furthermore, in some embodiments, the method further includes: if exiting the low-power mode, switching the clock of the RTC back to the crystal oscillator clock for counting, and at the same time modifying the error value of the RTC timing to 0. When not in the low-power mode, the crystal oscillator clock is used for counting, ensuring the accuracy of timing. At the same time, when counting using the crystal oscillator clock, no calibration is required, so the error value of the RTC timing is modified to 0.
[0056] Furthermore, when the chip needs to enter the low-power mode again in the normal mode, the calibration process before entering the low-power mode again is performed.
[0057] An embodiment of the present invention provides a method for low-power and high-precision RTC counting of an SSD main control chip, including: in a low-power mode, waking up the crystal oscillator clock, obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock; updating the error value of the RTC timing according to the timing deviation, and performing error calibration on the OSC clock based on the error value, and at the same time turning off the crystal oscillator clock; in the embodiment of the present invention, by waking up the crystal oscillator clock in the low-power mode to calibrate the OSC clock, the timing error in the low-power mode is calibrated to meet the error requirements of the system, and at the same time the power consumption is also kept within the index range allowed by the low power consumption.
[0058] Corresponding to the above method for low-power and high-precision RTC counting of an SSD main control chip, the present invention also provides a device for low-power and high-precision RTC counting of an SSD main control chip. The device for low-power and high-precision RTC counting of an SSD main control chip includes units for executing the above method for low-power and high-precision RTC counting of an SSD main control chip, and the device for low-power and high-precision RTC counting of an SSD main control chip can be configured in a terminal. Specifically, the device for low-power and high-precision RTC counting of an SSD main control chip includes:
[0059] A wake-up unit, configured to wake up the crystal oscillator clock in a low-power mode, and obtain the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock;
[0060] A calibration unit, configured to update the error value of the RTC timing according to the timing deviation, perform error calibration on the OSC clock based on the error value, and at the same time turn off the crystal oscillator clock.
[0061] In some embodiments, such as this embodiment, the waking up the crystal oscillator clock in the low-power mode includes:
[0062] In the low-power mode, waking up the crystal oscillator clock at intervals of a preset cycle time.
[0063] In some embodiments, such as this embodiment, the obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock includes:
[0064] Performing counting for a preset fixed duration through the crystal oscillator clock to obtain a first count value;
[0065] Obtaining a second count value of the OSC clock within the fixed duration;
[0066] Calculating the difference between the first count value and the second count value as the timing deviation.
[0067] In some embodiments, such as this embodiment, updating the error value of the RTC timing according to the timing deviation includes:
[0068] Configuring the timing deviation into the error register of the RTC.
[0069] In some embodiments, such as this embodiment, performing error calibration on the OSC clock based on the error value includes:
[0070] Periodically calibrating the count value of the OSC clock based on the error value.
[0071] In some embodiments, such as this embodiment, the low-power high-precision RTC counting device of the SSD main control chip further includes:
[0072] An execution unit, configured to, before entering the low-power mode, execute the steps of obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock; updating the error value of the RTC timing according to the timing deviation, performing error calibration on the OSC clock based on the error value, and simultaneously turning off the crystal oscillator clock.
[0073] In some embodiments, such as this embodiment, the low-power high-precision RTC counting device of the SSD main control chip further includes:
[0074] A switching unit, configured to, if exiting the low-power mode, switch the clock of the RTC back to the crystal oscillator clock for counting, and simultaneously modify the error value of the RTC timing to 0.
[0075] It should be noted that those skilled in the art can clearly understand that the specific implementation processes of the above-mentioned low-power high-precision RTC counting device of the SSD main control chip and each unit can refer to the corresponding descriptions in the foregoing method embodiments. For the sake of convenience and brevity of description, they will not be elaborated here.
[0076] The above-mentioned low-power high-precision RTC counting device of the SSD main control chip can be implemented in the form of a computer program, and this computer program can run on a computer device as shown in Figure 3 shown.
[0077] Please refer to Figure 3 , Figure 3 which is a schematic block diagram of a computer device provided by an embodiment of the present application. The computer device 500 can be a terminal or a server.
[0078] The computer device 500 includes a processor 502, a memory, and a network interface 505 connected through a system bus 501. Among them, the memory can include a non-volatile storage medium 503 and an internal memory 504.
[0079] The non-volatile storage medium 503 can store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, it can cause the processor 502 to execute a low-power and high-precision RTC counting method for an SSD main control chip.
[0080] The processor 502 is used to provide computing and control capabilities to support the operation of the entire computer device 500.
[0081] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, it can cause the processor 502 to execute a low-power and high-precision RTC counting method for an SSD main control chip.
[0082] The network interface 505 is used for network communication with other devices. Those skilled in the art can understand that the above structure is only a block diagram of some structures related to the solution of this application, and does not constitute a limitation on the computer device 500 to which the solution of this application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.
[0083] Among them, the processor 502 is used to run the computer program 5032 stored in the memory to implement the steps of the low-power and high-precision RTC counting method for the SSD main control chip, specifically including the following steps:
[0084] In the low-power mode, wake up the crystal oscillator clock, and obtain the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock;
[0085] Update the error value of the RTC timing according to the timing deviation, perform error calibration on the OSC clock based on the error value, and at the same time turn off the crystal oscillator clock.
[0086] In some embodiments, such as this embodiment, the waking up the crystal oscillator clock in the low-power mode includes:
[0087] In the low-power mode, wake up the crystal oscillator clock at intervals of a preset cycle time.
[0088] In some embodiments, such as this embodiment, the obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock includes:
[0089] Perform counting for a preset fixed duration through the crystal oscillator clock to obtain a first count value;
[0090] Obtain a second count value of the OSC clock within the fixed duration;
[0091] Calculate the difference between the first count value and the second count value as the timing deviation.
[0092] In some embodiments, such as this embodiment, the updating the error value of the RTC timing according to the timing deviation includes:
[0093] Configure the timing deviation into the error register of the RTC.
[0094] In some embodiments, such as this embodiment, the error calibration of the OSC clock based on the error value includes:
[0095] Periodically calibrate the count value of the OSC clock based on the error value.
[0096] In some embodiments, such as this embodiment, the method further includes:
[0097] Before entering the low power mode, execute the steps of obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock; updating the error value of the RTC timing according to the timing deviation, performing error calibration on the OSC clock based on the error value, and at the same time turning off the crystal oscillator clock.
[0098] In some embodiments, such as this embodiment, the method further includes:
[0099] If exiting the low power mode, switch the RTC clock back to the crystal oscillator clock for counting, and at the same time modify the error value of the RTC timing to 0.
[0100] It should be understood that in the embodiments of the present application, the processor 502 may be a central processing unit (CPU), and the processor 502 may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0101] Those of ordinary skill in the art can understand that all or part of the processes in the methods of implementing the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a storage medium, and the storage medium is a computer-readable storage medium. The computer program is executed by at least one processor in the computer system to implement the process steps of the above method embodiments.
[0102] Therefore, the present invention also provides a storage medium. The storage medium can be a computer-readable storage medium. The storage medium stores a computer program. When the computer program is executed by a processor, the processor performs the following steps:
[0103] In the low-power mode, wake up the crystal oscillator clock, and obtain the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock;
[0104] According to the timing deviation, update the error value of the RTC timing, and perform error calibration on the OSC clock based on the error value, and at the same time turn off the crystal oscillator clock.
[0105] In some embodiments, such as this embodiment, the waking up the crystal oscillator clock in the low-power mode includes:
[0106] In the low-power mode, wake up the crystal oscillator clock at intervals of a preset cycle time.
[0107] In some embodiments, such as this embodiment, the obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock includes:
[0108] Perform counting for a preset fixed duration through the crystal oscillator clock to obtain a first count value;
[0109] Obtain a second count value of the OSC clock within the fixed duration;
[0110] Calculate the difference between the first count value and the second count value as the timing deviation.
[0111] In some embodiments, such as this embodiment, the updating the error value of the RTC timing according to the timing deviation includes:
[0112] Configure the timing deviation into the error register of the RTC.
[0113] In some embodiments, such as this embodiment, the performing error calibration on the OSC clock based on the error value includes:
[0114] Periodically calibrate the count value of the OSC clock based on the error value.
[0115] In some embodiments, such as this embodiment, the method further includes:
[0116] Before entering the low-power mode, perform obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock; update the error value of the RTC timing according to the timing deviation, perform error calibration on the OSC clock based on the error value, and at the same time turn off the crystal oscillator clock.
[0117] In some embodiments, such as this embodiment, the method further includes:
[0118] If exiting the low-power mode, switch the clock of the RTC back to the crystal oscillator clock for counting, and at the same time modify the error value of the RTC timing to 0.
[0119] The storage medium is a physical, non-transitory storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disc, etc., various physical storage media that can store program codes. The computer-readable storage medium can be non-volatile or volatile.
[0120] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.
[0121] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of each unit is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.
[0122] The steps in the method embodiments of the present invention can be adjusted, combined, and deleted according to actual needs. The units in the device embodiments of the present invention can be combined, divided, and deleted according to actual needs. In addition, the functional units in each embodiment of the present invention can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit.
[0123] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on such an understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention.
[0124] In the above embodiments, the descriptions of the various embodiments have their own emphases. For the parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0125] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.
[0126] As described above, the above are only the specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A low-power and high-precision RTC counting method for an SSD master control chip, characterized in that: include: In the low power consumption mode, the crystal oscillator clock is awakened, and the timing deviation of the OSC clock of the SSD main control chip is obtained based on the crystal oscillator clock; The error value of the RTC timing is updated according to the timing deviation, the error of the OSC clock is calibrated based on the error value, and the crystal oscillator clock is turned off at the same time.
2. The low-power and high-precision RTC counting method of the SSD master control chip according to claim 1 is characterized in that: The step of waking up the crystal oscillator clock in the low power consumption mode includes: In low power mode, the crystal oscillator clock is awakened at preset cycle time intervals.
3. The low-power and high-precision RTC counting method of the SSD master control chip according to claim 1 is characterized in that: The obtaining the timing deviation of the OSC clock of the SSD main control chip based on the crystal oscillator clock includes: Counting a preset fixed time length by using the crystal oscillator clock to obtain a first count value; Obtaining a second count value of the OSC clock within the fixed duration; A difference between the first count value and the second count value is calculated as the timing deviation.
4. The low-power and high-precision RTC counting method of the SSD master control chip according to claim 1, characterized in that: The updating of the RTC timing error value according to the timing deviation includes: The timing deviation is configured into the error register of the RTC.
5. The low-power and high-precision RTC counting method of the SSD master control chip according to claim 1, characterized in that: The error calibration of the OSC clock based on the error value comprises: The count value of the OSC clock is periodically calibrated based on the error value.
6. The low-power and high-precision RTC counting method of the SSD master control chip according to claim 1, characterized in that: The method further comprises: Before entering the low power consumption mode, the steps of obtaining the timing deviation of the OSC clock of the SSD master control chip based on the crystal oscillator clock, updating the error value of the RTC timing according to the timing deviation, performing error calibration on the OSC clock based on the error value, and shutting down the crystal oscillator clock are performed.
7. The low-power and high-precision RTC counting method of the SSD master control chip according to claim 1, characterized in that: The method further comprises: If you exit the low power mode, switch the RTC clock back to the crystal oscillator clock for counting, and modify the RTC timing error value to 0.
8. A low-power and high-precision RTC counting device for an SSD main control chip, characterized in that: The method comprises a unit for executing the method according to any one of claims 1 to 7.
9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 1 to 7 can be implemented.