Message processing module, data processing method, processor and chip

Abstract

The invention relates to a message processing module, a data processing method, a processor and a chip, and the method comprises the steps: an instruction decoding module decodes a network acceleration instruction to obtain a first read address and a first operation code, and transmits the first read address and the first operation code to an instruction pipeline processing logic module; the network acceleration instruction refers to a self-defined instruction generated based on an RISC-V standard instruction; the instruction pipeline processing logic module sends the first read address to a Fast RegFile module; the Fast RegFile module outputs data corresponding to the first read address to the Inbuffer; the Fast RegFile module is a data storage unit realized by adopting a register; the Inbuffer outputs a first source operand stored in the Inbuffer to an instruction pipeline processing logic module according to data corresponding to the first read address; the instruction pipeline processing logic module operates the first source operand according to the first operation code; the network acceleration instruction can be efficiently processed, and the performance of the network processor is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and particularly to a message processing module, a data processing method, a network processor, and a chip. Background Art

[0002] A multi-core and multi-threaded network processor is an efficient way to process network data packet flows. By leveraging multiple cores (Cores) and multiple threads (Threads) to process data flows in parallel, it achieves high throughput and low latency. Figure 1 As a schematic diagram of a message processing module of a network processor, in Figure 1 the message processing module, the register file module and the Inbuffer are designed in a parallel access form to improve the processing speed of the message processor.

[0003] However, there is a special instruction in the message instructions. This type of special instruction needs to sequentially read the storage structure twice to obtain the source operand, that is, read the data in the first storage structure, and use the read data as the read address for reading the second storage structure, so as to obtain the source operand. Obviously, Figure 1 in the message processing module of Figure 1 since the register file module and the Inbuffer module are designed for parallel access, the register file module cannot provide the data (i.e., the address for accessing the Inbuffer) required by the Inbuffer before the end of the current clock cycle, resulting in the Inbuffer ignoring the data output by the register file module and causing the source data reading to fail. Thus, the message processing module in

[0004] cannot process this type of network acceleration instruction, resulting in poor performance of the message processing module. Summary of the Invention

[0004] The purpose of this application is to propose a message processing module, a data processing method, a network processor, and a chip to improve the performance of the network processor.

[0005] An embodiment of this application provides a message processing module, including an instruction decoding module, an instruction pipeline processing logic module, a Fast RegFile module, and an Inbuffer; The instruction decoding module is configured to receive a network acceleration instruction, decode the network acceleration instruction to obtain a first read address and a first operation code, and send the first read address and the first operation code to the instruction pipeline processing logic module; the network acceleration instruction refers to a custom instruction generated based on the RISC-V standard instruction; The instruction pipeline processing logic module is configured to send the first read address to the Fast RegFile module; The Fast RegFile module is used to output the data stored therein corresponding to the first read address to the Inbuffer; the Fast RegFile module is a data storage unit implemented by registers and includes a plurality of general-purpose registers; The Inbuffer is used to output the first source operand stored therein to the instruction pipeline processing logic module according to the data corresponding to the first read address; The instruction pipeline processing logic module is further used to operate on the first source operand according to the first operation code.

[0006] In some solutions, a register file module is further included; The instruction decoding module is further used to receive general instructions, decode the general instructions to obtain a second read address and a second operation code, and send the second read address and the second operation code to the instruction pipeline processing logic module; the general instructions refer to RISC-V standard instructions; The instruction pipeline processing logic module is further used to send the second read address to the register file module; The register file module is used to output the second source operand stored therein to the instruction pipeline processing logic module according to the second read address; the register file module is a data storage unit implemented by a random access memory; The instruction pipeline processing logic module is further used to operate on the second source operand according to the second operation code.

[0007] In some solutions, the Fast RegFile module includes a first write data module, a first address indexing unit, and a register component, and the register component includes a plurality of registers; The first write data module is used to receive a write instruction and write the data to be written into the register component for storage according to the write instruction; The first address indexing unit is used to generate a first read command according to the first read address; The register component is used to output the data stored therein corresponding to the first read address to the Inbuffer according to the first read command.

[0008] In some solutions, the register file module includes a second write data module, a second address indexing unit, a random access memory, and an ECC check module; The second write data module is used to receive a second write instruction and write the second source operand into the RAM for storage according to the second write instruction; The second address indexing unit is used to generate a second read command according to the second read address; The random access memory is used to output the second source operand according to the second read command; The ECC check module is used to check the second source operand and use it as the output data of the current read access.

[0009] An embodiment of the present application further provides a data processing method. The method is implemented based on the above-mentioned packet processing module, and the method includes: The instruction decoding module receives a network acceleration instruction, decodes the network acceleration instruction to obtain a first read address and a first operation code, and sends the first read address and the first operation code to the instruction pipeline processing logic module; the network acceleration instruction is a custom instruction generated based on the RISC-V standard instruction; The instruction pipeline processing logic module sends the first read address to the Fast RegFile module; The Fast RegFile module outputs the data stored therein corresponding to the first read address to the Inbuffer; The Inbuffer outputs the first source operand stored therein corresponding to the data corresponding to the first read address to the instruction pipeline processing logic module; The instruction pipeline processing logic module operates on the first source operand according to the first operation code.

[0010] In some solutions, the packet processing module further includes a register file module; The instruction decoding module receives a general instruction, decodes the general instruction to obtain a second read address and a second operation code, and sends the second read address and the second operation code to the instruction pipeline processing logic module; the general instruction refers to the RISC-V standard instruction; The instruction pipeline processing logic module sends the second read address to the register file module; The register file module outputs the second source operand stored therein according to the second read address to the instruction pipeline processing logic module; The instruction pipeline processing logic module operates on the second source operand according to the second operation code.

[0011] In some solutions, the Fast RegFile module includes a first write data module, a first address indexing unit, and a register component, and the register component includes a plurality of registers; The first write data module receives a write instruction and writes the data to be written into the register component for storage according to the write instruction; The first address indexing unit generates a first read command according to the first read address; The register component outputs the data stored corresponding to the first read address to the Inbuffer according to the first read command.

[0012] In some solutions, the register file module includes a second write data module, a second address indexing unit, a random access memory, and an ECC verification module; The second write data module receives a second write instruction and writes the first source operand into the random access memory for storage according to the second write instruction; The second address indexing unit generates a second read command according to the second read address; The random access memory outputs the second source operand according to the second read command; The ECC verification module verifies the second source operand and uses it as the output data for the current read access.

[0013] An embodiment of the present application further provides a network processor, including the packet processing module described in the above embodiment.

[0014] An embodiment of the present application further provides a chip, including the network processor described in the above embodiment.

[0015] The embodiment of the present application provides a packet processing module, a data processing method, a network processor, and a chip. The packet processing module includes an instruction decoding module, an instruction pipeline processing logic module, a Fast RegFile module, and an Inbuffer. The instruction decoding module receives a network acceleration instruction (a custom instruction generated based on the RISC-V standard instruction, that is, the special type of instruction mentioned in the background art), decodes the network acceleration instruction to obtain a first read address and a first operation code, and sends the first read address and the first operation code to the instruction pipeline processing logic module. The instruction pipeline processing logic module sends the first read address to the Fast RegFile module. The Fast RegFile module outputs the data stored therein corresponding to the first read address to the Inbuffer. The Inbuffer outputs the first source operand stored therein to the instruction pipeline processing logic module according to the data corresponding to the first read address, completing the reading of the source operand. It should be noted that the Fast RegFile module is a data storage unit implemented by a register built with a hardware circuit. Compared with implementing the RISC-V general register function using a RAM, the Fast RegFile module in this embodiment can achieve fast response, output the data stored therein corresponding to the first read address to the Inbuffer before the end of this cycle, thereby realizing the processing of this type of instruction. In addition, the instruction pipeline processing logic module only needs to initiate one read access to the Fast RegFile module to read the corresponding source operand, realizing the reading of the source operand in 3 clock cycles, shortening the time required to process data, and greatly improving the performance of the network processor. Description of the Drawings

[0016] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 It is a schematic diagram of the packet processing module of the network processor disclosed in the background art part.

[0018] Figure 2 It is a schematic diagram of the structure of a packet processing module in an embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of the structure of a packet processing module in another embodiment of the present application.

[0020] Figure 4Schematic diagram of the structure of the Fast RegFile module in an embodiment of the present application.

[0021] Figure 5 Schematic diagram of the structure of the register file module in an embodiment of the present application.

[0022] Figure 6 Flowchart of a data processing method in an embodiment of the present application. Detailed description of the specific implementation

[0023] The detailed description of the drawings is intended to illustrate some embodiments of the present application, rather than representing the only form in which the present application can be implemented. It should be understood that the same or equivalent functions can be completed by different embodiments intended to be included within the spirit and scope of the present application.

[0024] Refer to Figure 2 , an embodiment of the present application provides a message processing module, including an instruction decoding module, an instruction pipeline processing logic module, a Fast RegFile module, and an Inbuffer; The instruction decoding module is configured to receive a network acceleration instruction, decode the network acceleration instruction to obtain a first read address and a first operation code, and send the first read address and the first operation code to the instruction pipeline processing logic module; the network acceleration instruction refers to a custom instruction generated based on the RISC-V standard instruction; Specifically, RISC-V (Reduced Instruction Set Computing - V) is an open instruction set architecture (ISA) with a concise instruction set and scalability. For example, Load and Store instructions are used for data loading and storing operations, such as LW, SW, etc.; for another example, Arithmetic and Logical instructions are used to perform arithmetic and logical operations, such as ADD, SUB, AND, OR, etc.; for another example, Control Transfer instructions are used to implement program flow control, such as JUMP, BRANCH, etc.; for another example, Conditional Branch instructions are used to perform branch jumps according to specific conditions, such as BEQ, BNE, etc.; for another example, Compare and Branch instructions are used to perform comparison operations and branch jumps according to the results, such as SLT, SLTU, etc.; for another example, Shift and Rotate instructions are used to perform shift or rotation operations on data, such as SLL, SRL, etc.; for another example, Immediate Value Operations instructions are used to perform operations on the immediate number and the value in the register, such as ADDI, ANDI, etc.; for another example, System Level Instructions are used to access system resources or perform privileged operations, such as ECALL, MRET, etc.; the above are only part of the standard instructions in the RISC-V ISA. In fact, RISC-V also supports more instructions and allows users to customize and extend instructions according to needs. This flexibility makes RISC-V highly customizable and adaptable in various application scenarios. The network acceleration instruction in this embodiment refers to a custom instruction generated based on the RISC-V standard instructions.

[0025] The instruction pipeline processing logic module is configured to send the first read address to the Fast RegFile module; The Fast RegFile module is configured to output the data stored therein corresponding to the first read address to the Inbuffer; the Fast RegFile module is a data storage unit implemented by a register built with a hardware circuit; The Inbuffer is configured to output the first source operand stored therein to the instruction pipeline processing logic module according to the data corresponding to the first read address; Specifically, the Inbuffer belongs to a custom data structure specifically used for custom instructions of a network processor and is used to store cell information and Meta information of packets in the network packet processing flow.

[0026] The instruction pipeline processing logic module is further configured to operate on the first source operand according to the first operation code; Based on the above description, it can be seen that this embodiment mainly improves the source operand reading step in the process of processing instructions in the backend pipeline, and provides a packet processing module. The packet processing module receives a network acceleration instruction (a custom instruction generated based on the RISC-V standard instruction, that is, the special type of instruction mentioned in the background technology) through the instruction decoding module, decodes the network acceleration instruction to obtain a first read address and a first operation code, and sends the first read address and the first operation code to the instruction pipeline processing logic module; the instruction pipeline processing logic module sends the first read address to the Fast RegFile module; the Fast RegFile module outputs the data stored in it corresponding to the first read address to the Inbuffer; the Inbuffer outputs the first source operand stored in it to the instruction pipeline processing logic module according to the data corresponding to the first read address, completing the reading of the source operand. It should be noted that the Fast RegFile module is a data storage unit implemented by registers and includes a plurality of general-purpose registers. Compared with implementing the RISC-V general-purpose register function using RAM, the Fast RegFile module in this embodiment can achieve fast response and output the data stored in it corresponding to the first read address to the Inbuffer before the end of this cycle, thereby realizing the processing of this type of instruction. In addition, the instruction pipeline processing logic module only needs to initiate one read access to the Fast RegFile module to read the corresponding source operand, realizing the reading of the source operand in 3 clock cycles, shortening the time required to process data, and greatly improving the performance of the network processor.

[0027] In some embodiments, referring to Figure 3 , the packet processing module further includes a register file module (GPRRegFile); The instruction decoding module is further configured to receive a general instruction, decode the general instruction to obtain a second read address and a second operation code, and send the second read address and the second operation code to the instruction pipeline processing logic module; the general instruction refers to the RISC-V standard instruction; The instruction pipeline processing logic module is further configured to send the second read address to the register file module; The register file module is configured to output a second source operand stored therein to the instruction pipeline processing logic module according to the second read address; the register file module is a data storage unit implemented by using a random access memory (RAM). The instruction pipeline processing logic module is further configured to operate on the second source operand according to the second operation code. Specifically, in this embodiment, the instruction pipeline processing logic module can be used to process the general instruction and the network acceleration instruction. The register file module is a data storage unit implemented by using a random access memory. The register file module is divided into multiple storage units according to addresses in the RAM, and each storage unit corresponds to a GPR (General Purpose Register, abbreviated as GPR); the Fast RegFile module is a data storage unit implemented by using a register built by a hardware circuit.

[0028] It should be noted that from the software perspective, assuming that the Fast RegFile module includes m GPRs, there are m GPRs in the register file module whose stored data is the same as that of the m GPRs in the Fast RegFile module. When writing to the m GPRs in the Fast RegFile module, the m GPRs in the register file module will also be written simultaneously. However, when processing the network acceleration instruction, the instruction decoding module decodes the network acceleration instruction to obtain a first read address and a first operation code, and sends the first read address and the first operation code to the instruction pipeline processing logic module. The first read address is the address of the GPR implemented by the storage unit in the RAM. However, the instruction pipeline processing logic module does not read data from the register file module according to the first read address, but reads data from the m GPRs in the Fast RegFile module according to the first read address, that is, sends the first read address to the FastRegFile module; the addresses of the m GPRs in the register file module and the m GPRs in the Fast RegFile module are in one-to-one correspondence.

[0029] When processing the general instruction, the instruction decoding module decodes the network acceleration instruction to obtain a second read address and a second operation code, and sends the second read address and the second operation code to the instruction pipeline processing logic module. The second read address is the address of the GPR implemented by the storage unit in the RAM, and the instruction pipeline processing logic module reads data from the register file module according to the second read address.

[0030] It should be understood that each thread has an independent register file (RegFile), which avoids sharing a set of registers among threads and prevents interference between threads, enabling multi-threaded programs to run correctly. The number and structure of GPRs in the Fast RegFile module depend on the design of the CPU used. In some CPUs, the number of GPRs is relatively small, while in others, there are more GPRs. GPRs are typically used to perform arithmetic and logical operations, save temporary variables and return values during function calls and returns, and save instruction addresses during jumps, etc. Therefore, the number of GPRs in the Fast RegFile module can be determined according to the actual situation.

[0031] For example, the instruction pipeline processing logic module of a network processor can adopt a 7-stage pipeline, namely the RR0 pipeline stage, RR1 pipeline stage, RR2 pipeline stage, EX pipeline stage, M0 pipeline stage, M1 pipeline stage, and WB pipeline stage. The RR0 pipeline stage is used to cache the signals decoded by the decoding module and also to initiate read operations on the register file module and the Fast RegFile module. The instruction pipeline processing logic module has a feed-forward network (bypass network), and the main function of the bypass network is to send the latest data, register index, and TID information generated by the EALU and WB into the bypass network for subsequent instructions to reference. In the RR0 stage, if the source operand appears on the bypass network, then the data on the bypass network needs to be given priority as the latest value of the source operand, and then RR0 gates this data to this stage and latches it into the RRI when the clock rising edge arrives. In the RR1 stage, if the source operand used by the instruction appears on the bypass network, then regardless of whether the valid field of the source operand in the pipeline signal has been set to true, the data on the bypass network is gated into this stage of the pipeline and waits for the pipeline to flow to the next stage EX, and at the same time, the valid field of the source operand is set to true. In the RR2 stage, if the source operand used by the instruction appears on the bypass network, then regardless of whether the valid field of the source operand in the pipeline signal has been set to true, the data on the bypass network is gated into this stage of the pipeline and waits for the pipeline to flow to the next stage EX.

[0032] In the EX stage, the main functions include: 1. Responsible for arithmetic and logical operations, memory access address, jump judgment, target address calculation of branch instructions, byte swap operation, bit operation, etc.; 2. Receive the bit data output by the Inbuffer; 3. Send the latest read data into the bypass network.

[0033] The M0 and M1 stages are the times for coordinating DTCM memory access. At the same time, the read data of each stage on the pipeline is sent to the bypass channel. This stage mainly coordinates with the 3-cycle read process of DTCM. At the same time, the read data in M0 and M1 is sent to the bypass network for subsequent instructions to use.

[0034] The WB stage is the last stage of single-cycle instruction execution. If there is data that needs to be written back to the GPR in this stage, then it directly occupies the write port of the register file module with the highest priority.

[0035] The WB stage needs to process: 1. Send the latest read data on the pipeline to the bypass, 2. Write the register file module and the Fast RegFile module.

[0036] In some embodiments, refer to Figure 4 , the Fast RegFile module includes a first write data module, a first address indexing unit, and a register component; The first write data module is used to receive a write instruction and write the data to be written into the register component for storage according to the write instruction; the write instruction includes the data to be written (the aforementioned "data corresponding to the first read address") and the corresponding write address, and the write address is the same as the first read address; The first address indexing unit is used to generate a first read command according to the first read address; specifically, in the source operand reading step, the instruction pipeline processing logic module obtains the corresponding first read address according to the network acceleration instruction, sends the first read address to the Fast RegFile module, the Fast RegFile module receives the first read address, generates a first read command through the first address indexing unit, and sends it to the register component; The register component is used to output the "data corresponding to the first read address" stored in it to the Inbuffer according to the first read command, and the "data corresponding to the first read address" has been written into the register component for storage through the first write data module before.

[0037] In some embodiments, refer to Figure 5 , the register file module (GPR RegFile) includes a second write data module, a second address indexing unit, a random access memory, and an ECC check module; The second write data module is used to receive a second write instruction and write the second source operand into the RAM for storage according to the second write instruction; the second write instruction includes the second source operand and the corresponding write address, and the write address is the same as the second read address; The second address indexing unit is configured to generate a second read command according to the second read address. Specifically, in the source operand reading step, the instruction pipeline processing logic module obtains a corresponding second read address according to a general instruction, and sends the second read address to the register file module. After receiving the second read address, the register file module generates a second read command through the second address indexing unit and sends it to the random access memory. The random access memory (RAM) is configured to output the second source operand according to the second read command. The second source operand has been previously written into the RAM through the second write data module for storage. The ECC checking module is configured to check the second source operand and use it as the output data for the current read access. Specifically, ECC (Error Correction Code) is a technology that can detect and correct data errors in memory. For applications with high requirements for the integrity and reliability of memory data, ECC checking is an important function.

[0038] Refer to Figure 6 , another embodiment of the present application further provides a data processing method, which is implemented based on the message processing module described in the above embodiment. The method includes the following steps: Step S10, the instruction decoding module receives a network acceleration instruction, decodes the network acceleration instruction to obtain a first read address and a first operation code, and sends the first read address and the first operation code to the instruction pipeline processing logic module. The network acceleration instruction refers to a custom instruction generated based on the RISC-V standard instruction. Step S20, the instruction pipeline processing logic module sends the first read address to the Fast RegFile module. Step S30, the Fast RegFile module outputs the data stored therein corresponding to the first read address to the Inbuffer. Step S40, the Inbuffer outputs the first source operand stored therein corresponding to the data corresponding to the first read address to the instruction pipeline processing logic module. Step S50, the instruction pipeline processing logic module operates on the first source operand according to the first operation code.

[0039] In some embodiments, the message processing module further includes a register file module. The method further includes the following steps: Step S60: The instruction decoding module receives a general instruction, decodes the general instruction to obtain a second read address and a second opcode, and sends the second read address and the second opcode to the instruction pipeline processing logic module; the general instruction refers to a RISC-V standard instruction. Step S70: The instruction pipeline processing logic module sends the second read address to the register file module. Step S80: The register file module outputs a second source operand stored therein to the instruction pipeline processing logic module according to the second read address. Step S90: The instruction pipeline processing logic module operates on the second source operand according to the second opcode.

[0040] In some embodiments, the Fast RegFile module includes a first write data module, a first address indexing unit, and a register component, and the register component includes a plurality of general-purpose registers. The method further includes the following steps: Step S100: The first write data module receives a write instruction, and writes the data to be written into the register component for storage according to the write instruction. Step S110: The first address indexing unit generates a first read command according to the first read address. Step S120: The register component outputs the data stored therein corresponding to the first read address to the Inbuffer according to the first read command.

[0041] In some embodiments, the register file module includes a second write data module, a second address indexing unit, a random access memory, and an ECC check module. The method further includes the following steps: Step S130: The second write data module receives a second write instruction, and writes the first source operand into the random access memory for storage according to the second write instruction. Step S140: The second address indexing unit generates a second read command according to the second read address. Step S150: The random access memory outputs the second source operand according to the second read command. Step S160: The ECC check module checks the second source operand and outputs the data as the output data for the current read access.

[0042] It should be noted that the method in this embodiment corresponds to the message processing module in the above embodiment. Therefore, for the parts not detailed in the method of this embodiment, reference can be made to the content of the message processing module in the above embodiment, and details are not described here again.

[0043] Another embodiment of the present application further provides a network processor, including a front-end pipeline module and the packet processing module described in the above embodiment.

[0044] Another embodiment of the present application further provides a chip, including the network processor described in the above embodiment.

[0045] The embodiments of the present application have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to technologies in the market, or to enable other ordinary skill in the art to understand the disclosed embodiments.

Claims

1. A message processing module, It is characterized in that It includes instruction decoding module, instruction pipeline processing logic module, Fast RegFile module and Inbuffer; The instruction decoding module is used to receive a network acceleration instruction, decode the network acceleration instruction to obtain a first read address and a first operation code, and send the first read address and the first operation code to the instruction pipeline processing logic module; the network acceleration instruction refers to a custom instruction generated based on the RISC-V standard instruction; The instruction pipeline processing logic module is used to send the first read address to the Fast RegFile module; The Fast RegFile module is used to output the data stored therein corresponding to the first read address to the Inbuffer; the Fast RegFile module is a data storage unit implemented by a register; The Inbuffer is used to output the first source operand stored therein to the instruction pipeline processing logic module according to the data corresponding to the first read address; The instruction pipeline processing logic module is further configured to operate the first source operand according to the first operation code.

2. The message processing module according to claim 1, It is characterized in that Also included is a register file module; The instruction decoding module is further used to receive a general instruction, decode the general instruction to obtain a second read address and a second operation code, and send the second read address and the second operation code to the instruction pipeline processing logic module; the general instruction refers to a RISC-V standard instruction; The instruction pipeline processing logic module is further used to send the second read address to the register file module; The register file module is used to output the second source operand stored therein to the instruction pipeline processing logic module according to the second read address; the register file module is a data storage unit implemented by a random access memory; The instruction pipeline processing logic module is further used to operate the second source operand according to the second operation code.

3. The message processing module according to claim 1, It is characterized in that The Fast RegFile module includes a first data writing module, a first address index unit, and a register component, wherein the register component includes a plurality of registers; The first data writing module is used to receive a write instruction and write the data to be written into the register component for storage according to the write instruction; The first address index unit is used to generate a first read command according to the first read address; The register component is used to output the data stored therein corresponding to the first read address to the Inbuffer according to the first read command.

4. The message processing module according to claim 2, It is characterized in that The register file module includes a second data writing module, a second address index unit, a random access memory, and an ECC check module; The second data writing module is used to receive a second writing instruction, and write the second source operand into the RAM for storage according to the second writing instruction; The second address index unit is used to generate a second read command according to the second read address; The random access memory is used to output the second source operand according to the second read command; The ECC checking module is used to check the second source operand and use it as output data for current read access.

5. A data processing method, It is characterized in that The method is implemented based on the message processing module according to any one of claims 1 to 4, and the method comprises: The instruction decoding module receives the network acceleration instruction, and decodes the network acceleration instruction to obtain a first read address and a first operation code; The instruction pipeline processing logic module sends the first read address to the Fast RegFile module; The Fast RegFile module outputs the stored data corresponding to the first read address to the Inbuffer; Inbuffer outputs the first source operand stored therein to the instruction pipeline processing logic module according to the data corresponding to the first read address; The instruction pipeline processing logic module operates the first source operand according to the first operation code.

6. The method according to claim 5, It is characterized in that The message processing module also includes a register file module; The instruction decoding module receives a general instruction, decodes the general instruction to obtain a second read address and a second operation code, and sends the second read address and the second operation code to the instruction pipeline processing logic module; the general instruction refers to a RISC-V standard instruction; The instruction pipeline processing logic module sends the second read address to the register file module; The register file module outputs the second source operand stored therein to the instruction pipeline processing logic module according to the second read address; The instruction pipeline processing logic module operates the second source operand according to the second operation code.

7. The method according to claim 5, It is characterized in that The Fast RegFile module includes a first data writing module, a first address index unit, and a register component, wherein the register component includes a plurality of registers; The first data writing module receives a write instruction, and writes the data to be written into the register component for storage according to the write instruction; A first address index unit generates a first read command according to the first read address; The register component outputs the stored data corresponding to the first read address to the Inbuffer according to the first read command.

8. The method according to claim 6, It is characterized in that The register file module includes a second data writing module, a second address index unit, a random access memory, and an ECC check module; The second data writing module receives a second writing instruction, and writes the first source operand into the random access memory for storage according to the second writing instruction; The second address index unit generates a second read command according to the second read address; The random access memory outputs the second source operand according to the second read command; The ECC check module checks the second source operand as output data for the current read access.

9. A network processor, It is characterized in that It comprises the message processing module described in any one of claims 1 to 4.

10. A chip, It is characterized in that Includes the network processor described in claim 9.

Images