Beat and anti-deadlock device and integrated system

Abstract

The present application discloses a beat-making and deadlock prevention device and an integrated system, which relates to the technical field of SOC systems. The device includes a beat-making module. When the slave module immediately responds to the operation request of the bus matrix, a release bus signal is output after a preset time delay through the beat-making module. When the slave module cannot immediately respond to the operation request, the release bus signal is output after a preset time delay for the preparation control signal. At the same time, when receiving a forced release control signal, the release bus signal is also output after a preset time delay through the beat-making module. Thus, it prevents the timing problems that occur when the signals transmitted between the host and the slave cannot reach in time, and can also output the release bus signal after the preset time period of the forced release control signal when a forced release control signal is required, which also prevents the timing problems of the forced release control signal.

Description

Technical Field

[0001] This application relates to the technical field of SOC systems, and particularly to a beating and deadlock prevention device and an integrated system. Background Art

[0002] In SOC design, it is the bus matrix that connects each host module and slave module together to form a complete SOC system. The slave module is usually connected to the bus matrix, and the interface connected to the bus matrix on the slave module is called the bus slave interface.

[0003] However, if the distance between the host and the slave is far, the signals sent between the host and the slave cannot reach as required, resulting in a timing problem between the host and the slave, and thus there is a metastability problem in the system. Summary of the Invention

[0004] This application provides a beating and deadlock prevention device and an integrated system to at least solve the timing problem between the host and the slave in the related art.

[0005] This application provides a beating and deadlock prevention device. The beating and deadlock prevention device is respectively connected to the bus matrix and the slave. The bus matrix includes: an access signal terminal, and the slave includes: a ready control terminal;

[0006] The beating and deadlock prevention device includes:

[0007] A beating module, which is respectively connected to the ready control terminal, the access signal terminal, and the forced release control terminal, and is used to receive the access signal and the ready control signal. After beating the access signal and the ready control signal for a preset time period, it controls the output of the extension request and the release bus signal;

[0008] The beating module is further used to output the release bus signal after delaying a preset time period whether it receives the access signal and / or the ready control signal when receiving the forced release control signal.

[0009] This application also provides an integrated system, including: a host, a bus matrix, a slave, and the above-mentioned beating and deadlock prevention device.

[0010] With this application, when the slave module immediately responds to the operation request of the bus matrix, the release bus signal is output after a delay of a preset duration through the pipelining module. Moreover, when the slave module cannot immediately respond to the operation request of the bus matrix, a preparation control signal is output by the slave module, and after the preparation control signal is no longer required, the release bus signal is output after a delay of a preset time period through the pipelining module. Meanwhile, when a forced release control signal is received, regardless of whether there is an access signal and / or a preparation control signal at present, the release bus signal is output after a delay of a preset time period through the pipelining module. Thus, when the host outputs access information to the slave, the transmission time of the access information is reserved, and when the slave sends a preparation control signal to the host, the transmission time of the preparation control signal is also reserved. Therefore, the timing problem that occurs when the signals transmitted between the host and the slave cannot reach in time is prevented. At the same time, when a forced release control signal is required, regardless of whether an access signal and / or a preparation control signal is received, the release bus signal can be timely output to the bus matrix, and the release bus signal is output after the preset time period of the forced release control signal, which also prevents the timing problem of the forced release control signal. The present invention can achieve the reserved pipelining time during the normal communication between the slave and the host through the pipelining module, can release the bus matrix when forced release is required, and can also reserve the pipelining time for forced release, thereby achieving the effect of integrating the pipelining function and the forced release function. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To more clearly illustrate the embodiments of the present application, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0012] Figure 1 A pipelining and deadlock prevention device provided by an embodiment of the present application;

[0013] Figure 2 Another pipelining and deadlock prevention device provided by an embodiment of the present application;

[0014] Figure 3 A detailed structure diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application;

[0015] Figure 4 A timing diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application;

[0016] Figure 5 Another timing diagram of a pipelining and deadlock prevention device provided by an embodiment of the present application;

[0017] Figure 6 Another timing diagram of a beat-making and deadlock-preventing device provided by an embodiment of the present application;

[0018] Figure 7 Another timing diagram of a beat-making and deadlock-preventing device provided by an embodiment of the present application. Detailed implementation manners

[0019] Next, the technical solutions in the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0020] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0021] To enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0022] The slave interface needs to return correct response signals such as resp / err, rdata, ready, etc. to the bus matrix so that the bus matrix can obtain information on whether the current access is normal / abnormal, the return value, and whether the access is completed. The signal names returned for different buses are slightly different. The slave interface of the slave module may cause the slave to deadlock due to certain defects, and the response returned to the bus matrix never returns the information indicating the end of the bus, resulting in the bus and the host being occupied all the time. At this time, it is necessary to end the deadlock occupation of the bus according to the timeout signal returned by the bus matrix.

[0023] In common bus matrices such as the AHB bus and APB 3.0 bus of the AMBA bus, when a slave module cannot immediately respond to an operation request from the bus matrix, it can pull the ready-related preparation control signal (hready in the AHB bus protocol of the bus and pready in the APB 3.0 bus protocol of the bus) to a low level to notify the bus matrix to extend the time that the operation request is reserved on the bus. When the response ends, the slave module can pull the ready-related preparation control signal to a high level to notify the bus matrix to continue with the next operation request. During this process, if an exception occurs in the accessed slave module and the ready signal is always pulled low, it will cause the bus matrix to deadlock, and thus the SOC system will deadlock.

[0024] Moreover, the distance between the host and the slave is far, resulting in the signals sent between the host and the slave not reaching as required, thus there are timing problems between the host and the slave, making the system have metastability problems.

[0025] An embodiment of the present application provides a pipelining and deadlock prevention device. The pipelining and deadlock prevention device is respectively connected to the bus matrix and the slave, as Figure 1 shown. The bus matrix includes: an access signal terminal, and the slave includes: a preparation control terminal;

[0026] The pipelining and deadlock prevention device includes:

[0027] A pipelining module 10, which is respectively connected to the preparation control terminal, the access signal terminal, and the forced release control terminal, and is used to receive the access signal and the preparation control signal. After pipelining the access signal and the preparation control signal for a preset time period, it controls the output of the extension request and the release bus signal;

[0028] The pipelining module 10 is further used to, when receiving the forced release control signal, whether receiving the access signal and / or the preparation control signal, delay the preset time period and then output the release bus signal.

[0029] Specifically, the bus matrix is such as the AHB bus and APB 3.0 bus of the AMBA bus. The preparation control terminal is the ready terminal of the slave, which is hready in the AHB bus protocol of the bus and pready in the APB 3.0 bus protocol of the bus. The slave outputs the preparation control signal through the preparation control terminal. If the preparation control signal is at a high level, it is used to notify the bus matrix to continue with the next operation request. If the preparation control signal is at a low level, it is used to notify the bus matrix to extend the operation to request the time reserved on the bus. The access signal terminal is the terminal for the host to send an access signal to the slave based on the bus matrix, and the forced release control terminal is the deadlock prevention port output by the SOC system, which can specifically be a soft reset terminal for controlling the reset of the slave, or a timeout signal, and the timeout signal is timeout. Both the slave reset and the timeout signal are used to output the release bus signal to the bus matrix.

[0030] Specifically, based on the beat module 10, the following three situations are implemented. First, when the host sends an access signal to the slave based on the bus matrix and the slave can process it in time (that is, when the ready control terminal of the slave does not output a ready signal), the beat module 10 outputs an extension request to the bus matrix, and after beating for a preset time period, outputs a bus release signal to the bus matrix. Second, when the host sends an access signal to the slave based on the bus matrix and the slave cannot process it in time, the slave outputs a ready control signal. At this time, the beat module 10 outputs an extension request to the bus matrix, and after the extension request ends (that is, when the ready control terminal of the slave outputs a ready completion signal), after beating for a preset time period, outputs a bus release signal to the bus matrix. Third, even if the beat module 10 does not receive a ready completion signal but receives a forced release control signal, after beating for a preset time period starting from the forced release control signal, it outputs a bus release signal to the bus matrix.

[0031] In summary, the beat module 10 implements the following three functions. When the host sends an access signal to the slave based on the bus matrix, even if the slave does not need to output a ready control signal, after beating for a preset time period for the access signal, a bus release signal is output, thus realizing the beating of the reserved time period for the host to send an access signal to the slave. It also realizes that after the slave outputs a ready completion signal, after beating for a preset time period, a bus release signal is output, thus realizing the beating for a preset time period for the ready completion signal when the slave sends a ready completion signal to the bus matrix. It also realizes that when a forced release signal is received, regardless of whether an access signal and / or a ready control signal is received, after beating for a preset time period, a bus release signal is output. It should be noted that the priority of the forced release control signal is higher than that of the access signal and / or the ready control signal.

[0032] With this application, when the slave module immediately responds to the operation request of the bus matrix, after a delay of a preset duration through the beat module, a bus release signal is output. And when the slave module cannot immediately respond to the operation request of the bus matrix, a preparation control signal is output at the slave module, and after the preparation control signal is no longer needed, after a delay of a preset time period through the beat module, a bus release signal is output. At the same time, when a forced release control signal is received, regardless of whether there is an access signal and / or a preparation control signal currently, after a delay of a preset time period through the beat module, a bus release signal is output. Thus, when the host outputs access information to the slave, the transmission time of the access information is reserved, and when the slave sends a preparation control signal to the host, the transmission time of the preparation control signal is also reserved. Therefore, when the signals transmitted between the host and the slave cannot reach in time, the timing problem is prevented. At the same time, when forced release is required, regardless of whether an access signal and / or a preparation control signal is received, a bus release signal can be timely output to the bus matrix, and after a preset time period of the forced release control signal, a bus release signal is output again, which also prevents the timing problem of the forced release control signal. The present invention can implement the reserved beat time during normal communication between the slave and the host through the beat module, can also release the bus matrix when forced release is required, and can reserve the beat time for forced release, thereby achieving the effect of integrating the beat function and the forced release function.

[0033] In an exemplary embodiment, as Figure 2 shown, the beat module 10 includes:

[0034] A first extension unit 11, which is respectively connected to the preparation control terminal, the access signal terminal, and the forced release control terminal, and is used for extending a preset time period for the access signal and outputting a first bus release signal when the access signal is received, and is used for extending a preset time period for the forced release control signal and outputting a first bus release signal when the forced release control signal is received;

[0035] Specifically, the first extension unit 11 is used for outputting an extension request starting from the access signal when the forced release control signal is not received and as long as the access signal is received, and outputting a first bus release signal after a preset time period. The first extension unit 11 is further used for outputting an extension request starting from the forced release control signal when the forced release control signal is received and outputting a first bus release signal after a preset time period. Optionally, the first extension unit 11 outputs the first bus release signal in a reset manner.

[0036] The second extension unit 12, the second extension unit 12 is respectively connected to the preparation control terminal and the forced release control terminal, and is used for outputting a second release bus signal after extending a preset time period when the preparation is completed upon receiving a preparation control signal, and is used for outputting a second release bus signal after extending a preset time period for the forced release control signal upon receiving a forced release control signal;

[0037] Specifically, the second extension unit 12 is used for outputting an extension request starting from the preparation control signal when the forced release control signal is not received and as long as the preparation control signal is received, and outputting a second release bus signal after a preset time period. The second extension unit 12 is further used for outputting an extension request starting from the access signal of the forced release control signal and outputting a second release bus signal after a preset time period when the forced release control signal is received. Optionally, the second extension unit 12 outputs the second release bus signal in a delayed manner.

[0038] The first control unit 13, the first control unit 13 is respectively connected to the first extension unit 11 and the second extension unit 12, and is used for outputting a release bus signal when receiving the first release bus signal and the second release bus signal.

[0039] Specifically, the first control unit 13 outputs a release bus signal only when both the first release bus signal and the second release bus signal are received, and does not output a release bus signal when only the first release bus signal or the second release bus signal is received, or when neither the first release bus signal nor the second release bus signal is received.

[0040] In an exemplary embodiment, as Figure 3 shown, the first extension unit 11 includes:

[0041] The reset control structure 11a, the reset control structure 11a is connected to the access signal terminal and is used for outputting a reset control signal when receiving an access signal;

[0042] The reset extension structure 11b, the reset extension structure 11b is connected to the preparation control terminal, the forced release control terminal and the reset control structure, and is used for receiving the reset control signal and extending it for a preset time period.

[0043] Specifically, when the reset control structure 11a receives an access signal, it outputs a reset control signal, so that the reset extension structure 11b resets for a preset time period, thereby outputting a first release bus signal. It should be noted that the reset control signal of the first extension unit 11 extends the preset time period by means of reset, which is different from the reset of the slave device. Optionally, the reset control structure 11a can be a control chip for outputting a reset control signal.

[0044] In an exemplary embodiment, asFigure 3 As shown in Figure 3 , the beat-playing and deadlock-preventing device further includes:

[0045] A synchronization signal module 20, whose input end is connected to the forced release control end, and whose output end is respectively connected to a first extension unit 11 and a second extension unit 12, for outputting the forced release control signal after synchronizing it with the slave machine.

[0046] Specifically, the synchronization signal module 20 performs data synchronization at a preset level for the forced release control signal. The synchronization signal module 20 is sync_data, the forced release control signal is force_rsp, and the forced release control signal output after synchronization is force_rsp_sync. The synchronization signal module 20 also sends the synchronized forced release control signal to the slave machine to control the reset of the slave machine. Thus, the reset signal of the slave machine is synchronized with the slave machine, solving the timing problem of the slave machine during reset. The synchronization signal module 20 can perform 3-level synchronization or 2-level synchronization.

[0047] Reference Figure 5 , the synchronization signal module 20 performs 3-level synchronization, that is, extends the forced release control signal for 3 beats. It should be noted that due to the influence of crossing clock domains, the synchronized forced release control signal output by the synchronization signal module 20 may have a one-cycle offset.

[0048] It should be noted that traditional bus management relies on the slave machine to actively release resources, but the system may be completely paralyzed in the case of a deadlock. This design realizes active intervention by the host through the forced release control signal, breaking the deadlock, which is an innovation at the hardware level for fault tolerance. In addition, in some emergency situations, if it is necessary to give high-priority slaves emergency priority to occupy the bus, the currently occupied slave can be released through the forced release control mechanism. In addition, because of the asynchronous reset and reset sequence problems of the slave machine and the host machine, directly resetting the slave machine may transmit metastability to the host machine. This invention performs synchronization during forced bus switching to avoid metastability. At the same time, technically, there is no need for a complex state machine or an additional arbiter, and fast fault isolation can be achieved only through logic signals, reducing the system complexity and cost. And currently, timing adjustment mostly relies on fixed delays or global clock synchronization, which is difficult to cope with dynamic environments (such as temperature changes, signal attenuation). This design inserts a "beat-playing" mechanism to dynamically compensate for timing deviations at the data link layer, improving communication reliability. Technically, it supports heterogeneous device hybrid networking, can flexibly adapt to different protocols (such as AHB / APB), and has strong scalability.

[0049] The present invention can also be applied to the following scenarios. First, it can achieve fault isolation and troubleshooting. In the case where a large number of low-power devices may be briefly offline due to network fluctuations or power supply problems, the dynamic bus release mechanism can quickly isolate the faulty node, or troubleshoot the faulty module by releasing the bus module by module. Second, it can achieve emergency bus release to ensure high-priority requirements. Key subsystems (such as radars and cameras) require high-priority bus access, and the communication delay must be extremely low. By forcibly releasing the bus, it is ensured that emergency instructions (such as brake signals) are transmitted first. Third, it can achieve improved dynamic stability under environmental (temperature, voltage) deviations. Monitor the environmental conditions, adaptively adjust the number of beats, improve the stability of the system under environmental deviations, adaptively compensate for clock drift and increased delay caused by temperature and voltage changes, reduce the retransmission rate, and improve the system stability.

[0050] Exemplarily, the synchronization signal module 20 performs 3-level or 2-level synchronization on the forced release control signal.

[0051] In an exemplary embodiment, as Figure 3 shown, the reset control structure 11a includes:

[0052] A first inverter N1, the input end of the first inverter N1 is connected to the access signal end;

[0053] A first register D1, the input end of the first register D1 is connected to the output end of the first inverter N1, and the output end of the first register D1 is used to output the reset control signal.

[0054] Optionally, the first register D1 is a MUX register.

[0055] Exemplarily, when the first inverter N1 receives the access signal as 1, it outputs 0 after passing through the first inverter N1, and the first register D1 outputs the reset control signal after receiving 0.

[0056] In an exemplary embodiment, as Figure 3 shown, the reset extension structure 11b includes:

[0057] A second inverter N2, the input end of the second inverter N2 is connected to the forced release control end;

[0058] A first selector M1, the first input end of the first selector M1 is connected to the output end of the second inverter N2, the second input end of the first selector M1 is connected to the preparation control end, and the selection end of the first selector M1 is connected to the synchronization signal module 20;

[0059] X cascaded second registers D2, the input end of the cascaded second registers D2 is connected to the output end of the first selector M1, the output end of the cascaded second registers D2 is connected to the first control unit 13, and the reset end of each second register D2 is connected to the output end of the first register D1, wherein X 1.

[0060] Specifically, when forced release is not required, when an access signal is sent through the access signal terminal, each second register D2 receives a reset control signal, and the cascaded second registers D2 are reset at the same time. The first second register D2 outputs 0 after being reset, and the second register D2 receives 0 and outputs 0, which are successively absorbed by the cascaded second registers D2 as the first release bus and then output to the first control unit 13. In the case of forced release, the forced release control signal 0 is inverted to 1 by the second inverter N2 and sent to the first selector M1. The first selector M1 outputs 1, and passes through the cascaded second registers D2 for a preset time period before being output as the first release bus. It should be noted that the number of Xs represents the number of beats in the preset time period of the access signal.

[0061] That is to say, when the application faces asynchronous forced change conditions such as asynchronous reset, it first performs data synchronization on the asynchronous reset, and then participates in data selection as the selection end of the first selector M1; in order to avoid the slave module causing the slave interface to change immediately before switching due to the asynchronous reset, the slave module is required to use the reset after data synchronization.

[0062] Optionally, the first selector M1 is a MUX (Multiplexer). The second register D2 is a MUX register.

[0063] In an exemplary embodiment, Figure 3 As shown, the second extension unit 12 is used to extend the ready control signal by a preset time period, and output the extended ready control signal as the second release bus signal.

[0064] Specifically, the second extension unit 12 extends the signal output by the preparation control terminal, that is, the preparation control signal is extended, and the non-preparation control signal is also extended. When the slave outputs the preparation control signal, it is 0, and when the preparation control signal does not need to be output, it is 1. When the second extension unit 12 receives the forced release control signal, it extends the forced release control signal for a preset time period and then outputs a second release bus signal.

[0065] In an exemplary embodiment, Figure 3 As shown, the second extension unit 12 includes:

[0066] The third inverter N3, the input terminal of the third inverter N3 is connected to the forced release control terminal;

[0067] The second selector M2, the first input terminal of the second selector M2 is connected to the output terminal of the third inverter N3, the second input terminal of the second selector M2 is connected to the preparation control terminal, and the selection terminal of the second selector M2 is connected to the synchronization signal module 20;

[0068] X cascaded third registers D3, the input terminals of the cascaded third registers D3 are connected to the output terminal of the second selector M2, and the output terminals of the cascaded third registers D3 are connected to the first control unit 13, where X 1.

[0069] Specifically, in the case of no forced release, when a preparation control signal is sent through the preparation control terminal, the cascaded third registers D3 delay the preparation control signal in sequence and then output it as the second release bus. In the case of forced release, the forced release control signal 0 is inverted to 1 by the third inverter N3 and sent to the second selector M2. The second selector M2 outputs 1, and after being delayed by the cascaded third registers D3 for a preset time period respectively, it is output as the second release bus signal. The number of X represents the number of beats of the preset time period of the access signal.

[0070] It should be noted that the number of cascaded third registers D3 is equal to the number of cascaded second registers D2.

[0071] In addition, the beat and deadlock prevention device may further include a beat duration control module, and the beat duration control module is respectively connected to the input and output paths of each second register D2 and each third register D3, that is, the beat duration control module selects a preset number Y of second registers D2 and a preset number Y of cascaded third registers D3 from the X cascaded second registers D2 and X cascaded third registers D3. That is, the output terminal of the Y-th second register D2 is directly connected to the first control unit 13, and the output terminal of the Y-th third register D3 is directly connected to the first control unit 13. Thus, the preset beat time is controlled. Furthermore, flexible control of the beat duration is achieved.

[0072] Optionally, the second selector M2 is a MUX (Multiplexer, multiplexer). The third register D3 is a MUX register.

[0073] In an exemplary embodiment, as Figure 3 , Figure 4 and Figure 5 shown, the first control unit 13 includes:

[0074] The first AND gate AND1, the first input terminal of the first AND gate AND1 is connected to the output terminal of the cascaded second register D2, the second input terminal of the first AND gate is connected to the output terminal of the cascaded third register D3, and the output terminal of the first AND gate AND1 is used to output a bus release signal.

[0075] Specifically, when the first AND gate AND1 receives the first bus release signal and the second bus release signal, it outputs a bus release signal. The first AND gate AND1 outputs a signal indicating no need to release the bus only when the first bus release signal or the second bus release signal is received. When the first AND gate AND1 does not receive the first bus release signal and the second bus release signal, it outputs a signal indicating no need to release the bus.

[0076] Exemplarily, referring to Figure 4 , the forced release control signal is 0, and the signal indicating no need for forced release is 1. The preparation control signal is 0, and the signal indicating no need for preparation is 1. The bus release signal is 1, and the signal indicating no need to release the bus is 0. The access signal is 1, and the signal indicating no need for access is 0.

[0077] Referring to Figure 3 and Figure 4 In a, if three second registers D2 are cascaded and three third registers D3 are cascaded. When there is no need for forced release, the selection signal received by the first selector M1 is 1, that is, the signal output by the first selector M1 is the signal of the second input terminal. At this time, if no preparation is required, the first selector M1 outputs 0 to the first second register D2. After passing through three second registers D2, 0 is output to the first control unit 13 for three beats. The selection signal received by the second selector M2 is 1, that is, the signal output by the second selector M2 is the signal of the second input terminal. At this time, if no preparation is required, the second selector M2 outputs 1 to the first third register D3. After passing through three second registers D2, 1 is transmitted to the first control unit 13. The first control unit 13 outputs 0 for three beats, that is, a signal indicating no need to release the bus, and then outputs 1, that is, a bus release signal.

[0078] Referring to Figure 3 and Figure 4 In b, when there is no need for forced release, if preparation is required, that is, the preparation control signal is 0, and the first selector M1 outputs 1 to the first second register D2. However, since each second register D2 receives a reset signal at this time, the first second register D2 outputs 0, and the cascaded second registers D2 sequentially output 0 to the first control unit 13. The second selector M2 outputs 0 to the first third register D3. After a delay of three third registers D3, a total of 0 for four beats is output to the first control unit 13, that is, a signal indicating no need to release the bus, and then outputs 1, that is, a bus release signal.

[0079] Referring toFigure 3 and Figure 5 , when forced release is required, that is, the forced release control signal is 0, after three - stage synchronization by the synchronization signal module 20, 0 is output. At this time, due to the cross - clock domain effect, there is a delay of 4 beats. The selection signal received by the first selector M1 is 0, that is, the signal output by the first selector M1 is the signal of the first input terminal. The forced release control signal 0 is inverted by the second inverter N2 to output 1. The first selector M1 outputs 1 to the first second register D2. At this time, the cascaded second register D2 outputs 1 to the first control unit 13. The selection signal received by the second selector M2 is 0, that is, the signal output by the second selector M2 is the signal of the first input terminal. The forced release control signal 0 is inverted by the third inverter N3 to output 1. The second selector M2 outputs 1 to the first third register D3. At this time, the cascaded third register D3 outputs 1 to the first control unit 13. That is to say, the first control unit 13 outputs 1 after a delay of 3 more beats, that is, releases the bus signal.

[0080] In an exemplary embodiment, as Figure 3 shown, the clock - ticking and dead - lock prevention device includes:

[0081] A control module 30, which is respectively connected to the clock - ticking control terminal, the clock - ticking module 10 and the preparation control terminal, is used to receive the clock - ticking control signal, and control whether the clock - ticking module 10 delays the access signal and the preparation control signal, and is also used to output a release bus signal that delays the forced release control signal by a preset time period when receiving the forced release control signal.

[0082] Specifically, the control module 30 is used to control whether the function of the clock - ticking module 10 is enabled. It should be noted that when the function of the clock - ticking module 10 is not enabled, if the forced release control signal is received, clock - ticking extension for a preset time period is still performed. Thus, the timing problem during reset is ensured, and the system being in a metastable state is prevented.

[0083] In an exemplary embodiment, as Figure 3 shown, the control module 30 includes:

[0084] A second control unit 31, the first input terminal of the second control unit 31 is connected to the clock - ticking control terminal, and the second input terminal of the second control unit 31 is connected to the output terminal of the synchronization signal module 20, and is used to output a clock - ticking signal when receiving the clock - ticking control signal and / or the forced release signal;

[0085] The routing control unit 32, the first input end of the routing control unit 32 is connected to the output end of the clocking module 10, the second input end of the routing control unit 32 is connected to the preparation control end, the output end of the selection end of the routing control unit is connected to the bus matrix, and the selection end of the routing control unit 32 is connected to the output end of the second control unit 31, and is used for outputting the bus release signal transmitted by the clocking module 10 to the bus matrix when receiving the clocking signal.

[0086] Specifically, when the second control unit 31 receives the no-clocking control signal and the no-forced release signal, it controls the routing control unit 32 to output the preparation control signal as the bus release signal to the bus matrix. When the second control unit 31 receives the clocking signal and the no-forced release signal, it controls the routing control unit 32 to output the bus release signal sent by the clocking module 10 to the bus matrix. When the second control unit 31 receives the no-clocking control signal and the forced release control signal, it controls the routing control unit 32 to output the bus release signal sent by the clocking module 10 to the bus matrix.

[0087] In an exemplary embodiment, as Figure 3 shown, the second control unit 31 includes:

[0088] The second AND gate AND2, the first input end of the second AND gate AND2 is connected to the clocking control end, the second input end of the second AND gate AND2 is connected to the output end of the synchronization signal module 20, and the output end of the second AND gate AND2 is connected to the routing control unit 32.

[0089] Specifically, the no-clocking control signal is 1, and the clocking control signal is 0. The no-forced release signal is 1, and the forced release signal is 0. When the second AND gate AND2 receives the no-clocking control signal and the no-forced release signal, that is, when receiving 1 and 1, it outputs 1. When the second AND gate AND2 receives the clocking control signal and the no-forced release signal, that is, when receiving 0 and 1, it outputs 0. When the second AND gate AND2 receives the no-clocking control signal and the forced release signal, that is, when receiving 1 and 0, it outputs 0. When the second AND gate AND2 receives the clocking control signal and the forced release signal, that is, when receiving 0 and 0, it outputs 0.

[0090] In an exemplary embodiment, as Figure 3 and Figure 5 shown, the routing control unit 32 includes:

[0091] The third selector M3, the first input end of the third selector M3 is connected to the output end of the clocking module 10, the second input end of the third selector M3 is connected to the preparation control end, the output end of the third selector M3 is connected to the bus matrix, and the selection end of the third selector M3 is connected to the output end of the second control unit 31.

[0092] Specifically, when the third selector M3 receives a selection terminal of 0, it outputs the signal output by the beating module 10 to the bus matrix. When the third selector M3 receives a selection terminal of 1, it outputs the ready control signal to the bus matrix.

[0093] Exemplarily, referring to Figure 5 , when there is no need for the beating control signal to be 1, if the slave device has a deadlock and has not released the bus, the bus is forcibly released by the forced release control signal 0. That is, when the forced release control signal is 0, the synchronization signal outputs 0 after 3 delays. The synchronized signal has a one-cycle offset due to the cross-clock domain effect, and then after 3 beating times of the beating module 10, the bus release signal is output. Because the synchronized signal has a one-cycle offset due to the cross-clock domain effect, the bus release signal also has a one-cycle offset.

[0094] In an exemplary embodiment, as Figure 3 , Figure 6 and Figure 7 shown, the beating and deadlock prevention device includes:

[0095] An access recognition module 40, which is respectively connected to the bus matrix and the access signal terminal, and is used to receive the access signal and output the access signal when detecting that the access signal is valid.

[0096] Specifically, the access recognition module 40 detects the validity of the access signal and only outputs it as the access signal when it is detected as valid. Thus, the validity of the transmitted access signal is improved.

[0097] Referring to Figure 6 , in the AHB protocol, the address / control command channel is AHB A / C CH, and the control signals it contains are such as hsel, htrans, etc. The ready control signal is hreadyin. That is, when the address / control instruction is 1 and the control signal is 1, it is determined as a valid access signal active_s.

[0098] Referring to Figure 7 , in the APB3.0 protocol, the address / control command channel is psel, and the control signals it contains are such as penable, etc. The valid access signal active_s, that is, when the address / control instruction is 1 and the control signal is 0, it is detected as a valid access signal. The ready control signal is pready.

[0099] Embodiments of the present application also provide an integrated system, which includes a host, a bus matrix, a slave, and a beat and deadlock prevention device. Thus, when the host outputs access information to the slave, the transmission time of the access information is reserved, and when the slave sends a ready control signal to the host, the transmission time of the ready control signal is also reserved. Therefore, the timing problem caused by the signal transmitted between the host and the slave not reaching in time is prevented. At the same time, when it is necessary to forcibly release the control signal, regardless of whether the access signal and / or the ready control signal is received, the bus release signal can be output to the bus matrix in time, and the bus release signal is output again after a preset time period for forcibly releasing the control signal, which also prevents the timing problem of forcibly releasing the control signal. The present invention can implement the reserved beat time during the normal communication between the slave and the host through the beat module, can release the bus matrix when forced release is required, and can reserve the beat time for forced release, thereby achieving the effect of integrating the beat function and the forced release function.

[0100] The above has introduced in detail a beat and deadlock prevention device and an integrated system provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A beat-making and deadlock-preventing device, characterized in that, The beat and deadlock prevention device is respectively connected to the bus matrix and the slave device. The bus matrix includes: an access signal terminal, and the slave device includes: a ready control terminal; The beat and deadlock prevention device includes: A beat module, which is respectively connected to the ready control terminal, the access signal terminal, and the forced release control terminal, and is used to receive the access signal and the ready control signal. After beating the access signal and the ready control signal for a preset time period, it controls the output of the extension request and the bus release signal. The beat module is further used to output the bus release signal after delaying a preset time period when receiving the forced release control signal.

2. The beat-playing and deadlock-preventing device according to claim 1, wherein The beat module includes: A first extension unit, which is respectively connected to the ready control terminal, the access signal terminal, and the forced release control terminal, and is used to, when receiving the access signal, output a first bus release signal after extending the access signal for a preset time period, and is also used to, when receiving the forced release control signal, output a first bus release signal after extending the forced release control signal for a preset time period; A second extension unit, which is respectively connected to the ready control terminal and the forced release control terminal, and is used to, when receiving the ready control signal, output a second bus release signal after the preparation is completed and extended for a preset time period, and is also used to, when receiving the forced release control signal, output a second bus release signal after extending the forced release control signal for a preset time period; A first control unit, which is respectively connected to the first extension unit and the second extension unit, and is used to output the bus release signal when receiving the first bus release signal and the second bus release signal.

3. The beat-making and deadlock prevention device according to claim 2, wherein The first extension unit includes: A reset control structure, which is connected to the access signal terminal and is used to output a reset control signal when receiving the access signal; A reset extension structure, which is connected to the ready control terminal, the forced release control terminal, and the reset control structure, and is used to receive the reset control signal and extend it for a preset time period.

4. The beat-making and anti-deadlock device according to claim 3, characterized in that, The beat and deadlock prevention device further includes: A synchronization signal module, the input end of which is connected to the forced release control terminal, and the output end of which is respectively connected to the first extension unit and the second extension unit, and is used to synchronize the forced release control signal with the slave device and then output it.

5. The beat-making and deadlock prevention device according to claim 4, wherein The reset control structure includes: A first inverter, the input end of which is connected to the access signal terminal; A first register, the input end of which is connected to the output end of the first inverter, and the output end of which is used to output the reset control signal.

6. The beat-making and deadlock prevention device according to claim 5, characterized in that, The reset extension structure includes: A second inverter, the input end of which is connected to the forced release control terminal; A first selector, the first input end of which is connected to the output end of the second inverter, the second input end of which is connected to the ready control terminal, and the selection end of which is connected to the synchronization signal module; X cascaded second registers, the input ends of the cascaded second registers are connected to the output end of the first selector, the output ends of the cascaded second registers are connected to the first control unit, and the reset ends of each of the second registers are connected to the output end of the first register, where X 1 7. The beat-making and deadlock prevention device according to claim 4, characterized in that The second extension unit is used to extend the ready control signal for a preset time period and output the extended ready control signal as the second release bus signal.

8. The beat-making and deadlock prevention device according to claim 7, characterized in that, The second extension unit includes: A third inverter, the input end of the third inverter is connected to the forced release control end; A second selector, the first input end of the second selector is connected to the output end of the third inverter, the second input end of the second selector is connected to the ready control end, and the selection end of the second selector is connected to the synchronization signal module; X cascaded third registers, the input end of the cascaded third registers is connected to the output end of the second selector, and the output end of the cascaded third registers is connected to the first control unit, where X 1.

9. The beat-playing and deadlock prevention device according to claim 2, characterized in that The first control unit includes: A first AND gate, the first input end of the first AND gate is connected to the output end of the cascaded second register, the second input end of the first AND gate is connected to the output end of the cascaded third register, and the output end of the first AND gate is used to output the release bus signal.

10. The beat-playing and deadlock prevention device according to claim 1, characterized in that, The pipelining and deadlock prevention device includes: A control module, the control module is respectively connected to the pipelining control end, the pipelining module and the ready control end, and is used to receive the pipelining control signal and control whether the pipelining module delays the access signal and the ready control signal, and is also used to output a release bus signal that delays the forced release control signal by a preset time period when receiving the forced release control signal.

11. The beat-making and deadlock prevention device according to claim 10, characterized in that, The control module includes: A second control unit, the first input end of the second control unit is connected to the pipelining control end, the second input end of the second control unit is connected to the output end of the synchronization signal module, and is used to output a pipelining signal when receiving the pipelining control signal and / or the forced release control signal; A routing control unit, the first input end of the routing control unit is connected to the output end of the pipelining module, the second input end of the routing control unit is connected to the ready control end, the output end of the selection end of the routing control unit is connected to the bus matrix, and the selection end of the routing control unit is connected to the output end of the second control unit, and is used to output the release bus signal transmitted by the pipelining module to the bus matrix when receiving the pipelining signal.

12. The beat-making and deadlock prevention device according to claim 11, wherein The second control unit includes: A second AND gate, the first input end of the second AND gate is connected to the pipelining control end, the second input end of the second AND gate is connected to the output end of the synchronization signal module, and the output end of the second AND gate is connected to the routing control unit.

13. The beat-making and deadlock prevention device according to claim 12, characterized in that, The routing control unit includes: A third selector, the first input end of the third selector is connected to the output end of the pipelining module, the second input end of the third selector is connected to the ready control end, the output end of the third selector is connected to the bus matrix, and the selection end of the third selector is connected to the output end of the second control unit.

14. The beat-making and deadlock prevention device according to claim 1, characterized in that, The pipelining and deadlock prevention device includes: An access identification module, the access identification module is respectively connected to the bus matrix and the access signal end, and is used to receive the access signal and output it when detecting that the access signal is valid.

15. An integrated system, characterized in that, The integrated system includes a host, a bus matrix, a slave, and the pipelining and deadlock prevention device according to any one of claims 1 to 14.

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