Method for improving time sequence triggering efficiency of ONFI interface

Abstract

The invention discloses a method for improving time sequence triggering efficiency of an ONFI interface, and relates to the technical field of solid state disk (SSD) and NAND Flash memory interfaces. According to the method, a template mechanism is introduced, the NFC can be driven to execute a series of time sequence operations through one-time template triggering of the CPU, compared with a traditional frequent register configuration mode, the access frequency of the CPU to the register is greatly reduced, the time sequence interval of the ONFI interface is effectively shortened, the data transmission bandwidth is remarkably improved, and through actual testing, in a typical storage application scene, the data transmission efficiency is greatly improved. The data bandwidth can be improved by more than 40%, the burden of a CPU in the aspect of time sequence control is reduced, more resources can be input into other key task processing, such as a data processing algorithm and system management, the overall performance and response speed of the SSD controller are improved, the multi-task processing capacity of the system is enhanced, and the service life of the SSD controller is prolonged. According to the invention, the template is supported to be stored in a CPU memory or an external storage space, and a user can flexibly select a storage mode according to system hardware resources, cost and performance requirements.

Description

Technical Field

[0001] The present invention relates to the technical field of the interface between a solid state drive (SSD) and a NAND Flash memory. More specifically, the present invention relates to a method for improving the timing trigger efficiency of the ONFI interface. Background Art

[0002] In storage technology, as an open NAND Flash interface protocol, ONFI stipulates four types of interface timings between an SSD controller and a NAND Flash memory, namely commands, addresses, data input, and data output, to ensure normal communication between the two and implement read, write, and erase operations of data. Usually, a CPU is integrated in an SSD controller chip, and these timings are triggered by configuring registers. Specifically, command, address, data input, and data output registers are set in the NFC module, and the CPU writes operations to the corresponding registers to trigger the corresponding timings. For example, during a write operation, commands, addresses, data input, and command registers are written in sequence to trigger a complete timing. However, in a system-on-chip, the CPU needs to frequently access NFC registers via the AMBA bus to generate timings. If the configuration interval is large, the ONFI interface timing interval will increase, seriously affecting the data bandwidth and becoming a key factor restricting the improvement of storage performance.

[0003] Therefore, it is necessary to invent a method for improving the timing trigger efficiency of the ONFI interface to solve the above problems. Summary of the Invention

[0004] In order to overcome the above-mentioned defects of the prior art, the present invention provides a method for improving the timing trigger efficiency of the ONFI interface to solve the problem that in a system-on-chip, the CPU needs to frequently access NFC registers via the AMBA bus to generate timings. If the configuration interval is large, the ONFI interface timing interval will increase, seriously affecting the data bandwidth and becoming a key factor restricting the improvement of storage performance as mentioned in the above background art.

[0005] In order to achieve the above object, the present invention provides the following technical solution: A method for improving the timing trigger efficiency of the ONFI interface, comprising the following steps:

[0006] Step 1: Create corresponding templates according to the usage scenarios of the NAND Flash memory;

[0007] Step 2: When the SSD controller chip is powered on, initialize all used templates into the memory of the CPU and assign a unique memory starting address to each template;

[0008] Step 3: When the CPU needs to trigger a certain template, accurately configure the starting address and template length corresponding to the template into the registers of the NFC;

[0009] Step 4: Based on the received template start address and length, NFC actively reads the template content from the CPU's memory through the AMBA bus;

[0010] Step 5: NFC parses the read template item by item and accurately sends the corresponding timing operations to the NAND Flash memory through the ONFI interface according to the parsing results;

[0011] As a further description of the above technical solution, the template described in Step 1 consists of several timing operations for implementing specific operations. The template includes a write template, a read template, and an erase template, and the sequence and content of the timing operations in each template strictly match the corresponding standard operation process;

[0012] As a further description of the above technical solution, the allocation of the memory start address in Step 2 is based on a memory management algorithm to ensure continuous and conflict-free address space;

[0013] As a further description of the above technical solution, the configuration process in Step 3 follows a specific register write protocol to ensure data integrity;

[0014] As a further description of the above technical solution, the reading process in Step 4 adopts a high-speed data transmission mechanism to ensure rapid and accurate data acquisition;

[0015] As a further description of the above technical solution, the parsing and sending process in Step 5 follows strict timing specifications to ensure the correctness of operations;

[0016] As a further description of the above technical solution, the content of the template can also be stored in an external storage space connected to the AMBA bus, and the external storage space needs to meet specific storage performance and reliability requirements;

[0017] As a further description of the above technical solution, during the power-on and initialization process in Step 2, the CPU writes all the templates to be used to the external storage space through the AMBA bus and records the start address and length corresponding to each template. The error correction coding technology is adopted during the writing process to ensure the accuracy of data storage;

[0018] As a further description of the above technical solution, when NFC needs to control the NAND Flash to execute operations, the CPU triggers the template and configures the corresponding start address and length into the registers of NFC. After receiving, NFC reads, parses the template from the external storage space and sends the timing operations. The execution efficiency of the whole process is equivalent to the way of storing the template based on the CPU memory.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. By introducing a template mechanism, a single template trigger of the CPU can drive the NFC to perform a series of timing operations. Compared with the traditional method of frequently configuring registers, the access frequency of the CPU to registers is greatly reduced, the timing interval of the ONFI interface is effectively shortened, and the data transmission bandwidth is significantly increased. Through actual testing, in typical storage application scenarios, the data bandwidth can be increased by more than 40%, reducing the burden of the CPU in timing control, enabling it to allocate more resources to other key task processing, such as data processing algorithms, system management, etc., improving the overall performance and response speed of the SSD controller, and enhancing the multitasking processing ability of the system;

[0021] 2. The present invention supports storing templates in the CPU memory or external storage space. Users can flexibly select the storage method according to system hardware resources, cost, and performance requirements, enhancing the applicability and scalability of the method, facilitating application and deployment in storage systems of different scales and application scenarios. Through standardized template design and strict operation procedures, errors and interferences that may be introduced due to frequent CPU operations are reduced, the accuracy and stability of ONFI interface operations are improved, the system failure risk is reduced, the service life of storage devices is extended, and data storage security is guaranteed; BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a schematic diagram of template execution for a method provided by the present invention to improve the timing trigger efficiency of the ONFI interface;

[0024] Figure 2 It is a template trigger flowchart for a method provided by the present invention to improve the timing trigger efficiency of the ONFI interface; DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] The following specific embodiments illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0026] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the following will further describe the present application in detail in combination with the drawings and specific implementation manners.

[0027] Referring to the attached Figure 1-2 , a method for improving the timing trigger efficiency of the ONFI interface in this embodiment includes the following steps:

[0028] Step 1: Create corresponding templates according to the usage scenarios of the NAND Flash memory;

[0029] Step 2: When the SSD controller chip is powered on, initialize all the used templates into the memory of the CPU and assign a unique memory starting address to each template;

[0030] Step 3: When the CPU needs to trigger a certain template, accurately configure the starting address and template length corresponding to the template into the registers of the NFC;

[0031] Step 4: The NFC actively reads the template content from the memory of the CPU through the AMBA bus according to the received template starting address and length;

[0032] Step 5: The NFC parses the read template item by item and accurately sends the corresponding timing operations to the NAND Flash memory through the ONFI interface according to the parsing results.

[0033] The templates in Step 1 are composed of several timing operations for implementing specific operations. The templates include write templates, read templates, and erase templates. And the sequence and content of the timing operations in each template strictly match the corresponding standard operation process. The allocation of the memory starting address in Step 2 is based on the memory management algorithm to ensure continuous and conflict-free address space. The configuration process in Step 3 follows a specific register writing protocol to ensure data integrity. The reading process in Step 4 adopts a high-speed data transmission mechanism to ensure fast and accurate data acquisition. The parsing and sending processes in Step 5 follow strict timing specifications to ensure the correctness of operations.

[0034] The content of the template can also be stored in an external storage space connected to the AMBA bus. The external storage space needs to meet specific storage performance and reliability requirements. During power-on and initialization, the CPU writes all the used templates to the external storage space through the AMBA bus and records the starting address and length corresponding to each template. The writing process adopts error correction coding technology to ensure the accuracy of data storage. When the NFC needs to control the NAND Flash to execute operations, the CPU triggers the template and configures the corresponding starting address and length into the registers of the NFC. After receiving it, the NFC reads, parses the template from the external storage space and sends the timing operations. The execution efficiency of the whole process is equivalent to the way of storing templates based on the CPU memory.

[0035] Finally, the above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for improving ONFI interface timing triggering efficiency, characterized in that: The following steps are involved: Step 1: Create a corresponding template based on the usage scenario of NAND Flash memory; Step 2: When the SSD controller chip is powered on, all used templates are initialized into the CPU's memory, and a unique memory start address is assigned to each template; Step 3: When the CPU needs to trigger a template, it will accurately configure the starting address and template length corresponding to the template into the NFC register; Step 4: NFC actively reads the template content from the CPU memory through the AMBA bus based on the received template start address and length; Step 5: NFC analyzes the read templates one by one, and accurately sends the corresponding timing operations to the NAND Flash memory through the ONFI interface based on the analysis results.

2. A method for improving ONFI interface timing triggering efficiency according to claim 1, characterized in that: The template described in step one is composed of several sequential operations for implementing specific operations, and the template includes a write template, a read template, and an erase template, and the sequence and content of the sequential operations in each template strictly match the corresponding standard operation process.

3. A method for improving ONFI interface timing triggering efficiency according to claim 2, characterized in that: The allocation of the memory start address described in step 2 is based on a memory management algorithm to ensure that the address space is continuous and conflict-free.

4. The method for improving ONFI interface timing triggering efficiency according to claim 3, characterized in that: The configuration process described in step three follows a specific register write protocol to ensure data integrity.

5. The method for improving ONFI interface timing triggering efficiency according to claim 4, characterized in that: The reading process described in step 4 uses a high-speed data transmission mechanism to ensure that data is quickly and accurately acquired.

6. A method for improving ONFI interface timing triggering efficiency according to claim 5, characterized in that: The parsing and sending process described in step 5 follows strict timing specifications to ensure correct operation.

7. A method for improving ONFI interface timing triggering efficiency according to claim 6, characterized in that: The content of the template may also be stored in an external storage space connected to the AMBA bus, and the external storage space needs to meet specific storage performance and reliability requirements.

8. The method for improving ONFI interface timing triggering efficiency according to claim 7, characterized in that: During the power-on and initialization process described in step 2, the CPU writes all templates used into the external storage space via the AMBA bus and records the starting address and length corresponding to each template. The writing process uses error correction coding technology to ensure data storage accuracy.

9. The method for improving ONFI interface timing triggering efficiency according to claim 8, characterized in that: When NFC needs to control NAND Flash to perform an operation, the CPU triggers the template and configures the corresponding starting address and length into the NFC register. After receiving it, NFC reads and parses the template from the external storage space and sends the timing operation. The execution efficiency of the whole process is comparable to that of the method based on CPU memory storage template.

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