A method for improving timing trigger efficiency of an onfi interface

Abstract

The application discloses a method for improving ONFI interface timing trigger efficiency, and relates to the technical field of solid state disk (SSD) and NAND Flash memory interface. The application introduces a template mechanism, and a series of timing operations can be driven by NFC through once template trigger of CPU. Compared with the traditional register configuration mode, the access frequency of CPU to the register is greatly reduced, the ONFI interface timing interval is effectively shortened, the data transmission bandwidth is significantly improved, and the data bandwidth can be improved by more than 40% in a typical storage application scene through actual test. The burden of CPU in timing control is reduced, more resources can be put into other key task processing, such as data processing algorithm and system management, the overall performance and response speed of the SSD controller are improved, and the multi-task processing capacity of the system is enhanced. The application supports template storage in CPU memory or external storage space, and the user can flexibly select the storage mode according to system hardware resources, cost and performance requirements.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) and NAND Flash memory interface technology, and more specifically, to a method for improving the timing triggering efficiency of the ONFI interface. Background Technology

[0002] In storage technology, ONFI, as an open NAND Flash interface protocol, specifies four interface timings between the SSD controller and the NAND Flash memory: command, address, data input, and data output. These timings ensure normal communication and facilitate data read, write, and erase operations. Typically, the SSD controller chip integrates a CPU, which triggers these timings by configuring registers. Specifically, the NFC module sets command, address, data input, and data output registers, and the CPU writes to these registers to trigger the corresponding timings. For example, during a write operation, the command, address, data input, and command registers are written sequentially to trigger the complete timing sequence. However, in on-chip systems, the CPU needs to frequently access the NFC registers via the AMBA bus to generate timings. If the configuration interval is large, it increases the ONFI interface timing interval, severely impacting data bandwidth and becoming a key factor restricting storage performance improvement.

[0003] Therefore, it is necessary to invent a method to improve the timing triggering efficiency of the ONFI interface to solve the above problems. Summary of the Invention

[0004] To overcome the aforementioned deficiencies in the prior art, this invention provides a method for improving the timing triggering efficiency of the ONFI interface. This addresses the problem mentioned in the background art, where the CPU frequently accesses the NFC register via the AMBA bus to generate timing data in an on-chip system. If the configuration interval is large, it will increase the timing interval of the ONFI interface, severely affecting data bandwidth and becoming a key factor restricting the improvement of storage performance.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a method for improving the timing triggering efficiency of an ONFI interface, comprising the following steps: Step 1: Create a corresponding template based on the usage scenario of NAND Flash memory. The template consists of several timing operations that implement specific operations. The template includes a write template, a read template, and an erase template. The order and content of the timing operations in each template strictly match the corresponding standard operation process. Step 2: When the SSD controller chip is powered on, initialize all the modules used into the CPU's memory and assign a unique memory starting address to each module; Step 3: When the CPU needs to trigger a certain template, it accurately configures the starting address and template length corresponding to that template into the NFC register; Step 4: Based on the received template start address and length, NFC actively reads the template content from the CPU's memory via the AMBA bus; Step 5: NFC parses the read template line by line, and sends the corresponding timing operations to the NAND Flash memory through the ONFI interface based on the parsing results; As a further description of the above technical solution, the allocation of the memory starting address in step two is based on a memory management algorithm to ensure that the address space is continuous and conflict-free; As a further description of the above technical solution, the configuration process in step three follows the register write protocol to ensure data integrity; As a further description of the above technical solution, the reading process in step four adopts a high-speed data transmission mechanism to ensure that the data is acquired quickly and accurately; As a further description of the above technical solution, the parsing and sending process described in step five follows timing specifications to ensure operational correctness.

[0006] Compared with the prior art, the beneficial effects of the present invention are: This invention introduces a template mechanism, allowing the CPU to drive the NFC to perform a series of timing operations with a single template trigger. Compared to the traditional method of frequently configuring registers, this greatly reduces the CPU's access frequency to registers, effectively shortens the ONFI interface timing interval, and significantly improves data transmission bandwidth. Actual testing shows that in typical storage application scenarios, data bandwidth can be increased by more than 40%, reducing the CPU's burden in timing control and allowing it to allocate more resources to other critical tasks, such as data processing algorithms and system management. This improves the overall performance and response speed of the SSD controller and enhances the system's multitasking capabilities. 2. This invention supports template storage in CPU memory or external storage space. Users can flexibly choose the storage method according to system hardware resources, cost and performance requirements, which enhances the applicability and scalability of the method and facilitates its application and deployment in storage systems of different scales and application scenarios. Through standardized template design and strict operation procedures, it reduces errors and interference that may be introduced by frequent CPU operations, improves the accuracy and stability of ONFI interface operation, reduces the risk of system failure, extends the service life of storage devices, and ensures data storage security. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0008] Figure 1 A template execution diagram illustrating a method for improving the timing triggering efficiency of an ONFI interface provided by this invention; Figure 2 A template triggering flowchart for a method to improve the timing triggering efficiency of the ONFI interface provided by the present invention; Detailed Implementation

[0009] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0011] See attached document Figure 1-2 This embodiment of a method for improving the timing triggering efficiency of an ONFI interface includes the following steps: Step 1: Create a corresponding template based on the usage scenarios of NAND Flash memory; Step 2: When the SSD controller chip is powered on, initialize all the modules used into the CPU's memory and assign a unique memory starting address to each module; Step 3: When the CPU needs to trigger a certain template, it accurately configures the starting address and template length corresponding to that template into the NFC register; Step 4: Based on the received template start address and length, NFC actively reads the template content from the CPU's memory via the AMBA bus; Step 5: NFC parses the read template line by line, and sends the corresponding timing operations to the NAND Flash memory through the ONFI interface based on the parsing results.

[0012] The template in Step 1 consists of several timing operations that implement specific operations. The template includes a write template, a read template, and an erase template. The order and content of the timing operations in each template strictly match the corresponding standard operation process. The allocation of the memory starting address in Step 2 is based on a memory management algorithm to ensure that the address space is continuous and conflict-free. The configuration process in Step 3 follows a specific register write protocol to ensure data integrity. The reading process in Step 4 uses a high-speed data transmission mechanism to ensure that data is acquired quickly and accurately. The parsing and sending process in Step 5 follows strict timing specifications to ensure the correctness of the operation.

[0013] The template content can also be stored in an external storage space connected to the AMBA bus. The external storage space must meet specific storage performance and reliability requirements. During power-on and initialization, the CPU writes all the templates used to the external storage space through the AMBA bus and records the starting address and length of each template. Error correction coding technology is used in the writing process to ensure data storage accuracy. When NFC needs to control NAND Flash to perform operations, the CPU triggers the template and configures the corresponding starting address and length into the NFC register. After receiving the template, the NFC reads and parses it from the external storage space and sends the timing operation. The execution efficiency of the whole process is comparable to that of the CPU memory-based template storage method.

[0014] In conclusion, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for improving the timing triggering efficiency of an ONFI interface, characterized in that: Includes the following steps: Step 1: Create a corresponding template based on the usage scenario of NAND Flash memory. The template consists of several timing operations that implement specific operations. The template includes a write template, a read template, and an erase template. The order and content of the timing operations in each template strictly match the corresponding standard operation process. Step 2: When the SSD controller chip is powered on, initialize all the modules used into the CPU's memory and assign a unique memory starting address to each module; Step 3: When the CPU needs to trigger a certain template, it accurately configures the starting address and template length corresponding to that template into the NFC register; Step 4: Based on the received template start address and length, NFC actively reads the template content from the CPU's memory via the AMBA bus; Step 5: NFC parses the read template line by line, and sends the corresponding timing operations to the NAND Flash memory through the ONFI interface based on the parsing results.

2. The method for improving the timing triggering efficiency of the ONFI interface according to claim 1, characterized in that: The allocation of the starting address of memory in step two is based on a memory management algorithm to ensure that the address space is contiguous and conflict-free.

3. The method for improving the timing triggering efficiency of the ONFI interface according to claim 2, characterized in that: The configuration process in step three follows the register write protocol to ensure data integrity.

4. The method for improving the timing triggering efficiency of the ONFI interface according to claim 3, characterized in that: The reading process in step four employs a high-speed data transmission mechanism to ensure fast and accurate data acquisition.

5. A method for improving the timing triggering efficiency of an ONFI interface according to claim 4, characterized in that: The parsing and sending process in step five follows timing specifications to ensure correct operation.

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