Method and device for supporting consistent multi-chip interconnection interruption

Abstract

The invention discloses a method and a device for supporting consistent multi-chip interconnection interruption. The method comprises the following steps: configuring the number of supported chips, and setting cross-chip parameters of the chips to determine the address of each chip and the depth of a routing table; the method comprises the following steps of: assigning a chip to be responsible for managing consistency, recording the chip as a management chip, configuring a routing table for each chip, mutually connecting all the chips, and assigning the number of low-speed peripheral interrupts managed by each chip; after the interrupt controller of a certain chip receives the interrupt, if the interrupt is a cross-chip interrupt, distributing the interrupt to the corresponding management chip through the network-on-chip and the high-speed interconnection interface according to the interrupt route configured in the routing table; and the management chip calls the interrupt processing program for processing and returns interrupt confirmation. The method can support current multi-chip interrupt consistency maintenance, realizes interrupt processing across any number of chips, improves the performance of a processor, and has the advantages of low hardware implementation complexity, small area overhead and high cost performance.

Description

Technical Field

[0001] The present invention relates to the technical field of multi-chip integration based on multi-chip systems, and particularly to a method and device for supporting coherent multi-chip interconnection interrupts. Background Art

[0002] In the past 50 years, the semiconductor industry has been advancing along the pace of Moore's Law. The density of transistors has been continuously increasing, gradually reaching the tens of billions level, bringing great challenges to density and cost. As Moore's Law approaches its limit, traditional single-chip semiconductor devices can no longer meet the performance or function requirements of some computationally intensive and workload-heavy applications. Multi-die systems are becoming a solution to transcend Moore's Law and address complex systemic challenges, expanding system functions faster in a cost-effective manner, reducing risks, achieving higher throughput with lower power consumption, and helping to meet the rapidly growing demand for processing power. At the same time, the emerging multi-chip module technology is a new generation of microelectronic packaging and assembly technology developed on the basis of printed circuit boards (PCBs) and surface mount technology (SMT) to adapt to the development direction of modern electronic systems towards short, small, light, thin, high-speed, high-performance, high-reliability, and low-cost. It is a powerful means to achieve system integration. With the development of multi-die systems, the number of integrated chips is increasing continuously, and traditional interrupt controllers are difficult to meet the interrupt interconnection and processing requirements in multi-die systems. Summary of the Invention

[0003] The technical problem to be solved by the present invention: In view of the above problems of the prior art, a method and device for supporting coherent multi-chip interconnection interrupts are provided. The present invention has the advantages of being able to expand chips and thus improve the performance of the processor, while having low hardware implementation complexity, small area overhead, and high cost performance.

[0004] To solve the above technical problems, the technical solution adopted by the present invention is as follows: A method for supporting coherent multi-chip interconnection interrupts, comprising: S101, configuring the number of supported chips through registers, setting cross-chip parameters of the chips to determine the addresses of each chip and the depth of the routing table; designating one chip to be responsible for management coherence as the management chip, configuring the routing table for each chip according to the depth of the routing table configured by the registers and interconnecting all the chips, and designating the number of slow peripheral interrupts managed by each chip; S102. When the interrupt controller of a certain chip receives an interrupt, it is dispatched to the processor core in the corresponding management chip or directly to the processor core in this chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table; the processor core calls the interrupt handling program for processing and returns an interrupt acknowledgment.

[0005] Optionally, the following configurations of the management chip and the remaining chips are kept consistent: the bit width of the routing attribute, the total number of slow peripheral interrupt groups, whether high-speed peripheral interrupts are supported, the security disable setting, the total number of supported chips, the chip address bit width, the number of routing attribute layers of the chip, and the number of cores supported by each chip.

[0006] Optionally, the routing table configured in step S101 consists of a set of registers that specify the connection relationships between any number of chips. The information configured includes: chip registers, which are used to describe the address for controlling cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, the status of routing table update, the connection status of the chip, etc.; chip default registers, which are used to describe the management chip responsible for managing consistency, the status of routing table update, etc.; chip status registers, which are used to describe the status of routing table consistency; configuring the routing table and interconnecting all chips in step S101 includes: S301. Configure the chip default register to specify a management chip to be responsible for managing consistency; S302. Configure the chip register of the chip responsible for managing consistency to specify the slow peripheral interrupt group managed by this chip; S303. Read the chip status register of the chip responsible for managing consistency until the routing table is in a consistent state; read the number of chips supported by the register configuration, and determine the addresses of each chip based on the cross-chip parameters of the chip. Traverse and select a chip from the set of chips other than the management chip as the chip to be connected; S304. Configure the chip register of the chip to be connected; S305. Read the chip default register until the routing table update is completed, and determine that the chip to be connected is connected; S306. Determine whether there are still un-traversed chips in the set of chips other than the management chip. If there are still un-traversed chips, continue to traverse and select a chip from the set of chips other than the management chip as the chip to be connected, and jump to step S304. Otherwise, determine that all chips are interconnected.

[0007] Optionally, the routing table is stored inside the interrupt controller, and each chip has a copy of the routing table. The information in the copies of the routing table in each chip should always be kept consistent. When the slow peripheral interrupt group allocation information or connection status of any chip changes, a synchronization operation of the copy of the routing table is triggered: S401, the chip where the slow peripheral interrupt group allocation information or connection status configuration has changed sends its configuration information to the management chip responsible for consistency management; S402, after receiving the request, the management chip responsible for consistency management updates the routing table; S403, the management chip responsible for consistency management sends the new routing table information to all connected chips to update the copies of the routing table inside the interrupt controller of each chip.

[0008] Optionally, in step S102, when the interrupt controller of a certain chip receives an interrupt, it includes judging the type of the interrupt. If the type of the interrupt is a slow peripheral interrupt, a high-speed peripheral interrupt, or a software interrupt type interrupt, then it is determined that the interrupt is a cross-chip interrupt, and it is dispatched to the processor core in the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table; otherwise, if the type of the interrupt is a private peripheral interrupt, then it is determined that the interrupt is a non-cross-chip interrupt, and it is directly dispatched to the processor core in this chip according to the interrupt routing configured in the routing table.

[0009] Optionally, step S102 also includes that when the interrupt is a non-cross-chip interrupt, directly dispatching it to the processor core in this chip according to the interrupt routing configured in the routing table includes: S501, the interrupt controller in this chip processes the interrupt by sending it to the processor core that initiated the private peripheral interrupt in this chip; S502, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its status to the active state; S503, after the processor core finishes processing, it clears the active state of the interrupt.

[0010] Optionally, the routing table groups multiple slow peripheral interrupts. Step S102 also includes that when the interrupt is a slow peripheral interrupt, directly dispatching it to the processor core in the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table includes: S601, obtain the configuration information of the slow peripheral interrupt group of this chip, and add the minimum value of the slow peripheral interrupt group to the number of slow peripheral interrupt groups to obtain the maximum value of the slow peripheral interrupt group; S602, compare the hardwired slow peripheral interrupt that is raised plus the minimum value of the slow peripheral interrupt group with the maximum value of the slow peripheral interrupt group; S603, if it is less than the maximum value of the slow peripheral interrupt group, obtain the routing information, send it to the specified processor core through the on-chip network and high-speed interconnect interface for processing, and jump to step S604; if it is greater than the maximum value of the slow peripheral interrupt group, report an error, end and exit. S604, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the status of the interrupt to the active state. S605, after the processor core finishes processing, clear the active state of the interrupt. Step S102 also includes that when the interrupt is a high-speed peripheral interrupt, it is dispatched to the processor core in the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table, including: S701, obtain the physical interrupt number and routing of the high-speed peripheral interrupt through conversion by the interrupt converter in the interrupt controller. S702, the interrupt controller sends it to the corresponding management chip through the on-chip network and high-speed interconnect interface according to the routing information. S703, read the interrupt configuration table to obtain the enable and priority information of the high-speed peripheral interrupt. S704, the interrupt controller sends the interrupt to the specified processor core for processing. S705, the processor core acknowledges the interrupt, and the interrupt controller clears the pending state of the high-speed peripheral interrupt. Step S102 also includes that when the interrupt is a software interrupt, it is dispatched to the processor core in the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table, including: S801, when the interrupt controller receives the software interrupt generation command, it returns a response to the processor core that initiates the software interrupt. S802, the interrupt controller sends the software interrupt to the specified processor core for processing according to the routing information. S803, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the status of the interrupt to the active state. S804, after the processor core finishes processing, clear the active state of the interrupt.

[0011] In addition, the present invention also provides a device supporting coherent multi-chip interconnect interrupts, including a microprocessor and a memory connected to each other, and the microprocessor is programmed or configured to execute the method for supporting coherent multi-chip interconnect interrupts.

[0012] In addition, the present invention also provides a computer-readable storage medium, in which a computer program is stored, and the computer program is used to be programmed or configured by a microprocessor to execute the method for supporting coherent multi-chip interconnect interrupts.

[0013] Compared with the prior art, the present invention mainly has the following advantages: The present invention includes adding multiple registers to achieve configuration of any number of chips. After configuring the number of chips, corresponding parameters, cross-chip address bit width, depth of the routing table, etc. will change accordingly. In addition, to support connection and consistency management of multiple chips, the register address space of the extended chip register is expanded. First, configure the chip default register to specify a chip management consistency. Secondly, configure the chip register to configure the slow peripheral interrupt group of this chip. Then complete the connection of all chips in sequence, initiate an interrupt, and send it to the corresponding processor core for processing according to its routing configuration. The processor core calls the interrupt handling program to perform interrupt response processing and return an interrupt confirmation. The present invention can support current multi-chip interrupt consistency maintenance, achieve interrupt processing across any number of chips, thereby improving the performance of the processor, and at the same time has the advantages of low hardware implementation complexity, small area overhead, and high cost performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of the basic process of the method according to an embodiment of the present invention.

[0015] Figure 2 It is a schematic diagram of the system topology structure according to an embodiment of the present invention.

[0016] Figure 3 It is a schematic diagram of multiple registers according to an embodiment of the present invention.

[0017] Figure 4 It is a schematic diagram of the routing table according to an embodiment of the present invention.

[0018] Figure 5 It is a schematic diagram of the routing table storage information according to an embodiment of the present invention.

[0019] Figure 6 It is a schematic diagram of the private peripheral interrupt processing flow according to an embodiment of the present invention.

[0020] Figure 7 It is a schematic diagram of the slow peripheral interrupt processing flow according to an embodiment of the present invention.

[0021] Figure 8 It is a schematic diagram of the high-speed peripheral interrupt processing flow according to an embodiment of the present invention.

[0022] Figure 9 It is a schematic diagram of the software interrupt processing flow according to an embodiment of the present invention.

[0023] Figure 10 It is a schematic diagram of the microprocessor connection topology structure of two sockets according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] Such as Figure 1As shown in the figure, the method for supporting coherent multi-chip interconnect interrupts in this embodiment includes: S101. Configure the number of supported chips (chips) through registers, set the cross-chip parameters of the chips to determine the addresses of each chip, and the depth of the routing table; designate one chip to be responsible for managing coherence as the management chip, configure the routing table for each chip according to the depth of the routing table configured by the register, and connect all the chips to each other; designate the number of slow peripheral interrupts that each chip is responsible for managing; in order to achieve complete coherence of the multi-chip configuration, this embodiment configures the number of supported chips through registers and sets relevant cross-chip parameters. In this embodiment, by designating which chip is responsible for managing coherence, configuring the routing table, designating the number of slow peripheral interrupts that each chip is responsible for managing, and connecting all the chips to each other; S102. When the interrupt controller of a certain chip receives an interrupt, it is dispatched to the processor core in the corresponding management chip or directly to the processor core in this chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table; the processor core calls the interrupt handling program to process it and returns an interrupt acknowledgment, as Figure 2 shown, where chip0 and chip1 respectively represent two different chips. It should be noted that Figure 2 only for exemplary illustration with two chips as an example, and the method of this embodiment is applicable to the case of multi-chip interconnection. Refer to Figure 2 . The microprocessor of this embodiment includes multiple chips, each chip includes an interrupt controller, an on-chip network, multiple processor cores, and a high-speed interconnect interface. The interrupt controller is connected to multiple slow peripherals and high-speed peripherals, and the interrupt controller is connected to multiple processor cores through the on-chip network. In order to achieve complete coherence of the connection and configuration of multiple chips, in this embodiment, the following configurations of the management chip and the remaining chips are kept consistent: the bit width of the routing attribute, the total number of slow peripheral interrupt groups, whether to support high-speed peripheral interrupts, the security disable setting, the total number of supported chips, the chip address bit width, the number of routing attribute layers of the chip, and the number of cores supported by each chip.

[0025] As Figure 3 shown, in this embodiment, a 32-bit multi-chip register is defined, and the register field is chip_num, which is used to identify the number of supported chips. After configuring chip_num, the following operations can be performed: S201. Set the number of supported chips according to chip_num; S202. Set the bit width of the cross-chip address according to the number of supported chips; S203. Set the depth of the routing table.

[0026] In this embodiment, the routing table configured in step S101 is composed of a group of registers that specify the connection relationships between any number of chips. The configured information includes: chip registers, which are used to describe the address for controlling cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, the status of routing table update, the connection status of the chip, etc.; chip default registers, which are used to describe the chip responsible for managing consistency, the status of routing table update, etc.; chip status registers, which are used to describe the status of routing table consistency, etc.

[0027] Configuring the routing table and interconnecting all chips in step S101 includes: S301, configuring the chip default register to specify a chip to be responsible for managing consistency; S302, configuring the chip register of the chip responsible for managing consistency to specify the slow peripheral interrupt group managed by this chip; S303, reading the chip status register of the chip responsible for managing consistency until the routing table is in a consistent state; reading the number of chips supported by the register configuration, and determining the addresses of each chip according to the cross-chip parameters of the chips, and traversing and selecting a chip from the chip set other than the management chip as the chip to be connected; S304, configuring the chip register of the chip to be connected; S305, reading the chip default register until the routing table update is completed, and determining that the chip to be connected is connected; S306, determining whether there are still chips in the chip set other than the management chip that have not been traversed. If there are still chips that have not been traversed, continue to traverse and select a chip from the chip set other than the management chip as the chip to be connected, and jump to step S304. Otherwise, it is determined that the interconnection of all chips is completed.

[0028] As Figure 4 shown, in this embodiment, the routing table is stored inside the interrupt controller. To maintain the consistency among multiple chips, each chip has a copy of the routing table (Chip0~Chipn), which is used to record information such as the allocation of slow peripheral interrupt groups, connection status, and consistency status of each chip. As Figure 5As shown, the chip number occupies 8 bits in [7:0], the minimum value of the slow peripheral interrupt group occupies 8 bits in [15:8], the number of slow peripheral interrupt groups occupies 8 bits in [23:16], the chip number of the management chip occupies 5 bits in [28:24], the connection status occupies 1 bit in

[29] , and the consistency status occupies 2 bits in [31:30], totaling 32 bits. And the routing table configuration information in each chip should always be consistent, and the slow peripheral interrupt group allocation information and connection status of any chip change. When the slow peripheral interrupt group allocation information and connection status of any chip change, the synchronization operation of the copy of the routing table is triggered: S401, the chip with the changed slow peripheral interrupt group allocation information and connection status sends its configuration information to the chip responsible for consistency management; S402, after receiving the request, the chip responsible for consistency management updates the routing table; S403, the chip responsible for consistency management sends the new routing table information to all connected chips to update the copy of the routing table inside the interrupt controller of each chip.

[0029] In this embodiment, it supports the processing of private peripheral interrupts, slow peripheral interrupts, high-speed peripheral interrupts, and software interrupt type interrupts, among which slow peripheral interrupts, high-speed peripheral interrupts, and software interrupt type interrupts support cross-chip processing. In step S102 of this embodiment, when the interrupt controller of a certain chip receives an interrupt, it includes judging the type of the interrupt. If the type of the interrupt is a slow peripheral interrupt, a high-speed peripheral interrupt, or a software interrupt type interrupt, it is determined that the interrupt is a cross-chip interrupt, and it is dispatched to the processor core in the corresponding management chip through the on-chip network and high-speed interconnect interface according to the interrupt routing configured in the routing table; otherwise, if the type of the interrupt is a private peripheral interrupt, it is determined that the interrupt is a non-cross-chip interrupt, and it is directly dispatched to the processor core in this chip according to the interrupt routing configured in the routing table.

[0030] As Figure 6 shown, step S102 also includes that when the interrupt is a non-cross-chip interrupt (private peripheral interrupt), directly dispatching it to the processor core in this chip according to the interrupt routing configured in the routing table includes: S501, the interrupt processor processes it by sending it to the processor core that initiated the private peripheral interrupt; S502, the processor core approves the interrupt and returns a response, and the interrupt controller sets its status to the active state; S503, after the processor core finishes processing, it clears the interrupt active state.

[0031] In this embodiment, the configuration of the routing table mainly affects the processing of slow peripheral interrupts. The routing table groups multiple slow peripheral interrupts as a group, specifically 32 slow peripheral interrupts as a group, supports 960 slow peripheral interrupts, that is, supports 30 slow peripheral interrupt groups.

[0032] like Figure 7 As shown, step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a slow peripheral interrupt, including: S601, obtaining configuration information of the slow peripheral interrupt group of the chip, and taking the minimum value of the slow peripheral interrupt group plus the number of the slow peripheral interrupt groups as the maximum value of the slow peripheral interrupt group; S602, comparing the minimum value of the slow peripheral interrupt hardwired line plus the slow peripheral interrupt group with the maximum value of the slow peripheral interrupt group; S603, if the speed is less than the maximum value of the slow peripheral interrupt group, the routing information is obtained and sent to the designated processor core for processing, and the process jumps to step S604; if the speed is greater than the maximum value of the slow peripheral interrupt group, an error is reported, and the process ends and exits; S604, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active; S605: The processor core completes the processing and clears the interrupt active state.

[0033] like Figure 8 As shown, step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table when the interrupt is a high-speed peripheral interrupt, including: S701, obtaining a physical interrupt number and a route of a high-speed peripheral interrupt through an interrupt converter in an interrupt controller; S702, the interrupt controller sends the message to the corresponding chip according to the route; S703, read the interrupt configuration table to obtain the enable and priority information of the high-speed peripheral interrupt; S704, the interrupt controller sends it to a designated processor core for processing; S705: The processor core acknowledges the interrupt and the interrupt controller clears the interrupt pending state.

[0034] like Figure 9 As shown, step S102 of this embodiment also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table when the interrupt is a software interrupt, including: S801, the interrupt controller receives a command to generate a software interrupt and returns a response to the processor core that initiated the software interrupt; S802, the interrupt controller sends the software interrupt to the specified processor core for processing according to the routing information; S803, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its status to the active state; S804, after the processor core finishes processing, it clears the interrupt active state.

[0035] In summary, the method of this embodiment includes adding multiple registers to implement the configuration of any number of chips. After configuring the number of chips, the corresponding parameters, the cross-chip address bit width, the depth of the routing table, etc. will change accordingly. In addition, to support the connection and consistency management of multiple chips, the register address space of the chip register is extended. First, configure the chip default register to specify a chip management consistency. Secondly, configure the chip register to configure the slow peripheral interrupt group of this chip. Complete the connection of all chips in sequence, initiate an interrupt, and send it to the corresponding processor core for processing according to its routing configuration. The processor core calls the interrupt handler to perform interrupt response processing and return an interrupt acknowledgment. The method of this embodiment can support the maintenance of multi-chip interrupt consistency in current multi-chips, can implement interrupt processing across any number of chips, thereby improving the performance of the processor, and at the same time has the advantages of low hardware implementation complexity, small area overhead, and high cost performance.

[0036] In addition, the present invention also provides a device for supporting high-speed peripheral message interrupts, including a microprocessor and a memory connected to each other. The microprocessor is programmed or configured to execute the method for supporting consistent multi-chip interconnection interrupts. As Figure 10 shown, multiple chips of the same socket Scoket or multiple chips of different sockets Scoket are connected through multiple high-speed interfaces, Figure 10 specifically, the microprocessors of 2 sockets Scoket, and each microprocessor includes 4 chips chip0-chip3. The interrupt controller of each chip is programmed or configured to execute the method for supporting consistent multi-chip interconnection interrupts.

[0037] In addition, the present invention also provides a computer-readable storage medium. The computer program stored in the computer-readable storage medium is used to be programmed or configured by the microprocessor to execute the method for supporting consistent multi-chip interconnection interrupts.

[0038] Those skilled in the art should understand that the technical solution provided by the present invention can be in the form of a method, a system, or a computer program product. Therefore, the present invention can be implemented in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can be in the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, and the combination of processes and / or blocks in the flowchart and / or block diagram, can be realized by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device realizes the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for realizing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0039] The above is only the preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, several improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A method for supporting consistent multi-chip interconnect interruption, characterized in that: include: S101, configure the number of supported chips through registers, set the cross-chip parameters of the chips to determine the addresses of each chip and the depth of the routing table; designate a chip responsible for managing consistency as the management chip, configure routing tables for each chip according to the depth of the routing table configured by the registers and connect all the chips to each other, and designate the number of slow peripheral interrupts that each chip is responsible for managing; S102, when the interrupt controller of a chip receives an interrupt, it dispatches it to the processor core in the corresponding management chip or directly to the processor core in the chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table; the processor core calls the interrupt handler to process it and returns an interrupt confirmation.

2. The method for supporting consistent multi-chip interconnect interruption according to claim 1, characterized in that: The following configurations of the management chip and the remaining chips remain consistent: the bit width of the routing attributes, the total number of slow peripheral interrupt groups, whether high-speed peripheral interrupts are supported, security disable settings, the total number of chips supported, the chip address bit width, the number of routing attribute layers of the chip, and the number of cores supported by each chip.

3. The method for supporting consistent multi-chip interconnect interruption according to claim 2, characterized in that: The routing table configured in step S101 is composed of a group of registers that specify the connection relationship between any number of chips, wherein the configured information includes: chip registers, which are used to describe the address of controlling cross-chip routing during cross-chip transmission, the starting value of the slow peripheral interrupt group managed by the chip, the number of slow peripheral interrupt groups managed by the chip, the status of routing table update, the connection status of the chip and other information; chip default registers, which are used to describe the management chip responsible for managing consistency, the routing table update status and other information; chip status registers, which are used to describe the consistency status of the routing table; configuring the routing table in step S101 and connecting all chips to each other includes: S301, configure the chip default register and designate a management chip to be responsible for managing consistency; S302, configuring the chip register responsible for managing the consistency chip, and specifying the slow peripheral interrupt group managed by the chip; S303, read the chip status register responsible for managing the consistency chip until the routing table is in a consistent state; read the number of chips supported by the register configuration, and determine the address of each chip according to the cross-chip parameters of the chip, and traverse and select a chip from the chip set other than the management chip as the chip to be connected; S304, configuring the chip register of the chip to be connected; S305, reading the chip default register until the routing table is updated and it is determined that the chip to be connected is connected; S306, determine whether there are still chips that have not been traversed in the chip set other than the management chip. If there are still chips that have not been traversed, continue to traverse and select one chip from the chip set other than the management chip as the chip that needs to be connected, and jump to step S304; otherwise, determine that all chips are connected to each other.

4. The method for supporting consistent multi-chip interconnect interruption according to claim 3, characterized in that: The routing table is stored inside the interrupt controller, and each chip has a copy of the routing table, and the information of the copy of the routing table in each chip must always be consistent. When the slow peripheral interrupt group allocation information or connection status of any chip changes, the synchronization operation of the copy of the routing table is triggered: S401, the chip where the slow peripheral interrupt group allocation information and connection status configuration change occurs sends its configuration information to the management chip responsible for consistency management; S402, after receiving the request, the management chip responsible for consistency management updates the routing table; S403, the management chip responsible for consistency management sends the new routing table information to all connected chips to update the copy of the routing table inside the interrupt controller of each chip.

5. The method for supporting consistent multi-chip interconnect interruption according to claim 1, characterized in that: In step S102, when the interrupt controller of a chip receives an interrupt, it determines the type of interrupt. If the interrupt type is a slow peripheral interrupt, a high-speed peripheral interrupt, or a software interrupt type interrupt, the interrupt is determined to be a cross-chip interrupt, and is dispatched to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table; otherwise, if the interrupt type is a private peripheral interrupt, the interrupt is determined to be a non-cross-chip interrupt, and is directly dispatched to the processor core in the current chip according to the interrupt route configured in the routing table.

6. The method for supporting consistent multi-chip interconnect interruption according to claim 5, characterized in that: Step S102 also includes directly dispatching the interrupt to the processor core in the current chip according to the interrupt route configured in the routing table when the interrupt is a non-cross-chip interrupt, including: S501, the interrupt controller in the chip processes the interrupt by sending the interrupt to the processor core in the chip that initiates the private peripheral interrupt; S502, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets its state to active; S503, after the processor core completes the processing, clear the active state of the interrupt.

7. The method for supporting consistent multi-chip interconnect interruption according to claim 5, characterized in that: The routing table is a group of multiple slow peripheral interrupts. Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a slow peripheral interrupt, including: S601, obtaining configuration information of the slow peripheral interrupt group of the chip, and taking the minimum value of the slow peripheral interrupt group plus the number of the slow peripheral interrupt groups as the maximum value of the slow peripheral interrupt group; S602, comparing the minimum value of the slow peripheral interrupt hardwired line plus the slow peripheral interrupt group with the maximum value of the slow peripheral interrupt group; S603, if the speed is less than the maximum value of the slow peripheral interrupt group, the routing information is obtained, and the information is sent to the designated processor core for processing through the on-chip network and the high-speed interconnect interface, and the process jumps to step S604; if the speed is greater than the maximum value of the slow peripheral interrupt group, an error is reported, and the process ends and exits; S604, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the state of the interrupt to an active state; S605, the processor core completes processing and clears the active state of the interrupt.

8. The method for supporting consistent multi-chip interconnect interruption according to claim 7, characterized in that: Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the interrupt route configured in the routing table when the interrupt is a high-speed peripheral interrupt, including: S701, obtaining a physical interrupt number and a route of a high-speed peripheral interrupt through an interrupt converter in an interrupt controller; S702, the interrupt controller sends the information to the corresponding management chip through the on-chip network and the high-speed interconnection interface according to the routing information; S703, read the interrupt configuration table to obtain the enable and priority information of the high-speed peripheral interrupt; S704, the interrupt controller sends the interrupt to a designated processor core for processing; S705, the processor core recognizes the interrupt, and the interrupt controller clears the suspended state of the high-speed peripheral interrupt; Step S102 also includes dispatching the interrupt to the processor core in the corresponding management chip through the on-chip network and the high-speed interconnect interface according to the interrupt route configured in the routing table when the interrupt is a software interrupt, including: S801, the interrupt controller receives a command to generate a software interrupt and returns a response to the processor core that initiated the software interrupt; S802, the interrupt controller sends the software interrupt to the designated processor core for processing according to the routing information; S803, the processor core acknowledges the interrupt and returns a response, and the interrupt controller sets the interrupt status to active; S804: The processor core completes the processing and clears the active state of the interrupt.

9. A device supporting consistent multi-chip interconnect interruption, comprising a microprocessor and a memory connected to each other, characterized in that: The microprocessor is programmed or configured to execute the method for supporting consistent multi-chip interconnect interruption as claimed in any one of claims 1 to 8.

10. A computer-readable storage medium having a computer program stored therein, characterized in that: The computer program is used to be programmed or configured by a microprocessor to execute the method for supporting consistent multi-chip interconnect interruption as claimed in any one of claims 1 to 8.

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