Port bandwidth allocation circuit and method of PCIe equipment

Abstract

The invention discloses a port bandwidth allocation circuit and method for PCIe equipment, the circuit comprises at least one CPU and a plurality of corresponding ports, the ports are inserted into the PCIe equipment through a socket circuit, the port bandwidth allocation circuit further comprises connectors connected with the ports, when the socket circuit of each port is inserted into the first PCIe equipment or the second PCIe equipment, different levels are output at the in-place detection end, and when the first PCIe equipment or the second PCIe equipment is inserted into the second PCIe equipment, different levels are output at the in-place detection end. When the second PCIe equipment with different bandwidth allocation modes is inserted, different voltage division circuits are formed, and the equipment detection signal end outputs different level voltages; the connector is used for detecting an in-place detection signal and an equipment detection signal and sending the signals to the CPU; and the CPU allocates the port bandwidth of the PCIe equipment according to the in-place detection signal and the equipment detection signal of each port. Therefore, the problem that IO resources are wasted by adopting dynamic bandwidth allocation or a fixed bandwidth allocation mode is not flexible in the prior art is solved.

Description

Technical Field

[0001] This application relates to the technical field of bus bandwidth allocation, and particularly relates to a port bandwidth allocation circuit and method for a PCIe device. Background Art

[0002] With the rapid development of the information age, technologies such as the Internet and artificial intelligence have covered all fields of society. This has led to an increasing number of functional requirements and more complex designs for servers. Meeting more functional requirements with limited logic resources is also a new challenge.

[0003] The chip logic resources on server products are limited, and different functional requirements require different amounts of logic resources. Currently, simple requirements can occupy a large amount of the chip's logic resources. If the design is improper, it will cause waste of logic resources, thereby affecting the introduction of other functional requirements.

[0004] For the existing Intel platform, a server includes at least one CPU (Central Processing Unit), and each CPU is connected to PCIe devices through PCIe (peripheral component interconnect express). The PCIe (peripheral component interconnect express) of each CPU is divided into 5 ports, and one port is connected to one PCIe device. The bandwidth allocation mode of each port can be configured as X16, X8, X4, or X1. In related technical solutions, in order to achieve dynamic bandwidth allocation for each PCIe port, for each port, the CPU needs to make a determination through 4 bit positions, which requires 4 IO (Input / Output) port pin resources. In this way, a single CPU will use 20 IO port pins to implement bandwidth allocation, and 2 CPUs will use 40 IO port pins, resulting in serious waste of IO resources. To save IO resources, each Port can adopt fixed bandwidth allocation, but this lacks flexibility. Summary of the Invention

[0005] The purpose of this application is to provide a port bandwidth allocation circuit and method for a PCIe device, which is used to solve the problem that existing dynamic bandwidth allocation wastes IO resources or the fixed bandwidth allocation method lacks flexibility.

[0006] In a first aspect, an embodiment of the present application provides a port bandwidth allocation circuit for a PCIe device. The circuit includes at least one CPU and multiple ports Port connected to each CPU. The ports Port are inserted into a first PCIe device or a second PCIe device through a socket circuit. The circuit further includes a connector connected to each port Port, where:

[0007] The socket circuit of each port Port includes a presence detection terminal and a device detection terminal. When the socket circuit is inserted into the first PCIe device or the second PCIe device, the presence detection terminal outputs different levels. When inserted into the second PCIe device with different bandwidth allocation modes, a different voltage division circuit is formed, and the device detection signal terminal outputs different level voltages as the voltage division terminal of the voltage division circuit;

[0008] The connector is used to detect the presence detection signal and the device detection signal according to the levels of the presence detection terminal and the device detection terminal and send them to the CPU;

[0009] The CPU determines to allocate a fixed bandwidth when the first PCIe device is inserted according to the presence detection signal and the device detection signal of each port Port. When it is determined that the second PCIe device is inserted, the bandwidth is allocated according to the corresponding bandwidth allocation mode according to the level voltage of the device detection signal.

[0010] For the above circuit in the embodiment of the present application, the connector only outputs two signals, namely the presence detection signal and the device detection signal, saving IO resources. Moreover, it can support the CPU to detect that the first PCIe device, the second PCIe device and the corresponding bandwidth allocation mode are currently inserted, so as to support the CPU to allocate the bandwidth of various types of inserted PCIe devices. While supporting dynamic bandwidth allocation, it also saves IO resources at the same time and will not cause waste of IO resources.

[0011] In some possible embodiments, the socket circuit includes a first socket circuit for inserting the first PCIe device and a second socket circuit for inserting the second PCIe device;

[0012] The first socket circuit includes a first presence detection terminal and a first device detection terminal. When the first PCIe device is not inserted, both the first presence detection terminal and the first device detection terminal are at a high level. When the first PCIe device is inserted, the first presence detection terminal is at a low level;

[0013] The second socket circuit includes a second presence detection terminal and a second device detection terminal. When the second PCIe device is not inserted, both the second presence detection terminal and the second device detection terminal are at a high level. When the second PCIe device is inserted, the second presence detection terminal is at a high level, and the first presence detection terminal outputs a low-level voltage corresponding to the bandwidth allocation mode of the second PCIe device.

[0014] The connector is used to output a presence detection signal and a device detection signal to the CPU according to the levels of the first presence detection terminal, the first device detection terminal, the second presence detection terminal, and the second device detection terminal.

[0015] In the above circuit provided by the embodiment of the present application, not only does the first socket circuit include a presence detection terminal and a device detection terminal, but the second socket circuit also includes a presence detection terminal and a device detection terminal. The connector in the embodiment of the present application connects the first socket circuit and the second socket circuit and outputs a presence detection signal and a device detection signal. By designing different level combinations in the embodiment of the present application, it is possible to detect the situation of neither the first PCIe device nor the second PCIe device being inserted, the first PCIe device being inserted, the second PCIe device being inserted, and the corresponding bandwidth allocation mode through only two signals, saving half of the IO resources compared with the prior art which requires 4 pins.

[0016] In some possible embodiments, the first PCIe device includes an NVME disk and a SAS / SATA disk. When the first socket circuit inserts the NVME disk, the first device detection terminal is at a low level. When the first socket circuit inserts the SAS / SATA disk, the first device detection terminal is at a high level; or

[0017] When the first socket circuit inserts the NVME disk, the first device detection terminal is at a high level. When the first socket circuit inserts the SAS / SATA disk, the first device detection terminal is at a low level.

[0018] In the embodiment of the present application, by the device detection signal being at a high level or a low level, it can be determined that the first PCIe device or the second PCIe device is currently inserted. When it is determined that the second PCIe device is inserted, in order to distinguish whether the inserted disk is an NVME disk or a SAS / SATA disk, different levels are correspondingly designed to be output at the device detection terminal, so that the type of the connected hard disk can be distinguished.

[0019] In some possible embodiments, the circuit further includes:

[0020] A signal transmission circuit connected between the connector and the CPU;

[0021] The signal transmission circuit includes a BMC and an IO detection module corresponding to each CPU. The IO detection module converts the voltages of the in-position detection signal and the device detection signal received from the connector connected to multiple ports Port of the corresponding CPU through the in-position detection pin and the device detection pin into corresponding register values and sends them to the BMC;

[0022] The BMC is used to transmit the register values corresponding to the in-position detection signal and the device detection signal to the corresponding CPU through the eSPI bus.

[0023] In the embodiment of the present application, the IO detection module can convert the voltage signal into a register value readable by I2C, output two corresponding signals, and transmit them to the BMC through I2C. The BMC then transmits them to the CPU through the eSPI protocol. These signals are input through the cable by the first socket circuit or the second socket circuit; the IO detection module converts the voltages of these two collected signals into register values for the CPU to perform PCIe bandwidth allocation for these 5 ports Port.

[0024] In some possible embodiments, the second socket circuit includes a first slot connected to the ground wire and multiple second slots. Each second slot is connected to the second device detection end through a voltage-dividing resistor, and the second device detection end is connected to the power supply through a pull-up resistor. Among them, when second PCIe devices with different bandwidth allocation modes are inserted, the first slot is connected to the corresponding number of second slots to form different voltage-dividing circuits.

[0025] In the embodiment of the present application, according to the connection of the second PCIe device with different bandwidth allocation modes to the second socket circuit, different voltages are divided by the number of connected second slots. Since the above second slots are connected to the second device detection end through voltage-dividing resistors, the more the number of connected second slots, the smaller the resistance value of the corresponding parallel voltage-dividing resistors, and the smaller the corresponding low-level voltage, thus realizing the distinction of different bandwidth modes.

[0026] In some possible embodiments, the first socket circuit is arranged on the backplane, the second socket circuit is a Riser card arranged on the main board, the first PCIe device is a hard disk, and the second PCIe device is a PCIe card corresponding to different bandwidth allocation modes.

[0027] The embodiment of the present application supports detecting whether a Rsier card is inserted into a PCIe card and the corresponding bandwidth allocation mode, and whether a hard disk is inserted on the backplane only through two signal pins, thereby supporting dynamic bandwidth allocation for the X1 mode, X4 mode, X8 mode, and X16 mode of the PCIe card.

[0028] In some possible embodiments, the resistance values of the voltage-dividing resistors connected to each second slot are equal;

[0029] The CPU pre - determines the low - level voltage of the device detection end corresponding to the voltage - dividing circuit corresponding to different bandwidth allocation modes according to the resistance value of the pull - up resistor, the power supply voltage, and the resistance value of the voltage - dividing resistor.

[0030] In the embodiments of the present application, the resistance values of the voltage - dividing circuits corresponding to different bandwidth allocation modes are relative, which can more conveniently pre - determine the voltage - dividing values corresponding to different bandwidth allocation modes.

[0031] In some possible embodiments, the CPU is specifically configured to determine that when the in - position detection signal is high and the device detection signal is high, the first socket circuit is not inserted with the first PCIe device and the second socket circuit is not inserted with the second PCIe device; when the in - position detection signal is low, it is determined that the first socket circuit is inserted with the first PCIe device; when the in - position detection signal is high and the device detection signal is at the low - level voltage, it is determined that the second socket circuit is inserted with the second PCIe device, and determine the corresponding bandwidth allocation mode according to the low - level voltage.

[0032] In the embodiments of the present application, the connector obtains the device detection signal and the in - position detection signal by detecting the first socket circuit and the second socket circuit. Through the above - designed level combinations in the embodiments of the present application, it can be identified whether a PCIe device is inserted and the type of the inserted PCIe device.

[0033] In some possible embodiments, the different bandwidth allocation modes include X1 mode, X4 mode, X8 mode, and X16 mode. When the second socket circuit is inserted with a second PCIe device in X1 mode, the first slot is connected to one second slot; when the second socket circuit is inserted with a second PCIe device in X4 mode, the first slot is connected to two second slots; when the second socket circuit is inserted with a second PCIe device in X8 mode, the first slot is connected to three second slots; when the second socket circuit is inserted with a second PCIe device in X16 mode, the first slot is connected to four second slots.

[0034] In the embodiments of the present application, according to the fact that the second PCIe device is connected to the second socket circuit through the gold fingers and the number of connected second slots is different, the number of second slots connected when the PCIe device of different bandwidth allocation modes is inserted into the second socket circuit is designed, so as to form different voltage - dividing circuits to identify the bandwidth allocation mode.

[0035] In a second aspect, the embodiments of the present application further provide a method for allocating port bandwidth of a PCIe device, including:

[0036] Receives the presence detection signals and device detection signals of multiple ports of each CPU transmitted by the connector, where the connector is used to detect the presence detection signal and device detection signal according to the levels of the presence detection terminal and device detection terminal of the socket circuit of each port;

[0037] According to the presence detection signal and device detection signal, it is determined that a fixed bandwidth is allocated when inserting the first PCIe device, and when inserting the second PCIe device, the bandwidth is allocated according to the level voltage of the device detection signal by connecting the pull-up resistor to the power supply.

[0038] The above-mentioned level combination designed in the embodiment of the present application can identify whether a PCIe device is inserted and the type of the inserted PCIe device. Since the type of the accessed PCIe device can be identified only through two signals, and when it is determined that a PCIe device is accessed, it supports allocating the bandwidth according to the corresponding bandwidth allocation mode according to the power supply of the device detection signal, thereby realizing dynamic bandwidth allocation while saving IO resources.

[0039] Other features and advantages of the present application will be described in the subsequent description, and, in part, will be obvious from the description, or will be understood by implementing the present application. The objectives and other advantages of the present application can be achieved and obtained by the structures specifically pointed out in the written description, claims, and drawings. Description of the Drawings

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. Obviously, the drawings introduced below are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 It is a schematic diagram of the PCIe bandwidth allocation scheme in the related art;

[0042] Figure 2 It is a schematic diagram of the port bandwidth allocation circuit of the PCIe device provided according to the embodiment of the present application;

[0043] Figure 3 It is a schematic diagram of the first gold finger of inserting a PCIe card in the related art;

[0044] Figure 4 It is a schematic diagram of the slot of the Riser card in the related art;

[0045] Figure 5 It is an equivalent circuit diagram corresponding to inserting a Riser card into a PCIe card in the related art;

[0046] Figure 6 Detailed circuit diagram of the port bandwidth allocation circuit of the PCIe device provided according to the embodiments of the present application;

[0047] Figure 7 Enlarged view of the connection between the IO detection module and the MCIO in the embodiments of the present application;

[0048] Figure 8 Schematic diagram of the slot of the Riser card provided according to the embodiments of the present application;

[0049] Figure 9 Equivalent circuit diagram corresponding to the PCIe card inserted in the X1 mode in the embodiments of the present application;

[0050] Figure 10 Equivalent circuit diagram corresponding to the PCIe card inserted in the X4 mode in the embodiments of the present application;

[0051] Figure 11 Equivalent circuit diagram corresponding to the PCIe card inserted in the X8 mode in the embodiments of the present application;

[0052] Figure 12 Equivalent circuit diagram corresponding to the PCIe card inserted in the X16 mode in the embodiments of the present application;

[0053] Figure 13 Flowchart of the port bandwidth allocation method of the PCIe device provided according to the embodiments of the present application. Detailed implementation manners

[0054] To further illustrate the technical solutions provided by the embodiments of the present application, the following will be described in detail with reference to the accompanying drawings and specific implementation manners. Although the embodiments of the present application provide the method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or non-creative labor. In steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiments of the present application. When the method is actually processed or executed by the control device, it may be executed in the order shown in the embodiments or drawings or executed in parallel.

[0055] Explanation of relevant technical terms involved in the embodiments of the present application is as follows:

[0056] 1) CPLD (Complex Programmable Logic Device, complex programmable logic unit): Users can burn the compiled CPLD program into the CPLD chip through a dedicated CPLD program burner, so as to realize the digital logic function of the program design. Therefore, the CPLD can replace discrete digital logic chips to realize various digital logic functions by writing a hardware program with specific logic.

[0057] 2) BMC (Baseboard Manager Controller): It is a small operating system independent of the server system. It is a chip integrated on the motherboard, and there are also products inserted on the motherboard in the form of PCI-E, etc. Its external manifestation is just a standard RJ45 network port, with a firmware system having an independent IP. Server clusters generally use BMC instructions for large-scale unattended operations, including remote management, monitoring, installation, restart, etc. of servers.

[0058] 3) MCIO (Mini Cool Edge Iuput / Output) connector: It is an interface technology that combines multiple physical channels into a high-speed data stream. According to application requirements, MCIO interfaces are divided into multiple types, among which MCIO 4I and MCIO 8I are the two most common types. MCIO 4I combines four physical channels into a high-speed data stream, achieving parallel data transmission and effectively improving the efficiency and real-time performance of data transmission. It supports multiple data transmission protocols such as PCIe, CXL, etc., and can meet the needs of different devices and applications.

[0059] 4) eSPI (Enhance Serial Peripheral interface), as a new communication bus between the CPU and low-speed peripherals, is compatible with SPI under a one-master-multiple-slaves architecture and introduces the concept of channels.

[0060] 5) PCIe (peripheral component interconnect express): It can be regarded as a more direct data connection to the motherboard. PCIe interfaces vary according to the bus bit width. A PCIe connection can be configured with at least data bandwidths of X1, X4, X8, and X16.

[0061] 6) PCB (PrintedCircuitBoard): It is an important electronic component, a support for electronic components, and a carrier for the electrical connection of electronic components;

[0062] 7) NVME (Non Volatile Memory Express): It is a logical device interface specification, a bus transmission protocol specification based on the device logical interface (equivalent to the application layer in a communication protocol), used to access non-volatile memory media attached through the PCI Express (PCIe) bus (such as solid-state disk drives using flash memory);

[0063] 8) SAS / SATA (Serial Attached SCSI / Serial Advanced Technology Attachment; Serial Attached Small Computer System Interface / Serial High-Technology Configuration Interface), where SAS stands for Serial Attached SCSI, which is a new generation of SCSI technology. Similar to the currently popular SATA hard drives, it uses serial technology to achieve higher transfer speeds and improves the internal space by shortening the connection cables, etc.;

[0064] 9) PRESENT: The device presence detection signal in the SFF-8639 specification. When the device is inserted or removed, the signal presents different levels.

[0065] 10) IFDET, the interface type detection signal in the SFF-8639 specification, i.e., the device detection signal. When an NVME drive or a SAS / SATA drive is inserted, the signal presents different levels.

[0066] For existing Intel platforms, a server may include multiple CPUs. As Figure 1 shown, the server CPU includes CPU0 and CPU1. The PCIe of each CPU is divided into 5 ports, Port. The CPU is connected to the CPLD through eSPI, and the CPLD is connected to the ports, Port, in the PCIe of each CPU. To achieve dynamic allocation of the data bandwidth for each port, specifically, each port can be configured into a bandwidth allocation mode of X16 mode, X8 mode, X4 mode, or X1 mode to insert PCIe devices with different bandwidth allocation modes. These configuration requirements are determined by 4 Bit bits, that is, four pins, BIF0, BIF1, BIF2, and BIF3, are introduced by the CPLD into the MCIO connector accessed by the corresponding port. Specifically, each CPU includes MCIO_0 - MCIO_4 connectors. By setting the high and low levels of the 4 Bit bits, the CPU determines the configured bandwidth allocation mode. Exemplarily, for each port, when BIF0, BIF1, BIF2, and BIF3 are 1, 0, 0, 0, the CPU determines that the configured bandwidth allocation mode is X1; when BIF0, BIF1, BIF2, and BIF3 are 0, 1, 0, 0, the CPU determines that the configured bandwidth allocation mode is X4; when BIF0, BIF1, BIF2, and BIF3 are 0, 0, 1, 0, the CPU determines that the configured bandwidth allocation mode is X8; when BIF0, BIF1, BIF2, and BIF3 are 0, 0, 0, 1, the CPU determines that the configured bandwidth allocation mode is X16.

[0067] In the above dynamic data bandwidth configuration method, since each port requires 4 pins, the 5 ports of the CPU need to be allocated into X16 mode, X8 mode, X4 mode or X1 mode according to the configuration requirements, a total of 20 BIF values are required. That is, a single CPU will use 20 pins to achieve bandwidth allocation, and 2 CPUs will use 40 pins. In this way, 40 pins on the CPLD will be occupied. The CPLD transfers the high and low levels of these 40 pins to the CPU through the eSPI protocol, and the CPU performs corresponding PCIe bandwidth allocation.

[0068] The above PCIe bandwidth allocation scheme will occupy a large amount of logic resources of the CPLD. Similarly, it will also occupy a part of the PCB board area and affect signal routing.

[0069] As another possible implementation, the current PCIe bandwidth allocation scheme is a fixed method, that is, a BIF value corresponding to a certain port. The pull-up and pull-down resistors corresponding to this BIF value are fixed, so that a corresponding fixed bandwidth allocation mode can be achieved. Although this method can save IO resources, it can only configure a unique bandwidth allocation mode and cannot dynamically configure X16, X8 or X4, lacking flexibility.

[0070] In view of the problems that dynamic bandwidth allocation wastes IO resources or the fixed bandwidth allocation method lacks flexibility in the related art. This application proposes a port bandwidth allocation circuit and method for PCIe devices that can perform dynamic bandwidth allocation for PCIe devices and save IO resources.

[0071] As Figure 2 shown, an embodiment of this application provides a port bandwidth allocation circuit for a PCIe device. The circuit includes at least one CPU and multiple ports connecting each CPU. The ports are inserted into a first PCIe device or a second PCIe device through a socket circuit. The circuit is also connected to a connector connected to each port, where:

[0072] The socket circuit of each port includes a presence detection end and a device detection end. When the socket circuit is inserted into the first PCIe device or the second PCIe device, the presence detection end outputs different levels. When inserted into the second PCIe device with different bandwidth allocation modes, different voltage dividing circuits are formed, and the device detection signal end outputs different level voltages as the voltage dividing end of the voltage dividing circuit;

[0073] The connector is used to detect the presence detection signal and the device detection signal according to the levels of the presence detection end and the device detection end and send them to the CPU;

[0074] The CPU determines to allocate a fixed bandwidth when the first PCIe device is inserted according to the presence detection signal and the device detection signal of each port Port, and determines that when the second PCIe device is inserted, the bandwidth is allocated according to the corresponding bandwidth allocation mode according to the level voltage of the device detection signal.

[0075] The port bandwidth allocation circuit of the PCIe device provided by the embodiment of the present application may be, but is not limited to, the motherboard circuit of the server. The motherboard circuit of the server usually includes multiple CPUs. The PCIe bus of each CPU is connected to the PCIe device through multiple ports Port. For each port Port, the PCIe device can be connected through the socket circuit. If the interface types of the PCIe devices are different, the corresponding socket circuits are different. In the embodiment of the present application, each port Port supports accessing the first PCIe device and the second PCIe device with different interface types. In some possible embodiments, the first PCIe device is a hard disk, and the second PCIe device is a PCIe card corresponding to different bandwidth allocation modes. The configurable bandwidth allocation modes of the PCIe card in the present application include X1 mode, X4 mode, X8 mode, and X16 mode. The hard disk includes an NVME disk, and the configurable bandwidth allocation mode of the NVME disk is fixed to the X4 mode.

[0076] In order to support the dynamic bandwidth allocation of the second PCIe device while saving IO resources in the embodiment of the present application, the circuit further includes a connector connected to each port Port. The socket circuit of each port Port includes a presence detection end and a device detection end. When the first PCIe device or the second PCIe device is inserted, the presence detection end outputs different levels. When the second PCIe device with different bandwidth allocation modes is inserted, different voltage dividing circuits are formed, and the device detection signal end outputs different level voltages as the voltage dividing end of the voltage dividing circuit. The connector is used to detect the presence detection signal and the device detection signal according to the levels of the presence detection end and the device detection end and send them to the CPU. Since different levels are output by the presence detection end when the first PCIe device or the second PCIe device is inserted, the CPU can determine whether the first PCIe device or the second PCIe device is inserted according to the level of the presence detection signal. As a possible implementation manner, when the first PCIe device is inserted, the presence detection signal is at a low level, and when the second PCIe device is inserted, the presence detection signal is at a high level, or when the first PCIe device is inserted, the presence detection signal is at a high level, and when the second PCIe device is inserted, the presence detection signal is at a low level. When it is determined that the second PCIe device is inserted, since the device detection signal end outputs different level voltages as the voltage dividing end of the voltage dividing circuit, the current corresponding bandwidth allocation mode can be determined according to the level voltage of the device detection signal, so as to support the dynamic bandwidth allocation of the inserted second PCIe device.

[0077] In the embodiments of the present application, the low level refers to the level with a voltage of 0, the high level refers to the level with a voltage of the power supply voltage, and the low-level voltage is the level between 0 and the power supply voltage.

[0078] In order to detect the non-insertion of the first PCIe device and the second PCIe device in the embodiments of the present application, other level combinations different from the level combinations corresponding to the in-position detection terminal and the device detection terminal when detecting the insertion of the first PCIe device or the second PCIe device can be set, so as to support the detection of the non-insertion of the first PCIe device and the second PCIe device.

[0079] In the above circuit of the embodiments of the present application, the connector only outputs two signals, namely the in-position detection signal and the device detection signal, which saves IO resources and supports the CPU to detect that neither the first PCIe device nor the second PCIe device is inserted, the first PCIe device is inserted, the second PCIe device is inserted, and the corresponding bandwidth allocation mode, so as to support the CPU to allocate bandwidth to various types of inserted PCIe devices. While supporting dynamic bandwidth allocation, it also saves IO resources at the same time and will not cause waste of IO resources.

[0080] In some possible embodiments, the first socket circuit is disposed on the backplane, the second socket circuit is a Riser card disposed on the motherboard, the above Riser card is connected to the PCIe card through the first gold finger, and the bandwidth allocation modes of the PCIe cards accessed by the Riser card include X1 mode, X4 mode, X8 mode, and X16 mode. The above hard disks include SAS / SATA disks and NVME disks, and the SAS / SATA disks or NVME disks are connected to the slots on the backplane through the second gold finger.

[0081] As Figure 3 shown is the plug schematic of the first gold finger in the related art. The plug of the first gold finger includes Present1#, Present2 N1, Present2 N2, Present2 N3, Present2 N4. As Figure 4The figure shows a schematic diagram of the Riser card slot, which includes slots Present1#, Present2_N1, Present2_N2, Present2_N3, and Present2_N4. When PCIe devices with different bandwidth allocation modes are inserted into the Riser card through the first gold fingers, the number of corresponding plugs connected to the slots is different. Among them, when a PCIe device in X1 mode is inserted, the plug Present1# is connected to the slot Present1#, and the plug Present2_N1 is connected to the slot Present2_N1. When a PCIe device in X4 mode is inserted, the plug Present1# is connected to the slot Present1#, the plug Present2_N1 is connected to the slot Present2_N1, and the plug Present2_N2 is connected to the slot Present2_N2. When a PCIe device in X8 mode is inserted, the plug Present1# is connected to the slot Present1#, the plug Present2_N1 is connected to the slot Present2_N1, the plug Present2_N2 is connected to the slot Present2_N2, and the plug Present2_N3 is connected to the slot Present2_N3. When a PCIe device in X16 mode is inserted, the plug Present1# is connected to the slot Present1#, the plug Present2_N1 is connected to the slot Present2_N1, the plug Present2_N2 is connected to the slot Present2_N2, the plug Present2_N3 is connected to the slot Present2_N3, and the plug Present2_N4 is connected to the slot Present2_N4. As Figure 5 The figure shows the corresponding equivalent circuit diagram after the Riser card is inserted into the PCIe device. According to the above equivalent circuit, it can be seen that after the Riser card is inserted into PCIe cards with different bandwidth allocation modes, the corresponding equivalent circuits are the same. In order to identify PCIe cards with different bandwidth allocation modes, additional circuits need to be added, or only one bandwidth allocation mode is supported.

[0082] In some possible embodiments, the first PCIe device includes an NVME disk and a SAS / SATA disk. In the related art, the slots on the backplane include PRESENT and IFDET, and the second gold finger includes plug PRESENT and IFDET. In the related art, in order to distinguish whether a hard disk is inserted on the backplane, that is, to distinguish the type of the inserted hard disk when a hard disk is inserted, the IFDET and PRESENT signals are used to distinguish whether a hard disk is inserted. That is, when it is determined that a hard disk is inserted, it is distinguished whether a SAS / SATA disk or an NVME disk is inserted. The specific hard disk classification and identification method is shown in Table 1, where H and L represent high level and low level respectively. If the IFDET signal is high level and the PRESENT signal is high level, it is determined that no hard disk is inserted. If IFDET is low level and the PRESENT signal is high level, then the inserted disk is an NVME disk. This is the hardware circuit set inside the hard disk. If IFDET is low level and the PRESENT signal is low level, then the inserted disk is a SAS / SATA disk.

[0083] Table 1

[0084] Hard Disk Type IFDET PRESENT NVME L H SAS / SATA L L No Device H H

[0085] In the related art, PRESENT and IFDET are only used to distinguish the type of the inserted hard disk. For the distinction of PCIe cards, other circuits are required, wasting IO resources or not supporting dynamic bandwidth allocation.

[0086] In the embodiment of the present application, the above-mentioned presence detection signal is IFDET, and the device detection signal is PRESENT. In the embodiment of the present application, the socket circuit includes a first socket circuit for inserting the first PCIe device and a second socket circuit for inserting the second PCIe device;

[0087] The first socket circuit includes a first presence detection end and a first device detection end. When the first PCIe device is not inserted, both the first presence detection end and the first device detection end are at high level. When the first PCIe device is inserted, the first presence detection end is at low level;

[0088] The second socket circuit includes a second presence detection end and a second device detection end. When the second PCIE device is not inserted, both the second presence detection end and the second device detection end are at high level. When the second PCIe device is inserted, the second presence detection end is at high level, and the first presence detection end outputs a low-level voltage corresponding to the bandwidth allocation mode of the second PCIe device;

[0089] The connector is used to output the presence detection signal and the device detection signal to the CPU according to the levels of the first presence detection end, the first device detection end, the second presence detection end, and the second device detection end.

[0090] In the embodiment of the present application, the connector outputs the in-position detection signal and the device detection signal to the CPU according to the levels of the first in-position detection terminal, the first device detection terminal, the second in-position detection terminal, and the second device detection terminal. A possible method is to perform a logical AND operation on the levels of the first in-position detection terminal and the second in-position detection terminal, and perform a logical AND operation on the levels of the second in-position detection terminal and the second in-position detection terminal. Thus, it can be determined that if both the in-position detection signal and the device detection signal are high levels, the first PCIe device and the second PCIe device are not inserted; if the in-position detection signal is low level, the first PCIe device is inserted; if the in-position detection signal is high level and the device detection signal is low level voltage, it is determined that the second PCIe device is inserted and the bandwidth allocation mode is determined according to the low level voltage.

[0091] In the above circuit provided by the embodiment of the present application, not only does the first socket circuit include the in-position detection terminal and the device detection terminal, but the second socket circuit also includes the in-position detection terminal and the device detection terminal. The connector of the embodiment of the present application accesses the first socket circuit and the second socket circuit through a cable to detect the in-position detection signal and the device detection signal, and designs different level combinations, so that only two signals can be used to realize the detection of neither the first PCIe device nor the second PCIe device being inserted, the first PCIe device being inserted, the second PCIe device being inserted, and the corresponding bandwidth allocation mode, saving half of the IO resources compared with the prior art method that requires 4 pins.

[0092] In some possible embodiments, the first PCIe device includes an NVME disk and a SAS / SATA disk. When the first socket circuit inserts the NVME disk, the first device detection terminal is at a low level; when the first socket circuit inserts the SAS / SATA disk, the first device detection terminal is at a high level; or

[0093] When the first socket circuit inserts the NVME disk, the first device detection terminal is at a high level; when the first socket circuit inserts the SAS / SATA disk, the first device detection terminal is at a low level.

[0094] In the embodiment of the present application, in order to distinguish the corresponding hard disk types when inserting a hard disk, when it is detected that a hard disk is inserted through the in-position detection signal being at a low level, the type of the inserted hard disk is further determined according to whether the device detection is at a high level or a low level. Table 2 shows the method for determining the type of the inserted PCIe device according to the level combination of the in-position detection signal IFDET and the device detection signal PRESENT.

[0095] Table 2

[0096]

[0097]

[0098] In some possible embodiments, the circuit further includes:

[0099] A signal transmission circuit connected between the connector and the CPU;

[0100] The signal transmission circuit includes a BMC and an IO detection module corresponding to each CPU. The IO detection module converts the voltages of the presence detection signal and the device detection signal received from the connector into corresponding register values through the presence detection pin and the device detection pin, and sends them to the BMC after connecting to multiple ports Port of the corresponding CPU;

[0101] The BMC is used to transmit the register values corresponding to the presence detection signal and the device detection signal to the corresponding CPU through the eSPI bus.

[0102] In this embodiment, the first socket circuit is disposed on the backplane, the second socket circuit is a Riser card disposed on the motherboard, the first PCIe device is a hard disk, and the second PCIe device is a PCIe card corresponding to different bandwidth allocation modes, such as Figure 6 The figure shows a schematic diagram of a port bandwidth allocation circuit for a PCIe device provided by an embodiment of the present application. The connector uses an MCIO connector. The server includes CPU0 and CPU1. Each PCIe bus has 5 ports Port. The 5-port Port Riser card and the backplane are connected to the MCIO_0 connector, MCIO_1 connector, MCIO_2 connector, MCIO_3 connector, and MCIO_4 connector through cables, as Figure 7 shown. The MCIO_0 connector detects the device detection signal Present0 and the presence detection signal IFDET0 and transmits them to the IO detection module. The MCIO_1 connector detects the device detection signal Present1 and the presence detection signal IFDET1 and transmits them to the IO detection module. The MCIO_2 connector detects the device detection signal Present1 and the presence detection signal IFDET2 and transmits them to the IO detection module. The MCIO_3 connector detects the device detection signal Present3 and the presence detection signal IFDET3 and transmits them to the IO detection module. The MCIO_4 connector detects the device detection signal Present4 and the presence detection signal IFDET4 and transmits them to the IO detection module.

[0103] The above IO detection module is an analog-to-digital conversion chip, which can convert voltage signals into register values readable by I2C; in the above circuit, two signals are output on the MCIO_0 to MCIO_4 connectors, and these signals are input by the Riser card or the backplane through the cable cable; after the analog-to-digital conversion chip collects the voltages of these two signals, they are converted into register values and transmitted to the BMC through I2C, and the BMC then transmits them to the CPU through the eSPI protocol, enabling the CPU to perform PCIe bandwidth allocation for these 5 ports Port.

[0104] In order to distinguish different bandwidth allocation modes when detecting the insertion of the second PCIe device in the embodiments of the present application, in some possible embodiments, the second socket circuit includes a first slot connected to the ground wire and a plurality of second slots, and each second slot is connected to the second device detection end through a voltage dividing resistor, and the second device detection end is connected to the power supply through a pull-up resistor. Among them, when second PCIe devices with different bandwidth allocation modes are inserted, the first slot is connected to the corresponding number of second slots to form different voltage dividing circuits.

[0105] In the embodiments of the present application, when the second PCIe device uses a PCIe card, as Figure 8 shown, the second socket circuit includes a first slot Present1# connected to the ground wire, a second slot Present2_N1, a second slot Present2_N2, a second slot Present2_N3, and a second slot Present2_N4. The second slot Present2_N1 is connected to the second device detection end Present through a voltage dividing resistor R2, the second slot Present2_N2 is connected to the second device detection end Present through a voltage dividing resistor R3, the second slot Present2_N3 is connected to the second device detection end Present through a voltage dividing resistor R4, and the second slot Present2_N4 is connected to the second device detection end Present through a voltage dividing resistor R5. The second device detection end Present is connected to the power supply V3 through a pull-up resistor R1.

[0106] When inserting a second PCIe device with different bandwidth allocation modes in the embodiments of the present application, the first slot is connected to the corresponding number of second slots to form different voltage-dividing circuits. In some possible embodiments, the different bandwidth allocation modes include X1 mode, X4 mode, X8 mode, and X16 mode. When the second socket circuit inserts a second PCIe device in X1 mode, the first slot is connected to one second slot. When the second socket circuit inserts a second PCIe device in X4 mode, the first slot is connected to two second slots. When the second socket circuit inserts a second PCIe device in X8 mode, the first slot is connected to three second slots. When the second socket circuit inserts a second PCIe device in X16 mode, the first slot is connected to four second slots.

[0107] According to the present application Figure 8 In the circuit shown, when the second socket circuit inserts a PCIe card in X1 mode, the first slot Present1# is connected to the second slot Present2_N1. When the second socket circuit inserts a PCIe card in X4 mode, the first slot Present1# is connected to the second slot Present2_N1 and the second slot Present2_N2. When the second socket circuit inserts a PCIe card in X8 mode, the first slot Present1# is connected to the second slot Present2_N1, the second slot Present2_N2, and the second slot Present2_N3. When the second socket circuit inserts a PCIe card in X16 mode, the first slot Present1# is connected to the second slot Present2_N1, the second slot Present2_N2, the second slot Present2_N3, and the second slot Present2_N3.

[0108] In some possible embodiments, the second PCIe device is connected to the Riser card through a gold finger, and the circuit of the gold finger is specifically as Figure 3 shown. The plug of the gold finger includes Present1#, Present2_N1, Present2_N2, Present2_N3, and Present2_N4. PCIe devices with different bandwidth allocation modes pass through Figure 3When the shown gold fingers are inserted into the Riser card, the number of corresponding plugs connected to the slots is different. Among them, when inserting a PCIe card in X1 mode, plug Present1# is connected to slot Present1#, and plug Present2_N1 is connected to slot Present2_N1. When inserting a PCIe card in X4 mode, plug Present1# is connected to slot Present1#, plug Present2_N1 is connected to slot Present2_N1, and plug Present2_N2 is connected to slot Present2_N2. When inserting a PCIe card in X8 mode, plug Present1# is connected to slot Present1#, plug Present2_N1 is connected to slot Present2_N1, plug Present2_N2 is connected to slot Present2_N2, and plug Present2_N3 is connected to slot Present2_N3. When inserting a PCIe card in X16 mode, plug Present1# is connected to slot Present1#, plug Present2_N1 is connected to slot Present2_N1, plug Present2_N2 is connected to slot Present2_N2, plug Present2_N3 is connected to slot Present2_N3, and plug Present2_N4 is connected to slot Present2_N4.

[0109] In some possible embodiments, the resistance values of the voltage-dividing resistors connected to each second slot are equal;

[0110] The CPU pre-determines the low-level voltage of the device detection end corresponding to the voltage-dividing circuit corresponding to different bandwidth allocation modes according to the resistance value of the pull-up resistor, the power supply voltage, and the resistance value of the voltage-dividing resistor. The resistance value of the above resistor can be, but is not limited to, 1000 ohms. In this way, the CPU can determine the bandwidth allocation mode adopted according to the low-level voltage of the device detection signal based on the in-position detection signal and the device detection signal when inserting the second PCIe card.

[0111] In some possible embodiments, the CPU is specifically configured to determine that when the in-position detection signal is high and the device detection signal is high, it is determined that the first socket circuit does not insert the first PCIe device and the second socket circuit does not insert the second PCIe device. When the in-position detection signal is low, it is determined that the first socket circuit inserts the first PCIe device. When the in-position detection signal is high and the device detection signal is low-level voltage, it is determined that the second socket circuit inserts the second PCIe device, and the corresponding bandwidth allocation mode is determined according to the low-level voltage.

[0112] Since the Present1# signal on the connector is directly grounded, the four signal lines of Present2_N1, Present2_N2, Present2_N3, and Present2_N4 are pulled up together through voltage-dividing resistors to output the Present terminal. If a PCIe card is plugged into the connector, the Present terminal outputs a low-level voltage after voltage division, and the CPU collects this low-level voltage to determine that the PCIe card has been inserted and successfully identifies the corresponding bandwidth allocation mode.

[0113] In some possible embodiments, when the Riser card is inserted into a PCIe card in X1 mode, the plug Present1# is connected to the slot Present1#, and the plug Present2_N1 is connected to the slot Present2_N1. The equivalent circuit is as Figure 9 shown. If the pulled-up power supply voltage is 3.3V, the output voltage of the Present terminal is 1.65V.

[0114] When the Riser card is inserted into a PCIe card in X4 mode, the plug Present1# is connected to the slot Present1#, the plug Present2_N1 is connected to the slot Present2_N1, and the plug Present2_N2 is connected to the slot Present2_N2. The equivalent circuit is as Figure 10 shown, and the output voltage of the Present terminal is 1.1V.

[0115] When the Riser card is inserted into a PCIe card in X8 mode, the plug Present1# is connected to the slot Present1#, the plug Present2_N1 is connected to the slot Present2_N1, the plug Present2_N2 is connected to the slot Present2_N2, and the plug Present2_N3 is connected to the slot Present2_N3. The equivalent circuit is as Figure 11 shown, and the output voltage of the Present segment is 0.825V.

[0116] When the Riser card is inserted into a PCIe card in X16 mode, the plug Present1# is connected to the slot Present1#, the plug Present2_N1 is connected to the slot Present2_N1, the plug Present2_N2 is connected to the slot Present2_N2, the plug Present2_N3 is connected to the slot Present2_N3, and the plug Present2_N4 is connected to the slot Present2_N4. The equivalent circuit is as Figure 12 shown, and the output voltage of the Present terminal is 0.66V.

[0117] In the embodiments of the present application, for four different bandwidth allocation modes, Present signals with different voltages can be output. The CPU can automatically allocate the PCIe ports into X16 mode, X8 mode, X4 mode, and X1 mode by detecting these voltage values. If no PCIe card is connected, the Present signal is 3.3V and no PCIe bandwidth allocation is required.

[0118] If the PCIe device is an NVMe hard disk, the voltage of the Present signal is also 3.3V, which may cause misjudgment. Therefore, the embodiments of the present application add a detection mechanism for the voltage of the IFDET signal. The IFDET signal on the backplane is default pulled up to 3.3V. If an NVMe hard disk is connected, the voltage value of the IFDET becomes 0V, and the port Port can be automatically allocated into X4 mode. The IFDET signal on the Riser card is also default pulled up to 3.3V, so as to determine that no Riser card and no hard disk are inserted when the IFDET signal and the Present signal are detected as high levels.

[0119] The way of bandwidth allocation corresponding to the in-position detection signal and the device detection signal detected by the IO detection module in the embodiments of the present application is shown in Table 3. The IO detection module transmits the information to the CPU through the I2C and eSPI protocols by detecting the different voltage values of the Present signal and the IFDET signal. The CPU uses Table 3 to allocate bandwidth for the PCIe device. The above solution can not only solve the problem of waste of logical resources, but also realize the function of automatic PCIe bandwidth allocation, which is more flexible.

[0120] Table 3

[0121]

[0122] In the related art, one CPU requires 20 pins to implement the single-CPU PCIe bandwidth allocation function and cannot distinguish the types of hard disks inserted in the hard disk Riser. The embodiments of the present application only require 10 pins to complete the identification of bandwidth allocation and the types of hard disks and Risers inserted, which can effectively solve the problem of waste of logical resources, and at the same time can also realize the function of automatic PCIe bandwidth allocation, which is more flexible.

[0123] Based on the same inventive concept, the embodiments of the present application also provide a method for allocating the port bandwidth of a PCIe device, as Figure 13 shown. The method includes:

[0124] Step 1301, receiving the in-position detection signal and the device detection signal of multiple ports Port of each CPU transmitted by the connector, where the connector is used to detect the in-position detection signal and the device detection signal according to the levels of the in-position detection end and the device detection end of the socket circuit of each port Port;

[0125] Step 1302: According to the in-position detection signal and the device detection signal, determine that a fixed bandwidth is allocated when the first PCIe device is inserted, and when the second PCIe device is inserted, allocate the bandwidth according to the level voltage of the device detection signal by connecting a pull-up resistor to the power supply.

[0126] In some possible embodiments, according to the in-position detection signal IFDET and the device detection signal Present, determining that a fixed bandwidth is allocated when the first PCIe device is inserted, and when the second PCIe device is inserted, allocating the bandwidth according to the level voltage of the device detection signal by connecting a pull-up resistor to the power supply includes:

[0127] When it is determined that the in-position detection signal IFDET is at a high level and the device detection signal Present is at a high level, it is determined that the first socket circuit does not insert the first PCIe device and the second socket circuit does not insert the second PCIe device. When it is determined that the in-position detection signal IFDET is at a low level, it is determined that the first socket circuit inserts the first PCIe device. When it is determined that the in-position detection signal IFDET is at a high level and the device detection signal Present is at a low level voltage, it is determined that the second socket circuit inserts the second PCIe device, and the connection of the pull-up resistor to the power supply is determined according to the low level voltage.

[0128] For the related implementation manners of the method embodiment of the present application, reference can be made to the embodiment of the above circuit, and the present application will not elaborate in detail.

[0129] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0130] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A port bandwidth allocation circuit for a PCIe device, the circuit comprising at least one CPU and a plurality of ports connected to the CPUs, the ports being inserted into a first PCIe device or a second PCIe device through a socket circuit, characterized in that: The circuit further comprises a connector connected to each port Port, wherein: The socket circuit of each port Port includes an in-position detection terminal and a device detection terminal. When the first PCIe device or the second PCIe device is inserted into the socket circuit, the in-position detection terminal outputs different voltage levels. When the second PCIe device with different bandwidth allocation modes is inserted into the socket circuit, a different voltage divider circuit is formed. The device detection signal terminal outputs different voltage levels as the voltage divider terminal of the voltage divider circuit. The connector is used to detect a presence detection signal and a device detection signal according to the levels of the presence detection terminal and the device detection terminal, and send them to the CPU; The CPU determines to allocate fixed bandwidth when inserting the first PCIe device based on the presence detection signal and device detection signal of each port Port, and allocates bandwidth by connecting the power supply according to the pull-up resistor based on the level voltage of the device detection signal when inserting the second PCIe device.

2. The circuit according to claim 1, characterized in that The socket circuit includes a first socket circuit for inserting a first PCIe device and a second socket circuit for inserting a second PCIe device; The first socket circuit includes a first presence detection terminal and a first device detection terminal. When the first PCIe device is not inserted, the first presence detection terminal and the first device detection terminal are both at a high level. When the first PCIe device is inserted, the first presence detection terminal is at a low level. The second socket circuit includes a second presence detection terminal and a second device detection terminal. When the second PCIe device is not inserted, the second presence detection terminal and the second device detection terminal are both at a high level. When the second PCIe device is inserted, the second presence detection terminal is at a high level, and the first presence detection terminal outputs a low level voltage corresponding to a bandwidth allocation mode of the second PCIe device. The connector is used to output a presence detection signal and a device detection signal to the CPU according to the levels of the first presence detection terminal, the first device detection terminal, the second presence detection terminal and the second device detection terminal.

3. The circuit according to claim 2, characterized in that The first PCIe device includes an NVME disk and a SAS / SATA disk, and when the first socket circuit is inserted into the NVME disk, the first device detection end is at a low level, and when the first socket circuit is inserted into the SAS / SATA disk, the first device detection end is at a high level; or When the first socket circuit is inserted into an NVME disk, the first device detection end is at a high level; when the first socket circuit is inserted into a SAS / SATA disk, the first device detection end is at a low level.

4. The circuit according to any one of claims 1 to 3, characterized in that: Also includes: A signal transmission circuit connected between the connector and the CPU; The signal transmission circuit includes a BMC and an IO detection module corresponding to each CPU. The IO detection module connects a connector connected to multiple ports of the corresponding CPU through an in-place detection pin and a device detection pin, converts the voltage of the in-place detection signal and the device detection signal received from the connector into a corresponding register value and then sends it to the BMC; The BMC is used to transmit register values ​​corresponding to the in-place detection signal and the device detection signal to the corresponding CPU through the eSPI bus.

5. The circuit according to claim 2 or 3, characterized in that: The second socket circuit includes a first slot connected to the ground wire and multiple second slots, each second slot is connected to the second device detection end through a voltage divider resistor, and the second device detection end is connected to the power supply through a pull-up resistor. When a second PCIe device with a different bandwidth allocation mode is inserted, the first slot is connected to a corresponding number of second slots to form different voltage divider circuits.

6. The circuit according to claim 2, characterized in that The first socket circuit is arranged on the backplane, the second socket circuit is a riser card arranged on the mainboard, the first PCIe device is a hard disk, and the second PCIe device is a PCIe card corresponding to different bandwidth allocation modes.

7. The circuit according to claim 5, characterized in that The voltage-dividing resistors connected to the second slots have equal resistance values; The CPU determines in advance the low level voltage of the device detection terminal corresponding to the voltage divider circuit corresponding to different bandwidth allocation modes according to the resistance value of the pull-up resistor, the power supply voltage and the resistance value of the voltage divider resistor.

8. The circuit according to claim 2, characterized in that The CPU is specifically used to determine that when the in-place detection signal is at a high level and the device detection signal is at a high level, it is determined that the first socket circuit is not inserted into the first PCIe device and the second socket circuit is not inserted into the second PCIe device, determine that the in-place detection signal is at a low level, determine that the first socket circuit is inserted into the first PCIe device, determine that the in-place detection signal is at a high level and the device detection signal is at a low level voltage, determine that the second socket circuit is inserted into the second PCIe device, and determine that the pull-up resistor is connected to the power supply according to the low level voltage.

9. The circuit according to claim 2, characterized in that The different bandwidth allocation modes include X1 mode, X4 mode, X8 mode and X16 mode. When the second socket circuit is inserted into the second PCIe device in X1 mode, the first slot is connected to one second slot. When the second socket circuit is inserted into the second PCIe device in X4 mode, the first slot is connected to two second slots. When the second socket circuit is inserted into the second PCIe device in X8 mode, the first slot is connected to three second slots. When the second socket circuit is inserted into the second PCIe device in X16 mode, the first slot is connected to four second slots.

10. A method for allocating port bandwidth of a PCIe device, characterized in that: include: A receiving connector transmits a plurality of in-position detection signals and a device detection signal of a plurality of ports of each CPU, wherein the connector is used to detect the in-position detection signal and the device detection signal according to the level of the in-position detection terminal and the device detection terminal of the socket circuit of each port; According to the presence detection signal and the device detection signal, a fixed bandwidth is allocated when the first PCIe device is inserted, and when the second PCIe device is inserted, a power supply allocation bandwidth is connected according to the pull-up resistor according to the level voltage of the device detection signal.

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