Multiplex interface and micro-display chip

Abstract

The invention discloses a multiplex interface which comprises an I < O > control assembly and N communication protocol control assemblies, the I < O > control assembly is used for receiving and sending data and determining a communication protocol adopted by the data, and the N communication protocol control assemblies are in communication connection with the I < O > control assembly. Wherein each communication protocol control group is used for decoding data transmitted by adopting a corresponding communication protocol, the communication protocols adopted by the communication protocol control components are different, and N is an integer greater than 1. The multiplexing interface supports the sharing of a plurality of communication protocols, and when the multiplexing interface is applied to the micro-display chip, the adaptation range of an upper computer can be wider, and the matching use is more flexible.

Description

Technical Field

[0001] The present invention relates to the technical field of light-emitting diodes, and particularly to a multiplexing interface and a microdisplay chip. Background Art

[0002] A micro light-emitting diode (Micro LED) microdisplay chip is a new type of LED structure obtained by thinning, miniaturizing, and arraying the original LED structure. It integrates arrayed micron-level LED units on an active addressing driving panel to achieve the lighting and individual control of the LED units, thereby outputting the desired display image.

[0003] In the control module of the existing microdisplay chip, usually only one communication interface is included. Therefore, the compatible host computer is relatively single and it is difficult to adapt to different display requirements. Summary of the Invention

[0004] In view of some or all of the problems in the prior art, a first aspect of the present invention provides a multiplexing interface, including:

[0005] An IO control component, which is used to receive and send data and determine the communication protocol adopted by the data; and

[0006] N communication protocol control components, which are communicatively connected to the IO control component, where each communication protocol control component is used to decode the data transmitted using the corresponding communication protocol, and the communication protocols adopted by the communication protocol control components are all different, where N is an integer greater than 1.

[0007] Further, the multiplexing interface includes at least one multiplexing pin, where the multiplexing pin supports multiple different communication protocols.

[0008] Further, the IO control component includes:

[0009] At least one multiplexer, which is used to transmit the input signal of the multiplexing pin to the corresponding communication protocol control component based on a selection signal; and

[0010] At least one demultiplexer, which is used to transmit the output signal of the corresponding communication protocol control component to an external module through the multiplexing pin based on a selection signal.

[0011] Further, the selection signal is written externally.

[0012] Further, the selection signal is written through an IO pin.

[0013] Further, the selection signal is set through a one-time programmable memory module or a one-time programmable module.

[0014] Further, the selection signal is determined by internal register parameters.

[0015] Further, the internal register parameters include N communication protocol locking parameters. If the communication protocol locking parameter is 0, the corresponding communication protocol control component is enabled. If the communication protocol locking parameter is 1, the corresponding communication protocol control component is unavailable.

[0016] Further, the N communication protocol control components include:

[0017] A QSPI control component that uses the QSPI protocol; and

[0018] I 2 C control component that uses the I 2 C protocol.

[0019] Further, the multiplexed pins include:

[0020] A first multiplexed pin that is configured as the multiplexing of the IO[2] pin of the QSPI control component and the SCL pin of the I 2 C control component; and

[0021] A second multiplexed pin that is configured as the multiplexing of the IO[3] pin of the QSPI control component and the SDA pin of the I 2 C control component.

[0022] Based on the multiplexing interface as described above, a second aspect of the present invention provides a microdisplay chip, which includes:

[0023] A control module that includes the multiplexing interface as described above, and the multiplexing interface is used to transmit the control signal and the original data from the host side to the inside of the control module; and

[0024] A display module that is electrically connected to the control module through a metal interconnection structure and is used to display an image based on the control of the control module.

[0025] Further, the control module further includes a register configuration array that is communicatively connected to the multiplexing interface and is used to store register configuration parameters.

[0026] Further, the control module further includes a data processing sub-module that is communicatively connected to the multiplexing interface and is used to preprocess the original data to convert it into data to be displayed.

[0027] Further, the preprocessing includes data compensation, and / or rotation processing, and / or flip processing.

[0028] Furthermore, the control module further includes a compensation cache component, which is communicatively connected to the data processing sub-module and is used to store cache information for compensating the original data.

[0029] Furthermore, the control module further includes:

[0030] a frame buffer component for storing the entire frame data to be displayed; and

[0031] a row data buffer component for storing the row data to be updated.

[0032] Furthermore, the control module further includes a bus interconnection sub-module, and the frame buffer component and the row data buffer component are communicatively connected to the signal processing sub-module through the bus interconnection sub-module.

[0033] Furthermore, the control module further includes:

[0034] a display control sub-module, which is communicatively connected to the frame buffer component and the row data buffer component and is used to transfer the data in the frame buffer component or the row data buffer component to the display module for display.

[0035] Furthermore, the display control sub-module includes:

[0036] a display control component (Display control) for reading the data to be displayed according to the working mode and controlling the row and column control components based on the data to be displayed to implement image display;

[0037] a row control component (row control) for controlling the scanning of the display area of the display module; and

[0038] a column control component (column control) for transferring data to the display module.

[0039] Furthermore, reading the data to be displayed according to the working mode includes:

[0040] if in video mode, reading the data to be displayed row by row from the row data buffer component; and

[0041] if in command mode, reading the entire frame data to be displayed from the frame buffer component.

[0042] Furthermore, the control module further includes a temperature compensation module LTC, which is communicatively connected to the display control sub-module and is used to compensate the display brightness according to the temperature.

[0043] Furthermore, the control module further includes a Flexible Memory Controller (FMC) for controlling an external flash.

[0044] Furthermore, the control module further includes a test control sub-module.

[0045] Furthermore, the control module further includes an IP switching sub-module SW for switching between an internal OSC and an external clock input, and an internal POR.

[0046] Furthermore, the control module further includes a One Time Programmable storage module (Efuse) for storing configuration parameters of the control module.

[0047] Furthermore, the control module further includes an internal oscillator OSC for generating an internal clock of the control module.

[0048] Furthermore, the control module further includes a temperature detection sub-module PVT for acquiring the temperature of the control module.

[0049] Furthermore, the control module further includes a Power-On Reset sub-module POR.

[0050] Furthermore, the control module further includes a Clock and Reset Module (CRG) for providing clock and reset signals.

[0051] Furthermore, the display module includes a plurality of micro light-emitting diode pixel units arranged in an array.

[0052] A multiplexing interface provided by the present invention supports the sharing of multiple communication protocols. When applied to a microdisplay chip, since it can support transmission protocols with different rates, its adaptability to a host computer is wider and its matching use is more flexible. The multiplexing interface includes multiplexing pins, which can also reduce the IO overhead and reduce the connection wires with the host computer. In addition, the multiplexing interface can be controlled by registers, further saving the IO overhead and making the control more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] To further clarify the above and other advantages and features of the embodiments of the present invention, more specific descriptions of the embodiments of the present invention will be presented with reference to the accompanying drawings. It can be understood that these drawings only depict typical embodiments of the present invention and thus will not be considered as limiting its scope. In the drawings, for clarity, the same or corresponding components will be denoted by the same or similar reference numerals.

[0054] Figure 1 A schematic structural diagram of a microdisplay chip showing an embodiment of the present invention;

[0055] Figure 2a and 2b shows a schematic diagram of the QSPI read / write timing;

[0056] Figure 3a and 3b shows the I 2 C data read / write timing diagram;

[0057] Figure 4 shows a schematic diagram of the structure of the second interface sub-module according to an embodiment of the present invention;

[0058] Figure 5 shows a schematic diagram of the structure of the IO control component according to an embodiment of the present invention;

[0059] Figure 6a and 6b shows a schematic diagram of the data flow when the first interface sub-module is adopted according to an embodiment of the present invention;

[0060] Figure 7 shows a schematic diagram of the data flow when the second interface sub-module is adopted according to an embodiment of the present invention;

[0061] Figure 8 shows a cross-sectional schematic diagram of the micro light-emitting diode structure according to an embodiment of the present invention; and

[0062] Figure 9 shows a cross-sectional schematic diagram of the micro light-emitting diode structure according to another embodiment of the present invention. Detailed implementation manners

[0063] In the following description, the present invention is described with reference to the embodiments. However, those skilled in the art will recognize that the embodiments can be implemented without one or more specific details or in combination with other alternative and / or additional methods, materials, or components. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring the inventive points of the present invention. Similarly, for purposes of explanation, specific quantities, materials, and configurations are set forth in order to provide a thorough understanding of the embodiments of the present invention. However, the present invention is not limited to these specific details. In addition, it should be understood that the embodiments shown in the drawings are illustrative representations and not necessarily drawn to scale.

[0064] In this specification, the reference to "an embodiment" or "the embodiment" means that the specific features, structures, or characteristics described in connection with the embodiment are included in at least one embodiment of the present invention. The phrase "in an embodiment" appearing throughout this specification does not necessarily all refer to the same embodiment.

[0065] It should be noted that the embodiments of the present invention describe the process steps in a specific order. However, this is only for explaining the specific embodiment and does not limit the sequence of the steps. On the contrary, in different embodiments of the present invention, the sequence of the steps can be adjusted according to the adjustment of the process.

[0066] To reduce the IO overhead and the connection lines with the host computer, the present invention provides a multiplexing interface, which includes an IO control component and a plurality of communication protocol control components. The plurality of communication protocol control components are communicatively connected to the IO control component, and the communication protocols adopted by each communication protocol control component are all different. The IO control component is used to receive and send data, determine the communication protocol adopted by the data, and then send the data to the corresponding communication protocol control component. The corresponding communication protocol control component decodes the data transmitted using the corresponding communication protocol. In some embodiments, the multiplexing interface mainly realizes interface multiplexing through multiplexing pins, that is, the multiplexing pins can support a plurality of different communication protocols, and the IO control component includes a multiplexer and a demultiplexer. Furthermore, the IO control component can transmit the input signal of the multiplexing pin to the corresponding communication protocol control component based on the selection signal provided by external writing or internal register parameters, or transmit the output signal of the corresponding communication protocol control component to an external module through the multiplexing pin.

[0067] The multiplexing interface can be applied to display components such as microdisplay chips, for example, so that it can support transmission protocols with different rates, and thus has a wider adaptation range for the host computer and is more flexible to use in combination.

[0068] The technical solution of the present invention will be further described below with reference to the accompanying drawings of the embodiments.

[0069] Figure 1 The structural schematic diagram of a microdisplay chip showing an embodiment of the present invention is as follows Figure 1 As shown, the microdisplay chip includes a control module 001 and a display module 002. The control module 001 and the display module 002 are both disposed on a substrate. The display module 002 is electrically connected to the control module 001 through a metal interconnect structure, such as a metal pillar. The control module 001 is used to control the display module 002 to realize image display. The display module 002 includes a micro light-emitting diode (Micro LED) array, which can realize three-color combined light color display or monochromatic display.

[0070] As Figure 1As shown, the control module 001 includes a first interface sub-module 101 and a second interface sub-module 102. The first interface sub-module 101 and the second interface sub-module 102 are used to transmit the control signals and original data of the host side to the inside of the control module. As mentioned above, the transmission protocols adopted by the first interface sub-module 101 and the second interface sub-module 102 are different.

[0071] As Figure 1 shown, in an embodiment of the present invention, the first interface sub-module 101 adopts the MIPI DPHY physical layer protocol and the DSI protocol layer. The first interface sub-module 101 includes a DPHY DSI interface. The DPHY physical layer protocol is a low-power serial transmission technology suitable for short-distance data transmission, and its overall power consumption is relatively low. The DPHY physical layer protocol uses differential two-wire signal transmission. As Figure 1 shown, the DPHY DSI interface includes CKN pins, CKP pins, DP0 pins and DN0 pins. Among them, the CKN pins and CKP pins are connected to the clock differential signal of MIPI, and the DP0 pins and DN0 pins are connected to the data differential signal of MIPI. In an embodiment of the present invention, the first interface sub-module further includes a data processing component (DSI Process), and the data processing component is used to unpack the data in the DSI packet format and reorganize the unpacked signals into signals that meet the timing requirements of the control module.

[0072] As Figure 1 shown, in an embodiment of the present invention, the second interface sub-module 102 adopts the QSPI transmission protocol. The QSPI transmission protocol is a high-speed data communication protocol based on the serial peripheral interface SPI, and it supports simultaneous data transmission on 4 data lines. As Figure 1 shown, the second interface sub-module 102 includes an SCLK pin, a CSB pin, and IO[0] to IO[3] pins. Among them, the SCLK pin is connected to the clock line to provide a clock signal to control the data transmission rate, the CSB pin is connected to the chip select line to select the connected slave device, and the IO[0] to IO[3] pins are connected to the data lines, which can be used as inputs or outputs and support four-way parallel data transmission.

[0073] Figure 2a And 2b shows the QSPI read / write timing schematic diagram. As shown in the figure, when there is no data transmission, the CSB pin is in the high level state. Once data transmission is received, it becomes low level, indicating that the current interface is selected and QSPI data transmission can be performed. As Figure 2aAs shown, the write data packet of QSPI includes an instruction CMD, an address ADDR, and N data segments Data0 to Data N. Among them, the instruction CMD is transmitted through the IO[0] pin, usually 8-bit data. The address and data are jointly transmitted by four IO pins. For example, each pin can synchronously transmit one bit of data in a certain data segment, and then complete the transmission of an 8-bit data within two clock cycles. The read data packet of QSPI is as Figure 2b shown. It is similar to the write data packet, but the difference is that there is an adjustment clock Dummy clk between the address and the data, which can be used to compensate for the delay during signal transmission, so as to ensure the accuracy and integrity of the data.

[0074] The control module 001, especially the DPHY DSI interface, often needs to configure corresponding functions through registers during actual use. These register parameters can be transmitted through a low-speed serial port interface. Based on this, in an embodiment of the present invention, an I 2 C interface is further provided to transmit configuration parameters for configuring registers and the like. I 2 The I2C bus is a two-way two-wire synchronous serial bus, which includes an SCL pin and an SDA pin. Among them, the SCL pin is connected to the clock line for synchronizing data reception and transmission, and the SDA pin is connected to the data line for transmitting data.

[0075] Figure 3a and 3b respectively show the timing diagrams of I 2 C data write operation and read operation. As shown in the figure, the I 2 C timing mainly includes a start signal S, a stop signal P, an acknowledgment signal A, and a data transmission W timing. Among them, when the SCL pin is at a high level and the SDA pin jumps from a high level to a low level, it indicates the start of I 2 C communication, which is the start signal S. When the SCL pin is at a high level and the SDA pin jumps from a low level to a high level, it indicates the end of I 2 C communication, which is the stop signal P. After each byte is transmitted, the receiver will pull the SDA pin low during the 9th clock pulse to indicate successful reception of the byte. If the receiver cannot successfully receive the byte, it will keep the SDA pin at a high level to indicate non-acknowledgment. And the data is transmitted one bit during each clock pulse of the SCL pin. Only when the SCL is at a low level can the level of the SDA change.

[0076] It can be seen that the I 2 C data transmission timing is relatively simple and only requires two pins. Therefore, in an embodiment of the present invention, in order to save IO overhead, the multiplexing interface as described above can be used to multiplex the I 2The C interface is multiplexed with the QSPI interface of the second interface sub-module 102. Specifically, 2 the SCL pin of the C interface is multiplexed with the IO[2] pin of the QSPI, and 2 the SDA pin of the C interface is multiplexed with the IO[3] pin of the QSPI.

[0077] Figure 4 The structural schematic diagram of the second interface sub-module showing an embodiment of the present invention is as follows. Figure 4 As shown, the second interface sub-module 102 includes an IO control component (QSPI / I 2 C IO_Ctrl), 2 a C control component (I 2 C_Controller) and a QSPI control component (QSPI_Controller). Among them, the IO control component is used to receive the control signals and original data transmitted by the host side, determine the transmission protocol adopted by the data according to the data format, and further transmit the data packet received by the IO pin to the QSPI_Controller or I 2 C_Controller according to the transmission protocol. The QSPI_Controller is used for QSPI transmission control. It decodes the relevant control signals and data of the QSPI protocol and transmits them to the inside of the control module, and 2 the C_Controller is used for I 2 C transmission control. It decodes the relevant control signals and data of the I 2 C protocol and transmits them to the inside of the control module.

[0078] Figure 5 The structural schematic diagram of the IO control component showing an embodiment of the present invention is as follows. Figure 5 As shown, the IO control component mainly includes a multiplexer MUX and a demultiplexer DEMUX. Among them, the first demultiplexer is used to transfer the signal transmitted by the multiplexed pin of IO[2] and SCL to the QSPI_Controller or I 2 C_Controller based on the selection signal SELECT. The second demultiplexer is used to transfer the signal transmitted by the multiplexed pin of IO[3] and SDA to the QSPI_Controller or I 2 C_Controller based on the selection signal SELECT, and the multiplexer is used to transfer the signal sent by the QSPI_Controller or I 2 C_Controller to the multiplexed pin of IO[3] and SDA according to the selection signal SELECT, and then transmit it to the host computer. It should be understood that QSPI or I 2During a single data packet transmission, the selection signal SELECT remains unchanged. Thus, through the multiplexer MUX and the demultiplexer DEMUX, it is ensured that during one transmission, at most only one port of the Controller is allowed to be connected to the corresponding pin, ensuring that no conflict occurs between the QSPI transmission and the I 2 C transmission.

[0079] In one embodiment of the present invention, the selection signal SELECT is written externally. For example, it can be written through an IO pin or set through a one-time programmable memory such as an Efuse or OTP.

[0080] In another embodiment of the present invention, the selection signal SELECT is configured through an internal register. Configuring through an internal register is more flexible than external control and can further reduce the IO overhead. Therefore, the control module further includes a register configuration array Registers array. The register configuration array is communicatively connected to the second interface sub-module 102 for controlling the configuration parameters of the second interface sub-module. In some other embodiments of the present invention, the register configuration array can also be used to configure the first interface sub-module 101, that is, the functions and settings of the DPHY DSI interface. In one embodiment of the present invention, the register configuration array mainly controls the multiplexing selection of the pins through the settings of two parameters, i2c_lock and qspi_lock. Specifically, when i2c_lock is 0, the I 2 C protocol can be used for transmission. When qspi_lock is 0, the QSPI protocol can be used for transmission.

[0081] Based on this, if i2c_lock is 0 and qspi_lock is also 0, both the QSPI protocol and the I 2 C protocol can be used. At this time, it is necessary to determine the SELECT signal according to the data transmitted by the host computer, that is, to determine whether the data on the multiplexed pin is transmitted to the QSPI_Controller or the I 2 C_Controller. Specifically, the SELECT signal is determined according to the CSB pin status. When the host computer uses the QSPI protocol for transmission, the CSB pin is at a low level. At this time, the IO control component will transmit the data on the multiplexed pin to the QSPI_Controller, and at this time, the I 2 C_Controller has no data transmission. When the host computer uses the I 2 C protocol for transmission, the CSB pin is at a high level. At this time, the IO control component will transmit the data on the multiplexed pin to the I 2The C_Controller, and there is no data transmission on the QSPI_Controller at this time. If i2c_lock is 1 and qspi_lock is 0, then at this time the I 2 C protocol is locked, and the QSPI protocol function is blocked, that is, the second interface sub-module only supports the I 2 C protocol. At this time, when the host computer uses the QSPI protocol for transmission, although the CSB pin will become low level, due to the blocking of the QSPI protocol function, there will be no data transmission on the QSPI_Controller and the I 2 C_Controller at this time. When the host computer uses the I 2 C protocol for transmission, the CSB pin is at high level, then at this time the IO control component will transmit the data of the multiplexed pin to the I 2 C_Controller, and there is no data transmission on the QSPI_Controller at this time. If i2c_lock is 0 and qspi_lock is 1, then at this time the QSPI protocol is locked, and the I 2 C protocol function is blocked, that is, the second interface sub-module only supports the QSPI protocol. At this time, when the host computer uses the I 2 C protocol for transmission, although the CSB pin will maintain high level, due to the blocking of the I 2 C protocol function, there will be no data transmission on the QSPI_Controller and the I 2 C_Controller at this time. When the host computer uses the QSPI protocol for transmission, the CSB pin becomes low level, then at this time the IO control component will transmit the data of the multiplexed pin to the QSPI_Controller, and there is no data transmission on the I 2 C_Controller at this time.

[0082] Through pin multiplexing, the host computer can use two protocol standards of QSPI / I 2 C to achieve directional data transmission with the control module. The overall wiring complexity is small, there is no additional IO overhead, and thus it can be adapted to more types of host computers and has a wider adaptation range.

[0083] Back to Figure 1, in an embodiment of the present invention, in order to improve the display effect, a data processing sub-module Algo is also built inside the control module 001. A variety of image processing algorithms are built in the data processing sub-module Algo, which can optimize and improve the data transmitted by the host computer and enhance the display image quality. In an embodiment of the present invention, the data processing sub-module Algo includes a variety of compensation algorithms, such as demura compensation, gamma compensation, etc., and also includes image adjustment algorithms such as rotation processing and flip processing. Among them, the demura compensation is mainly used to solve the problem of uneven brightness and color. It obtains the gamma value of the Mura pixels, and calculates the gray level value that the Mura pixels should be compensated at each gray level based on the target gamma value, and then performs corresponding compensation processing on the Mura pixels according to the calculation result, so as to eliminate the phenomenon of uneven brightness and color on the display panel. Gamma compensation is used to adjust the brightness of the image to make it more in line with the perception characteristics of the human eye. Specifically, it adjusts the gamma curve of the image, making the dark part of the image clearer and the bright part relatively blurred, thereby improving the overall visual effect of the image. In an embodiment of the present invention, the data processing sub-module Algo can configure whether each built-in algorithm is enabled through the register configuration array Registers array. At the same time, some parameters and / or calculated values required by the algorithm can be stored in the compensation cache component. In an embodiment of the present invention, the compensation cache component includes a demura buffer and a gamma buffer, where the demura buffer is used to store demura data, and the gamma buffer is used to store gamma data. In actual application, the data processing sub-module Algo reads the data in the demura buffer and / or gamma buffer, and performs operations with the original data transmitted by the host computer, optimizes the original data, and converts it into data to be displayed, making the display more perfect.

[0084] In an embodiment of the present invention, two data buffer components are embedded in the control module 001: a frame buffer component frame buffer and a line data buffer component line buffer. Based on this, the control module 001 can implement video mode control and command mode control. Among them, video mode means writing data line by line into the line data buffer component and scrolling and scanning for display line by line. Video mode has a low delay and has advantages in a high-speed moving environment. Command mode writes the data of the entire frame into the frame buffer component, then overall pours it into the storage component of the display module itself, and then performs scanning display through line control. Command mode can perform partial refreshing, and thus has a lower requirement for the driving speed of the host computer in this mode, and its power consumption is also lower. In command mode, if the data to be displayed changes, it is not necessary to transmit all the frame data, and only some of the data needs to be changed.

[0085] In an embodiment of the present invention, when the first interface sub-module 101, that is, the MIPI protocol, is adopted, both video mode and command mode can be supported. If video mode is adopted, as Figure 6a shown, the data received through the first interface sub-module 101 is first reorganized by DSI Process into a signal that meets the timing requirements of the control module. The reorganized signal is optimized line by line through the data processing sub-module Algo. Among them, the data required for compensation calculation is read from the gamma buffer and / or demura buffer. The optimized data to be displayed is stored line by line in the line buffer and poured into the display module through the display control sub-module for scrolling and scanning display line by line. It can be seen that in video mode, a higher requirement is imposed on the data transmission rate. If command mode is adopted, as Figure 6b shown, the data received through the first interface sub-module 101 is first reorganized by DSI Process into a signal that meets the timing requirements of the control module, and then one frame or part of the image data of the reorganized data is written into the data processing sub-module Algo according to the row and column addresses for optimization processing. Among them, the data required for compensation calculation is read from the gamma buffer and / or demura buffer. The optimized data is stored in the corresponding address space of the frame buffer according to the row and column addresses, and finally poured into the display module as a whole through the display control sub-module. In addition, while transmitting image data using the MIPI protocol, it is also possible to further 2The C interface writes the configuration parameters into the register configuration array Registersarray, and then the register array passes them to other sub - modules or components, thereby enabling the configuration of algorithms or display modes, etc. in the data - processing sub - module Algo.

[0086] When the second interface sub - module 102, i.e., the QSPI protocol, is adopted, since the transmission efficiency of the QSPI protocol is relatively low, it is difficult to support the video mode with high latency requirements and only supports the command mode. At this time, the line buffer does not participate in data transmission and image display. Figure 7 The schematic diagram of the data flow when the second interface sub - module 102 is adopted in an embodiment of the present invention is shown. As Figure 7 shown, when the QSPI protocol is adopted, first, the configuration parameters can be written into the register configuration array Registers array through the QSPI protocol, and then the Registers array passes them to other sub - modules or components, thereby enabling the configuration of algorithms or display modes, etc. in the data - processing sub - module Algo. Then, one frame or part of the image data of the data received by the second interface sub - module 102 is written into the data - processing sub - module Algo according to the row and column addresses for optimization processing. Among them, the data required for compensation operations is read from the gamma buffer and / or demura buffer. The optimized data is stored in the corresponding address space of the frame buffer according to the row and column addresses, and finally, the whole is poured into the display module through the display control sub - module.

[0087] As described above, in the embodiment of the present invention, it is necessary to pour the data into the display module through the display control sub - module and control the display of the image. As Figure 1As shown, in one embodiment of the present invention, the display control sub-module includes a display control component (Display control), a row control component (row control), and a column control component (column control). Among them, the display control component is used to read the data to be displayed from the frame buffer or line buffer according to the working mode, and further control the row and column control components to achieve image display. Specifically, the Display control drives the image data in the frame buffer or line buffer to the row control and column control according to the synchronization flag and display configuration parameters, and then writes the data into the display module. Then, the Display control controls the display module 002 to display the corresponding data according to the configuration parameters. In addition, in one embodiment of the present invention, the host computer can also query or debug the status of the chip by reading the data or status information in the Registers array, frame buffer, and line buffer. In one embodiment of the present invention, the row control component is used to control the scanning of the display area of the display module, and the column control component is used to transmit data to the display module.

[0088] In one embodiment of the present invention, as Figure 1 shown, the gamma buffer, demura buffer, line buffer, and frame buffer are all interconnected with the data processing sub-modules such as the Algo and DSI Process sub-modules or components through the bus interconnection sub-module Bus Matrix for communication.

[0089] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a temperature compensation sub-module LTC, which is communicably connected to the display control sub-module and is used to compensate the display brightness according to the temperature.

[0090] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a Flexible Memory Controller (FMC), which is used to control the external flash.

[0091] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a test control sub-module (test control), which is used for the test control of the chip.

[0092] In one embodiment of the present invention, asFigure 1 As shown, the control module further includes an IP switching sub-module SW for switching between an internal OSC and an external clock input, as well as an internal POR.

[0093] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a one-time programmable storage module (Efuse) for storing some or all of the configuration parameters of the control module.

[0094] In one embodiment of the present invention, as Figure 1 shown, the control module further includes an internal oscillator OSC for generating the internal clock of the control module.

[0095] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a temperature detection sub-module PVT for obtaining the temperature of the control module, thereby ensuring that the internal temperature of the chip does not become too high and preventing the chip from being burned out.

[0096] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a power-on reset sub-module POR for power-on reset to ensure that the chip operates at a relatively stable voltage.

[0097] In one embodiment of the present invention, as Figure 1 shown, the control module further includes a clock and reset module CRG for providing an external clock and reset signals EXCKIN and EXRSTN.

[0098] The circuit structures and functions of LTC, FMC, testcontrol, SW, Efuse, OSC, PVT, POR, and CRG can be implemented by conventional technical means in the art and will not be elaborated herein.

[0099] In one embodiment of the present invention, the display module 002 includes a micro light-emitting diode array. As described above, in the embodiments of the present invention, the control module can be used for either three-color combination to form color or monochromatic display. Therefore, in some embodiments, the micro light-emitting diode array may include a single-layer micro light-emitting diode structure formed in an array form, as Figure 8 and 9 shown.

[0100] Figure 8 Shows a cross-sectional schematic diagram of a micro light-emitting diode structure according to one embodiment of the present invention. As Figure 8 shown, the micro light-emitting diode structure includes a pixel driving backplane 110, a lower electrode layer 120, a conductive layer 130, a light-emitting mesa 140, an upper electrode layer 150, a passivation layer 160, and a microlens 170.

[0101] For convenience, "up" is used to denote away from the pixel driving backplane 110, "down" denotes towards the pixel driving backplane 110, and other directional terms such as top, bottom, above, below, directly below, beneath, etc. are interpreted accordingly.

[0102] Micro light-emitting diodes are the basic elements that make up micro light-emitting diode pixels. Each micro light-emitting diode pixel may include one or more micro light-emitting diode structures. A plurality of micro light-emitting diode pixels are arranged in an array to form a micro light-emitting diode display screen or a micro light-emitting diode chip. For example, each pixel in a color micro light-emitting diode chip may include a plurality of micro light-emitting diode structures of different colors, while each pixel in a monochromatic micro light-emitting diode chip may include only one color of micro light-emitting diode structure.

[0103] In an embodiment of the present invention, the size of each micro light-emitting diode chip does not exceed 1 cm, preferably does not exceed 20 microns. The micro light-emitting diode structures are formed in an array in the micro light-emitting diode chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light-emitting diode structure is at the nanometer level, for example, 20 nm to 100 nm. In some embodiments, the pitch of the micro light-emitting diode array, that is, the minimum center-to-center distance between micro light-emitting diodes, may be between about 2 microns and about 50 microns. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0104] In some embodiments, the pixel driving backplane 110 may employ an integrated circuit chip. The pixel driving backplane 110 includes a substrate, a driving circuit, and contact pads 111. Each micro light-emitting diode corresponds to a contact pad 111, and the contact pad 111 is electrically connected to the lower electrode layer 120. Each driving circuit is a pixel driver. In some cases, the driving circuit is a thin-film transistor pixel driver or a silicon CMOS pixel driver. In one embodiment, the substrate of the pixel driving backplane 110 is a Si substrate. In another embodiment, the substrate of the pixel driving backplane 110 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. The pixel driving backplane 110 is used to control the lighting and extinguishing of the micro light-emitting diodes within each pixel. In one embodiment, the material of the contact pad 111 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0105] In some embodiments of the present invention, the pixel driving backplane can be electrically connected to each micro - light - emitting diode in the micro - light - emitting diode array through separate metal interconnections. In some embodiments, each micro - light - emitting diode can be individually electrically controlled by the pixel driving backplane. In some embodiments, the pixel driving backplane can be electrically connected to the electrodes of the micro - light - emitting diode chips through metal interconnections. In some embodiments, a dielectric layer can be formed in the gaps between the micro - light - emitting diodes. In some embodiments, the dielectric layer can also be formed in the gaps between the interconnections.

[0106] In one embodiment, the lower electrode layer 120 can be a metal - bonding composite layer. The light - emitting mesa 140 of the micro - light - emitting diode can be bonded to the surface of the pixel driving backplane 110 through the metal - bonding composite layer 120, and the bonding can be completed by means such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding. In one embodiment, the metal - bonding composite layer 120 can be disposed on the pixel driving backplane 110. In another embodiment, the metal - bonding composite layer 120 grows on the pixel driving backplane 110. In one embodiment, the thickness of the metal - bonding composite layer 120 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the metal - bonding composite layer 120 is 0.3 μm. In some embodiments, the material of the metal - bonding composite layer 120 is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, Ag, and Sn. The metal - bonding composite layer 120 can include an ohmic - contact layer and a metal - bonding layer. In some cases, the metal - bonding composite layer 120 includes two metal layers. One of the two metal layers is deposited on a layer above the metal - bonding layer in the LED. The corresponding bonding metal layer is deposited on the pixel driving backplane 110. For example, the metal - bonding composite layer 120 can be Au - Au bonding, Au - Sn bonding, Au - In bonding, Ti - Ti bonding, Cu - Cu bonding, or a combination of the above. For example, if Au - Au bonding is selected, then two Au layers respectively require a Cr layer as an adhesion layer and a Pt layer as an anti - diffusion layer. The Pt layer is located between the Au layer and the Cr layer. The Cr and Pt layers are located on the top and bottom of the two bonded Au layers. In some embodiments, when the thicknesses of the two Au layers are substantially the same, at high pressure and high temperature, the Au on the two layers diffuses into each other to bond the two layers together.

[0107] In some embodiments, the metal - bonding composite layer 120 can also be used as a reflector to reflect the light emitted from the light - emitting mesa 140 above.

[0108] In some embodiments, the conductive layer 130 is formed on the bottom surface of the light-emitting mesa 140 for forming an electrical connection between the light-emitting mesa 140 and the metal bonding composite layer 120. In some embodiments, the conductive layer 130 can be a conductive transparent layer that is transparent to the light emitted by the light-emitting mesa 140 to improve conductivity and light transmittance. In some embodiments, the upper electrode layer 150 is formed on the top surface of the light-emitting mesa 140, and the upper electrode layer 150 is electrically connected to a current spreading structure or a top electrode (not shown).

[0109] In one embodiment, the conductive layer 130, the upper electrode layer 150, and their connecting components can be one or a combination of one or more of, such as graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0110] The light-emitting mesa 140 includes a first-type epitaxial layer 141, a second-type epitaxial layer 143, and a light-emitting layer 142 therebetween. The first-type epitaxial layer 141 is electrically connected to the conductive layer 130. The second-type epitaxial layer 143 is electrically connected to the upper electrode layer 150. In some embodiments, the light-emitting mesa of each micro light-emitting diode in the micro light-emitting diode array can be a micron-level light-emitting mesa. In the three-layer structure, the first-type epitaxial layer 141 is closest to the driving backplane 110; the light-emitting layer 142 is located above the first-type epitaxial layer and is farther from the driving backplane 110; the second-type epitaxial layer 143 is located above the light-emitting layer 142 and is the farthest from the driving backplane 110. In some embodiments, the light-emitting layer 142 is formed by a plurality of stacked quantum well layers, particularly superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers. In some embodiments, the first-type epitaxial layer 141 is a semiconductor material of a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first-type epitaxial layer 141 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the first-type epitaxial layer 141 can include, from top to bottom, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer; in addition, an ohmic contact layer can be formed below the window layer. In some embodiments, the second-type epitaxial layer 143 is a semiconductor material of a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second-type epitaxial layer 143 can be, but is not limited to, materials composed of Ga, N, As, P, In, or Al, etc. In addition, the second-type epitaxial layer 143 can include, from top to bottom, but is not limited to, a confinement layer and a waveguide layer; in addition, in some embodiments, an ohmic contact layer can be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0111] In some embodiments, the first type of epitaxial layer 141 is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer 143 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer 143 can be a material layer of a second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the first type of epitaxial layer 141 can be a material layer of a first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 142 includes a multi-quantum well layer and an electron blocking layer, and the multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 142 further includes an electron blocking layer, and the electron blocking layer is disposed on a first side of the light-emitting layer, and the first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type of epitaxial layer 141 can also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer 143 is an N-type GaN layer or an N-type AlGaN layer.

[0112] In some embodiments, the light-emitting layer 142 includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9, and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0113] In some embodiments, one of the first type of epitaxial layer 141 and the second type of epitaxial layer 143 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is from 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3。The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is from 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is from 50 nm to 75 nm, for example 65 nm.

[0114] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is from 0.3 to 0.5, for example x is 0.5. In such embodiments, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is from 10 nm to 30 nm, for example 20 nm.

[0115] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is from 0.5 to 0.9 and the range of y is from 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is from 50 nm to 70 nm, for example 65 nm.

[0116] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, for example 30 nm.

[0117] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, for example x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, for example 20 nm.

[0118] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0119] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0120] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 , and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0121] In some embodiments, the electrode polarity of the conductive layer 130 is determined by the first type epitaxial layer 141, and the electrode polarity of the upper electrode layer 150 is determined by the second type epitaxial layer 143. The electrode polarity of the conductive layer 130 is opposite to that of the upper electrode layer 150. The conductive layer 130 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 150 is an electrode with a polarity opposite to that of the conductive layer 130, for example, an N electrode or a cathode electrode, and vice versa.

[0122] In one embodiment, the light-emitting mesa 140 may be a platform with a trapezoidal cross-section, and the lateral dimension of the bottom of the light-emitting mesa is larger than that of the top. There is an inclination angle between the side wall of the semiconductor light-emitting mesa 140 and the bottom of the semiconductor light-emitting mesa, and this inclination angle is less than or equal to 90°. In one embodiment, the range of the inclination angle of the side wall of the light-emitting mesa is: 45° to 90°. In one embodiment, the lateral dimension of the bottom of the light-emitting mesa exceeds 2 micrometers. In one embodiment, the lateral dimension of the top of the light-emitting mesa does not exceed 1.5 micrometers. In one embodiment, the lateral dimension of the metal bonding composite layer is larger than the lateral dimension of the bottom of the light-emitting mesa.

[0123] In some embodiments, the light-emitting mesa 140 may emit red light, blue light, green light or light of any other color.

[0124] In some embodiments, the passivation layer 160 coats the side surfaces of the metal bonding composite layer 120, the conductive layer 130, and the light-emitting mesa 140. In some embodiments of the present invention, the passivation layer 160 may also cover a part of the side surface of the upper electrode layer 150, and a part of the top surface of the upper electrode layer 150 is exposed to form an electrical connection with the top electrode. In other embodiments of the present invention, the passivation layer 160 does not cover the top surface and the side surface of the upper electrode layer 150, so that the upper electrode layers 150 of adjacent LED structures can be connected to each other as a whole to form a common cathode or anode. In some embodiments of the present invention, the passivation layer 160 coats the side surfaces of the metal bonding composite layer 120, the conductive layer 130, the first-type epitaxial layer 141, the light-emitting layer 142, and a part of the side surface of the second-type epitaxial layer 143.

[0125] In one embodiment, the material of the passivation layer is a transparent insulating material, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0126] In one embodiment, the insulating medium 180 fills the gap between the light-emitting mesas 140. The insulating medium 180 is transparent to the light emitted by the light-emitting mesas 140.

[0127] In some embodiments, the insulating medium 180 is made of a dielectric material such as a solid inorganic material or a plastic material. In some embodiments, the solid inorganic material includes SiO 2 、Al 2 O 3 、Si 3 N 4 、SiCN、HfO 2 、Ta 2 O 5 、TiO 2 、ZrO 2 、La 2 O 3, MgO, phosphosilicate glass (PSG), borophosphosilicate glass, or any combination thereof. In some embodiments, the plastic material includes polymers such as SU-8, PermiNex, benzocyclobutene (BCB), or a transparent plastic (resin) including spin-on glass (SOG), or an adhesive Micro Resist BCL-1200, or any combination thereof. In some embodiments, the insulating dielectric 180 can facilitate the light emitted from the LED structure to pass through.

[0128] In some embodiments, the microlens 170 is formed on top of the light-emitting mesa 140. The lateral dimension of the bottom of the microlens 170 can be greater than the lateral dimension of the micro-LED light-emitting region. In some embodiments, the lateral dimension of the bottom of the microlens 170 can be equal to the lateral dimension of the micro-LED light-emitting region.

[0129] In some embodiments, one microlens 170 can cover multiple lensless micro-LEDs. A plurality of microlenses form a microlens array. The microlens array is disposed above the micro-LED array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro-LED, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro-LED. The microlens is mainly used to converge and / or collimate light. For example, by adjusting parameters such as the thickness and curvature of the microlens, the focal point of the microlens can be located in the light-emitting mesa of the micro-LED. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. In one embodiment, the typical shape of the bottom cross-section of each microlens includes a circle, a square, a rectangle, and a hexagon. The microlenses in the microlens array of the display panel can be the same or different in terms of shape, curvature, optical power, size, base, spacing, etc.

[0130] In some embodiments, the shape of the microlens 170 can be a curved hemisphere or a positive hemisphere. In some embodiments, the height of the microlens 170 is not greater than 2 microns. In some embodiments, the height of the microlens 170 is not greater than 1 micron. In some embodiments, the height of the microlens 170 is not greater than 0.5 micron. In some embodiments, the width of the microlens 170 is not greater than 4 microns. In some embodiments, the width of the microlens 170 is not greater than 3 microns. In some embodiments, the width of the microlens 170 is not greater than 2 microns. In some embodiments, the width of the microlens 170 is not greater than 1 micron. In some embodiments, the width-to-height ratio of the microlens 170 is greater than 1.5.

[0131] In some embodiments, the microlens 170 can be made of various materials that are transparent to light of each wavelength emitted by the micro light-emitting diodes. Exemplary transparent materials for the microlens 170 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 170 is made of photoresist. In some embodiments, the microlens is directly deposited on the surface of the micro light-emitting diode by chemical vapor deposition (CVD) technology.

[0132] Figure 9 A cross-sectional schematic view showing a micro light-emitting diode structure according to another embodiment of the present invention. As Figure 9 shown, the micro light-emitting diode structure includes a pixel driving backplane 210, a lower electrode layer 220, a conductive layer 230, a light-emitting mesa 240, an upper electrode layer 250, a passivation layer 260, a microlens 270, an insulating dielectric 280, and a reflective layer 290.

[0133] The light-emitting mesa 240 includes a first-type epitaxial layer 241, a second-type epitaxial layer 243, and a light-emitting layer 242 located therebetween. The first-type epitaxial layer 241 is electrically connected to the conductive layer 230. The second-type epitaxial layer 243 is electrically connected to the upper electrode layer 250. Figure 9 The light-emitting mesa 240 shown and Figure 8 The difference between the light-emitting mesa 140 shown is that the cross-sectional shape of the light-emitting mesa 240 is an inverted trapezoid. The lateral dimension of the bottom of the light-emitting mesa is smaller than the lateral dimension of the top. There is an inclination angle between the side wall of the semiconductor light-emitting mesa 140 and the bottom of the semiconductor light-emitting mesa, and the inclination angle is greater than or equal to 90°. In one embodiment, the inclination angle range of the side wall of the light-emitting mesa is: 90° to 135°.

[0134] In some embodiments, the passivation layer 260 coats the conductive layer 230 and the sides of the light-emitting mesa 240. In some embodiments of the present invention, the tops of the second-type epitaxial layers 243 of adjacent light-emitting mesas 240 are connected to each other, and the passivation layer 260 covers the bottom surface of the connected part of the second-type epitaxial layer 243. At least a part of the bottom surface of the light-emitting mesa 240 is not covered by the passivation layer 260, and the conductive layer 230 is located on the bottom surface of the light-emitting mesa 240 and forms an electrical connection therewith. The material of the passivation layer 260 is a transparent insulating material, for example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, and silicon nitride.

[0135] In some embodiments, the reflective layer 290 is formed on the surfaces of the passivation layer 260 and the conductive layer 230 that are away from the light-emitting mesa 240.

[0136] In some embodiments, the reflective layer 290 may be a metal layer with a high reflectivity, which includes one or more metals such as Pt, Rh, Al, Au, and Ag, including TiO 2 / SiO 2 stacked DBR layer, or any other layer with total reflection characteristics, including a multilayer omnidirectional reflector (ODR), or a combination thereof.

[0137] In some embodiments, the reflective layer 290 may be one or more reflective coatings. One or more reflective coatings can reflect the light emitted from the light-emitting region, thereby enhancing the brightness and luminous efficiency of the micro-LED panel or display. For example, the light emitted from the light-emitting region can reach one or more reflective coatings and can be reflected upward by one or more reflective coatings.

[0138] Since the reflective layer can be made of a conductive material, there is a gap 291 between the reflective layers of adjacent micro mesa structures, thereby avoiding short circuits between adjacent light-emitting mesa.

[0139] In one embodiment, the insulating dielectric 280 fills the gap between the light-emitting mesa 240. The insulating dielectric 280 is transparent to the light emitted by the light-emitting mesa 240. The material of the insulating dielectric 280 is similar to that of the insulating dielectric 180, and for the sake of simplicity of this specification, it will not be repeated here.

[0140] In some embodiments, the light-emitting mesa 240 of the micro light-emitting diode can be bonded to the surface of the pixel driving backplane 210 through a hybrid bonding process. For example, in the hybrid bonding process, an oxide bonding layer is deposited on the bottom of the light-emitting mesa structure; a corresponding oxide bonding layer is deposited on the substrate 110. Then, vias can be formed in the oxide bonding layer and filled with metal to form the lower electrode layer 220. A CMP process can be performed on the surface of the lower electrode layer 220 such that the surface of the lower electrode layer 220 is flush with the surface of the oxide bonding layer. Then, the light-emitting mesa 240 is bonded to the substrate 210 under high pressure and high temperature. In some embodiments, the lower electrode layer 220 electrically connects the contact 211 on the substrate 210 and the light-emitting mesa 240 above the lower electrode layer 220, acting as a P electrode.

[0141] In one embodiment, the upper electrode layer 250 is formed on the top surface of the light-emitting mesa 240, and the second-type epitaxial layer 243 is electrically connected to the upper electrode layer 250. The material of the upper electrode layer 250 is similar to that of the upper electrode layer 150, and for the sake of simplicity of this specification, it will not be repeated here. In some embodiments, the microlens 270 is formed on the top of the light-emitting mesa 240. The material of the microlens 270 is similar to that of the microlens 170, and for the sake of simplicity of this specification, it will not be repeated here.

[0142] In an embodiment of the present invention, the above-described micro light-emitting diodes or other similar micro light-emitting diodes form micro light-emitting diode pixels, and multiple micro light-emitting diode pixels are arranged in an array to form a micro light-emitting diode display chip.

[0143] It should be understood that in some other embodiments of the present invention, the display module may also adopt other common micro light-emitting diode array structures in the art, and the structure of the micro light-emitting diodes is not limited to the embodiments described above.

[0144] A control module and a micro display chip of the present invention integrate a variety of communication interfaces, making the adaptation range to the host computer wider. In addition, the control module can support both command mode and video mode control at the same time. Among them, the video mode drive can bring low latency and has advantages in a high-speed moving environment. The command mode can perform partial refresh, without the need to transmit all frame data, as long as some of the data is changed, thereby making the driving speed requirement for the host computer lower and bringing lower power consumption.

[0145] Although the embodiments of the present invention have been described above, it should be understood that they are presented only as examples and not as limitations. It is obvious to those skilled in the relevant art that various combinations, variations, and changes can be made to them without departing from the spirit and scope of the present invention. Therefore, the width and scope of the present invention disclosed herein should not be limited by the above-described exemplary embodiments, but should be defined only by the appended claims and their equivalents.

Claims

1. A multiplexing interface, characterized in that: include: An IO control component configured to receive and send data and determine a communication protocol used by the data; as well as N communication protocol control components are communicatively connected to the IO control component, wherein each communication protocol control component is configured to decode data transmitted using a corresponding communication protocol, and the communication protocols used by each communication protocol control component are different, wherein N is an integer greater than 1.

2. The multiplexing interface according to claim 1, characterized in that: The multiplexing interface includes at least one multiplexing pin, wherein the multiplexing pin supports a plurality of different communication protocols.

3. The multiplexing interface as claimed in claim 2, characterized in that: The IO control component includes: at least one multiplexer configured to transmit an input signal of the multiplexed pin to a corresponding communication protocol control component based on a selection signal; and At least one demultiplexer is configured to transmit the output signal of the corresponding communication protocol control component to the external module through the multiplexing pin based on the selection signal.

4. The multiplexing interface as claimed in claim 3, characterized in that: The selection signal is written from the outside.

5. The multiplexing interface according to claim 4, characterized in that: The selection signal is written via the IO pin.

6. The multiplexing interface according to claim 4, characterized in that: The selection signal is set through a one-time burning storage module or a one-time programmable module.

7. The multiplexing interface according to claim 3, characterized in that: The selection signal is determined by internal register parameters.

8. The multiplexing interface according to claim 7, characterized in that: The internal register parameters include N communication protocol locking parameters. If the communication protocol locking parameter is 0, the corresponding communication protocol control component is enabled. If the communication protocol locking parameter is 1, the corresponding communication protocol control component is unavailable.

9. The multiplexing interface according to claim 2, characterized in that: The N communication protocol control components include: A QSPI control component that uses the QSPI protocol; and I 2 C control component, which uses I 2 C protocol.

10. The multiplexing interface according to claim 9, characterized in that: The multiplexed pins include: The first multiplexed pin is configured as the IO[2] pin of the QSPI control component and the I 2 C controls the multiplexing of the SCL pin of the component; and The second multiplexed pin is configured as the IO[3] pin of the QSPI control component and the I 2 C controls the multiplexing of the SDA pin of the component.

11. A micro display chip, characterized in that: include: A control module, comprising the multiplexing interface according to any one of claims 1 to 10, wherein the multiplexing interface is configured to transmit the control signal and the original data of the host end to the interior of the control module; as well as The display module is electrically connected to the control module through a metal interconnection structure and is configured to display an image based on the control of the control module.

12. The micro display chip according to claim 11, characterized in that: The control module also includes a register configuration array, which is communicatively connected to the multiplexing interface and is configured to store register configuration parameters.

13. The micro display chip according to claim 11, characterized in that: The control module further includes a data processing submodule, which is communicatively connected to the multiplexing interface and is configured to pre-process the original data to convert it into data to be displayed.

14. The micro display chip according to claim 13, characterized in that: The preprocessing includes data compensation, and / or rotation processing, and / or flipping processing.

15. The micro display chip according to claim 13, characterized in that: The control module further includes a compensation cache component, which is communicatively connected to the data processing submodule and is configured to store compensation information, wherein the compensation information is configured to perform data compensation on the original data.

16. The micro display chip according to claim 13, characterized in that: The control module also includes: a frame buffer component configured to store a whole frame of data to be displayed; and A row data cache component is configured to store data to be displayed row by row.

17. The micro display chip according to claim 16, characterized in that: The control module further comprises a bus interconnection submodule, through which the frame buffer component and the row data buffer component are communicatively connected with the data processing submodule.

18. The micro display chip according to claim 16, characterized in that: The control module also includes: The display control submodule is communicatively connected with the frame buffer component and the row data buffer component, and is configured to transmit the data in the frame buffer component or the row data buffer component to the display module for display.

19. The micro display chip according to claim 18, characterized in that: The display control submodule includes: A display control component, which is configured to read the data to be displayed according to the working mode, and control the row and column control components based on the data to be displayed to realize image display; a row control component configured to control scanning of a display area of ​​the display module; and A column control component is configured to transmit data to the display module.

20. The micro display chip according to claim 19, characterized in that: Reading the data to be displayed according to the working mode includes: If in command mode, reading the entire frame data to be displayed from the frame buffer component; and If in video mode, the data to be displayed is read line by line from the line data buffer component.

21. The micro display chip according to claim 18, characterized in that: The control module also includes a temperature compensation module, which is communicatively connected to the display control submodule and is configured to compensate display brightness according to temperature.

22. The micro display chip according to claim 11, characterized in that: The control module includes a flexible storage controller configured to control an external flash.

23. The micro display chip according to claim 11, characterized in that: The control module also includes a test control submodule.

24. The micro display chip according to claim 11, characterized in that: The control module further includes an IP switching submodule configured to switch the internal OSC and external clock inputs, and the internal POR.

25. The micro display chip according to claim 11, characterized in that: The control module also includes a one-time burning storage module, which is configured to store configuration parameters of the control module.

26. The micro display chip according to claim 11, characterized in that: The control module further comprises an internal oscillator OSC configured to generate an internal clock of the control module.

27. The micro display chip according to claim 11, characterized in that: The control module further includes a temperature detection submodule, which is configured to obtain the temperature of the control module.

28. The micro display chip according to claim 11, characterized in that: The control module also includes a power-on reset submodule.

29. The micro display chip according to claim 11, characterized in that: The control module further comprises a clock and reset module CRG, which is configured to provide clock and reset signals.

30. The micro display chip according to claim 11, characterized in that: The display module includes a plurality of micro light emitting diode structures arranged in an array.

31. The micro display chip as claimed in claim 30, characterized in that: The micro light emitting diode structure comprises: a lower electrode layer, which is electrically connected to the substrate; A light-emitting mesa, which is bonded to the substrate through a lower electrode layer of the call number, wherein the cross section of the light-emitting mesa is a regular trapezoid or an inverted trapezoid, and comprises, from bottom to top, a first type epitaxial layer, a light-emitting layer, and a second type epitaxial layer; a conductive layer formed on the bottom surface of the light-emitting mesa and configured to form an electrical connection between the light-emitting mesa and the lower electrode layer; an upper electrode layer, which forms the top surface of the light-emitting mesa and is electrically connected to the current spreading layer; and The passivation layer covers the conductive layer and the side surfaces of the light-emitting mesa.

32. The micro display chip as claimed in claim 31, characterized in that: The material of the first type epitaxial layer is a material layer of a first conductivity type including at least two or more elements of Ga, N, As, Al, In, and P, and the second type epitaxial layer is a material layer of a second conductivity type including at least two or more elements of Ga, N, As, Al, In, and P, and the first conductivity type is different from the second conductivity type; the light-emitting layer includes a multi-quantum well layer, wherein the multi-quantum well layer is an InGaN / GaN multi-quantum well layer, an InGaN / Al GaN multi-quantum well layer, or an InGaAs / Al GaAs multi-quantum well layer; and An electron blocking layer is disposed on a first side of the light emitting layer, where the first side refers to a side along which electrons migrate out of the light emitting layer.

33. The micro display chip as claimed in claim 30, characterized in that: The display module further comprises a micro lens array, and the micro lens array is located above the micro light emitting diode structure.

Images