Chip logic function verification method, computer equipment, program product and medium

Abstract

The invention provides a chip logic function verification method, computer equipment, a program product and a medium. The chip logic function verification method comprises the following steps: obtaining a division scheme of a back-end design for each sub-module of a chip, so that the chip is re-divided into a plurality of to-be-verified modules; obtaining an RTL design scheme corresponding to the to-be-verified module; keeping the port of the to-be-verified module unchanged, and obtaining a gate-level netlist corresponding to the RTL design scheme; physical implementation of the to-be-verified module is carried out through the gate-level netlist and an EDA tool, and a design netlist after physical implementation is obtained; according to the design netlist, obtaining the time sequence information of each to-be-verified module after the time sequence convergence and the first time delay from the port of each to-be-verified module to the target register, and respectively subtracting the first time delay from the preset time delay to mark the port of each to-be-verified module so as to perform logic function verification with the time sequence information on the to-be-verified module. According to the scheme, optimization of manpower and calculator resources in the whole design process can be achieved, and the efficiency of chip logic function verification is improved.

Description

Technical Field

[0001] The present invention relates to the field of chip design technology, and in particular to a chip logic function verification method, computer equipment, program product and medium. Background Art

[0002] The chip design stage is divided into the front-end design stage and the back-end design stage according to the process: the front-end design stage is responsible for logic function design and logic function verification without timing information; the back-end design stage is based on the netlist file containing design information provided by the front-end design to perform physical implementation and physical verification, and provide the netlist and timing information file after physical implementation based on the physical information of the design; the front-end design then performs logic function verification with timing information based on the netlist and timing information file after physical implementation, and the chip design is completed if the verification is passed.

[0003] With the rapid development of integrated circuits, the scale of chips is getting larger and larger, and they will contain many modules of different sizes. However, the standards for module division of the entire chip in front-end design and back-end design are different. When designing and verifying the front-end, it is mainly based on the tightness of the logic connection, while the back-end design also considers the size of the logic on the basis of the tightness of the logic connection. This leads to conflicts between the front-end design and the back-end design in the processing of modules: the front-end design expects each module to be processed in its original state based on efficiency and timing verification considerations; while for some larger modules, the back-end design expects to disassemble them into multiple smaller modules for processing to avoid exceeding the processing scale of the EDA tool. Similarly, for some smaller modules, the back-end design expects to merge them to improve the efficiency of back-end verification. Therefore, there is an urgent need for a chip logic function verification solution that can take into account the needs of front-end design and back-end design without increasing the complexity of the entire design process, and realize the optimization of human and computer resources in the entire design process. Summary of the invention

[0004] The purpose of the present invention is to provide a chip logic function verification method, computer equipment, program product and medium, so as to realize the splitting and merging of arbitrary modules of the original level of the front end by the back end without increasing the workload of the front end or the back end, thereby realizing the optimization of human and computer resources in the entire design process and improving the efficiency of chip logic function verification.

[0005] The technical solution provided by the present invention is as follows: In a first aspect, the present application provides a chip logic function verification method, comprising the steps of: Obtaining a back-end design division scheme for each submodule of the chip to be verified, so that the chip to be verified is re-divided into a plurality of modules to be verified; Performing logic function verification without timing information on the module to be verified, and obtaining a register transfer level design scheme corresponding to the module to be verified; Keeping the port of the module to be verified unchanged, obtaining a gate-level netlist corresponding to the register transfer-level design scheme; Keeping the port of the module to be verified unchanged, physically implementing the module to be verified through the gate-level netlist and EDA tools, and obtaining a design netlist corresponding to the module to be verified after the physical implementation; Acquire timing information of each of the modules to be verified after timing closure according to the design netlist; According to the timing information, a first delay from the port of each module to be verified to its corresponding target register is obtained, and the port of each module to be verified is marked with a second delay obtained by subtracting the first delay from the preset delay, so as to perform logical function verification on the module to be verified with timing information.

[0006] In some embodiments, when the first sub-module is disassembled into several first modules to be verified through the division scheme, the logic function verification without timing information is performed on the first module to be verified, and the register transfer level design scheme of two layers of the first sub-module and several first modules to be verified corresponding to the first sub-module are obtained, the port of the first sub-module is kept unchanged, and the gate-level netlist corresponding to the register transfer level design scheme is obtained.

[0007] In some embodiments, when several second sub-modules are merged into a second module to be verified through the division scheme, the second module to be verified is subjected to logic function verification without timing information, and the register transfer level design scheme of two layers of the second module to be verified and several second sub-modules corresponding to the second module to be verified is obtained, the ports of several second sub-modules are kept unchanged, and the gate-level netlist corresponding to the register transfer level design scheme is obtained.

[0008] In some implementations, the step of acquiring the timing information of each module to be verified after timing closure according to the design netlist includes: The ports of the modules to be verified are kept unchanged, and the timing of the modules to be verified is repaired according to the design netlist until the timing convergence is achieved, and the timing information of each module to be verified after the timing convergence is obtained.

[0009] In some implementations, the preset delay is 60%-80% of the entire clock cycle from the port of the module to be verified to the target register.

[0010] In some implementations, the partitioning scheme includes disassembling, merging, or maintaining the original state of each sub-module of the chip to be verified.

[0011] In some implementations, the step of obtaining a first delay from a port of each module to be verified to a target register according to the timing information includes: The first delay from the port of each module to be verified to the target register is captured from the timing information through a script.

[0012] In a second aspect, the present application provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the chip logic function verification method described in the first aspect.

[0013] In a third aspect, the present application provides a computer storage medium having a computer program or instructions stored thereon, which, when executed by a processor, implements the steps of the chip logic function verification method described in the first aspect.

[0014] In a fourth aspect, the present application provides a computer program product, including a computer program or instructions, which, when executed by a processor, implement the steps of the chip logic function verification method described in the first aspect.

[0015] Through the chip logic function verification method, computer equipment, program product and medium provided by the present invention, in the entire chip design process, only simple tool settings are added, the layers and ports to be maintained by the front end are maintained, and short script commands are used to complete the update and statistics of timing information. The back end can then arbitrarily split and merge the original layers of the front end without causing an increase in the workload of the front end or the back end, thereby optimizing the human and computer resources in the entire design process and optimizing the chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present solution.

[0017] Figure 1 It is a flowchart of logic function verification in the chip design process; Figure 2 It is a schematic diagram of the top-level modules of a chip; Figure 3 It is a schematic diagram of module splitting of a chip after back-end optimization; Figure 4 It is a timing diagram of different ports of a chip when each module is processed separately and the logic function is verified; Figure 5 It is a timing diagram of different ports of a chip when the modules are combined and processed and the logic function is verified; Figure 6 It is a schematic diagram of the overall process of an embodiment of the present invention; Figure 7 It is a schematic diagram of the first delay captured by each module to be verified in one embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0019] In order to simplify the drawings, only the parts related to the present invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0020] like Figure 1 As shown in the figure, the design stage of the chip is divided into the front-end design stage and the back-end design stage according to the process: the front-end design stage is responsible for the logic function design and the logic function verification without timing information; the back-end design stage is to do physical implementation and physical verification based on the netlist file containing the design information provided by the front-end design, and provide the netlist and timing information file after physical implementation based on the physical information of the design; the front-end design then does the logic function verification with timing information based on the netlist and timing information file after physical implementation, and the chip design is completed if the verification passes.

[0021] However, with the rapid development of integrated circuits, the scale of chips is getting larger and larger, and they will contain many modules of different sizes, such as Figure 2 The top layer of a chip shown includes multiple modules such as A, B, C, D, E, F, G, and during design, different designers are generally responsible for designing the top layer and the parallel development of each module A, B, C, D, E, F, G to speed up the chip design progress.

[0022] During this design process, the front-end design and the back-end design have different standards for module division of the entire chip, which will lead to inconsistent module solutions for the expected chip division, resulting in certain conflicts. Specifically, the front-end design and verification are mainly based on the tightness of the logic connection, while the back-end design also considers the size of the logic based on the tightness of the logic connection. This leads to conflicts in the processing of modules between the front-end design and the back-end design: the front-end design expects each module to remain in its original state for processing based on efficiency and timing verification considerations; for some larger modules, the back-end design expects to disassemble them into multiple smaller modules for processing to avoid exceeding the processing scale of the EDA tool. Similarly, for some smaller modules, the back-end design expects to merge them for processing to improve the efficiency of back-end verification.

[0023] Specifically, Figure 2 Taking the chip distribution shown as an example, the B module and the C module are relatively suitable for the module scale of the back-end EDA tool to process; the scale of the A module is much larger than that of the B module and the C module, which exceeds the scale that the back-end EDA tool can process. Therefore, from the perspective of the back-end, the A module needs to be divided into smaller modules, such as A1 module and A2 module for processing; and the D / E / F / G modules are relatively small in scale, and the back-end EDA tool can process a larger scale, so from the perspective of the back-end, it is more inclined to merge the D / E / F / G modules together for processing, and merging multiple modules for processing can avoid the waste of human and machine resources caused by processing multiple modules in parallel. At the same time, merging the D / E / F / G modules may also lead to area optimization. For example, the area of ​​the D module itself is mainly occupied by the wiring, and the area occupied by the logic unit itself is relatively low. The E module itself has fewer wiring, and the area mainly occupied by the logic unit. If the D / E module is separated into two modules for physical implementation, the physical boundaries of each other are isolated and cannot be used by each other; but if the D / E modules are merged together, the areas of each other can be absorbed by each other, and the total area used will be smaller than the area of ​​the D / E modules implemented separately. Therefore, according to the above example, the original Figure 2 The corresponding module splitting scheme in has been modified by the backend as follows Figure 3 Module distribution shown.

[0024] In summary, there are two types of conflicts that need to be resolved in the front-end and back-end processing of module merging and disassembly: (1) Larger modules on the front end need to be further disassembled on the back end; (2) Smaller modules on the front end need to be further merged on the back end.

[0025] In conflict (1), the reason why the front-end does not want to do further disassembly is that the front-end verification platform hopes that A is a complete subsystem, so that the input and output ports are clear and there is a mature protocol, which is easier to verify. The correctness of the subsystem can be quickly verified with fewer input combinations and corresponding clear output results. If A is split into two smaller modules A1+A2, the division of A1 and A2 is more of a structure combined according to the scale within the system. The input and output ports of A1 and A2 themselves are no longer so corresponding to the mature protocol. When the front-end designers need to verify, they need to spend more energy to study the input combinations of each function of the split subsystem on the A1 / A2 ports and the corresponding clear output results. This workload may be very large (even impossible to complete within a certain period of time).

[0026] In conflict (2), the reason why the front-end does not want to make further merges is that when the D / E / F / G modules are optimized in the back-end, for each module, the back-end EDA tool may generate / copy some new ports and optimize / merge some original ports. In this way, when the front-end designers do timing information verification based on the netlist after the back-end physical design, they need to do a lot of research to map with the original ports and understand the functional changes. This workload will be very huge and may even be impossible to complete in a certain period of time. In addition, because the processing of the EDA tool may be inconsistent each time, it is necessary to wait until the last version of the physical design optimized netlist is completed before specifically studying the mapping between ports. This is even more unacceptable in terms of work planning. At the same time, if D / E / F / G is treated as a separate module, each module in D / E / F / G has a fixed physical boundary, so there is a certain consistency in the timing between different ports of each module. When the front-end performs logic function verification with timing function, such as Figure 4 As shown in the figure, a fixed delay can be given to all ports, and the timing of the ports can be easily adjusted so that the timing of the entire port can be met, completing the functional verification with timing information; however, when D / E / F / G are merged into a new module, the ports of D / E / F / F themselves have become module pins of the soft module, so the timing between different ports of each module is quite different, such as Figure 5 As shown, it is difficult for the front end to adjust the port timing with the same fixed delay, resulting in a large amount of subsequent work.

[0027] Therefore, there is an urgent need for a chip logic function verification solution that can take into account the needs of front-end design and back-end design without increasing the complexity of the entire design process, and achieve optimization of human and computer resources in the entire design process. This solution aims at the conflict between the front-end and back-end designs in the design process of the entire chip on the module division scheme. Without increasing the complexity of the entire design process, the optimization of the module division scheme by the back-end design is taken as the basis, so that the entire back-end process design can be optimized in terms of human and machine resources, as well as chip area optimization; at the same time, through script and tool settings, the needs of front-end verification can be met without changing (i.e., without increasing / reducing and changing the port function definition) the ports of the modules to be verified defined by each front-end, and the timing information required by the port can be conveniently given so that the timing of the port can be met. The following is a detailed description of this solution in conjunction with the accompanying drawings: In one embodiment, the reference specification Figure 6 , the present application provides a chip logic function verification method, comprising the steps of: S100, obtaining a division scheme of the back-end design for each sub-module of the chip to be verified, so that the chip to be verified is re-divided into a plurality of modules to be verified.

[0028] Specifically, the division scheme includes disassembling, merging or maintaining the original state of each submodule of the chip to be verified. Figure 2 Taking the chip distribution shown as an example, the B module and the C module are relatively suitable for the scale of the back-end EDA tool to process, and can remain unchanged; while the A module is relatively large, exceeding the scale that the back-end EDA tool can process, so the A module is divided into smaller A1 modules and A2 modules; while the D / E / F / G modules are relatively small in size, the D / E / F / G modules can be merged into the H module for processing. This application does not limit the specific disassembly and merging schemes, and can be flexibly adjusted according to needs and hardware conditions.

[0029] S200 , performing logic function verification without timing information on the module to be verified, and obtaining a register transfer level design scheme corresponding to the module to be verified.

[0030] That is, after the chip to be verified is redivided into several modules to be verified, the front-end design is first performed, the logic function of the modules to be verified is verified without timing information, and the register transfer level design scheme corresponding to the modules to be verified is obtained.

[0031] For different types of modules to be verified, if the first submodule is disassembled into several first modules to be verified through the division scheme, the logic function verification of the first module to be verified without timing information is performed, and the register transfer level design scheme of the first submodule and several first modules to be verified corresponding to the first submodule is obtained. Figure 2Taking the chip distribution shown in the figure as an example, this scheme obtains the register transfer level design (RTL design) of two levels A+A1 / A2. If, when the partitioning scheme is adopted, several second submodules are merged into the second module to be verified, the logic function verification of the second module to be verified without timing information is performed, and the register transfer level design scheme of two levels of the second module to be verified and several second submodules corresponding to the second module to be verified is obtained. Figure 2 Taking the chip distribution shown as an example, the RTL design of the two-layer hierarchy of H+D / E / F / G is obtained.

[0032] S300 , keeping the ports of the module to be verified unchanged, and obtaining a gate-level netlist corresponding to the register transfer-level design solution.

[0033] Based on the RTL design and the list of modules to be verified provided by the front end, the ports of the modules to be verified are kept unchanged, and a gate-level netlist corresponding to the front-end RTL design is generated. If the first submodule is disassembled into several first modules to be verified through the partitioning scheme, the ports of the first submodule are kept unchanged, and the gate-level netlist corresponding to the register transfer level design scheme is obtained. Figure 2 Taking the chip distribution shown in FIG. 1 as an example, the ports of module A are kept unchanged, and the gate-level netlist corresponding to the register transfer level design scheme is obtained. If, when the partitioning scheme is adopted, several second submodules are merged into the second module to be verified, the ports of several second submodules are kept unchanged, and the gate-level netlist corresponding to the register transfer level design scheme is obtained. Figure 2 Taking the chip distribution shown as an example, the ports of the D / E / F / G modules are kept unchanged to obtain the gate-level netlist corresponding to the register transfer level design scheme.

[0034] S400 , keeping the port of the module to be verified unchanged, physically implementing the module to be verified through a gate-level netlist and EDA tools, and obtaining a design netlist corresponding to the module to be verified after the physical implementation.

[0035] Physical implementation includes automatic layout and routing, etc. The physical implementation of the module to be verified is performed according to the gate-level netlist information through EDA tools. During the physical implementation process of the EDA tool, the ports of the module to be verified must be kept unchanged to generate the design netlist after physical implementation.

[0036] S500 , obtaining timing information of each module to be verified after timing closure according to the design netlist.

[0037] In a specific implementation, the timing information of each module to be verified after timing convergence is obtained according to the design netlist, including: keeping the port of the module to be verified unchanged, performing timing repair on the module to be verified according to the design netlist until timing convergence is achieved, and obtaining the timing information of each module to be verified after timing convergence.

[0038] S600. Obtain a first delay from a port of each module to be verified to its corresponding target register according to the timing information, and mark the port of each module to be verified with a second delay obtained by subtracting the first delay from the preset delay, so as to perform logic function verification on the module to be verified with timing information.

[0039] According to the timing information, the first delay from the port of each module to be verified to the target register is obtained, including: using a script to capture the first delay from the port of each module to be verified to its corresponding target register from the timing information. This application does not limit the specific form of the script, as long as it can complete the capture work. Figure 7 As shown, this solution uses a script to capture the first delay T_delay that each front-end needs to maintain from the port of the module to be verified to the target register. Generally, in order to meet the setup time and hold time, the delay from the port to the target register is increased to the preset delay, which is 60%-80% of the entire clock cycle from the port of the module to be verified to the target register, for example, 70% of the entire clock cycle. At each front-end, the port of the module to be verified needs to be marked according to the second delay of 0.7×cycle-T_delay, so as to perform logic function verification with timing information on the module to be verified.

[0040] Through the chip logic function verification method provided in the present application, in the entire chip design process, only simple tool settings are added, the layers and ports that the front-end wants to maintain are maintained, and short script commands are used to complete the update and statistics of timing information. The back-end can then arbitrarily split and merge the original layers of the front-end without causing an increase in the workload of the front-end or back-end, thereby optimizing the human and computer resources in the entire design process and further optimizing the chip area.

[0041] In one embodiment, the present application provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the chip logic function verification method of the aforementioned embodiment.

[0042] In one embodiment, the present application provides a computer storage medium having a computer program or instruction stored thereon, which implements the steps of the chip logic function verification method of the aforementioned embodiment when the computer program or instruction is executed by a processor.

[0043] In one embodiment, the present application provides a computer program product, including a computer program or instructions, which implement the steps of the chip logic function verification method of the aforementioned embodiment when the computer program or instructions are executed by a processor.

[0044] It should be noted that the above embodiments can be freely combined as needed. The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims

1. A chip logic function verification method, characterized in that: Includes steps: Obtaining a back-end design division scheme for each submodule of the chip to be verified, so that the chip to be verified is re-divided into a plurality of modules to be verified; Performing logic function verification without timing information on the module to be verified, and obtaining a register transfer level design scheme corresponding to the module to be verified; Keeping the port of the module to be verified unchanged, obtaining a gate-level netlist corresponding to the register transfer-level design scheme; Keeping the port of the module to be verified unchanged, physically implementing the module to be verified through the gate-level netlist and EDA tools, and obtaining a design netlist corresponding to the module to be verified after the physical implementation; Acquire timing information of each of the modules to be verified after timing closure according to the design netlist; According to the timing information, a first delay from the port of each module to be verified to its corresponding target register is obtained, and the port of each module to be verified is marked with a second delay obtained by subtracting the first delay from the preset delay, so as to perform logical function verification on the module to be verified with timing information.

2. The chip logic function verification method according to claim 1, characterized in that: When the first submodule is disassembled into a plurality of first modules to be verified by the division scheme, the first module to be verified is verified without timing information, and the register transfer level design scheme of the first submodule and the plurality of first modules to be verified corresponding to the first submodule at two levels is obtained. The ports of the first submodule are kept unchanged, and the gate-level netlist corresponding to the register transfer-level design scheme is obtained.

3. The chip logic function verification method according to claim 1, characterized in that: When a plurality of second submodules are merged into a second module to be verified through the division scheme, a logic function verification without timing information is performed on the second module to be verified, and a register transfer level design scheme of two levels of the second module to be verified and a plurality of second submodules corresponding to the second module to be verified is obtained. The ports of a plurality of the second submodules are kept unchanged, and the gate-level netlist corresponding to the register transfer-level design scheme is obtained.

4. The chip logic function verification method according to claim 1, characterized in that: The step of obtaining the timing information of each module to be verified after timing closure according to the design netlist includes: The ports of the modules to be verified are kept unchanged, and the timing of the modules to be verified is repaired according to the design netlist until the timing convergence is achieved, and the timing information of each module to be verified after the timing convergence is obtained.

5. The chip logic function verification method according to claim 1, characterized in that: The preset delay is 60%-80% of the entire clock cycle from the port of the module to be verified to the target register.

6. The chip logic function verification method according to claim 1, characterized in that: The partitioning scheme includes disassembling, merging or maintaining the original state of each submodule of the chip to be verified.

7. The chip logic function verification method according to claim 1, characterized in that: The step of obtaining the first delay from the port of each module to be verified to the target register according to the timing information includes: The first delay from the port of each module to be verified to its corresponding target register is captured from the timing information through a script.

8. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the chip logic function verification method according to any one of claims 1 to 7.

9. A computer storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the chip logic function verification method described in any one of claims 1 to 7 are implemented.

10. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the chip logic function verification method described in any one of claims 1 to 7 are implemented.

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