Layout and wiring process verification method and device, electronic equipment and storage medium

Abstract

The invention provides a layout and wiring process verification method and device, electronic equipment and a storage medium, and belongs to the technical field of integrated circuits. According to the method, verification cases in a to-be-tested batch group are respectively input into a target device, layout wiring is carried out on the verification cases, a layout wiring result of each verification case is obtained, and a verification report of the target device is generated according to the layout wiring results. And generating a new verification case according to the to-be-configured information under the condition that the target device is analyzed to have the to-be-configured information according to the verification report, so as to integrate the new and old verification cases to perform layout and wiring verification again until the to-be-configured information does not exist. Thus, omission of verification scenes is avoided, it is ensured that the layout and wiring verification process can cover all verification scenes of each device, meanwhile, new verification cases which are not verified are generated quickly and accurately, technicians do not need to check one by one and then manually configure the verification cases, time consumption is reduced, and verification efficiency is greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and more particularly, to a method, apparatus, electronic device, and storage medium for verifying a placement and routing process. Background Art

[0002] In the design process of a Field Programmable Gate Array (FPGA), the verification of the placement and routing process is a crucial step, which ensures that the design meets the electrical and physical specifications and can operate properly at the expected clock frequency. With the increasing demand for FPGA applications, the requirements for its placement and routing process and reliability are also rising. Therefore, the verification of the placement and routing process has become an essential step in ensuring the quality of FPGA products.

[0003] However, the placement and routing process verification methods in the related art have problems of incomplete scenario coverage and low efficiency. Therefore, there is an urgent need for a placement and routing process verification method that can comprehensively cover various scenarios and has high efficiency. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a method, apparatus, electronic device, and storage medium for verifying a placement and routing process, which can more comprehensively cover various verification scenarios of the device and greatly improve the verification efficiency.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] In a first aspect, the present invention provides a method for verifying a placement and routing process, the method comprising:

[0007] Inputting each verification case in a batch of cases to be tested into a target device respectively to perform placement and routing on each verification case, so as to obtain the placement and routing result of each verification case;

[0008] Generating a verification report of the target device according to the placement and routing result;

[0009] Generating configuration information to be configured for the target device according to the verification report;

[0010] Judging whether the configuration information to be configured is empty;

[0011] If not, generating a new verification case according to the configuration information to be configured, using the new verification case and the original verification cases as a new batch of cases to be tested, and returning to execute the step of inputting each verification case in the batch of cases to be tested into the target device respectively to perform placement and routing on each verification case, so as to obtain the placement and routing result of each verification case.

[0012] Optionally, the placement and routing result includes various resources and clock information used in the verification case;

[0013] The step of generating a verification report for the target device based on the placement and routing result includes:

[0014] Preprocess each of the placement and routing results to eliminate incorrect placement and routing results;

[0015] Obtain the resource ratio of various resources in the verification case according to the usage numbers of various resources in the remaining placement and routing results and the total numbers of various resources of the target device;

[0016] Obtain the maximum clock frequency from the clock information of the remaining placement and routing results;

[0017] Integrate the resource ratios of various resources and the maximum clock frequency to obtain a verification report for the target device.

[0018] Optionally, the placement and routing result further includes a simulation file of the verification case;

[0019] The step of preprocessing each of the placement and routing results to eliminate incorrect placement and routing results includes:

[0020] For each verification case, extract a verification performance value from the placement and routing result of the verification case, and simulate the simulation file in the placement and routing result to obtain the implemented function after placement and routing of the verification case;

[0021] Obtain incorrect cases where the placement and routing do not meet the expected results from each verification case according to the verification performance value and the implemented function;

[0022] Eliminate the placement and routing results of the incorrect cases and send an error alarm message for the incorrect cases.

[0023] Optionally, the verification report includes the resource ratio of various resources in the verification case and the maximum clock frequency;

[0024] The step of generating the to-be-configured information for the target device according to the verification report includes:

[0025] Determine uncovered items from the usage rate levels of various resources according to the resource ratio of various resources; where each usage rate level corresponds to a resource usage rate interval;

[0026] Generate an uncovered item corresponding to the maximum clock frequency in the case where the maximum clock frequency in the verification report is less than the maximum clock frequency of the target device;

[0027] Combining all the above-mentioned uncovered items, the configuration information to be configured for the target device is obtained.

[0028] Optionally, the step of determining the uncovered items from the usage rate levels of various resources according to the resource proportion of various resources includes:

[0029] For each usage rate level of each type of resource, according to the resource proportions of the type of resource, the total number of resource proportions falling within the usage rate level is statistically calculated to obtain the coverage value of the usage rate level;

[0030] Taking the usage rate levels with a coverage value of zero in various resources as the uncovered items.

[0031] Optionally, the step of generating a new verification case according to the configuration information to be configured includes:

[0032] When the configuration information to be configured only includes the uncovered item of the maximum clock frequency, taking the verification case corresponding to the maximum clock frequency in each layout and routing result as the reference case, and based on the reference case, obtaining a new verification case;

[0033] When the configuration information to be configured only includes the uncovered items of various resources, traversing and combining the uncovered items of various resources to obtain a new verification case;

[0034] When the configuration information to be configured includes the uncovered item of the maximum clock frequency and the uncovered items of various resources, traversing and combining the uncovered items of various resources to obtain a new verification case, and taking the verification case corresponding to the maximum clock frequency in each layout and routing result as the reference case, and based on the reference case, obtaining a new verification case.

[0035] Optionally, the step of obtaining a new verification case based on the reference case includes:

[0036] Lowering the logic level of the reference case and taking the reference case with the lowered logic level as the new verification case.

[0037] In a second aspect, the present invention provides a layout and routing process verification device, including a layout and routing module, a report generation module, a report analysis module, a judgment module, and a case generation module;

[0038] The layout and routing module is configured to input each verification case in the to-be-tested batch group into the target device respectively, so as to perform layout and routing on each verification case respectively, and obtain the layout and routing result of each verification case;

[0039] The report generation module is used to generate a verification report for the target device according to the layout and routing result;

[0040] The report analysis module is used to generate the information to be configured for the target device according to the verification report;

[0041] The judgment module is used to judge whether the information to be configured is empty;

[0042] The case generation module is used, when the information to be configured is not empty, to generate a new verification case according to the information to be configured, use the new verification case and the original verification cases as a new batch of cases to be tested, and instruct the layout and routing module to input each verification case in the new batch of cases to be tested into the target device respectively, so as to perform layout and routing on each verification case respectively, and obtain the layout and routing result of each verification case.

[0043] In a third aspect, the present invention provides an electronic device, including a processor and a memory, where the memory stores a computer program that can be executed by the processor, and the processor can execute the computer program to implement the layout and routing process verification method as described in the first aspect.

[0044] In a fourth aspect, the present invention provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, it implements the layout and routing process verification method as described in the first aspect.

[0045] For the layout and routing process verification method, device, electronic device and storage medium provided by the embodiments of the present invention, the method inputs each verification case in the batch of cases to be tested into the target device respectively, so as to perform layout and routing on each verification case respectively, obtain the layout and routing result of each verification case, generate a verification report for the target device according to the layout and routing result, and when it is analyzed according to the verification report that there is information to be configured for the target device, generate a new verification case according to the information to be configured, so as to comprehensively perform layout and routing verification on the new and old verification cases until there is no information to be configured. In this way, the omission of verification scenarios is avoided, it is ensured that the layout and routing verification process can cover all verification scenarios of each device, and at the same time, new verification cases that have not been verified are generated quickly and accurately, without the need for technicians to check one by one and then manually configure, which reduces the time consumption and greatly improves the verification efficiency.

[0046] To make the above objects, features and advantages of the present invention more obvious and understandable, the following specifically gives preferred embodiments and cooperates with the attached drawings to make detailed descriptions as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show certain embodiments of the present invention and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0048] Figure 1 It shows a schematic diagram of the system architecture of the layout and routing process verification system provided by the embodiments of the present invention.

[0049] Figure 2 It shows a schematic diagram of the module architecture of the electronic device provided by the embodiments of the present invention.

[0050] Figure 3 It shows a schematic diagram of the process of the layout and routing process verification method provided by the embodiments of the present invention.

[0051] Figure 4 It shows Figure 3 a schematic diagram of the process of some sub-steps of step 13 in

[0052] Figure 5 It shows Figure 4 a schematic diagram of the process of some sub-steps of step 131 in

[0053] Figure 6 It shows Figure 3 a schematic diagram of the process of some sub-steps of step 15 in

[0054] Figure 7 It shows a schematic diagram of the module architecture of the layout and routing process verification device provided by the embodiments of the present invention.

[0055] Explanation of reference numerals: 10 - layout and routing process verification system; 110 - verification device; 120 - FPGA chip; 20 - electronic device; 210 - memory; 220 - processor; 230 - communication module; 30 - layout and routing process verification device; 310 - layout and routing module; 320 - report generation module; 330 - report analysis module; 340 - judgment module; 350 - case generation module. Detailed implementation manners

[0056] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Usually, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0057] Accordingly, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0058] It should be noted that relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

[0059] The layout and routing process verification method provided by the embodiments of the present invention can be applied to Figure 1 the layout and routing process verification system 10 shown in the figure. The layout and routing process verification system 10 includes a verification device 110 and multiple FPGA development boards. Each FPGA development board includes an FPGA chip 120 and peripheral interfaces (such as USB interfaces, Ethernet interfaces, HDMI interfaces, etc.). The verification device 110 is communicatively connected to the FPGA chip 120 through the peripheral interfaces.

[0060] Software tools required in the FPGA design process, such as layout tools, routing tools, and simulation tools, are installed on the verification device 110, and the verification device 110 can be, but is not limited to, a personal computer, a laptop computer, etc.

[0061] The verification device 110 is used to implement the layout and routing process verification method provided by the embodiments of the present invention.

[0062] Please refer to Figure 2 which is a block diagram of an electronic device 20. The electronic device 20 can be Figure 1 the verification device 110 in the layout and routing process verification system 10 shown in the figure. The electronic device 20 includes a memory 210, a processor 220, and a communication module 230. The elements of the memory 210, the processor 220, and the communication module 230 are directly or indirectly electrically connected to each other to achieve data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses or signal lines.

[0063] Among them, the memory 210 is used to store programs or data. The memory 210 can be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Programmable Read-Only Memory (EPROM), an Electric Erasable Programmable Read-Only Memory (EEPROM), etc.

[0064] The processor 220 is used to read / write the data or programs stored in the memory 210 and perform corresponding functions. For example, Figure 1 In the layout and routing process verification system 10 shown, the processor 220 of the verification device 110 reads the computer program stored in the memory 210 to implement the layout and routing process verification method provided by the embodiments of the present invention.

[0065] The communication module 230 is used to establish a communication connection between the verification device 110 and the device through a communication interface and is used to send and receive data through the communication interface. For example, Figure 1 In the layout and routing process verification system 10 shown, the verification device 110 sends and receives data with each FPGA chip 120 through a communication interface.

[0066] It should be understood that Figure 2 The structure shown is only a schematic diagram of the structure of the verification device 110, and the verification device 110 may further include more or fewer components than those shown in Figure 2 or have a configuration different from that shown in Figure 2 . Figure 2 Each component shown in can be implemented by hardware, software, or a combination thereof.

[0067] To solve the problems of incomplete scenario coverage and low efficiency existing in the existing layout and routing process verification methods, embodiments of the present invention provide a layout and routing process verification method. Referring to Figure 3 , it includes steps 11 to 19. Thus, it is made that: Figure 1 In the layout and routing process verification system 10 shown, the verification device 110, with the structure shown in Figure 2 , when the processor 220 executes the computer program stored in the memory 210, implements steps 11 to 19.

[0068] Step 11: Input each verification case in the batch group to be tested into the target device respectively to perform placement and routing for each verification case, and obtain the placement and routing results of each verification case.

[0069] Among them, a verification case implements one function of the target device, and these functions can be but are not limited to: timing, FIFO function, signal integrity, interface function, performance, power consumption, etc. The target device can be any FPGA chip.

[0070] Step 13: Generate a verification report for the target device based on the placement and routing results.

[0071] Step 15: Generate the configuration information to be configured for the target device according to the verification report.

[0072] Step 17: Determine whether the configuration information to be configured is empty. If not, execute Step 19; if so, end the verification.

[0073] Step 19: Generate new verification cases according to the configuration information to be configured, and use the new verification cases and the original verification cases as the new batch group to be tested.

[0074] Moreover, after executing Step 19, return to execute Step 11 to use the method of the above Steps 11 to 19 for the verification cases of the new batch group to be measured, and repeat the above process until the configuration information to be configured is empty, that is, confirm that all verification scenarios are covered.

[0075] Exemplarily, in combination with Figure 1 the placement and routing process verification system 10 shown, the verification device 110 automatically generates a batch group to be tested (including multiple verification cases) according to various resources of the target device (including logical resources (such as look-up tables, logic units, etc.), registers, I / O (input / output interfaces), block random access memories 210 (Block RAM, BRM), digital signal processing modules (DSP), etc.) and timing, or is manually input or selected and configured by a technician to obtain a batch group to be tested.

[0076] Furthermore, the verification device 110 determines the target device from multiple FPGA chips 120. The verification device 110 selects an unplaced and unrouted verification case from the batch group to be tested through the peripheral interface on the FPGA development board where the target device is located, inputs the verification case into the target device, and performs placement and routing on the FPGA that has input the verification case to obtain the placement and routing results of a verification case. After repeating multiple times, the placement and routing results of each verification case are obtained.

[0077] It should be noted that when there are multiple identical target devices, layout and routing can be performed on multiple verification cases simultaneously. In addition, layout means placing logic units such as logic gates and flip-flops required by the verification cases into the logic units of the target device, and routing means allocating actual physical paths for the connections between logic units in the target device. The layout and routing can be any known layout and routing method, which will not be elaborated here.

[0078] After obtaining the layout and routing results of all verification cases, the verification device 110 generates a verification report for the target device based on each layout and routing result. Then, the verification report is analyzed to obtain the configuration information to be configured for the target device. When the configuration information to be configured is empty, it means that all verification scenarios are covered, and the layout and routing verification ends. When the configuration information to be configured is not empty, it means that not all verification scenarios are covered. The verification device 110 generates a new verification case for the configuration information to be configured, and forms a new batch of cases to be tested by combining the new and old verification cases, and repeats the verification process until it is confirmed that all verification scenarios of the target device are covered, that is, the verification of all functions is completed.

[0079] In the layout and routing verification in the related art, verification is usually carried out by manually preparing cases, which is difficult to cover all verification scenarios, and the operation of manually preparing cases is slow and complex, resulting in low verification efficiency.

[0080] The above layout and routing process verification method automatically performs layout and routing of batch cases, generates a verification report, analyzes the verification report to confirm whether all verification scenarios are covered, regenerates a verification case for the configuration information to be configured based on the configuration information to be configured, and repeats the verification process, avoiding omission of verification scenarios, and ensuring that the layout and routing verification process can cover all verification scenarios of each device. At the same time, it automatically and quickly and accurately generates new verification cases that have not been verified, without the need for technicians to check one by one and then manually configure, reducing the time consumption, reducing the verification complexity, and greatly improving the verification efficiency.

[0081] Among them, after the layout and routing of each verification case is completed, the FPGA design verification tool on the verification device will automatically generate the layout and routing results, which include various resources and clock information used by the verification case, as well as the simulation file of the verification case (usually a bitstream file).

[0082] After obtaining the layout and routing results, in step 13, a pre-deployed verification report generation tool can be used to generate a verification report, or a preset rule can be used to generate a verification report, and its implementation method is not limited.

[0083] In order to make the verification report accurately reflect the scenarios covered by the currently laid-out and routed verification cases, the idea of eliminating incorrect layout and routing results and separately counting various scenario factors is introduced during the generation of the verification report. Refer toFigure 4 In step 13, the process of generating the verification report for the target device includes steps 131 to 137.

[0084] In step 131, preprocess each placement and routing result to eliminate incorrect placement and routing results.

[0085] Here, the preprocessing method can be set flexibly. For example, it can be to compare the placement and routing result of each verification case with the expected result. If they are inconsistent, the placement and routing result of this verification case is eliminated as an incorrect result. It can also be to compare the implemented function of the placement and routing result with the expected function. If the two are inconsistent, it is eliminated as an incorrect result. And the above methods are only examples, and their implementation methods are not limited.

[0086] It should be understood that the essence of an incorrect placement and routing result is a verification case error. In order to accurately identify and eliminate incorrect placement and routing results (verification cases) to avoid interference with verification, the concept of determining incorrect placement and routing results based on the implemented function and verification performance values (including different rates, pass rates, running times, etc.) is introduced in the preprocessing of step 131. Refer to Figure 5 which includes steps 1311 to 1315.

[0087] In step 1311, for each verification case, extract the verification performance value from the placement and routing result of the verification case, and simulate the simulation file in the placement and routing result to obtain the implemented function after placement and routing of the corresponding verification case.

[0088] Among them, the verification performance values include the routing completion rate, pass rate, running time, running memory, etc. of the verification case. The routing completion rate refers to the probability that the design can be successfully routed during the FPGA placement and routing process. The pass rate refers to the proportion of successful completion of placement and routing under certain conditions. The running time refers to the time required to complete the FPGA placement and routing process. After completing the placement and routing, the verification performance value and the simulation file can be extracted from the placement and routing result. The simulation file is essentially a bitstream file.

[0089] The verification device 110 runs the simulation file on the simulation tool to obtain the functional simulation result, that is, the implemented function after placement and routing of the verification case.

[0090] In step 1313, based on the verification performance value and the implemented function, obtain the incorrect cases where the placement and routing do not reach the expected result from each verification case.

[0091] Each verification case is configured according to the expected results. Therefore, the verification performance and implemented functions of the verification case are compared item by item with the corresponding items in the expected results, that is, the implemented function is compared with the expected function, the running time is compared with the expected running time, the through rate is compared with the expected through rate, etc. When one of them is inconsistent, the verification case can be regarded as an error case.

[0092] Step 1315, eliminate the layout and routing results of the error case, and send out the error alarm information of the error case.

[0093] The error alarm information is used to alert developers of the error case so that they can modify or correct it in time.

[0094] Through the above steps 1311 to 1315, quickly and accurately identify each incorrect verification case and its layout and routing results, and timely eliminate the layout and routing results of the error case to avoid its interference with the verification and the discrimination of the verification scenario coverage, making the layout and routing process verification more well-founded and credible, improving the verification accuracy, and thus improving the quality of FPGA products.

[0095] Step 133, obtain the resource occupancy ratio of various resources in the verification case according to the usage numbers of various resources in the remaining layout and routing results and the total numbers of various resources of the target device.

[0096] Each layout and routing result includes the numbers of various resources such as logic, registers, input / output interfaces (IO), BlockRAM, digital signal processing modules, etc. used by the verification case, the IOBank usage, and clock information (clock frequency, number of clocks, and logic levels), etc. Therefore, for each type of resource, calculate the ratio of the number of this type of resource used in a verification case to the total number of various resources in the target device to obtain a resource occupancy ratio of this type of resource for the verification (that is, the resource occupancy ratio of this type of resource in this verification case).

[0097] Among them, IOBank refers to a group of I / O pins sharing power supply (that is, input / output interfaces). An FPGA product (that is, an FPGA chip) usually has one or more IOBanks. For each IOBank, count the number of IOs belonging to this IOBank from the IOs used in a verification case, and use the ratio of this number to the total number of IOs of the IOBank as a resource occupancy ratio of this IOBank.

[0098] Step 135, obtain the maximum clock frequency from the clock information of the remaining layout and routing results.

[0099] Extract the corresponding clock frequencies from each layout and routing result, and after comparison, the maximum clock frequency and the verification case that generates this maximum clock frequency can be obtained.

[0100] Step 137, obtain the verification report of the target device by synthesizing the resource ratios and maximum clock frequencies of various resources.

[0101] Through the above steps 131 to 137, count the resource ratios of various resources in the correct placement and routing results one by one to obtain the verification report, ensuring the accuracy of the verification report. Moreover, this verification report can clearly display the usage of various resources (logic, registers, I / O, I / O banks, digital processing modules), maximum clock frequency, etc. of the placement and routing of the current batch group to be tested, so as to facilitate the analysis of whether the coverage of the verification cases is comprehensive.

[0102] After obtaining the verification report, any implementation method can be adopted in step 15 to analyze the verification report to generate the information to be configured. For example, it can be by traversing and comparing one by one to identify the verification scenarios not appearing in the verification report, or it can be to analyze the resource coverage and timing coverage in the verification cases in parallel, and its implementation method is not limited.

[0103] Refer to Figure 6 , the process of generating the information to be configured for the target device in step 15 can include steps 151 to 155.

[0104] Step 151, determine the uncovered items from the usage rate levels of various resources according to the resource ratios of various resources.

[0105] Among them, each type of resource has multiple pre-configured usage rate levels (which can also be understood as configuration options), and each usage rate level corresponds to a resource usage rate interval.

[0106] For example, divide the usage rate interval of the logic resources into 20 equal parts. At this time, there are 20 usage rate levels for the configuration options of the logic resources, namely Logic_Level_1 to Logic_Level_20. Among them, the resource usage rate interval corresponding to Logic_Level_1 is 0% to 5%, and the resource usage rate area corresponding to Logic_Level_20 is 95% to 100%.

[0107] Similarly, the usage rate range of registers is evenly divided into 20 levels, and there are 20 levels of register configuration options, namely Register_Level_1 to Register_Level_20. Among them, the resource usage rate range corresponding to Register_Level_1 is 0% to 5%, and the resource usage rate range corresponding to Register_Level_20 is 95% to 100%. The resource usage rate range of IO can also be evenly divided into 20 levels, and there are 20 levels of IO configuration options, namely IO_Level_1 to IO_Level_20. The same applies to the usage rate levels of the IO Bank. The usage rate range of the block random access memory is also evenly divided into 20 levels, corresponding to the usage rate levels (i.e., configuration options) BlockRAM_Level_1 to BlockRAM_Level_20 respectively. The usage rate range of the digital processing module is also evenly divided into 20 levels, corresponding to the usage rate levels DSP_Level_1 to DSP_Level_20 respectively.

[0108] On this basis, for each usage rate level of each type of resource, according to the proportion of each resource of this type of resource in the verification report, the total proportion of resources falling within this usage rate level is counted to obtain the coverage value of this usage rate level. Furthermore, if the coverage value of a certain usage rate level of a certain type of resource is zero, it means that this usage rate level is not covered by verification; otherwise, it means that this usage rate level is covered by verification. Therefore, the usage rate levels with a coverage value of zero among various types of resources are used as uncovered items.

[0109] Step 153, when the maximum clock frequency in the verification report is less than the maximum clock frequency of the target device, generate an uncovered item corresponding to the maximum clock frequency.

[0110] The uncovered item corresponding to the maximum clock frequency can only include the flag of the clock frequency, or can also include the flag of the clock frequency, as well as the verification cases corresponding to the maximum clock frequency in the verification report, the number of clocks, and the logic levels.

[0111] Step 155, synthesize each uncovered item to obtain the configuration information to be configured for the target device.

[0112] When there is no uncovered item, the configuration information to be configured is empty. When there is an uncovered item, the configuration information to be configured includes the usage rate levels of various types of resources that are not covered by verification and / or the maximum clock frequency.

[0113] It should be noted that the various types of resources and timings mentioned above are only examples. In actual applications, there may be more or fewer levels, resources, and timings to be verified for coverage.

[0114] Through the above steps 151 to 155, analyze the usage of various resources (logic, registers, IO, IO Bank, digital processing modules), maximum clock frequency, etc. in the verification case layout during the timing in the verification report by means of one-by-one comparison, and perform relevant configurations according to the analysis results to avoid missing information and make the information to be configured more accurate.

[0115] It should be understood that the non-empty information to be configured means that there are scenarios that have not been verified. In the case where the information to be configured is non-empty, the information to be configured is used for feedback to automatically generate verification cases corresponding to the information to be configured in step 19, that is, to specifically generate verification cases with each uncovered item in the information to be configured.

[0116] In step 19, new verification cases can be generated in any implementable manner. For example, for each uncovered item, one configured option that has been verified can be selected from each of the other types of resources and combined with the uncovered item to form a new verification case. New verification cases can also be generated according to other preset rules.

[0117] In order to make the new batch group to be tested contain verification cases for all verification scenarios and improve verification efficiency, during the process of generating new verification cases in step 19, an uncovered item of the maximum clock frequency is introduced to independently generate new verification cases, and the uncovered items of various resources are first traversed and combined for different types of resource uncovered items, and then combined with the configured options that have been verified for the remaining types of resources to form the concept of new verification cases.

[0118] When the information to be configured only includes the uncovered item of the maximum clock frequency, the verification cases corresponding to the maximum clock frequency in each layout and routing result are used as the benchmark cases, and based on the benchmark cases, new verification cases are obtained.

[0119] When the information to be configured only includes the uncovered items of various resources, the uncovered items of various resources are traversed and combined to obtain new verification cases.

[0120] When the information to be configured includes the uncovered item of the maximum clock frequency and the uncovered items of various resources, the process of generating new verification cases is a combination of the above two situations. That is, the uncovered items of various resources are traversed and combined to obtain new verification cases corresponding to the maximum clock frequency, and the verification cases corresponding to the maximum clock frequency in each layout and routing result are used as the benchmark cases, and based on the benchmark cases, new verification cases corresponding to each resource type are obtained.

[0121] By first combining the uncovered items of various types of resources and then combining them with the verified covered options of the missing resources to generate new verification cases, a new verification case can contain multiple uncovered items. Compared with the method where a verification case only contains one uncovered item, the number of new verification cases is greatly reduced. Thus, the number of cases for the new round of placement and routing verification is reduced, and further, the verification time and resource consumption are reduced, greatly improving the verification efficiency.

[0122] In addition, when including the uncovered item with the maximum clock frequency, the verification case corresponding to the maximum clock frequency in each placement and routing result is used as the reference case to generate new verification cases. This enables the maximum clock frequency of the new verification cases to reach the maximum clock frequency of the target device as quickly as possible, thus avoiding the situation where the coverage target of the maximum clock frequency of the target device is not achieved after multiple loops, and further improving the verification efficiency.

[0123] Specifically, when including the uncovered items of various types of resources, first traverse and combine the uncovered items of different types of resources to obtain multiple intermediate cases. Then, for each intermediate case, determine the missing resources of the intermediate case, randomly select one verified covered configuration option for each missing resource, and combine the intermediate case with the selected configuration options to obtain a new verification case.

[0124] Taking the uncovered items of the to-be-configured information (i.e., the optional configuration options) including Logic_Level_1 to Logic_Level_20 of the logic resources, Register_Level_1 to Register_Level_20 of the register resources, IO_Level_1 to IO_Level_20 of the IO resources, BlockRAM_Level_1 to BlockRAM_Level_20 of the Block RAM, and DSP_Level_1 to DSP_Level_20 of the DSP resources as an example.

[0125] During the process of generating new verification cases, the uncovered items of the logic resources, register resources, IO resources, Block RAM resources, and DSP resources will be traversed and case combinations will be generated. First, starting from the uncovered items of the logic resources, fix the selected option of the logic resources as Logic_Level_1, and the uncovered items of the other register resources, IO resources, Block RAM resources, and DSP resources are traversed one by one from none, Level_1 to Level_20 to obtain some new verification cases. Then, the uncovered items of the logic resources are incremented in sequence until Logic_Level_20, and the uncovered items of the other resources are traversed from none, Level_1 to Level_20.

[0126] Next, fix the uncovered items of the register resources, and traverse the uncovered items of other resources from none, Level_1 to Level_20 one by one until the uncovered items of the register resources increase to Register_Level_20. Third, fix the uncovered items of the IO resources, and traverse the uncovered items of other resources from none, Level_1 to Level_20 until the uncovered items of the IO resources increase to Register_Level_20. Fourth, fix the uncovered items of the Block RAM resources, and traverse the uncovered items of other resources from none, Level_1 to Level_20 one by one until the uncovered items of the Block RAM resources increase to BlockRAM_Level_20. Fifth, fix the uncovered items of the DSP resources, and traverse the uncovered items of other resources from none, Level_1 to Level_20 one by one until the configuration options of the DSP resources increase to DSP_Level_20. Determine whether the case combination already exists. If not, generate the cases corresponding to the combination.

[0127] In addition, in order to quickly cover the scenario of the maximum clock frequency of the target device with the verification cases, the process of generating new verification cases corresponding to the maximum clock frequency can be as follows: lower the logic level of the reference case, and use the reference case with the lowered logic level as the new verification case.

[0128] Among them, the frequency difference between the maximum clock frequency of the reference case and the maximum clock frequency of the target device can be calculated, and then the difference corresponding to the frequency difference can be calculated by using a preset logic level and frequency conversion formula. According to this difference, lower the logic level of the reference case, that is, obtain the new verification case.

[0129] By generating new verification cases in the above manner, not only can the amount of new verification cases be reduced, but also the verification cases can quickly cover the entire verification scenario. At the same time, the way of generating cases is efficient and fast, and the case coverage is high. Thus, the efficiency of the placement and routing process is improved, which helps to improve the quality and reliability of FPGA products.

[0130] Based on the same concept as the above placement and routing process verification method, referring to Figure 7 , the embodiment of the present invention also provides a placement and routing process verification device 30, which can be applied to Figure 1 the verification device 110 shown in the figure. The placement and routing process verification device 30 includes a placement and routing module 310, a report generation module 320, a report analysis module 330, a judgment module 340, and a case generation module 350.

[0131] The placement and routing module 310 is used to input each verification case in the batch group to be tested into the target device respectively, so as to perform placement and routing on each verification case respectively, and obtain the placement and routing results of each verification case.

[0132] Among them, the verification case implements a function of the target device.

[0133] The report generation module 320 is configured to generate a verification report for the target device according to the placement and routing result.

[0134] The report analysis module 330 is configured to generate the information to be configured for the target device according to the verification report.

[0135] The judgment module 340 is configured to judge whether the information to be configured is empty.

[0136] The case generation module 350 is configured to, when the information to be configured is not empty, generate new verification cases according to the information to be configured, use the new verification cases and the original verification cases as a new batch of cases to be tested, and instruct the placement and routing module 310 to input each verification case in the new batch of cases to be tested into the target device respectively, so as to perform placement and routing on each verification case respectively to obtain the placement and routing result of each verification case.

[0137] Under the collaborative action of the above-mentioned placement and routing process verification device 30, the placement and routing module 310, the report generation module 320, the report analysis module 330, the judgment module 340 and the case generation module 350, the placement and routing of batch cases are automatically performed, a verification report is generated, the verification report is analyzed to confirm whether all verification scenarios are covered, new verification cases for the information to be configured are regenerated according to the information to be configured, and the verification process is performed again, avoiding omission of verification scenarios, ensuring that the placement and routing verification process can cover all verification scenarios of each device. At the same time, new verification cases that have not been verified are automatically, quickly and accurately generated, without the need for technicians to check one by one and then manually configure, reducing the time consumption, reducing the verification complexity, and greatly improving the verification efficiency.

[0138] For the specific implementation and effects of the placement and routing process verification device 30, reference can be made to the description of the implementation of the placement and routing process verification method in the above text. For example, for the specific implementation and effects of the placement and routing module 310, reference can be made to the description of the relevant content in step 11 in the above text; for the specific implementation and effects of the report generation module 320, reference can be made to the description of the relevant content in step 13 in the above text; for the specific implementation and effects of the report analysis module 330, reference can be made to the description of the relevant content in step 15 in the above text; for the specific implementation and effects of the judgment module 340, reference can be made to the description of the relevant content in step 17 in the above text; for the specific implementation and effects of the case generation module 350, reference can be made to the description of the relevant content in step 19 in the above text, which will not be elaborated here.

[0139] In addition, each module of the above layout and routing process verification device 30 can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in or independent of the processor 220 in the electronic device 20 in the form of hardware, or stored in the memory 210 of the electronic device 20 in the form of software, so that the processor 220 can call and execute the operations corresponding to each of the above modules to implement the layout and routing process verification method provided above.

[0140] An embodiment of the present invention also provides an electronic device 20, including a processor 220 and a memory 210. The memory 210 stores a computer program that can be executed by the processor 220. The processor 220 can execute the computer program to implement the layout and routing process verification method proposed in the embodiment of the present invention.

[0141] An embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by the processor 220, it implements the layout and routing process verification method proposed in the embodiment of the present invention.

[0142] In summary, the layout and routing process verification method, device, electronic device, and storage medium provided by the embodiments of the present invention have at least the following beneficial effects:

[0143] (1) Clearly obtain the resource usage of the verification case through the verification report, and eliminate error information through the functional simulation results of the simulation file generated by layout and routing, making the layout and routing process verification more well-founded and credible;

[0144] (2) Configure new verification cases by traversing the uncovered items, improving the efficiency, controllability of case generation, and coverage of the layout and routing process verification, and ensuring the process quality of FPGA products;

[0145] (3) Automatically and efficiently generate new verification cases, avoiding the inefficiency of manually writing verification cases, improving the verification speed of FPGA products, and reducing the operation complexity of verification.

[0146] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than that marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, as well as the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0147] In addition, in each embodiment of the present invention, the functional modules can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0148] If the described functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories, random access memories, magnetic disks, or optical discs that can store program codes.

[0149] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A layout and routing process verification method, characterized in that: The method comprises: Inputting each verification case in the batch group to be tested into the target device respectively, so as to perform layout and routing on each verification case respectively, and obtain the layout and routing result of each verification case; Generating a verification report of the target device according to the layout and routing results; Generating information to be configured for the target device according to the verification report; Determine whether the information to be configured is empty; If not, a new verification case is generated according to the information to be configured, and the new verification case and the original verification case are used as a new batch group to be tested, and the step of inputting each verification case in the batch group to be tested into the target device respectively is returned to execute, so as to perform layout and routing on each verification case respectively, and obtain the layout and routing results of each verification case.

2. The layout and routing process verification method according to claim 1, characterized in that: The layout and routing results include various resources and clock information used in the verification case; The step of generating a verification report of the target device according to the layout and routing result includes: Preprocessing each of the layout and routing results to eliminate erroneous layout and routing results; Obtaining resource proportions of various resources in the verification case according to the number of used resources of various resources in the remaining layout and routing results and the total number of various resources of the target device; Obtaining a maximum clock frequency from the clock information of the remaining placement and routing results; The resource proportions of various types of resources and the maximum clock frequency are comprehensively considered to obtain a verification report of the target device.

3. The layout and routing process verification method according to claim 2, characterized in that: The layout and routing results also include simulation files for verification cases; The step of preprocessing each of the layout and routing results to eliminate erroneous layout and routing results includes: For each of the verification cases, extracting a verification performance value from the layout and routing result of the verification case, and simulating a simulation file in the layout and routing result to obtain an implementation function of the verification case after layout and routing; According to the verification performance value and the implemented function, obtaining, from each of the verification cases, an error case in which the layout and routing does not achieve the expected result; The layout and routing results of the error case are eliminated, and error warning information of the error case is issued.

4. The layout and routing process verification method according to any one of claims 1 to 3, characterized in that: The verification report includes resource proportions and maximum clock frequencies of various resources in the verification case; The step of generating the information to be configured of the target device according to the verification report comprises: According to the resource proportions of each type of resources, uncovered items are determined from the utilization rate levels of each type of resources; wherein each of the utilization rate levels corresponds to a resource utilization rate interval; In a case where the maximum clock frequency in the verification report is less than the maximum clock frequency of the target device, generating an uncovered item corresponding to the maximum clock frequency; The uncovered items are combined to obtain the to-be-configured information of the target device.

5. The layout and routing process verification method according to claim 4, characterized in that: The step of determining uncovered items from the utilization rate levels of various types of resources based on the resource proportions of various types of resources includes: For each utilization rate level of each type of resource, according to the resource ratios of each type of resource, the total number of resource ratios falling within the utilization rate level is counted to obtain a coverage value of the utilization rate level; The usage level in each resource category with a coverage value of zero is regarded as an uncovered item.

6. The layout and routing process verification method according to claim 1, characterized in that: The step of generating a new verification case according to the information to be configured includes: When the information to be configured includes only the uncovered item of the maximum clock frequency, the verification case corresponding to the maximum clock frequency in each of the placement and routing results is used as a reference case, and a new verification case is obtained based on the reference case; When the information to be configured only includes uncovered items of various types of resources, traverse and combine the uncovered items of various types of resources to obtain new verification cases; When the information to be configured includes the maximum clock frequency and uncovered items of various types of resources, the uncovered items of various types of resources are traversed and combined to obtain a new verification case, and the verification case corresponding to the maximum clock frequency in each layout and routing result is used as a benchmark case, and a new verification case is obtained based on the benchmark case.

7. The layout and routing process verification method according to claim 6, characterized in that: The step of obtaining a new verification case based on the benchmark case includes: The logic level of the reference case is lowered, and the reference case with the lowered logic level is used as a new verification case.

8. A layout and routing process verification device, characterized in that: It includes layout and routing module, report generation module, report analysis module, judgment module and case generation module; The layout and routing module is used to input each verification case in the batch group to be tested into the target device respectively, so as to perform layout and routing on each verification case respectively, and obtain the layout and routing result of each verification case; The report generation module is used to generate a verification report of the target device according to the layout and routing results; The report analysis module is used to generate the to-be-configured information of the target device according to the verification report; The judging module is used to judge whether the information to be configured is empty; The case generation module is used to generate a new verification case according to the information to be configured when the information to be configured is not empty, use the new verification case and the original verification case as a new batch group to be tested, and instruct the layout and routing module to input each verification case in the new batch group to be tested into the target device respectively, so as to perform layout and routing on each verification case respectively, and obtain the layout and routing result of each verification case.

9. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores a computer program executable by the processor, and the processor can execute the computer program to implement the layout and routing process verification method according to any one of claims 1 to 7.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the layout and routing process verification method according to any one of claims 1 to 7 is implemented.

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