Phase-locked loop circuit adopting current calibration and calibration method

Abstract

The invention discloses a phase-locked loop circuit adopting current calibration and a calibration method, and relates to the technical field of phase-locked loop circuits. According to the calibration method, a calibration signal is adjusted, and then the current of a current source array is changed according to the target output frequency of a flow-controlled oscillator, so that the tuning range of the flow-controlled oscillator is close to the target output frequency; according to the phase-locked loop circuit, a current source array and a flow-controlled oscillator are introduced, and after calibration is conducted through the current calibration method, the phase-locked loop circuit divides the frequency required by a target into superposition of a plurality of intervals with small tuning ranges by adjusting the magnitude of the current, so that the frequency required by the target is obtained. On the premise that a large-range clock frequency change range is guaranteed, it is guaranteed that the KVCO is a small value, and the stability and noise performance of the phase-locked loop circuit are guaranteed.

Description

Technical Field

[0001] The present invention relates to the technical field of phase-locked loop circuits, and particularly relates to a phase-locked loop circuit and a calibration method using current calibration. Background Art

[0002] The relationship between the double data rate physical layer interface (DDR PHY) and the phase-locked loop (PLL) circuit is inseparable. The PLL is the core module for the DDR PHY to achieve high-speed and stable data transmission. The phase-locked loop circuit is mainly responsible for generating and calibrating high-frequency clock signals to ensure strict synchronization of data and clock.

[0003] The double data rate memory controller module DDR IP has a large demand for the output clock frequency range. Currently, the Solid State Technology Association (JEDEC) standard stipulates that the variation range of the clock frequency is 200Mhz to 5Ghz. The variation range of the clock frequency is affected by two aspects: the voltage range output by the charge pump and KVCO (the ratio of the change in the output frequency of the voltage-controlled oscillator VCO to the change in the control voltage). Because the voltage range output by the charge pump is limited, in the traditional circuit structure, the value of KVCO is often large. The problem of a large KVCO value usually leads to: an increase in the sensitivity of the voltage-controlled oscillator VCO to input noise, affecting the noise performance of the PLL; an increase in the requirement for the CP output voltage range, resulting in a charge and discharge current mismatch of the CP; the inability to guarantee the KVCO linearity, affecting the PLL noise performance and loop stability. In view of this problem, it is necessary to develop and design a new phase-locked loop circuit structure. Summary of the Invention

[0004] The object of the present invention is to provide a phase-locked loop circuit and a calibration method using current calibration. On the one hand, the present invention provides a calibration method for a phase-locked loop circuit using current calibration, which is applied before the phase-locked loop circuit starts to work to perform circuit calibration on the phase-locked loop circuit. This method adjusts the value of the calibration signal K_CODE_B<5:0>, changes the current magnitude of the current source array (IBAND) according to the target output frequency of the current-controlled oscillator (ICO), and performs current calibration, finally making the tuning range of the current-controlled oscillator (ICO) near the target output frequency of the PLL circuit. Thus, it ensures that the phase-locked loop PLL circuit locks the clock signal in the optimal working state and improves the working efficiency of the phase-locked loop circuit; on the other hand, the present invention provides a phase-locked loop circuit using current calibration. This phase-locked loop circuit introduces a current source array (IBAND) and a current-controlled oscillator (ICO) in its structure. By adjusting the magnitude of the current, the relatively large VCO frequency range defined by the Joint Electron Device Engineering Council (JEDEC) standard can be divided into the superposition of multiple intervals with smaller tuning ranges, realizing the guarantee of a smaller value of KVCO on the premise of meeting the change range of the output clock frequency. It ensures the stability and noise performance of the phase-locked loop (PLL) circuit.

[0005] The object of the present invention is achieved by the following technical means: In the first aspect, the present invention provides a phase-locked loop circuit using current calibration. The phase-locked loop (PLL) circuit includes: a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a current source array (IBAND), a current-controlled oscillator (ICO), and a frequency divider (DIV).

[0006] The phase frequency detector (PFD) is mainly used to compare the rising edge (or falling edge) of the reference clock (REF_CLK) and the feedback clock (FBK_CLK), detect the phase difference and frequency difference between the two, and output two digital pulse signals UP and DN, the pulse width of which is proportional to the phase and frequency differences between the two.

[0007] The charge pump (CP) is mainly used to convert the UP / DN digital pulses of the phase frequency detector (PFD) into analog current (or voltage). When it is the UP signal, it injects current (or voltage) into the loop filter; when it is the DN signal, it extracts current (or voltage) from the filter to drive the low-pass filter (LPF).

[0008] The low-pass filter (LPF) is arranged between the output end of the charge pump (CP) and the input end of the current source array (IBAND), and is used to filter out the high-frequency noise in the output current of the charge pump (CP), smooth the high-frequency ripple output by the charge pump (CP), generate the voltage Vlpf, and control the current flowing through the resistor Ri; The described current source array (IBAND) is arranged between the output end of the low-pass filter (LPF) and the input end of the current-controlled oscillator (ICO), and is used to provide a programmable current source, realize the dynamic adjustment of current parameters, copy the current passing through the resistor Ri in the low-pass filter (LPF), and control the output of the current-controlled oscillator (ICO). The described current-controlled oscillator (ICO) is arranged between the output end of the current source array (IBAND) and the input end of the frequency divider (DIV), and outputs a clock signal that meets the expected frequency and phase according to the current magnitude. The described frequency divider (DIV) is arranged after the current-controlled oscillator (ICO) and connected to the phase frequency detector (PFD), and is used to divide the frequency of the clock signal output by the current-controlled oscillator (ICO), and output the feedback clock signal FBK_CLK to the phase frequency detector (PFD) to complete the closed loop of the circuit.

[0009] Compared with the traditional PLL circuit structure, the above PLL circuit introduces a current source array (IBAND) and a current-controlled oscillator (ICO). The PLL circuit combines the low-pass filter (LPF) with the current source array (IBAND), and based on the structure of the current-controlled oscillator (ICO), thereby realizing that in the PLL circuit, by adjusting the current magnitude, the current is divided into the superposition of multiple intervals with smaller tuning ranges, and a large frequency change range is realized on the premise of ensuring a small KVCO, ensuring the stability and noise performance of the PLL circuit.

[0010] The working principle of the improved PLL circuit is as follows: The phase frequency detector (PFD) generates signals UP and DN that control the charge pump (CP) to charge and discharge by comparing the frequency and phase difference between the reference clock (REF_CLK) and the feedback clock (FBK_CLK). The output voltage CP_OUT of the CP controls the current magnitude of the current source array (IBAND) after passing through the low-pass filter (LPF), and then the controlled oscillator (ICO) outputs a clock that meets the expected frequency and phase according to the current magnitude.

[0011] Furthermore, in the working principle of the above PLL circuit, the more specific working processes of the low-pass filter (LPF), the control current source array (IBAND), and the current-controlled oscillator (ICO) parts are as follows: The output voltage CP_OUT of the charge pump (CP) is output to the positive input terminal of the active filter in the low-pass filter (LPF). After feedback, a voltage Vlpf is generated, which further controls the current flowing through Ri in the low-pass filter (LPF) circuit section. Then, under the action of the operational amplifier OP-Amp in the sub-structure of the active filter OP, a voltage Vctrl is generated, which further controls the current source array (IBAND) to copy the current passing through Ri (where the value of Ri and the ratio (KICO) of the output frequency change amount of ICO to the control current change amount determine the magnitude of PLL KVCO. Based on this relationship, the magnitude of the above current is adjusted, and the frequency range is divided into the superposition of multiple smaller tuning ranges, so as to ensure a smaller KVCO value on the premise of achieving a large frequency change range). Finally, the current-controlled oscillator (ICO) outputs a clock that meets the desired frequency and phase according to the current magnitude.

[0012] Before the above-mentioned phase-locked loop circuit (PLL) starts to work, it needs to perform current calibration using the current calibration method described in the present invention.

[0013] In a second aspect, the present invention provides a calibration method for a phase-locked loop circuit using current calibration, which is applied to the above-mentioned phase-locked loop (PLL) circuit.

[0014] The purpose of the current calibration method is to modulate the current magnitude of the current source array (IBAND) according to the target output frequency of the current-controlled oscillator (ICO), so that the tuning range of the current-controlled oscillator (ICO) is near the target output frequency. Ensure that the phase-locked loop PLL circuit locks the clock signal in an optimal working state, thereby improving the working efficiency of the phase-locked loop circuit.

[0015] The control code (code) for modulating the current magnitude of the current source array (IBAND) is the calibration signal K_CODE_B<5:0>.

[0016] The calibration signal K_CODE_B<5:0> is a 6-bit binary code (code). The larger the code (code), the smaller the current of the current source array (IBAND); the smaller the code, the larger the current of the current source array (IBAND).

[0017] The calibration signal K_CODE_B<5:0> needs to be converted into a 63-bit thermometer code K_CODE<62:0> by a decoder according to the decoding rule during operation.

[0018] The process principle of the described current calibration method is as follows: First, close the switch SW1 (switch SW1 is a working switch in the low-pass filter (LPF) part of the circuit), and then set the calibration signal K_CODE_B<5:0> to an intermediate gear. The purpose is to make the current-controlled oscillator (ICO) work at an intermediate frequency. Set the division coefficient of the frequency divider (DIV) according to the target frequency of the phase-locked loop (PLL) circuit. Then, compare the frequencies of the reference clock (REF_CLK) and the feedback clock (FBK_CLK) to obtain the comparison result KBAND_UP. If the frequency of the reference clock (FBK_CLK) is higher, then the comparison result KBAND_UP = 1 (when the reference clock frequency is higher, the calibration signal K_CODE_B<5:0> needs to be increased to reduce the frequency). At this time, the calibration signal K_CODE_B<5:0> is incremented by 1, and the operation is repeated until KBAND_UP = 0. At this time, KBAND_UP undergoes a transition, indicating that the magnitude relationship between the frequencies of the reference clock (REF_CLK) and the feedback clock (FBK_CLK) has changed. Use the calibration signal K_CODE_B<5:0> at this moment as the final result of calibration. If the frequency of the feedback clock (FBK_CLK) is lower, then KBAND_UP = 0 (when the reference clock frequency is lower, the calibration signal K_CODE_B<5:0> needs to be decreased to increase the frequency). At this time, the calibration signal K_CODE_B<5:0> is decremented by 1 until KBAND_UP = 1. Use the calibration signal K_CODE_B<5:0> at this time as the final result of calibration. The larger the calibration signal K_CODE_B<5:0>, the smaller the current of the current source array (IBAND); the smaller the calibration signal K_CODE_B<5:0>, the larger the current of the current source array (IBAND). Complete the current calibration based on the final result of the calibration signal K_CODE_B<5:0>.

[0019] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention designs a current calibration method for a phase-locked loop (PLL) circuit, enabling the adjustment of the magnitude of the current of the current source array by adjusting the value of the calibration signal K_CODE_B<5:0> according to the target output frequency of the current-controlled oscillator, so that the tuning range of the current-controlled oscillator is near the target output frequency of the phase-locked loop circuit, ensuring that the phase-locked loop circuit locks the clock signal in an optimal working state and improving the working efficiency of the phase-locked loop circuit.

[0020] The present invention adopts a novel phase-locked loop circuit with current calibration. For the relatively large VCO frequency range defined by the JEDEC standard, by adjusting the magnitude of the current, this frequency range can be divided into the superposition of multiple intervals with smaller tuning ranges, so as to ensure that KVCO is a smaller value under the requirement of a large clock frequency change range. This reduces the requirement for the voltage range of the CP output by the phase-locked loop PLL circuit; it ensures excellent KVCO linearity, which is beneficial to the loop stability of the PLL; and it improves the anti-interference ability of the phase-locked loop circuit PLL to external noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and form a part of this specification, indicating the embodiments in line with the present invention, and are used together with the specification to explain the principles of the present invention.

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0023] Figure 1 It is a structural diagram of a phase-locked loop PLL circuit adopting a current calibration method provided for this embodiment; Figure 2 It is a specific circuit structural diagram of a low-pass filter LPF + current source array IBAND provided for this embodiment; Figure 3 It is a current calibration flow chart provided for this embodiment; Figure 4 It is a schematic diagram of the decoding rule of the calibration signal K_CODE_B<5:0> provided for this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0025] It should be noted that all directional indications (such as up, down, left, right, front, back...) in the embodiments of the present invention are only used to explain the relative position relationship and movement conditions between components in a specific posture. If this specific posture changes, the directional indications will also change accordingly.

[0026] In addition, the descriptions involving "first", "second", etc. in the present invention are for descriptive purposes only, and should not be construed as indicating or implying their relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions between various embodiments may be combined with each other, but it must be based on the fact that those of ordinary skill in the art can implement them. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0027] Embodiment 1 This embodiment provides a phase-locked loop circuit using current calibration, as Figure 1 shown. The phase-locked loop circuit specifically includes: a phase frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a current source array (IBAND), a current-controlled oscillator (ICO), and a frequency divider (DIV).

[0028] The phase frequency detector (PFD) is mainly used to compare the rising edge (or falling edge) of the reference clock (REF_CLK) and the feedback clock (FBK_CLK), detect the phase difference and frequency difference between the two, and output two digital pulse signals UP and DN, the pulse widths of which are proportional to the phase and frequency differences between the two.

[0029] The charge pump (CP) is mainly used to convert the output UP / DN digital pulse signal of the phase frequency detector (PFD) into an analog current (or voltage). When it is the UP signal, it injects current (or voltage) into the loop filter; when it is the DN signal, it extracts current (or voltage) from the filter to drive the low-pass filter (LPF).

[0030] The low-pass filter (LPF) is arranged between the output end of the charge pump (CP) and the input end of the current source array (IBAND), and is used to filter out the high-frequency noise in the output current of the charge pump (CP), smooth the high-frequency ripple output by the charge pump (CP), generate a voltage Vlpf, and control the current flowing through the resistor Ri; The current source array (IBAND) is arranged between the output end of the low-pass filter (LPF) and the input end of the current-controlled oscillator (ICO), and is used to provide a programmable current source, realize the dynamic adjustment of current parameters, copy the current passing through the resistor Ri in the low-pass filter (LPF), and regulate the output of the current-controlled oscillator (ICO); The current-controlled oscillator (ICO) is arranged between the output end of the current source array (IBAND) and the input end of the frequency divider (DIV), and outputs a clock signal that meets the desired frequency and phase according to the current magnitude; The frequency divider (DIV) is arranged after the current-controlled oscillator (ICO) and connected to the phase-frequency detector (PFD), and is used to divide the clock signal output by the current-controlled oscillator (ICO), and output the feedback clock signal FBK_CLK to the phase-frequency detector (PFD) to complete the closed-loop of the circuit.

[0031] The specific working steps of the phase-locked loop circuit after current calibration by the current calibration method provided by the present invention are as follows: S1: The phase-frequency detector (PFD) generates signals UP and DN for controlling the charge and discharge of the charge pump (CP) by comparing the frequency and phase difference between the reference clock REF_CLK and the feedback clock FBK_CLK; S2: The charge pump (CP) outputs the voltage CP_OUT after receiving the charge and discharge signals UP and DN output by the phase-frequency detector (PFD); S3: CP_OUT controls the current magnitude of the current source array (IBAND) after passing through the low-pass filter (LPF); S4: The current-controlled oscillator (ICO) outputs a clock signal that meets the desired frequency and phase of the circuit according to the current magnitude of the current source array (IBAND).

[0032] Furthermore, as Figure 2 shown, the more specific working process principle of step S3 is as follows: S3-1: The output voltage CP_OUT of the charge pump (CP) is output to the positive input terminal of the active filter OP, and after feedback, the voltage Vlpf is generated; S3-2: The voltage Vlpf generated by feedback is used to control the current flowing through the resistor Ri of the low-pass filter (LPF) sub-structure; S3-3: The voltage Vctrl is generated under the action of the sub-structure operational amplifier (OP-Amp) of the active filter (OP); S3-4: The generated voltage Vctrl is used to control the current source array (IBAND) to copy the current passing through the resistor Ri to complete the final current control process.

[0033] When the phase-locked loop (PLL) circuit is working, Figure 1 As shown, the VREF input to the low-pass filter (LPF) + current source array (IBAND) part is the power supply voltage, and the preferred value is VDD / 2. The other input calibration signal K_CODE_B<5:0> is generated by the current calibration method provided by the present invention, and after decoding, a 63-bit thermometer code K_CODE<62:0> is generated for controlling the current magnitude of the IBAND.

[0034] It should be noted that the value of Ri and the ratio (KICO) of the change in the output frequency of the injection - controlled oscillator (ICO) to the change in the control current determine the magnitude of the PLL KVCO. Based on this relationship, by adjusting the magnitude of the current, the frequency can be divided into the superposition of multiple intervals with smaller tuning ranges. Under the condition of achieving a large frequency change range, the KVCO can be ensured to be a smaller value. This reduces the requirement for the voltage range of the output of the charge pump (CP) in the phase - locked loop PLL circuit; it ensures excellent linearity of the KVCO, which is beneficial to the stability of the PLL loop; and it improves the anti - interference ability of the phase - locked loop circuit PLL to external noise.

[0035] Embodiment 2 This embodiment provides a calibration method for a phase - locked loop circuit using current calibration, which is applied to the above - mentioned phase - locked loop circuit to perform current calibration on the current source array (IBAND).

[0036] The working principle is as follows: The calibration signal K_CODE_B<5:0> is used as the code of the current source array (IBAND). The larger the calibration signal K_CODE_B<5:0>, the smaller the current of the current source array (IBAND); the smaller the calibration signal K_CODE_B<5:0>, the larger the current of the current source array (IBAND). The frequencies of the reference clock REF_CLK and the feedback clock FBK_CLK are compared to obtain the comparison result KBAND_UP. If the frequency of FBK_CLK is higher, then KBAND_UP = 1, and the code needs to be increased to reduce the frequency; if the frequency of FBK_CLK is lower, then KBAND_UP = 0, and the code needs to be decreased to reduce the frequency. Finally, the frequencies of REF_CLK and FBK_CLK are made close. Preferably, the frequency of the feedback clock REF_CLK is a fixed 50Mhz.

[0037] As Figure 3 described, the specific calibration process is as follows: A1: Set the calibration signal K_CODE_B<5:0> to the middle gear. In this embodiment, the middle gear is set to the calibration signal K_CODE_B<5:0>=110000, so that the calibration signal K_CODE_B<5:0> works at an intermediate frequency.

[0038] A2: According to the target frequency of the phase - locked loop circuit, set the division ratio of the frequency divider (DIV). Preferably, the division ratio is the target frequency / 50Mhz.

[0039] A3: Compare the frequencies of the reference clock REF_CLK and the feedback clock FBK_CLK. If the frequency of the feedback clock FBK_CLK is higher, then KBAND_UP = 1; if the frequency of the feedback clock FBK_CLK is lower, then KBAND_UP = 0.

[0040] A4: When the comparison result KBAND_UP = 1, the calibration signal K_CODE_B<5:0> is incremented by 1 and the operation is repeated until KBAND_UP = 0. At this time, a transition occurs in KBAND_UP, indicating that the frequency relationship between the reference clock REF_CLK and the feedback clock FBK_CLK has changed. The calibration signal K_CODE_B<5:0> at this time is used as the final calibration result to complete the calibration. If the comparison result KBAND_UP = 0, the calibration signal K_CODE_B<5:0> is decremented by 1 and the operation is repeated until KBAND_UP = 1 and a transition occurs in KBAND_UP. At this time, it indicates that the frequency relationship between the reference clock REF_CLK and the feedback clock FBK_CLK has changed, and the calibration signal K_CODE_B<5:0> at this time is used as the final calibration result. The larger the calibration signal K_CODE_B<5:0>, the smaller the current of the current source array (IBAND); the smaller the calibration signal K_CODE_B<5:0>, the larger the current of the current source array (IBAND). The current calibration work is completed based on the final result of the calibration signal K_CODE_B<5:0>.

[0041] This calibration method can adjust the current magnitude of the current source array (IBAND) according to the target output frequency of the current-controlled oscillator (ICO), so that the tuning range of the current-controlled oscillator (ICO) is near the target output frequency. It ensures that the phase-locked loop circuit locks the clock signal in an optimal working state, improving the working efficiency of the phase-locked loop circuit. After calibration is completed, the phase-locked loop PLL loop can start to intervene. The phase-frequency detector (PFD) detects the frequency and phase relationship between the reference clock REF_CLK and the feedback clock FBK_CLK, generates UP and DN signals to charge and discharge CP_OUT, completes the modulation of the current magnitude of the resistor Ri in the low-pass filter (LPF), and further controls the oscillation frequency of the controlled oscillator (ICO), so that the phase-locked loop PLL circuit reaches a stable state and outputs a clock signal with the target desired frequency and phase of the circuit to complete the final frequency locking.

[0042] Embodiment III As Figure 4 shown, this embodiment provides a decoding rule for the calibration signal K_CODE_B<5:0>, which is applied to the above current calibration method.

[0043] The calibration signal K_CODE_B<5:0> is a 6-bit binary control code, which is used to control the current magnitude of the current source array (IBAND) of the phase-locked loop PLL circuit during current calibration. The larger the calibration signal K_CODE_B<5:0>, the smaller the current of the current source array (IBAND) of the circuit.

[0044] K_CODE<62:0> is the 63-bit thermometer code, and K_CODE<62:0> is generated after decoding by the current calibration method provided by the present invention.

[0045] When performing current calibration work, the calibration signal K_CODE_B<5:0> is converted into a 63-bit thermometer code K_CODE<62:0> through a decoder according to the illustrated decoding rule. After conversion, it can ensure the linearity of current control, reduce transient errors, and ensure the monotonicity of current switching.

[0046] See Figure 1 、 Figure 2 and Figure 3 As shown, according to the above Embodiment 1, Embodiment 2, and Embodiment 3, the working process principle and usage flow of the entire current calibration and phase-locked loop PPL circuit of the present invention are as follows: First, perform current calibration: Close the switch SW1, set the calibration signal K_CODE_B<5:0> to the middle gear, let the current-controlled oscillator (ICO) work at an intermediate frequency, set the division factor of the frequency divider (DIV) according to the target frequency of the phase-locked loop PLL circuit, compare the frequencies of the reference clock REF_CLK and the feedback FBK_CLK, perform logical operations based on the comparison result KBAND_UP. When the comparison result KBAND_UP generates a jump, obtain the calibration result of the final calibration signal K_CODE_B<5:0>, and realize the calibration modulation of the current magnitude of the current source array (IBAND), so that the tuning range of the oscillator (ICO) is near the target output frequency of the phase-locked loop PLL circuit to complete the calibration task; When SW1 is disconnected, the phase-locked loop (PLL) circuit starts to work on its own: The phase-frequency detector (PFD) detects the frequency and phase relationship between the reference clock REF_CLK and the feedback clock FBK_CLK, generates UP and DN signals to charge and discharge the charge pump (CP). The charge pump (CP) outputs a voltage CP_OUT to the + terminal of the active filter OP in the low-pass filter (LPF) sub-structure. After feedback, a voltage Vlpf is generated. Then, the voltage Vlpf generated by feedback is used to control the current flowing through the resistor Ri in the low-pass filter (LPF) sub-structure. Subsequently, under the action of the operational amplifier (OP-Amp) in the active filter (OP) sub-structure, a voltage Vctrl is generated. The generated voltage Vctrl is used to control the current source array (IBAND) to copy the current passing through Ri. By controlling the magnitude of the current flowing through the resistor Ri (the value of Ri and the ratio of the output frequency change of the voltage-controlled oscillator (ICO) to the control current change (KICO) determine the magnitude of PLL KVCO. Based on this relationship, by adjusting the magnitude of the current, the frequency can be divided into the superposition of multiple intervals with smaller tuning ranges, ensuring that KVCO is a smaller value while achieving a large frequency change range), and then the oscillation frequency of the voltage-controlled oscillator (ICO) is controlled, so that the phase-locked loop (PLL) circuit reaches a stable state, outputs a clock signal with the target expected frequency and phase of the circuit, and completes the final frequency locking.

[0047] By using the above-mentioned current-calibrated phase-locked loop (PLL) circuit, the large voltage-controlled oscillator (VCO) frequency range defined by the Solid State Technology Association (JEDEC) standard can be divided into the superposition of multiple intervals with smaller tuning ranges by adjusting the magnitude of the current, so as to ensure that KVCO is a smaller value on the premise of ensuring a large clock frequency change range, and ensure the stability and noise performance of the PLL circuit.

[0048] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, any brief modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A phase-locked loop circuit using current calibration, characterized in that: Includes frequency detector, phase detector, charge pump, low pass filter, current source array, current controlled oscillator and frequency divider; The low-pass filter is arranged between the output end of the charge pump and the input end of the current source array, and is used to filter out the high-frequency noise in the output current of the charge pump, smooth the high-frequency ripple output by the charge pump, generate a voltage Vlpf, and control the current flowing through the resistor Ri; The current source array is arranged between the output end of the low-pass filter and the input end of the current-controlled oscillator, and is used to provide a programmable current source, realize dynamic adjustment of current parameters, copy the current passing through the resistor Ri in the low-pass filter, and regulate the output of the current-controlled oscillator; The current-controlled oscillator is arranged at the output end of the current source array and the input end of the frequency divider, and outputs a clock signal that meets the desired frequency and phase according to the current size; The phase frequency detector and the charge pump are the initial signal input ends of the circuit, and are subsequently connected to a low-pass filter; the input reference clock signal REF CLK is received by the phase frequency detector and fed back to the charge pump, and the output voltage CP_OUT of the charge pump regulates the low-pass filter and the current source array; The frequency divider is arranged after the current-controlled oscillator and connected to the frequency detector and phase detector, and is used to divide the frequency of the clock signal output by the current-controlled oscillator, and output the feedback clock signal FBK_CLK to the frequency detector and phase detector, thereby completing the closed loop of the circuit.

2. A phase-locked loop circuit using current calibration according to claim 1, characterized in that: When the phase-locked loop circuit is working, the low-pass filter inputs the power supply voltage signal VREF, and the current source array inputs the calibration signal K_CODE_B<5:0>.

3. A phase-locked loop circuit using current calibration according to claim 1, characterized in that: The low-pass filter is provided with a substructure active filter and an operational amplifier, the active filter is used to generate a voltage Vlpf, the operational amplifier is used to generate a voltage Vctrl, and the resistor Ri is replicated through a voltage-controlled current source array.

4. A calibration method for a phase-locked loop circuit using current calibration, applied to a phase-locked loop circuit using current calibration as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: A1: Set the calibration signal K_CODE_B<5:0> to the middle gear, so that the current-controlled oscillator works at a middle frequency; A2: Set the frequency divider factor according to the target frequency of the phase-locked loop circuit; A3: Compare the frequencies of the reference clock REF_CLK and the feedback clock FBK_CLK. If the frequency of the feedback clock FBK_CLK is higher, the comparison result KBAND_UP=1; if the frequency of the feedback clock FBK_CLK is lower, the comparison result KBAND_UP=0; A4: When the comparison result KBAND_UP=1, the calibration signal K_CODE_B<5:0>+1 is repeated until the comparison result KBAND_UP=0. The comparison result KBAND_UP jumps and the calibration signal K_CODE_B<5:0> is used as the final result of the calibration to complete the current calibration. When the comparison result KBAND_UP=0, the calibration signal K_CODE_B<5:0>-1 is repeated until the comparison result KBAND_UP=1. The calibration signal K_CODE_B<5:0> is used as the final result of the calibration to complete the current calibration.

5. A method for calibrating a phase-locked loop circuit using current calibration according to claim 4, characterized in that: The intermediate gear setting of the calibration signal K_CODE_B<5:0> and the frequency division coefficient setting of the frequency divider are both determined according to the target output frequency of the phase-locked loop.

6. The calibration method of a phase-locked loop circuit using current calibration according to claim 4, characterized in that: The calibration signal K_CODE_B<5:0> controls the closing and closing of the current switches of the current source array. The larger the calibration signal K_CODE_B<5:0> is, the smaller the current of the current source array is; the smaller the calibration signal K_CODE_B<5:0> is, the larger the current of the current source array is.

7. The calibration method of a phase-locked loop circuit using current calibration according to claim 4, characterized in that: The calibration signal K_CODE_B<5:0> is a 6-bit binary code. During current calibration, the calibration signal K_CODE_B<5:0> is converted into K_CODE<62:0> by a decoder according to a decoding rule.

8. The method for calibrating a phase-locked loop circuit using current calibration according to claim 7, characterized in that: The decoding rule is used to translate the 6-bit binary calibration signal K_CODE_B<5:0> into a 63-bit thermometer code K_CODE<62:0>.

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