A phase-locked loop circuit and a calibration method using current calibration

Abstract

The application discloses a phase-locked loop circuit and a calibration method thereof, and relates to the technical field of phase-locked loop circuits.The calibration method adjusts a calibration signal, and then changes the current size of a current source array according to a target output frequency of a current-controlled oscillator, so that the tuning range of the current-controlled oscillator is near the target output frequency.The phase-locked loop circuit introduces the current source array and the current-controlled oscillator, and after being calibrated by the above-mentioned current calibration method, the phase-locked loop circuit divides the target required frequency into the superposition of multiple intervals with small tuning ranges by adjusting the current size, so that the KVCO is ensured to be a small value on the premise of ensuring a large range of clock frequency variation, and the stability and noise performance of the phase-locked loop circuit are ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of phase-locked loop circuit, and particularly relates to a phase-locked loop circuit adopting current calibration and a calibration method. BACKGROUND

[0002] The double data rate physical layer interface (DDR PHY) is closely related to the phase-locked loop (PLL) circuit. The PLL is a core module for realizing high-speed and stable data transmission of the DDR PHY. The phase-locked loop circuit is mainly responsible for generating and calibrating a high-frequency clock signal to ensure strict synchronization between data and the clock.

[0003] The double data rate memory controller module DDR IP has a large demand for the output clock frequency range. At present, the standard of the Joint Electron Device Engineering Council (JEDEC) stipulates that the clock frequency range is 200 Mhz-5Ghz. The clock frequency range is affected by the voltage range of the charge pump output and KVCO (the ratio of the change amount of the VCO output frequency to the change amount of the control voltage). Because the voltage range of the charge pump output is limited, the value of KVCO is usually large under the traditional circuit structure. The problem of the large KVCO value usually leads to the following problems: the sensitivity of the VCO to the input noise increases, which affects the noise performance of the PLL; the CP output voltage range requirement increases, which leads to the charge and discharge current mismatch of the CP; the KVCO linearity cannot be guaranteed, which affects the noise performance and loop stability of the PLL. In view of the problem, it is necessary to develop and design a new type of phase-locked loop circuit structure. SUMMARY

[0004] The application aims to provide a phase-locked loop circuit and a calibration method thereof. The application provides a calibration method of a phase-locked loop circuit with current calibration, which is applied to circuit calibration of the phase-locked loop circuit before the phase-locked loop circuit starts to work. The method changes the current size of the current source array (IBAND) according to the target output frequency of the current-controlled oscillator (ICO) by adjusting the value of the calibration signal K_CODE_B<5:0>, and performs current calibration, so that the tuning range of the current-controlled oscillator (ICO) is near the target output frequency of the PLL circuit. Thus, the phase-locked loop PLL circuit can be locked with the optimal working state, and the working efficiency of the phase-locked loop circuit is improved. The application also provides a phase-locked loop circuit with current calibration. The phase-locked loop circuit introduces the current source array (IBAND) and the current-controlled oscillator (ICO) in structure, divides the larger VCO frequency range defined by the JEDEC standard into multiple smaller intervals by adjusting the current size, and realizes the smaller KVCO value under the premise of meeting the output clock frequency range. The stability and noise performance of the phase-locked loop (PLL) circuit are ensured.

[0005] The application is achieved by the following technology:

[0006] In the first aspect, the application provides a phase-locked loop circuit with current calibration, which comprises a phase-frequency detector (PFD), a charge pump (CP), a low-pass filter (LPF), a current source array (IBAND), a current-controlled oscillator (ICO) and a frequency divider (DIV).

[0007] The phase-frequency detector (PFD) is mainly used for comparing the rising edges (or falling edges) of a reference clock (REF_CLK) and a feedback clock (FBK_CLK), detecting the phase difference and frequency difference of the two, and outputting two digital pulse signals UP and DN, the pulse width of which is proportional to the phase difference and frequency difference of the two.

[0008] The charge pump (CP) is mainly used for converting the UP / DN digital pulse of the phase-frequency detector (PFD) into an analog current (or voltage), injecting the current (or voltage) into the loop filter when the UP signal is input, extracting the current (or voltage) from the filter when the DN signal is input, and driving the low-pass filter (LPF).

[0009] The low-pass filter (LPF) is arranged between the output end of the charge pump (CP) and the input end of the current source array (IBAND), and is used for filtering the high-frequency noise in the output current of the charge pump (CP), smoothing the high-frequency ripple output by the charge pump (CP), generating a voltage Vlpf, and controlling the current flowing through the resistor Ri.

[0010] The current source array (IBAND) is arranged between the output end of the low-pass filter (LPF) and the input end of the current-controlled oscillator (ICO), and is used to provide programmable current sources, realize dynamic adjustment of current parameters, copy the current passing through the resistor Ri in the low-pass filter (LPF), and regulate the output of the current-controlled oscillator (ICO).

[0011] The current-controlled oscillator (ICO) is arranged at the output end of the current source array (IBAND) and the input end of the frequency divider (DIV), and outputs a clock signal meeting the expected frequency and phase according to the current size.

[0012] The frequency divider (DIV) is arranged after the current-controlled oscillator (ICO) and is connected with the phase-frequency detector (PFD), and is used to divide the clock signal output by the current-controlled oscillator (ICO), output a feedback clock signal FBK_CLK to the phase-frequency detector (PFD), and complete the closed loop of the circuit.

[0013] Compared with the traditional PLL circuit structure, the above-mentioned phase-locked loop (PLL) circuit introduces the current source array (IBAND) and the current-controlled oscillator (ICO). The phase-locked loop (PLL) circuit is combined with the current source array (IBAND) through the low-pass filter (LPF) and is based on the structure of the current-controlled oscillator (ICO), so that the phase-locked loop (PLL) circuit is realized. By adjusting the size of the current, the current is divided into multiple intervals with small tuning ranges, the large frequency range is realized under the premise of ensuring the small KVCO, and the stability and noise performance of the PLL circuit are ensured.

[0014] The working principle of the improved phase-locked loop (PLL) circuit is as follows: the phase-frequency detector (PFD) compares the frequency and phase difference of the reference clock (REF_CLK) and the feedback clock (FBK_CLK), generates signals UP and DN for controlling the charging and discharging of the charge pump (CP), the output voltage CP_OUT of the CP controls the current size of the current source array (IBAND) after passing through the low-pass filter (LPF), and then the current-controlled oscillator (ICO) outputs a clock meeting the expected frequency and phase according to the current size.

[0015] Further, in the working principle of the above-mentioned phase-locked loop (PLL) circuit, the working process of the low-pass filter (LPF), the current source array (IBAND) and the current-controlled oscillator (ICO) is more specific as follows:

[0016] The charge pump (CP) outputs a voltage CP_OUT to a positive input terminal of an active filter in a low pass filter (LPF), generates a voltage Vlpf after feedback, and then controls a current flowing through Ri in the low pass filter (LPF) circuit part, and then generates a voltage Vctrl under the action of an operational amplifier OP-Amp in a substructure of the active filter OP, and then controls the current source array (IBAND) to copy the current flowing through Ri (wherein the value of Ri and the ratio (KICO) of the output frequency variation of ICO to the control current variation determine the size of the PLL KVCO, based on the relationship, the size of the current is adjusted, the frequency range is divided into multiple intervals with smaller tuning ranges, and the KVCO value is ensured to be smaller in the premise of realizing a large frequency variation range), and finally the current-controlled oscillator (ICO) outputs a clock signal meeting the expected frequency and phase according to the current size.

[0017] The phase-locked loop circuit (PLL) needs to be calibrated by the current calibration method of the application before starting to work.

[0018] In a second aspect, the application provides a calibration method of a phase-locked loop circuit using current calibration, which is applied to the phase-locked loop (PLL) circuit.

[0019] The purpose of the current calibration method is to modulate the current size of the current source array (IBAND) according to the target output frequency of the current-controlled oscillator (ICO), so that the tuning range of the current-controlled oscillator (ICO) is near the target output frequency. Ensure that the phase-locked loop PLL circuit locks the clock signal in the optimal working state, thereby improving the working efficiency of the phase-locked loop circuit.

[0020] The control code (code) for modulating the current size of the current source array (IBAND) is the calibration signal K_CODE_B<5:0>.

[0021] The calibration signal K_CODE_B<5:0> is a 6-bit binary code (code), and the larger the code (code) is, the smaller the current of the current source array (IBAND) is; the smaller the code is, the larger the current of the current source array (IBAND) is.

[0022] The calibration signal K_CODE_B<5:0> needs to be converted into a 63-bit temperature code K_CODE<62:0> by a decoder according to the decoding rule when working.

[0023] The principle of the current calibration method is as follows: firstly, close the switch SW1 (the switch SW1 is a working switch in a low-pass filter (LPF) part of a circuit), then set the calibration signal K_CODE_B<5:0> to an intermediate gear, so as to make the current-controlled oscillator (ICO) work at an intermediate frequency, set the frequency division factor of the frequency divider (DIV) according to the target frequency of the phase-locked loop (PLL) circuit, then compare the frequencies of the reference clock (REF_CLK) and the feedback clock (FBK_CLK) to obtain a comparison result KBAND_UP, if the frequency of the feedback clock (FBK_CLK) is higher, then the comparison result KBAND_UP=1 (the frequency of the reference clock is higher, and the calibration signal K_CODE_B<5:0> needs to be increased to reduce the frequency), at this time, the calibration signal K_CODE_B<5:0>+1, repeat the operation until KBAND_UP=0, at this time, the jump of KBAND_UP occurs, which indicates that the frequency relationship between the reference clock (REF_CLK) and the feedback clock (FBK_CLK) has changed, and the calibration signal K_CODE_B<5:0> at this time is used as the final result of calibration; if the frequency of the feedback clock (FBK_CLK) is lower, then KBAND_UP=0 (the frequency of the reference clock is lower, and the calibration signal K_CODE_B<5:0> needs to be reduced to increase the frequency), at this time, the calibration signal K_CODE_B<5:0>-1, until KBAND_UP=1, the calibration signal K_CODE_B<5:0> at this time is used as the final result of calibration. The greater the calibration signal K_CODE_B<5:0> is, the smaller the current of the current source array (IBAND) is; the smaller the calibration signal K_CODE_B<5:0> is, the greater the current of the current source array (IBAND) is, and the final result of the calibration signal K_CODE_B<5:0> is used to complete the calibration of the current.

[0024] Compared with the prior art, the present application has the following beneficial effects:

[0025] The present application designs a current calibration method for a phase-locked loop (PLL) circuit, so that the value of the calibration signal K_CODE_B<5:0> can be adjusted, thereby adjusting the current size of the current source array according to the target output frequency of the current-controlled oscillator, making the tuning range of the current-controlled oscillator near the target output frequency of the phase-locked loop circuit, ensuring that the phase-locked loop circuit locks the clock signal in the optimal working state, and improving the working efficiency of the phase-locked loop circuit.

[0026] The application adopts a new phase-locked loop circuit with current calibration, divides the large VCO frequency range defined by the JEDEC standard into multiple small tuning range intervals through adjusting the size of the current, and ensures a small KVCO value under the requirement of a large clock frequency variation range, reduces the voltage range requirement of the phase-locked loop PLL circuit for the CP output, ensures excellent KVCO linearity, is beneficial to the loop stability of the PLL, and improves the anti-interference of the phase-locked loop circuit PLL to external noise. BRIEF DESCRIPTION OF DRAWINGS

[0027] The drawings incorporated in the specification and constituting a part of the specification illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the application.

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

[0029] Figure 1 A phase-locked loop PLL circuit structure diagram using a current calibration method is provided for the embodiment.

[0030] Figure 2 A specific circuit structure diagram of a low-pass filter LPF+current source array IBAND is provided for the embodiment.

[0031] Figure 3 A current calibration flowchart is provided for the embodiment.

[0032] Figure 4 A calibration signal K_CODE_B<5:0> decoding rule schematic diagram is provided for the embodiment. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative effort are within the protection scope of the present application.

[0034] It should be noted that all directionality indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present application are only used to explain the relative position relationship, movement condition, etc. between components in a certain posture, and if the certain posture changes, the directionality indications also change accordingly.

[0035] In addition, the description related to "first", "second" and the like in the present application is only for the purpose of description, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include at least one of the features. In addition, the technical solutions of various embodiments can be combined with each other, but it must be based on the realization of ordinary skilled in the art, when the combination of technical solutions appears contradictory or unachievable, it should be considered that the combination of technical solutions does not exist, nor within the protection scope required by the present application.

[0036] Embodiment one

[0037] The present embodiment provides a phase-locked loop circuit using current calibration, as shown in Figure 1 The phase-locked loop circuit specifically comprises: a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a current source array (IBAND), a current controlled oscillator (ICO) and a frequency divider (DIV).

[0038] The phase frequency detector (PFD) is mainly used to compare the rising edges (or falling edges) of the reference clock (REF_CLK) and the feedback clock (FBK_CLK), detect the phase difference and frequency difference of the two, and output two digital pulse signals UP and DN, the pulse width of which is proportional to the phase and frequency difference of the two.

[0039] The charge pump (CP) is mainly used to convert the output UP / DN digital pulse signal of the phase frequency detector (PFD) into an analog current (or voltage), UP signal, inject current (or voltage) into the loop filter; DN signal, extract current (or voltage) from the filter, drive the low pass filter (LPF).

[0040] The low pass filter (LPF) is arranged between the output end of the charge pump (CP) and the input end of the current source array (IBAND), which is used to filter out the high frequency noise in the output current of the charge pump (CP), smooth the high frequency ripple output by the charge pump (CP), generate a voltage Vlpf, and control the current flowing through the resistor Ri;

[0041] The current source array (IBAND) is arranged between the output end of the low pass filter (LPF) and the input end of the current controlled oscillator (ICO), which is used to provide programmable current source, realize dynamic adjustment of current parameters, copy the current through the resistor Ri in the low pass filter (LPF), and control the output of the current controlled oscillator (ICO);

[0042] The current-controlled oscillator (ICO) is arranged at the output end of the current source array (IBAND) and the input end of the frequency divider (DIV), and outputs a clock signal meeting the expected frequency and phase according to the current size;

[0043] The frequency divider (DIV) is arranged after the current-controlled oscillator (ICO) and connected with the phase-frequency detector (PFD), and is used for frequency-dividing the clock signal output by the current-controlled oscillator (ICO) and outputting a feedback clock signal FBK_CLK to the phase-frequency detector (PFD), so as to complete the closed loop of the circuit.

[0044] The specific working steps of the phase-locked loop circuit after the current calibration method provided by the application is performed are as follows:

[0045] S1: The phase-frequency detector (PFD) generates signals UP and DN for controlling the charging and discharging of the charge pump (CP) by comparing the frequency and phase difference of the reference clock REF_CLK and the feedback clock FBK_CLK;

[0046] S2: The charge pump (CP) outputs a voltage CP_OUT after receiving the charging and discharging signals UP and DN output by the phase-frequency detector (PFD);

[0047] S3: The CP_OUT controls the current size of the current source array (IBAND) after passing through the low-pass filter (LPF);

[0048] S4: The current-controlled oscillator (ICO) outputs a clock signal meeting the expected frequency and phase of the circuit according to the current size of the current source array (IBAND).

[0049] Further, as shown in Figure 2 The specific working process principle of step S3 is as follows:

[0050] S3-1: The output voltage CP_OUT of the charge pump (CP) is output to the positive input end of the active filter OP, and a voltage Vlpf is generated after feedback;

[0051] S3-2: The voltage Vlpf generated by feedback is used to control the current flowing through the resistor Ri of the low-pass filter (LPF) substructure;

[0052] S3-3: The voltage Vctrl is generated under the action of the operational amplifier (OP-Amp) in the substructure of the active filter (OP);

[0053] S3-4: The generated voltage Vctrl is used to control the current source array (IBAND) to copy the current passing through the resistor Ri, and the final current control process is completed.

[0054] When the phase-locked loop (PLL) circuit works, Figure 1The low pass filter (LPF) + current source array (IBAND) part shown inputs VREF as a power supply voltage, preferably with a value of VDD / 2, and another input calibration signal K_CODE_B<5:0> is generated by the current calibration method provided by the application, and a 63-bit thermometer code K_CODE<62:0> is generated through decoding to control the IBAND current size.

[0055] It should be noted that the value of Ri and the ratio (KICO) of the output frequency variation of the flow control oscillator (ICO) to the control current variation determine the size of the PLL KVCO. Based on this relationship, by adjusting the size of the current, the frequency is divided into multiple superimposed intervals with smaller tuning ranges, which can ensure a smaller KVCO value while achieving a large frequency variation range. Thus, the voltage range requirement of the charge pump (CP) output by the phase-locked loop (PLL) circuit is reduced; the excellent KVCO linearity is ensured, which is beneficial to the loop stability of the PLL; and the anti-interference of the phase-locked loop circuit PLL to external noise is improved.

[0056] Embodiment two

[0057] The embodiment provides a calibration method of a phase-locked loop circuit using current calibration, which is applied to the phase-locked loop circuit and performs current calibration of the current source array (IBAND).

[0058] The working principle is that the calibration signal K_CODE_B<5:0> is used as the code of the current source array (IBAND), the larger the calibration signal K_CODE_B<5:0> is, the smaller the current of the current source array (IBAND) is; the smaller the calibration signal K_CODE_B<5:0> is, the larger the current of the current source array (IBAND) is. The frequencies of the reference clock REF_CLK and the feedback clock FBK_CLK are compared to obtain a comparison result KBAND_UP, if the frequency of the FBK_CLK is higher, then KBAND_UP=1, the code needs to be increased to reduce the frequency; if the frequency of the FBK_CLK is lower, then KBAND_UP=0, the code needs to be reduced to reduce the frequency, and finally the frequencies of the REF_CLK and the FBK_CLK are close to each other, and the frequency of the feedback clock REF_CLK is preferably fixed at 50Mhz.

[0059] As Figure 3 The specific calibration process is as follows:

[0060] A1: Set the calibration signal K_CODE_B<5:0> to an intermediate gear, and in this embodiment, the intermediate gear is set to K_CODE_B<5:0>=110000, so that the calibration signal K_CODE_B<5:0> works at an intermediate frequency.

[0061] A2: According to the target frequency of the phase-locked loop circuit, the frequency division factor of the frequency divider (DIV) is set, and the preferred frequency division factor is the target frequency / 50Mhz.

[0062] A3: The frequencies of the reference clock REF CLK and the feedback clock FBK CLK are compared, if the frequency of the feedback clock FBK CLK is higher, then KBAND UP=1; if the frequency of the feedback clock FBK CLK is lower, then KBAND UP=0.

[0063] A4: When the comparison result KBAND UP=1, then the calibration signal K_CODE_B<5:0>+1, repeat the operation until KBAND UP=0, at this time KBAND UP produces a jump, indicating that the frequency size relationship between the reference clock REF CLK and the feedback clock FBK CLK has changed, using the calibration signal K_CODE_B<5:0> at this time as the final result of calibration, completing the calibration; if the comparison result KBAND UP=0, then the calibration signal K_CODE_B<5:0>-1, repeat the operation until KBAND UP=1, KBAND UP produces a jump at this time, indicating that the frequency size relationship between the reference clock REF CLK and the feedback clock FBK CLK has changed, using the calibration signal K_CODE_B<5:0> at this time as the final result of calibration. The larger the calibration signal K_CODE_B<5:0>, the smaller the current of the current source array (IBAND); the smaller the calibration signal K_CODE_B<5:0>, the larger the current of the current source array (IBAND), and the final result of the calibration signal K_CODE_B<5:0> is completed according to the calibration signal K_CODE_B<5:0>.

[0064] The calibration method can adjust the current size of the current source array (IBAND) according to the target output frequency of the flow-controlled oscillator (ICO), so that the tuning range of the flow-controlled oscillator (ICO) is near the target output frequency. Ensure that the phase-locked loop circuit locks the clock signal in the optimal working state, and improves the working efficiency of the phase-locked loop circuit. After the calibration is completed, the phase-locked loop PLL loop can start to intervene, the frequency and phase detector (PFD) detects the frequency and phase relationship between the reference clock REF CLK and the feedback clock FBK CLK, generates UP and DN signals to charge and discharge CP OUT, completes the current size modulation of the resistor Ri in the low-pass filter (LPF), and further controls the oscillation frequency of the oscillator (ICO), so that the phase-locked loop PLL circuit reaches a stable state, outputs the clock signal of the target expected frequency and phase of the circuit, and completes the final frequency locking.

[0065] Embodiment three

[0066] AsFigure 4 The decoding rule of the calibration signal K_CODE_B<5:0> provided by the embodiment is shown in the figure and is applied to the current calibration method described above.

[0067] The calibration signal K_CODE_B<5:0> is a 6-bit binary control code, which is used to control the current size of the current source array (IBAND) of the phase-locked loop PLL circuit during current calibration. The larger the calibration signal K_CODE_B<5:0> is, the smaller the current of the current source array (IBAND) is.

[0068] K_CODE<62:0> is a 63-bit thermometer code, which is generated after decoding by the current calibration method provided by the present application.

[0069] During the current calibration work, the calibration signal K_CODE_B<5:0> is converted into a 63-bit thermometer code K_CODE<62:0> by the decoder according to the decoding rule shown in the figure, which can ensure the linearity of current control, reduce transient error, and ensure the monotonicity of current switching.

[0070] Referring to Figure 1 , Figure 2 and Figure 3 According to the above embodiment one, embodiment two and embodiment three, the working principle and use process of the whole current calibration and phase-locked loop PPL circuit of the present application are as follows:

[0071] First, current calibration is performed: close the switch SW1, set the calibration signal K_CODE_B<5:0> to the middle gear, make the current-controlled oscillator (ICO) work at a middle frequency, set the frequency division factor of the frequency divider (DIV) according to the target frequency of the phase-locked loop PLL circuit, compare the frequencies of the reference clock REF_CLK and the feedback FBK_CLK, perform logical operation according to the comparison result KBAND_UP, obtain the final calibration result of the calibration signal K_CODE_B<5:0> when the comparison result KBAND_UP jumps, realize the calibration and modulation of the current size of the current source array (IBAND), make the tuning range of the current-controlled oscillator (ICO) near the target output frequency of the phase-locked loop PLL circuit, and complete the calibration task.

[0072] Disconnect SW1, the phase-locked loop PLL circuit itself starts to work: the frequency discriminator (PFD) detects the frequency and phase relationship of the reference clock REF_CLK and the feedback clock FBK_CLK, generates UP and DN signal pair to charge pump (CP) to charge and discharge, the charge pump (CP) output voltage CP_OUT to the + end of the low pass filter (LPF) substructure active filter OP, through the feedback to generate voltage Vlpf, and then use the voltage Vlpf generated by feedback to control the current flowing through the low pass filter (LPF) substructure resistor Ri, then generate voltage Vctrl under the action of the operational amplifier (OP-Amp) in the active filter (OP) substructure, use the generated voltage Vctrl to control the current source array (IBAND) to copy the current through Ri, the size of the current flowing through the resistor Ri (the value of Ri and the ratio of the change of the output frequency of the current controlled oscillator (ICO) to the change of the control current (KICO) determine the size of the PLL KVCO. Based on this relationship, the frequency can be divided into multiple smaller intervals by adjusting the size of the current, and the KVCO can be ensured to be smaller in the realization of a large range of frequency change range), and then control the oscillation frequency of the current controlled oscillator (ICO), so that the phase-locked loop PLL circuit reaches a stable state, and the output circuit outputs a clock signal with the target expected frequency and phase, and completes the final frequency locking.

[0073] The above current calibrated phase-locked loop PLL circuit can divide the larger voltage controlled oscillator (VCO) frequency range defined by the Solid State Technology Association (JEDEC) standard into multiple smaller intervals by adjusting the size of the current, so as to ensure that the KVCO is smaller in the realization of a large range of clock frequency change range, and ensure the stability and noise performance of the PLL circuit.

[0074] The above is only a preferred embodiment of the present application, not any form of limitation on the present application, although the present application has been disclosed as above, however, it is not intended to limit the present application, any person skilled in the art, without departing from the scope of the present application, can make some changes or modifications of the above disclosed technical content as equivalent embodiments, but as long as it does not deviate from the technical solution of the present application, according to the technical essence of the present application, any modification, equivalent change and modification of the above embodiments, all still belong to the scope of the present application.

Claims

1. A phase-locked loop circuit employing current calibration, characterized in that: This includes frequency and phase detectors, charge pumps, low-pass filters, current source arrays, current-controlled oscillators, and frequency dividers; The low-pass filter is set between the output terminal of the charge pump and the input terminal of the current source array. It is used to filter out high-frequency noise in the output current of the charge pump, smooth the high-frequency ripple of the charge pump output, generate voltage Vlpf, and control the current flowing through resistor Ri. The current source array is positioned between the output of the low-pass filter and the input of the current-controlled oscillator to provide a programmable current source, enabling dynamic adjustment of the current parameters. It replicates the current passing through the resistor Ri in the low-pass filter to regulate the output of the current-controlled oscillator. The aforementioned current-controlled oscillator is set at the output end of the current source array and the input end of the frequency divider, and outputs a clock signal that satisfies the desired frequency and phase according to the current magnitude; The frequency and phase detector and the charge pump are the initial signal input terminals of the circuit, which are then connected to a low-pass filter. The input reference clock signal REF CLK is received by the frequency and phase detector and fed back to the charge pump. The output voltage CP_OUT of the charge pump regulates the low-pass filter and the current source array. The frequency divider is placed after the flow-controlled oscillator and connected to the frequency and phase detector. It is used to divide the clock signal output by the flow-controlled oscillator and output the feedback clock signal FBK_CLK to the frequency and phase detector to complete the closed loop of the circuit.

2. The phase-locked loop circuit with current calibration according to claim 1, characterized in that, When the phase-locked loop circuit is working, the low-pass filter receives the power supply voltage signal VREF, and the current source array receives the calibration signal K_CODE_B<5:0>.

3. A phase-locked loop circuit with current calibration according to claim 1, characterized in that, The low-pass filter is equipped with a substructure active filter and an operational amplifier. The active filter is used to generate voltage Vlpf, and the operational amplifier is used to generate voltage Vctrl. The resistor Ri is replicated by a voltage-controlled current source array.

4. A calibration method for a phase-locked loop circuit using current calibration, applied to a phase-locked loop circuit using current calibration as described in any one of claims 1 to 3, characterized in that, Includes the following steps: A1: Set the calibration signal K_CODE_B<5:0> to the middle setting so that the flow-controlled oscillator operates at a middle frequency; A2: Set the division coefficient of the frequency divider according to the target frequency of the phase-locked loop circuit; A3: Compare the frequencies of the reference clock REF_CLK and the feedback clock FBK_CLK. If the frequency of the feedback clock FBK_CLK is higher, the comparison result KBAND_UP=1; if the frequency of the feedback clock FBK_CLK is lower, the comparison result KBAND_UP=0. A4: When the comparison result KBAND_UP=1, the calibration signal K_CODE_B<5:0>+1 is incremented, and the process repeats until the comparison result KBAND_UP=0. A jump occurs in the comparison result KBAND_UP, and the calibration signal K_CODE_B<5:0> at this point is used as the final calibration result to complete the current calibration. When the comparison result KBAND_UP=0, the calibration signal K_CODE_B<5:0>-1 is decremented, and the process repeats until the comparison result KBAND_UP=1. The calibration signal K_CODE_B<5:0> at this point is used as the final calibration result to complete the current calibration.

5. A calibration method for a phase-locked loop circuit using current calibration according to claim 4, characterized in that, The intermediate setting of the calibration signal K_CODE_B<5:0> and the division coefficient setting of the frequency divider are both determined based on the target output frequency of the phase-locked loop.

6. The calibration method for a phase-locked loop circuit using current calibration according to claim 4, characterized in that, The calibration signal K_CODE_B<5:0> controls the opening and closing of the current switch of the current source array. The larger the calibration signal K_CODE_B<5:0>, the smaller the current of the current source array; the smaller the calibration signal K_CODE_B<5:0>, the larger the current of the current source array.

7. The calibration method for a phase-locked loop circuit using current calibration according to claim 4, characterized in that, The calibration signal K_CODE_B<5:0> is a 6-bit binary code. During current calibration, the calibration signal K_CODE_B<5:0> is converted into K_CODE<62:0> by a decoder according to the decoding rules.

8. The calibration method for a phase-locked loop circuit using current calibration according to claim 7, characterized in that, The decoding rules are used to translate the 6-bit binary calibration signal K_CODE_B<5:0> into the 63-bit thermometer code K_CODE<62:0>.

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