Method and System for Constructing High-Speed Differential Signal Transmission Model

Abstract

The present invention relates to the technical field of electronic circuits, and in particular, to a method and system for constructing a high-speed differential signal transmission model. The method includes the following steps: obtaining printed circuit board design data and extracting differential signal line data; constructing a high-speed differential signal transmission model according to the differential signal line data; performing signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; identifying the position of the crosstalk source based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detecting via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluating the degree of thermal accumulation based on the via misalignment data; identifying the electrical fault area of the circuit board based on the degree of thermal accumulation; and extracting the stack-up structure information according to the printed circuit board design data. The present invention improves the accuracy and reliability of the high-speed differential signal transmission model based on electronic circuit technology, and significantly improves the signal transmission quality and the electrical fault detection rate.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and particularly to a method and system for constructing a high-speed differential signal transmission model. Background Art

[0002] A printed circuit board (PCB) includes circuit design and wiring technologies, involving multi-layer wiring, differential signal traces, impedance control, trace length matching, wiring topology, etc., for ensuring the transmission quality and synchronization of high-speed signals. In the modeling process of traditional high-speed differential signal transmission models, the physical structure characteristics (such as trace width, line spacing, via structure, reference layer change, etc.) in the signal transmission path are not comprehensively considered, and it is easy to ignore the fine extraction of parasitic parameters on the critical path of high-speed differential signals, resulting in low model accuracy; when dealing with complex electromagnetic coupling problems such as time-domain reflection, frequency-domain loss, and crosstalk effect in high-speed signals, idealized assumptions are often used, making it difficult to truly reflect the transmission behavior of differential signals in actual multi-layer PCB boards or high-speed interconnect structures; the model construction process highly depends on manual operations and expert experience, lacking a unified automated modeling process, with low efficiency and being easily interfered by human factors; there is a lack of an adaptive evaluation mechanism for model accuracy, making it difficult to flexibly adjust parameters or correct model errors for different application scenarios, thus restricting its popularization and application in high-bandwidth, high-rate, and high-density interconnect designs. Summary of the Invention

[0003] Based on this, it is necessary for the present invention to provide a method and system for constructing a high-speed differential signal transmission model to solve at least one of the above technical problems.

[0004] To achieve the above object, a method for constructing a high-speed differential signal transmission model includes the following steps:

[0005] Step S1: Obtain printed circuit board design data, and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data;

[0006] Step S2: Identify the crosstalk source position based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detect via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the thermal accumulation degree based on the via misalignment data; identify the electrical fault area of the circuit board based on the thermal accumulation degree;

[0007] Step S3: Extract the stack-up structure information according to the printed circuit board design data; perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; optimize the pad layout according to the interlayer delamination data;

[0008] Step S4: Reconstruct the signal routing according to the electrical fault area of the circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0009] The present invention constructs an automated modeling and optimization method for high-speed differential signal transmission scenarios, which can effectively improve the modeling accuracy of differential signals, the authenticity of transmission simulation, and the fault identification ability. In the modeling stage, the differential signal line information is directly extracted based on the printed circuit board design data, and physical structure features such as trace width, line spacing, via structure, and reference layer change are integrated, enabling the high-speed differential signal transmission model to comprehensively reflect the actual wiring structure, improving the accuracy of parasitic parameter extraction and the integrity of transmission path modeling. In the signal simulation stage, by simulating signal transmission on the model, differential signal behavior data under the actual operating conditions is obtained, providing high-precision input for subsequent crosstalk identification and avoiding errors caused by overly idealized assumptions in traditional models. Combining the crosstalk source coordinates to detect via misalignment, and then calculating the thermal accumulation degree based on the current path perturbation in the misaligned area, making the identification of the electrical fault area more targeted and structurally relevant, and solving the problem of incomplete manual judgment. By further extracting the stack-up structure information to achieve interlayer delamination detection, the integrity of the internal structure can be refined and identified, and on this basis, the pad layout is dynamically optimized to effectively avoid the hidden impact of structural failure points on signal connection. Finally, through the signal routing reconstruction guided by the fault area and the start point offset compensation control, the differential signal path is more balanced, significantly improving the equal transmission effect and synchronization of the signal, and feeding the compensation data back to the high-speed differential signal transmission model to achieve adaptive optimization and update. The overall process integrates three types of data features: structure perception, transmission perception, and fault perception, breaking the limitation of the traditional modeling process dominated by human experience and lacking fine structural parameter input, and realizing the full-process automated closed-loop from the construction to the optimization of the high-speed differential signal transmission model, improving the accuracy, reliability, and application promotion efficiency of the model.

[0010] Preferably, this specification also provides a construction system based on the high-speed differential signal transmission model for executing the construction method of the high-speed differential signal transmission model as described above. The construction system based on the high-speed differential signal transmission model includes:

[0011] A signal transmission simulation module, which is used to obtain the printed circuit board design data and extract the differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data;

[0012] An electrical fault identification module, which is used to identify the position of the crosstalk source based on the data transmitted by high-speed differential signals to obtain the crosstalk source coordinates; detect the misalignment of vias based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the degree of thermal accumulation based on the via misalignment data; identify the electrical fault area of the printed circuit board based on the degree of thermal accumulation;

[0013] A pad layout optimization module, which is used to extract the stack structure information according to the printed circuit board design data; perform interlayer peeling detection based on the stack structure information to obtain interlayer peeling data; optimize the pad layout according to the interlayer peeling data;

[0014] A differential equal-length compensation module, which is used to reconstruct the signal routing according to the electrical fault area of the printed circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0015] The construction system of the high-speed differential signal transmission model of the present invention, which can implement any construction method of the high-speed differential signal transmission model of the present invention, is used as the medium for the operation and signal transmission between various modules to complete the construction method of the high-speed differential signal transmission model. The internal modules of the system cooperate with each other, improving the accuracy and reliability of the high-speed differential signal transmission model, and significantly enhancing the signal transmission quality and electrical fault detection rate. Description of the Drawings

[0016] By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more obvious:

[0017] Figure 1 It is a schematic flow chart of the steps of a method for constructing a high-speed differential signal transmission model of the present invention;

[0018] Figure 2 It is a detailed schematic flow chart of step S1 in the present invention;

[0019] Figure 3 It is a detailed schematic flow chart of step S3 in the present invention;

[0020] The realization, functional characteristics and advantages of the purpose of the present invention will be further described with reference to the embodiments and the drawings. Detailed Embodiments

[0021] The technical method of the present invention will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those skilled in the art within the scope of the present invention without creative work belong to the protection scope of the present invention.

[0022] In addition, the drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus the repeated description thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. The functional entities may be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor methods and / or microcontroller methods.

[0023] It should be understood that although the terms "first", "second", etc. may be used herein to describe various units, these units should not be limited by these terms. These terms are only used to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, the first unit may be referred to as the second unit, and similarly the second unit may be referred to as the first unit. The term "and / or" used herein includes any and all combinations of one or more of the listed related items.

[0024] To achieve the above object, please refer to Figures 1 to 3 , the present invention provides a method for constructing a high-speed differential signal transmission model, and the method includes the following steps:

[0025] Step S1: Obtain printed circuit board design data and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data;

[0026] In this embodiment, all design data is obtained from the PCB design file. The design data can be extracted by importing Gerber files or IPC-2581 file formats. Use design software (such as Allegro PCB Designer, KiCad, or OrCAD) to read these files and extract the differential signal line data. The extraction of differential signal line data includes identifying the two signal lines of a differential signal pair. According to the definition of the differential signal pair, parameters such as the spacing, width, hierarchical structure, and trace length between these two lines need to be recorded in detail. To accurately extract this data, special attention is paid to the line spacing and line width, and the current impedance test method is used to verify whether the signal lines meet the design standards. The parameters of the line spacing and line width are set according to the IPC-2221 standard, with the line width being 0.25 mm and the spacing being 0.2 mm. At this time, all the geometric and electrical parameters of the differential signal lines have been extracted from the design file. Next, based on the extracted differential signal line data, a high-speed differential signal transmission model is constructed. This process uses transmission line theory (such as microstrip line theory), and uses the dielectric constant of the PCB material and the signal frequency to calculate the impedance characteristics, delay, and loss of signal transmission. For differential signals, first, the characteristic impedance of each signal line needs to be calculated. Generally, the differential impedance is set to 100 Ω, and the formula Z = (where L is the inductance and C is the capacitance) is used to calculate the impedance value. L and C can be calculated from the geometric parameters of the transmission line. Use transmission line simulation software, such as Ansys HFSS or Keysight ADS, to simulate the constructed transmission model, analyze the signal propagation delay, signal attenuation, and its performance in the frequency range. When simulating, set the simulation frequency range from 1 MHz to 10 GHz to cover the common high-speed signal frequency bands, and evaluate the transmission characteristics at different frequencies. Through the high-speed differential signal transmission model, the propagation data of the signal is obtained, including information such as signal delay, amplitude loss, and phase change. These information will provide basic data for the identification of crosstalk sources and the detection of electrical faults in the subsequent steps.

[0027] Step S2: Identify the crosstalk source location based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detect the via misalignment based on the crosstalk source coordinates to obtain the via misalignment data, and evaluate the thermal accumulation degree based on the via misalignment data; identify the electrical fault area of the circuit board based on the thermal accumulation degree;

[0028] In this embodiment, a spectrum analysis tool (such as Keysight VNA or Ansys HFSS) is used to analyze the signal data and calculate the crosstalk amplitude of each signal. The threshold of the crosstalk amplitude is set to -20 dB. If the crosstalk amplitude of a certain signal pair exceeds this threshold, then this signal pair is determined to be a potential crosstalk source. At this time, the position of the crosstalk source needs to be identified through the specific coordinates of the signal path. The export function in the PCB design software (such as Allegro or KiCad) is used to extract the path coordinate information of the differential pair and mark the specific position of the crosstalk source. After identifying the position of the crosstalk source, the detection of via misalignment is carried out. By extracting via data, the PCB is inspected using an X-ray scanning device to obtain the image data of the vias, and image processing software (such as MATLAB or OpenCV) is used to process the via images to detect whether there is misalignment of the vias. The standard for via misalignment is set such that an offset greater than 0.1 mm is considered an offset. If the via offset exceeds this standard, it is recorded as a misaligned via. According to the via misalignment data, the degree of heat accumulation is evaluated. By setting up a heat conduction simulation model, finite element analysis software (such as ANSYS or COMSOL) is used for thermal stress analysis. The initial heat source temperature is set to 70 °C, and the via misalignment data is used as input to calculate the temperature distribution in the via area. The diffusion process of heat in the PCB is simulated through the heat conduction equation to determine the heat concentration area. The degree of heat accumulation is evaluated by the temperature change in the area around each via. The temperature change threshold is set to 5 °C. If the temperature change exceeds this threshold, it is considered that there is a risk of heat accumulation in this area. Based on the heat accumulation degree data, the electrical fault area of the circuit board is identified. By evaluating the electrical performance of the heat accumulation area and combining the influence of heat, an electrical simulation tool (such as CST Studio) is used to further analyze the electrical fault area of the circuit. The identification criterion for the electrical fault area is electrical failure or unstable signal transmission, which is calibrated in combination with the simulation results to determine the position of the fault area.

[0029] Step S3: Extract the stack-up structure information according to the printed circuit board design data; perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; optimize the pad layout according to the interlayer delamination data;

[0030] In this embodiment, first, the stack-up structure information is extracted from the PCB design file. The number of layers, the material type and thickness of each layer are obtained through Gerber files or IPC-2581 standard files. The standard stack-up structure is set to 8 layers, the material is selected as FR4, and the interlayer dielectric constant is 4.2. By parsing the layer information in the design file, the thickness and material properties of each layer are extracted, and the distance between layers and the material type are recorded. According to the stack-up structure information, interlayer delamination detection is performed. The interlayer delamination detection is carried out by an X-ray CT scanner to obtain the cross-sectional image of each layer and analyze the bonding situation between layers. If the bonding layer of a certain layer is broken or separated, and the delamination standard is set as more than 10% of the layer area showing delamination, then it is considered that there is interlayer delamination in this area. Image processing software (such as MATLAB) is used to analyze the X-ray image, calculate the area and position of the delamination area, and obtain the interlayer delamination data. Based on the interlayer delamination data, the pad layout is optimized. The goal of pad layout optimization is to ensure that the pad area avoids overlapping with the delamination area. By modifying the size and position of the pads, the relative position of the pads and signal lines is adjusted to avoid problems such as stress concentration or poor conductivity. The pad size is set according to the standard IPC-2221, and the pad diameter is selected as 1 mm and the edge distance is 0.5 mm. The PCB design tool (such as Allegro or KiCad) is used to adjust the pad layout and regenerate the optimized design file.

[0031] Step S4: Reconstruct the signal routing according to the electrical fault area of the circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain the equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0032] In this embodiment, according to the signal path planning algorithm, the signal lines are redesigned using a routing tool (such as Allegro PCB Designer or KiCad) to avoid the fault area. During the reconstruction process, it is necessary to ensure the impedance matching of the signal lines. The differential signal line impedance is set to 100 Ω, and the same line width and spacing are adopted (for example, the line width is 0.25 mm and the spacing is 0.2 mm) to ensure stable signal transmission. Differential equal-length compensation is performed on the pad layout according to the signal routing. The compensation step adjusts the length of the signal lines by comparing the length differences of the differential pair signal lines to ensure that the lengths of the two signal lines are the same. Specifically, if the length difference between the two signal lines is 5 mm, a 5-mm extension part is added to the shorter signal line to ensure that the lengths of the two signal lines are exactly equal. The compensation data is verified through a simulation tool (such as Ansys HFSS) to ensure that the compensated signal lines can achieve the best impedance matching and transmission efficiency.

[0033] Preferably, step S1 is specifically:

[0034] Step S11: Obtain the printed circuit board design data and extract the differential signal line data;

[0035] In this embodiment, the design data of the printed circuit board (PCB) is imported. This data is usually provided in Gerber file format or IPC-2581 format and contains all the design information of the circuit board, including signal line layout, via positions, layer stack structure, etc. Use PCB design software (such as Allegro PCB Designer, KiCad or OrCAD) to read the design file to ensure that all necessary data can be extracted. The core task of extracting differential signal line data is to identify and extract all differential pair signal lines. These differential pairs consist of a pair of signal lines, usually located on the same layer and maintaining a fixed spacing from each other. Specifically, find all pairs of lines defined as differential signals in the design file and record the geometric characteristics of each line, such as line width, spacing and routing path. For each signal line, the line width and spacing information need to be extracted according to the standard PCB design requirements (such as IPC-2221). If the line width is 0.25 mm and the spacing of the differential pair is 0.2 mm, these parameters need to be recorded one by one. In addition, the layer information where the signal line is located needs to be extracted, usually a two-layer or multi-layer structure.

[0036] Step S12: Restore the signal propagation path based on the differential signal line data;

[0037] In this embodiment, based on the extracted differential signal line data, the signal propagation path needs to be restored first. To this end, the data of the differential signal lines should first be mapped to the actual layout of the PCB to determine the specific propagation path of the signal from the source point to the target point. Use signal integrity analysis tools (such as Ansys HFSS, Keysight ADS or CST Studio) to simulate the signal propagation. Input the geometric parameters of the differential signal lines, including line width, spacing, signal frequency, etc., and combine the dielectric constant, conductivity of the PCB material and the signal frequency to perform the simulation of the signal propagation path. The simulation tool will calculate the path of the signal propagating from the starting point along the differential signal line to the target point and consider factors such as the electrical characteristics between different dielectric layers, signal delay, loss, etc. During this process, special attention needs to be paid to issues such as the electrical length, propagation speed, signal reflection of each signal line to ensure the accuracy of the signal propagation path.

[0038] Step S13: Identify the impedance mutation regions according to the signal propagation path; Adjust the differential signal line spacing based on the impedance mutation regions;

[0039] In this embodiment, impedance mutations usually occur where the geometric structure of the signal line changes, such as at via locations, where the width of the signal line changes, or in the transition region between different material layers. To identify these mutation regions, it is necessary to analyze the reflection coefficient (S11) and transmission loss of the signal in combination with simulation data. Set the reflection coefficient threshold to -10 dB. When the reflection coefficient is higher than this threshold, it indicates that there is a problem with the impedance matching of the signal, and thus there is an impedance mutation region. By accurately measuring the impedance value of the signal line, the regions with obvious impedance changes are found. After identifying these regions, it is necessary to adjust the spacing of the differential signal lines to restore impedance matching. The adjustment of the differential signal line spacing is based on the standard impedance value, and the target impedance is usually set to 100 Ω. According to the impedance mutation conditions in different regions, the spacing of the signal lines is adjusted to ensure that the impedance of the signal lines remains stable within the mutation region. Usually, the spacing adjustment range is from 0.1 mm to 0.3 mm to meet the target impedance requirements.

[0040] Step S14: Identify and calculate the trace delay based on the signal propagation path; adjust the length of the differential signal lines based on the trace delay;

[0041] In this embodiment, the trace delay refers to the propagation time of the signal from the source point to the target point, which is usually determined by the signal propagation speed and the length of the signal line. Through simulation tools (such as Ansys HFSS or Keysight ADS), a detailed analysis of the signal propagation path is carried out to obtain the propagation delay of each signal line. The formula for delay is: Delay = Trace Length / Signal Propagation Speed, where the signal propagation speed is related to the dielectric constant of the PCB and is usually calculated by the formula: ; where is the speed of light, is the dielectric constant. According to the simulation results, calculate the propagation delay of each signal line and record the delay time of each signal line. To ensure synchronous signal transmission, especially for high-speed differential signals, the delay of the signal pair should be kept as consistent as possible. Therefore, for each differential signal line, according to the actually measured delay, appropriately adjust the length of the signal line. If the delay difference between the two signal lines exceeds 5 ns, it is necessary to adjust the length of one of the signal lines to ensure the delay matching of the differential signal pair. When adjusting the signal line length, ensure that the impedance of the signal line remains stable and is not affected. The length adjustment is usually achieved by extending or contracting the path of a certain signal line, and the standard range of length adjustment is usually ±10 mm. During the adjustment process, carefully monitor the impedance of each signal line to avoid affecting the signal quality.

[0042] Step S15: Construct a high-speed differential signal transmission model based on the differential signal line spacing and the differential signal line length;

[0043] In this embodiment, the geometric parameters of each group of differential pair signal lines are extracted based on the actual wiring data in the printed circuit board, including the line width of each signal line, the line spacing between differential pairs, the trace length, and the PCB layer where the wiring is located. The electrical parameters of the base material medium used in this PCB are collected, including basic material properties such as dielectric constant, loss factor, and conductor resistivity. According to the extracted structural parameters of a line width of 0.25 mm and a line spacing of 0.2 mm, and referring to the design constraint of the standard differential impedance control target of 100 Ω, each group of differential pairs in the transmission path is parametrically modeled in the structural modeling tool. During the model construction process, the simulation analysis tool Ansys HFSS based on the finite element method in the frequency domain is selected, and the dielectric constant of the PCB board is defined as 4.5 in the environment settings. At the same time, the boundary conditions of the model are clearly set, such as the reference layer definition, port excitation type, frequency sweep range, etc. In the model, the relative position relationship between the transmission line and the reference ground layer is constructed layer by layer according to the PCB stack structure to ensure that the electric field boundary is reasonably closed. An excitation signal is applied at the input end of the transmission path, and the working frequency range is set to cover the frequency bandwidth required for the rising time of the transmission signal. For example, the working frequency is set in the range of 5 GHz to 20 GHz. The electromagnetic field simulation calculation is run in the model to extract the transmission parameters of each differential signal path at the corresponding frequency, including key indicators such as differential mode impedance, common mode impedance, delay characteristics, insertion loss, and phase change. At the same time, the coupling strength between wirings and the crosstalk risk are evaluated. To further analyze the influence of the multi-layer structure on the signal quality, it is also necessary to accurately describe the thickness distance between each signal layer and its upper and lower reference grounds in the model, and consider the inductance effect of the via section and the impedance change of the dielectric transition band in the interlayer conduction structure modeling to ensure that the model still has a true reflection ability in the high-frequency state. Finally, the complete transmission parameter data of this group of differential pairs in the target frequency band is output as the basic data source for subsequent differential pair wiring optimization and timing control.

[0044] Step S16: Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data.

[0045] In this embodiment, a simulation software (such as Ansys HFSS, Keysight ADS, CST Studio) is used to simulate the signal transmission process. Information such as the frequency, amplitude, and signal source of the differential signal is input, and the signal transmission situation in the PCB is simulated. During the simulation, the frequency range is selected from 1 MHz to 10 GHz, covering common high-speed signal frequency bands. The simulation results will include information such as signal propagation delay, signal amplitude attenuation, phase change, and crosstalk. Various electrical parameters during the signal transmission process are calculated through the simulation tool to obtain signal transmission data. These data include impedance values, signal attenuation rates, delay times, etc. for each differential signal pair at different frequencies, which are used to evaluate and optimize the signal transmission characteristics and provide a basis for subsequent design optimization.

[0046] Preferably, step S16 is specifically as follows:

[0047] Step S161: Import the high-speed differential signal transmission model into the signal simulation software;

[0048] In this embodiment, the high-speed differential signal transmission model needs to be imported into the simulation software, such as Ansys HFSS or Keysight ADS, etc. This process first requires associating the existing PCB design data with the electromagnetic simulation model (including differential signal lines, impedance characteristics, routing paths, etc.) and importing them into the simulation environment. During the import process, confirm the compatibility between the design file format and the simulation software to ensure that the hierarchical information, routing paths, and electrical characteristics in the design file are correctly identified and loaded. After the import, perform necessary checks to ensure that the electrical characteristics of all models, such as impedance values, signal source settings, and signal propagation paths, are correct.

[0049] Step S162: Set the signal frequency range to 100 MHz - 10 GHz, the signal amplitude range to 0.5 V - 3.3 V, and the signal waveform to a sine wave in the simulation software;

[0050] In this embodiment, the signal frequency range needs to be set from 100 MHz to 10 GHz. Such a frequency range covers the working frequency bands of typical high-speed differential signals. The signal amplitude range is set to 0.5 V to 3.3 V, which can simulate the signal transmission characteristics at different voltage levels. The signal waveform is set to a sine wave, which is a common signal waveform and is used to simplify the analysis of the signal spectrum characteristics in high-speed signal simulation. When setting the frequency and amplitude, the specific values should be selected through experiments or design requirements to ensure that these parameters meet the actual design needs during the simulation. After setting these parameters in the simulation software, a preliminary verification is required to confirm that the signal waveform, frequency, and amplitude meet the expectations.

[0051] Step S163: Set the differential impedance range to 80Ω - 120Ω and the single - ended impedance range to 40Ω - 60Ω in the simulation software;

[0052] In this embodiment, the differential impedance in the simulation software is set to 80Ω to 120Ω, and the single - ended impedance is set to 40Ω to 60Ω. Differential impedance refers to the impedance between two signal lines, while single - ended impedance is the impedance between each signal line and the ground. To ensure the complete transmission of signals, these impedance ranges need to be consistent with the physical design used in the actual circuit design. When setting, these impedance values are derived by analyzing physical parameters such as trace width, spacing, and dielectric constant in the PCB layout. If it is found in the simulation that the actual measured impedance does not match the set value, the signal line spacing or width in the design needs to be adjusted until the simulation impedance is consistent with the set value.

[0053] Step S164: Set the signal source type to differential signal pair, the transmission line type to microstrip line, the signal transmission line length to 10mm - 300mm, and the signal line spacing range to 0.1mm - 1.0mm in the simulation software;

[0054] In this embodiment, differential signal pairs are particularly important in high - speed signal transmission because they can effectively reduce crosstalk and signal interference. In this step, the signal transmission line length is set to 10mm to 300mm, and the signal line spacing range is set to 0.1mm to 1.0mm. The transmission line length directly affects the propagation delay and transmission characteristics of the signal, and the spacing of the signal lines has a direct impact on the differential impedance. Therefore, according to the signal frequency, design requirements, and other electrical characteristics, the length and spacing of the signal lines are reasonably selected. The setting of these parameters is based on the signal frequency, the high - speed characteristics of the signal, and the requirements of the circuit design to ensure the reliability of the simulation results.

[0055] Step S165: Run the signal transmission simulation program in the simulation software and output high - speed differential signal transmission data.

[0056] In this embodiment, the signal transmission simulation program in the simulation software starts running, and a detailed electromagnetic field simulation of the set differential signal line is performed by the parser. During this process, the transmission characteristics of the signal (such as delay, reflection, attenuation, etc.) are calculated according to the simulation model, and the transmission data is output. The output data includes information such as the delay, crosstalk, voltage waveform, and reflection loss of each signal line. These data are crucial for the subsequent signal optimization design. After the simulation is completed, the output data needs to be analyzed to verify whether the signal transmission characteristics meet the design requirements and to identify any potential signal problems, such as impedance mismatch, excessive reflection loss, etc.

[0057] Preferably, the specific position of identifying the crosstalk source in step S2 is:

[0058] Extract low transmission efficiency signal data based on high-speed differential signal transmission;

[0059] In this embodiment, it is necessary to analyze the simulation results of high-speed differential signal transmission and extract the regions with relatively low signal transmission efficiency. These regions usually exhibit excessive signal attenuation, uneven delay, or strong reflection. In the simulation data, the signal regions with low transmission efficiency are usually represented by the abnormal values of parameters such as signal transmission loss, reflection loss, and transmission delay. For example, the signal loss is higher than the set threshold (such as the loss exceeding -3 dB), or the signal delay deviates from the expected value by more than the specified standard (such as exceeding 5 ns). By analyzing this data, the corresponding low-efficiency transmission regions are extracted and further marked as low transmission efficiency signal data.

[0060] Represent a low transmission efficiency circuit board according to the low transmission efficiency signal data, and perform image acquisition on the low transmission efficiency circuit board to obtain a low transmission efficiency circuit board image;

[0061] In this embodiment, according to the analysis result of the signal transmission data, the design of the PCB circuit board is screened, the regions with relatively low transmission efficiency are identified, and these regions are marked on the PCB design drawing. Then, a high-resolution camera or scanner (such as an optical microscope or a CT scanning device) is used to perform image acquisition on these calibrated regions. The accuracy of image acquisition should ensure that the specific wire routing layout of the circuit board can be clearly displayed, and the specific width, spacing of the wire routing, and the connected components can be distinguished. During the image acquisition process, it is necessary to select an appropriate magnification ratio and focal length according to the size of the PCB and the distribution of the calibrated regions to ensure that the acquired image has sufficient clarity and details.

[0062] Identify the wire routing path based on the low transmission efficiency circuit board image; Calculate the wire routing spacing according to the wire routing path;

[0063] In this embodiment, image processing is performed on the collected circuit board images. Usually, image processing software (such as OpenCV or Matlab) is used for edge detection to identify the routing paths in the circuit board. Through preprocessing methods such as grayscale conversion and binarization, the routing paths are made more obvious for subsequent analysis. After image processing, the path information of the lines is extracted through algorithms, and the starting and ending points of the traces are identified to complete the extraction of the routing paths. Measurements are taken on the identified routing paths to calculate the minimum distance between the lines. The calculation of the trace spacing can be completed by measuring the distance between the paths. Usually, the vertical distance between two traces is measured using image processing tools to calculate its minimum value. According to different design requirements and standards, a reasonable spacing threshold is set, such as 0.2 mm. Areas exceeding this threshold can be considered to have too large or too small spacing, which in turn affects the signal transmission efficiency. At this time, the calculation result of the spacing needs to be compared with the design standard to determine whether there are design problems.

[0064] Calculate the trace angle based on the routing path and identify the sharp turning regions of the traces in the circuit board image with low transmission efficiency based on the trace angle;

[0065] In this embodiment, it is necessary to calculate the trace angle of each signal line based on the routing path data in the image. This can be achieved by identifying the corner points or turning points on the path and calculating the change in the path direction. Through angle calculation, the regions with sharp turns are identified, such as regions where the angle is greater than 45°. The sharp turning regions of the traces usually cause uneven signal transmission, so the identification of these regions is crucial for further analysis and optimization.

[0066] Identify the small-spacing regions of the traces in the sharp turning regions of the traces based on the trace spacing;

[0067] In this embodiment, it is necessary to further subdivide the sharp turning region to identify the small-spacing regions of the traces within this region. The small-spacing regions usually refer to regions where the distance between two traces is less than the design standard (such as less than 0.2 mm). This step can be achieved by detailed measurement of the trace spacing within the sharp turning region to identify the regions with too small spacing. These small-spacing regions are prone to signal interference and crosstalk, so special attention is required.

[0068] Perform electromagnetic field simulation based on the small-spacing regions of the traces to obtain electromagnetic field simulation data;

[0069] In this embodiment, electromagnetic field simulation is performed on the identified small trace pitch area. Simulation software (such as Ansys HFSS or Keysight ADS) is used to simulate the distribution of electromagnetic fields in this area, usually based on the finite element analysis (FEA) or finite difference time domain (FDTD) method. The electromagnetic field simulation data includes parameters such as electric field strength, magnetic field distribution, and corresponding crosstalk and reflection. During the simulation process, factors such as signal frequency, impedance characteristics of the traces, and dielectric materials are considered to generate the electromagnetic field distribution map of this area. The simulation accuracy and parameter selection need to meet the requirements of the actual circuit design to ensure the high accuracy of the simulation results.

[0070] Identify the electromagnetic field enhancement area based on the electromagnetic field simulation data;

[0071] In this embodiment, the electromagnetic field simulation results are analyzed to identify areas with higher electromagnetic field strength, and these areas are the electromagnetic field enhancement areas. Through post-processing of the simulation data, the electromagnetic field strength of each area is calculated, and areas where the electric field strength exceeds a certain threshold (such as 100 V / m) are marked as electromagnetic field enhancement areas. The electromagnetic field enhancement areas usually indicate positions with relatively serious signal interference and require further optimization of the design.

[0072] Map the electromagnetic field enhancement area to the small trace pitch area to obtain the crosstalk source area and record it as the crosstalk source coordinates.

[0073] In this embodiment, the electromagnetic field enhancement area is matched with the small trace pitch area. Through the spatial coordinate system, the electromagnetic field enhancement area is mapped to the corresponding small trace pitch area to identify the area causing crosstalk. During the mapping process, based on the position relationship on the coordinate axes, the overlapping part of the electromagnetic field enhancement area and the small trace pitch area is determined. These overlapping areas are the crosstalk source areas. Finally, the coordinates of the crosstalk source areas are recorded, and these coordinate data are saved for subsequent optimization design and analysis.

[0074] Preferably, the degree of heat accumulation in step S2 is specifically:

[0075] Extract the via coordinates based on the crosstalk source coordinates;

[0076] In this embodiment, based on the coordinate data of the identified crosstalk source area, the via coordinates involved in signal interference are extracted. These vias are usually located on the critical paths of the circuit board and cause crosstalk problems. Using the interlayer connection information in the PCB design file, the positions of the vias are checked. By calibrating the coordinate points of the vias one by one in the design drawing, the via area related to the crosstalk source is identified, ensuring that the extraction process is carried out according to the design standards (such as the minimum via pitch and diameter) to avoid omission or misidentification.

[0077] Perform X-ray scanning according to the via coordinates to obtain via X-ray scanning data; reconstruct the 3D image of the via based on the via X-ray scanning data;

[0078] In this embodiment, first, locate these vias in the circuit board according to the extracted via coordinates. Use X-ray imaging technology for scanning, and the scanning parameters should be selected according to the via size, material, and circuit board thickness. For example, the energy range of the X-ray can be set from 50 keV to 100 keV to ensure that it can penetrate the circuit board and accurately detect the via structure. The image data obtained by X-ray scanning can clearly show the internal structure, shape of the via, and its connection with the circuit board. The scanning accuracy should reach 0.01 mm to ensure that the size and position of the via can be accurately recorded. Fuse the multi-angle X-ray data obtained by scanning, and use computer tomography (CT) algorithms or stereoscopic reconstruction techniques for data processing to generate a 3D image of the via. During the reconstruction process, combine information such as the geometric features and X-ray transmittance of the via to obtain an accurate 3D structure model of the via. The accuracy of this process should be controlled within 0.05 mm to ensure the reliability of the 3D image.

[0079] Divide the via penetration amount based on the via 3D image to obtain local penetrated via data and global penetrated via data;

[0080] In this embodiment, according to the 3D structure image of the via, divide the via into different regions (such as local regions and global regions). The local penetration amount usually refers to the penetration depth of the via within a small range and is affected by local material properties; the global penetration amount represents the overall penetration performance of the via. During the processing, use algorithms (such as image segmentation algorithms) to divide each region of the via and calculate the penetration depth of each region. For example, the local penetrated via data can be obtained by measuring the relationship between the diameter and depth of a certain part of the via, while the global penetrated via data is calculated based on the overall size and depth of the via.

[0081] Calculate the lateral position offset based on the local penetrated via data;

[0082] In this embodiment, according to the local penetrated via data, calculate the lateral offset of the via in the PCB. The lateral offset reflects the deviation degree of the via from the design center line and is usually determined by comparing the difference between the actual via position and the theoretical design position. The parameters involved in this calculation include the actual coordinates, design coordinates of the via, and the allowable deviation range (such as 0.1 mm). The calculation formula of the lateral offset can use the Euclidean distance formula for accurate calculation.

[0083] Calculate the depth misalignment offset based on the global penetrated via data;

[0084] In this embodiment, according to the global via-through hole data, the depth offset of the via is calculated. The depth misalignment offset represents the difference between the actual depth and the designed depth of the via, and is usually calculated by comparing the differences in the actual and designed positions of the via between different layers. This calculation needs to take into account the manufacturing tolerance and thermal expansion effect of the via. The calculation result of the depth offset should be compared with the tolerance standard in the design specification (such as 0.2 mm) to determine whether it exceeds the allowable error range.

[0085] Integrate the lateral position offset and the depth misalignment offset to obtain the via misalignment data;

[0086] In this embodiment, the lateral position offset and the depth misalignment offset are integrated to obtain the comprehensive via misalignment data. This data represents the degree of deviation of the via in three dimensions, and usually the square root of the sum of the squares of the lateral offset and the depth offset is used to obtain the comprehensive deviation value of the via misalignment. This comprehensive deviation value should be compared with the allowable deviation standard in the design. For example, the comprehensive deviation of the via misalignment should not exceed 0.3 mm.

[0087] Determine the coefficient of thermal expansion of the via material based on the via misalignment data; perform a thermal conduction simulation of the circuit board according to the coefficient of thermal expansion of the via material to obtain the circuit board thermal conduction data;

[0088] In this embodiment, according to the via misalignment data, the coefficient of thermal expansion of the via material is calculated using the thermal expansion theory. According to the calculation formula of the coefficient of thermal expansion:

[0089] ;

[0090] where represents the change in length, represents the coefficient of thermal expansion, represents the original length, represents the change in temperature. By actually measuring the relationship between the via misalignment data and the change in temperature, the coefficient of thermal expansion of the via material is inversely calculated. This process needs to control the range of temperature change. For example, the temperature change can be set to increase from 25°C to 125°C to ensure the accuracy of the result. Use a thermal conduction simulation software (such as ANSYS or COMSOL) to perform a thermal conduction simulation of the circuit board. During the simulation, parameters such as the geometric structure of the circuit board, material properties (including the coefficient of thermal expansion of the via material), and temperature gradient need to be input. The simulation result will show the thermal distribution of the circuit board under temperature change conditions and output the corresponding thermal conduction data, such as the temperature change in a specific area. During the simulation process, the temperature gradient can be set from 25°C to 125°C, and the heat source position and heat flux density can be adjusted according to the actual application conditions.

[0091] Thermal stress detection is performed on the via misalignment data according to the thermal conduction data of the circuit board to obtain the via thermal stress data; the degree of via tearing is evaluated based on the via thermal stress data;

[0092] In this embodiment, first, according to the thermal conduction data of the circuit board, the thermal stress in the area where the via is located is calculated. Thermal stress is usually generated by the uneven expansion of materials caused by temperature changes. When calculating, combining the geometric shape of the via, material properties, and coefficient of thermal expansion, the thermal stress formula is used for calculation, where is the thermal stress, is the elastic modulus of the material, is the coefficient of thermal expansion, is the temperature change. Through this formula, the thermal stress distribution data of the via can be obtained. The degree of via tearing is usually evaluated by calculating the area where the thermal stress exceeds a certain threshold. If the thermal stress exceeds the set tearing threshold (such as 50 MPa), it is considered that there is a risk of tearing in this via. This evaluation process involves the distribution map of thermal stress and the setting of the tearing threshold, which needs to be set according to the properties and standards of the via material.

[0093] Identify the heat accumulation area according to the degree of via tearing; evaluate the degree of thermal accumulation based on the heat accumulation area.

[0094] In this embodiment, through the thermal stress data, the high-temperature areas around the via are identified. These areas usually show higher thermal stress values, resulting in damage to the via structure. In this process, a thermal stress threshold is set, such as a thermal stress value exceeding 60 MPa, as the calibration standard, and then these areas are identified and marked as heat accumulation areas. By analyzing the thermal stress distribution in these heat accumulation areas, the degree of thermal accumulation in this area is evaluated. The method for evaluating the degree of thermal accumulation is to perform time integration on the thermal stress to obtain the total heat in this area, and then reflect the thermal load situation that this area has endured during long-term use, providing a basis for subsequent design optimization.

[0095] Preferably, step S2 for identifying the electrical fault area of the circuit board is specifically:

[0096] Evaluate the welding quality based on the degree of thermal accumulation to obtain welding data;

[0097] In this embodiment, based on the thermal stress integral value in the heat accumulation area obtained in the previous step, the long-term thermal energy change trend of the heat accumulation area is analyzed. Combining parameters such as the spatial range, heat accumulation intensity, and temperature peak duration of each heat accumulation area, the thermal distribution characteristics of the welding area are extracted. By setting a thermal energy accumulation threshold, such as the thermal stress time integral value reaching 1.2×10 6Above Pa·s, calibrate the heat load level of this area. Compare the heat load level with the welding process parameters. For example, if the welding temperature is 260°C and the welding duration is 3 seconds, calculate the heat capacity absorption capacity at this position and conduct a comparative analysis in combination with the thermophysical property parameters of the welding material such as thermal conductivity (unit: W / m·K) and thermal diffusivity (unit: mm² / s). Finally, determine the welding quality evaluation grade at this place. The quality grade is classified into three categories: overheating, insufficient heat, or uniform heat, and the welding data is output.

[0098] Statistically calculate the solder usage based on the welding data; calculate the solder accumulation volume based on the solder usage; determine the solder filling state based on the solder accumulation volume; evaluate the solder joint firmness based on the solder filling state; predict the solder joint detachment risk based on the solder joint firmness;

[0099] In this embodiment, by performing a combined operation on the heat input power, duration, and welding range area of each welding point in the welding data, estimate the flow range and solidification cross-sectional area of the solder after heating. Combine the initial density and distribution characteristics of the solder paste type to statistically calculate the actual solder mass consumed by each solder joint. For example, when using Sn63Pb37 solder with a density of 8.4 g / cm³, calculate the solder volume based on the solder joint area and solder layer thickness (such as a thickness of 0.15 mm) and calculate the mass in combination with the density, and finally output the solder usage. For "calculate the solder accumulation volume based on the solder usage", divide the solder mass obtained in the previous stage by the solder density to obtain the solder accumulation volume at each solder joint. Taking Sn63Pb37 solder as an example, with a density of 8.4 g / cm³, if the solder usage at a certain solder joint is 0.0126 g, the accumulation volume is 0.0015 cm³. Further confirm whether there are characteristics such as excessive accumulation, uniform distribution, or welding voids of the solder in combination with the solder joint geometry. Determine the filling state based on the ratio between the theoretical welding space size and the actual solder volume of each solder joint. If the ratio is between 0.9 and 1.1, it is determined as normal filling; if it is less than 0.9, it is determined as insufficient filling; if it is greater than 1.1, it is determined as excessive solder accumulation. The filling state data is recorded in the welding database, indicating the state values of each solder joint and the corresponding geometric coordinates. Conduct a composite calculation in combination with the filling state and the solder joint area contact rate. The solder joint firmness is calibrated using a percentage scoring system with three weight indicators: filling ratio, contact area rate, and heat distribution consistency. For example, the filling ratio weight accounts for 50%, the area contact rate weight accounts for 30%, and the heat consistency weight accounts for 20%. Each indicator is scored according to the quantitative scoring standard and then weighted and synthesized to output the firmness score and classify and mark it. Adopt a stepped risk judgment standard. When the solder joint firmness score is lower than 60 points, it is calibrated as a high risk; when the score is between 60 and 75, it is calibrated as a medium risk; when the score is above 75, it is calibrated as a low risk. Extract the positions of all high-risk solder joints to form a solder joint detachment risk list, along with the risk level, coordinates, and score details of each solder joint.

[0100] Extract the solder joint detachment positions based on the solder joint detachment risk; obtain the signal trace positions on the circuit board; perform a solder coverage area mapping on the signal trace positions according to the solder joint detachment positions to obtain solder coverage area data;

[0101] In this embodiment, screen out all high-risk solder joint coordinates from the solder joint detachment risk list as the solder joint detachment positions, and these coordinates will be used as the key input parameters in the subsequent mapping operation. Call the recognized trace paths in the circuit board image recognition data, and extract the two-dimensional coordinate point set of the trace in the PCB board plan view according to the trace vector path. After the coordinate conversion, the path data is unified into the same reference coordinate system as the solder joint coordinates to ensure the accuracy of subsequent matching. Calculate the shortest distance between the solder joint detachment coordinates and the signal trace path, and set 3mm as the matching threshold range. If the distance from any line segment on a certain signal path to the solder joint detachment coordinates is less than the threshold, it is considered that the trace is covered by the corresponding solder point. Extract these trace areas to form a solder coverage area data set, and mark the start and end point coordinates of the path segment and the corresponding solder joint numbers.

[0102] Conduct a resistance conduction test based on the solder coverage area data to obtain resistance conduction data;

[0103] In this embodiment, for the solder coverage path segment, use a multi-channel four-probe conduction test device to apply a fixed voltage (such as 1V) to both ends of the aforementioned solder coverage area and measure the passing current, and calculate the resistance value according to Ohm's law. Set the resistance value upper limit standard to 0.5Ω. If the measured resistance value exceeds the upper limit, it is determined that the conduction is abnormal, record this path segment as an abnormal conduction segment, and save the corresponding coordinate and measured resistance value data to form a resistance conduction data table.

[0104] Determine the electrical fault area of the circuit board based on the resistance conduction data.

[0105] In this embodiment, perform position clustering processing on the abnormal conduction segments. If multiple abnormal segments are concentrated in a certain area and the area exceeds 100mm², it is determined as an electrical fault area. The coordinates of this area are generated by the minimum bounding rectangle of the boundary points of multiple abnormal path segments, and compared with the signal trace diagram to determine the affected signal category and the position where signal distortion occurs. Finally, output the spatial coordinates and area of the electrical fault area, and the statistical data of abnormal resistance values.

[0106] Preferably, step S3 is specifically as follows:

[0107] Step S31: Extract the stack-up structure information according to the printed circuit board design data;

[0108] In this embodiment, the design layer number, thickness of each layer, dielectric material type, copper foil thickness, and specific positions of signal layers and ground layers for high-speed differential signal transmission of the PCB are obtained from the Gerber design file and the BOM (Bill of Materials) list. In the specific extraction operation, a CAD parsing tool is used to parse the structures of files such as.Drl,.GTL,.GBL,.GTS in the Gerber file, identify the functional attributes of each layer (signal layer, ground layer, power layer, etc.), and record the thickness parameters, dielectric constant (for example, the dielectric constant of FR4 material is 4.5), loss factor (for example, tanδ = 0.02), and thickness of the interlayer adhesive (for example, 0.1 mm) of each layer in XML structure. All structure information needs to be uniformly converted into a stack coordinate system in the Z-axis direction for subsequent machining path and mechanical simulation.

[0109] Step S32: Determine the edge milling process based on the stack structure information; perform via edge milling simulation according to the edge milling process to obtain via edge milling data;

[0110] In this embodiment, the stack thickness and material hardness data are read. According to the IPC-2221A standard, the edge milling method is specified for plates with different thicknesses and materials. For example, when the total thickness is less than 1.6 mm, a single high-speed milling method is used, and when the total thickness exceeds 2.4 mm, a multi-stage layered milling method is used. The edge milling tool selects a tungsten carbide milling cutter with a diameter of 0.8 mm, the spindle speed is set at 40000 rpm, and the feed rate is set at 1200 mm / min. A finite element cutting force simulation tool (such as Abaqus or ANSYS Mechanical) is used to perform local mesh division around the via (the element size does not exceed 0.01 mm), input the above parameters for cutting force path simulation, and extract the stress state distribution map of each layer, edge breakage morphology data, and local via wall deformation conditions. The output data format is uniformly a three-dimensional matrix form including coordinates (x, y, z), maximum shear stress, and cutting heat source distribution as the via edge milling data.

[0111] Step S33: Screen via edge milling samples according to the via edge milling data, and irradiate the via edge milling samples with a high-energy electron beam to obtain high-energy electron beam irradiation data; capture the diffraction pattern based on the high-energy electron beam irradiation data; identify the crystal morphology according to the diffraction pattern; determine the grain deformation according to the crystal morphology to obtain grain deformation data; evaluate the residual stress of edge milling based on the grain deformation data;

[0112] In this embodiment, area samples with the peak shear stress exceeding 220 MPa are selected from the milling edge data, and prepared into small samples with the size of 2 mm × 2 mm × PCB thickness. The cross-section of the sample is cut using the FIB (Focused Ion Beam) technology, and irradiated by a high-energy electron beam in the TEM (Transmission Electron Microscope) mode. The beam current energy is set to 200 keV, the beam current density is controlled within 10 A / cm², the exposure time is controlled within 5 seconds, and the diffraction pattern is collected. The change in the crystal arrangement angle in the diffraction pattern is identified using the Selected Area Electron Diffraction (SAED) method. If the lattice rotation is greater than 2° and the change in the interplanar spacing exceeds 0.05 Å, it is calibrated as grain deformation. The dislocation density inside the grain is recorded and converted into the Mises equivalent stress (using the Taylor factor M = 3.06). Finally, the residual stress value (unit: MPa) of each grain unit is output and bound to the coordinates, forming the grain deformation data and the milling edge residual stress data.

[0113] Step S34: Perform lamination crack analysis on the lamination structure information based on the milling edge residual stress to obtain lamination crack data;

[0114] In this embodiment, taking the residual stress data as the input boundary condition, it is imported into the three-dimensional lamination structure finite element model. The Cohesive Zone Modeling is defined for the interfaces between layers, and the shear strength threshold of each layer interface is set to 45 MPa, and the critical fracture energy is 0.25 N / mm. By calculating the stress action value of the residual stress on each layer bonding surface and comparing it with the interface strength threshold, the interface regions showing signs of shear failure or peeling are located. In the analysis output result, the three-dimensional position, failure mode (shear, tension, crushing), and interface number of each failed element are marked. The crack points are clustered and connected into a crack path using the Delaunay triangulation method to form a complete lamination crack data set.

[0115] Step S35: Predict the interlayer peeling risk based on the lamination crack data to obtain interlayer peeling data.

[0116] In this embodiment, the total sum of the interface crack lengths between layers is statistically calculated from the crack path data, and the ratio is calculated with the total interface length of each layer. The peeling risk determination criterion is set: when the crack length ratio exceeds 30% and the crack depth exceeds 1 / 3 of the total layer thickness, it is calibrated as a high peeling risk. Each peeling region is output as peeling volume data with three-dimensional coordinate marks, and includes the crack starting point, crack path direction, and the surrounding material hardness comparison data, constituting the interlayer peeling data set.

[0117] Step S36: Optimize the pad layout according to the interlayer peeling data.

[0118] In this embodiment, the high-risk areas in the delamination dataset are overlaid with the wiring diagrams of the signal layers in the PCB design to identify the solder joints whose pad areas are located in the high-risk delamination areas. According to the IPC-7095 standard, for the transmission path of high-speed differential signals, the pad pitch should be greater than 0.25 mm, and the signal turning angle should not be less than 135°. For the pads with high-risk areas, the layout is reconstructed by offsetting them to the low-stress areas. The offset distance is set according to the crack gradient direction. For example, if the direction of the maximum shear stress in the gradient direction is the X-axis direction, then a Y-axis offset of 0.3 mm is made to avoid the delamination path. The newly added positions of the pads should meet the requirement that the consistency error of the original wiring length does not exceed ±5%. Finally, the updated pad layout file (in the format of ODB++ or IPC2581) is output for the symmetric and consistent processing of the high-speed differential signal paths.

[0119] Preferably, step S36 is specifically as follows:

[0120] Step S361: Calculate the delamination depth based on the interlayer delamination data; calculate the delamination length based on the interlayer delamination data; calculate the interlayer delamination area based on the delamination depth and the delamination length;

[0121] In this embodiment, the interlayer delamination data is obtained by performing layer-by-layer tomographic scanning on the PCB stack structure using an X-ray interlayer scanner (model YXLON FF35 CT). The image resolution is set to 5 μm, and the scanning depth is set to 2 mm. The scanned images are processed by an image processing algorithm for edge detection, using the Sobel operator combined with the Canny edge extraction method to identify the starting and ending points of the interlayer delamination. The pixel distances measured in the image coordinate system are converted through the system calibration parameters (each pixel represents 5 μm) to obtain the actual physical dimensions of the delamination area. The calculation of the delamination depth is based on the vertical pixel difference of the Z-axis scan, combined with the layer thickness standard (the thickness of each dielectric layer is 0.1 mm), to calculate the physical thickness of the delamination section in the vertical direction. The delamination length is calculated based on the maximum boundary span of the delamination area in the XY plane. The contour tracking technique (using the findContours function in OpenCV) is used to extract the delamination contour, and the major axis of the contour is fitted (using the least squares ellipse fitting method) to extract its major axis length as the delamination length. Finally, the calculation of the interlayer delamination area is based on the product of the delamination length and the delamination depth. The calculation formula is: delamination area A = delamination length L × delamination depth D, where L and D are in millimeters. For example, in a certain stack area, the measured delamination length is 3.2 mm and the delamination depth is 0.1 mm, then the delamination area is 0.32 mm².

[0122] Step S362: Mark the interlayer delamination area based on the interlayer delamination area; perform risk division based on the interlayer delamination area. If the interlayer delamination area is greater than or equal to 30% of the interlayer delamination area, a high-risk interlayer delamination area is obtained; if the interlayer delamination area is less than 30% of the interlayer delamination area, a low-risk interlayer delamination area is obtained.

[0123] In this embodiment, the delamination area is marked by setting a fixed rasterized area. The entire PCB plane is meshed in units of 10mm×10mm, and each grid cell serves as a delamination detection area. The coordinates of the delamination area are mapped to the grid coordinate system through the GIS spatial mapping method (using the RasterToPolygon tool in ArcPy), and the ratio of the cumulative delamination area in each grid to the total grid area is statistically calculated. Based on the standard judgment threshold, if the ratio of the delamination area to the total area of the grid is greater than or equal to 30%, it is marked as a high-risk interlayer delamination area; if it is less than 30%, it is marked as a low-risk interlayer delamination area. For example, in a 10mm×10mm grid, the cumulative delamination area reaches 3.5mm², and the proportion of the delamination area in this area is 3.5%. According to the threshold, it is determined as a low-risk area; while if the delamination area in a grid is 35mm² and the proportion is 35%, it is marked as a high-risk area.

[0124] Step S363: Adjust the pad size based on the low-risk interlayer delamination area to obtain pad size data;

[0125] In this embodiment, the initial pad size is set to a diameter of 0.5mm according to the design standard. To reduce the reflection interference of electrical signals and improve signal integrity in low-risk areas, the pad size is adjusted in these areas according to the minimum distance from the center of the pad to the edge of the delamination area. If the distance is greater than 2mm, the pad diameter is adjusted to 0.6mm; if it is between 1.5mm and 2mm, the pad size remains 0.5mm; if it is less than 1.5mm, the pad diameter is adjusted to 0.4mm. This adjustment operation is completed using the "Pad Stack Manager" module in the EDA tool Altium Designer. After batch reading the coordinates of the low-risk areas, the "pad template mapping function" is called to match and update the target pad size. The adjusted size data is exported as a CSV format file, and the fields include pad ID, coordinates, size before adjustment, size after adjustment, and the risk area level where it is located.

[0126] Step S364: Adjust the pad material based on the high-risk interlayer delamination area to obtain pad material data;

[0127] In this embodiment, the initial pad material is copper (Cu), and the material conductivity is 5.8×10 7S / m. According to the requirements of antioxidant and mechanical stress resistance for high-speed differential signal transmission, a metal material with higher peel strength is used instead, such as nickel-gold alloy (ENIG), whose conductivity is 2.2×10 7 S / m, and the peel strength is increased by about 35%. The high-risk pad numbers are identified by laser marking (the laser device model is Keyence ML-Z9510), and the material replacement marks are made at the corresponding positions of the high-risk pads. The material replacement uses the electroless plating process. A nickel layer (with a thickness controlled at 5μm) is applied to the surface of the original copper pad, and then a gold layer (with a thickness controlled at 0.05μm) is applied. After each batch replacement, SEM (scanning electron microscope) is used for interface bonding detection to ensure that the boundary of the replacement area is clear, without voids and microcracks. The data of the replaced pad materials includes pad numbers, positions, original materials, new materials, and replacement thickness information, which are uniformly recorded in the structural material form and linked with the subsequent welding temperature parameters for control.

[0128] Step S365: Integrate the pad size data and the pad material data, and determine the optimized pad layout.

[0129] In this embodiment, a script tool (such as Python combined with Altium API) is used to merge the aforementioned pad size CSV and pad material data, perform an inner join match with the pad ID as the primary key, and output an optimized pad layout list. The fields include: pad ID, X coordinate, Y coordinate, diameter, metal type, and risk level. The optimized pad layout file is exported in Gerber format, which complies with the IPC-2581 standard, and DRC (design rule check) verification is performed to ensure that the adjusted pads do not conflict with the surrounding electrical structures such as traces and vias. After verification, the pad layout file is bound and imported into the differential pair routing module together with the differential signal routing scheme to complete the final layout of the high-speed differential signal path.

[0130] Preferably, step S4 is specifically:

[0131] Step S41: Reconstruct the signal routing according to the electrical fault area of the circuit board; extract the differential signal line directions based on the signal routing;

[0132] In this embodiment, based on the electrical fault detection results, the two-dimensional coordinate information of the fault area is loaded into the wiring design platform. The fault area is marked as an impassable area on the circuit diagram, and at the same time, wiring reconstruction rules are set: it is prohibited for any newly built signal path to pass through the space within 5 millimeters of the boundary of the fault area. Subsequently, in the wiring editing tool, manually or with the help of an automatic wiring plug-in, the existing differential signal lines are adjusted for obstacle avoidance wiring to ensure that the path length is controlled within the range of ±3% of the original wiring length, the wiring width is uniformly set to 5 mils, and it shall not cross or overlap with other existing signal layers. After the wiring is completed, all differential pair signal lines are renumbered through the signal network grouping function, and the coordinate sequence of the path nodes of each pair of signal lines is extracted to form the routing data. The extraction of the routing needs to strictly extract the path nodes in the order of the physical layout, and completely retain the start and end points and the corner point coordinates of each path segment for subsequent spatial relationship analysis with the pad area.

[0133] Step S42: Calculate the pad pitch based on the pad layout;

[0134] In this embodiment, the position coordinates of the centers of all pads are used as reference points for numbering, and the numbering is based on the logical network grouping order. Using the graphic analysis module in the wiring design tool, by calling the straight-line distance analysis function between coordinate points, the center distance between the pads at both ends of all differential pairs is analyzed in turn. The analysis result of the pitch of each pair of pads is marked with the actual physical length, and the unit is uniformly millimeters, and the precision is reserved to three decimal places. When measuring, it is also necessary to check whether the unit is consistent with the wiring drawing. If there is a scaling ratio, it needs to be converted according to the actual ratio. After the pitch measurement of all differential pads is completed, a comparison table containing the pad pair number and the pitch value is established as the structural basis for differential signal influence analysis.

[0135] Step S43: Identify the differential signal line influence area for the pad pitch according to the routing of the differential signal line to obtain the differential signal line influence area data;

[0136] In this embodiment, the routing coordinate sequence of the differential signal line is compared with the pad positions, and the extension recognition is performed on each signal line path segment. A strip area is established along the routing of the signal line, and the width of this area is set to 0.5 millimeters. The pad numbers whose center coordinates fall into this strip area are screened out. Each differential pair signal line needs to mark the influence ranges of its left line and right line respectively to form two independent strip coverage areas. During the recognition process, the relative positions of each pad and the signal line path are recorded. If the center point is less than 0.25 millimeters away from the path line, it is determined to be affected by this signal line. Finally, all the pad numbers, path numbers, and start and end coordinate ranges within the influence band of each signal line are packed to form an influence area data set, which is used to guide the subsequent start-end identification operation.

[0137] Particularly importantly, step S43 includes the following steps:

[0138] Step S431: Extract the coordinates of differential signal lines according to the routing of differential signal lines;

[0139] In this embodiment, based on the differential signal line information extracted from the printed circuit board (PCB) design data, the routing of differential signal lines on the circuit board is determined. Differential signal lines usually consist of two parallel signal lines, and their spacing, length, layout, and routing all have an important impact on the signal transmission performance. In this step, it is necessary to extract the signal routing data from the PCB design file (such as Gerber file) or CAD software. By parsing the file, the starting and ending coordinates of the signal lines are extracted, and the intermediate point information of each path is recorded. The extraction of differential signal line coordinates needs to ensure accuracy, usually requiring the accuracy of coordinate points to be at the micron level to ensure the accuracy of subsequent calculations. During the data extraction process, according to the layout rules of the circuit, the starting end, routing, connection method of the signal line, and its relative position to other lines should be comprehensively recorded.

[0140] Step S432: Statistically calculate the outer edge spacing of pads based on the pad spacing;

[0141] In this embodiment, by analyzing the pad layout in the PCB design diagram, the geometric dimension information of the pads is extracted. The outer edge spacing of pads refers to the distance between the outer edges of adjacent pads, and this data is very crucial for analyzing the influence area of differential signal lines. In this step, first, the geometric data of each pad, including the diameter or width, is extracted from the design file. Then, based on the extracted pad position data, the distance between the outer edges of adjacent pads is calculated. This distance is obtained by subtracting the radius or diameter of each pad from the distance between the center points of the two pads. This process requires high-precision distance calculation to avoid signal crosstalk or electrical short circuit caused by too small pad spacing. When statistically calculating the outer edge spacing of pads, the multi-layer design of the PCB should be considered to ensure that the pad spacing of each layer is independently statistically calculated and recorded, thereby providing accurate basic data for subsequent identification of the signal influence area.

[0142] Step S433: Perform a minimum distance calculation on the outer edge spacing of pads according to the coordinates of differential signal lines to obtain the minimum distance data;

[0143] In this embodiment, for each differential signal line, the relative positions of its two ends and the pads are determined, and the shortest distance from the outer edge of each pad to the differential signal line is calculated. During this process, the differential signal line is regarded as two parallel lines, and the pad is regarded as a structure with a circular or elliptical edge. To calculate the minimum distance, the distance formula in geometry is used to analyze the distance between the differential signal line and the outer edge of the pad. In actual operation, this calculation can be automatically completed by PCB design software or a custom calculation program, and high-precision floating-point arithmetic is used to ensure the accuracy of the distance calculation. For each pair of differential signal lines and the outer edge of the pad, the minimum distance value is recorded as the basic data for subsequent identification of the signal influence area.

[0144] Step S434: Mark the differential signal line influence area according to the minimum distance data to obtain the differential signal line influence area data.

[0145] In this embodiment, the influence area refers to those areas that are relatively close to the differential signal line and are affected by signal transmission. At this time, an influence threshold needs to be set, and this threshold is usually determined by design rules or signal quality requirements. For example, if the minimum distance is less than the set threshold, it is considered that the pad or area is affected by the differential signal line. In actual operation, a certain range around each pad is marked through programming to form the influence area data. The size of this area is related to the spacing of the signal lines and the electrical characteristics in the PCB design. The marking of the influence area is based on the calculated minimum distance data and combines the direction information of the differential signal line to draw the geometric shape of the affected area. During this process, using the visualization function of computer-aided design (CAD) software, the influence area can be intuitively displayed and further analyzed. These data are ultimately used for subsequent signal optimization and layout adjustment to ensure signal integrity and transmission quality.

[0146] Step S44: Identify the starting end of the differential signal line according to the differential signal line influence area data;

[0147] In this embodiment, by comparing the starting point coordinates in the differential signal line direction data with the positions of each pad in the influence area, the pair of pad points with the closest distance is found and determined as the starting pad of the differential pair signal line. If there are multiple pad center points with equal distances from the starting point, these pads are prioritized according to their numbering order, and the pad with a lower number is preferentially selected as the starting end. This operation needs to be verified point by point through the pad management tool in the routing editor to ensure that there is a consistent logical network number between the starting end pad and the signal path. The confirmed starting end pad number, coordinates, and the signal line number where it is located are written into the identification result table together to provide an accurate reference point for the starting point offset before compensation.

[0148] Step S45: Calculate the starting point offset according to the starting end of the differential signal line;

[0149] In this embodiment, after selecting the starting ends of each pair of differential signal lines, the distance between the starting positions of their two paths is measured. Using the path node reading function, the starting coordinates of the first segments of the two differential signal lines are extracted respectively. The spatial offset between these two starting points is measured in a plane, and its offset length and relative direction are recorded. If the offset direction is a non-vertical angle, the offset angle also needs to be recorded as an auxiliary parameter. This offset value serves as the core calculation benchmark for equal-length compensation required, and all differential pairs need to undergo this operation. Finally, a set of compensation basic parameters is formed, including the numbers of each differential line, the coordinates of the two starting points, the offset distance, and the offset direction, serving as the input basis for the differential pair compensation wiring process.

[0150] Step S46: Based on the starting point offset, perform differential equal-length compensation to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0151] In this embodiment, the compensation method selects the serpentine folding-back wiring process. A folding-back path segment is introduced within the allowable range of the wiring length. The interval length of each folding-back path is determined according to the offset amount and shall not be less than 5 mils. During the layout of the folding-back path, it is necessary to avoid areas with dense components, power supply wiring areas, and high-frequency signal interference areas. At the same time, the wiring width should be kept consistent with the main line, and rounded corners should be used for the turns to reduce the risk of signal reflection. After the compensation wiring is completed, the equal-length verification function module is called to detect the length difference before and after compensation to ensure that the difference does not exceed 5 mils. The compensation wiring data, including the coordinates, length, and direction information of the newly added path segment, is all written into the structure parameter concentrator of the high-speed differential signal transmission model. Finally, the model reconstruction function is called to load the updated signal network structure containing the compensation path to achieve the structural reconstruction of the high-speed differential transmission path.

[0152] Especially importantly, step S46 includes the following steps:

[0153] Step S461: Calculate the compensation path length based on the starting point offset;

[0154] In this embodiment, the starting physical coordinate positions of each pair of differential signal lines are extracted from the high-speed differential line layout diagram. These coordinates need to be parsed from the PCB design file, and the design file format is the standard ODB++ or IPC-2581 format. By parsing the defined area of the wiring layer (Layer) therein, the starting point data of the line segment corresponding to the signal line number is obtained. The starting positions of the signal lines are usually automatically assigned by the wiring tool. However, due to the asymmetric arrangement of logic chips or connector pins during the layout process, there are often physical offsets in the starting positions of the two lines in the differential pair. The extracted coordinate data is formatted in a unified unit (such as millimeters), and then the distance between the starting ends of the two differential lines is measured in a grid comparison manner. This measurement is based on the point-to-point comparison operation in the two-dimensional image coordinate system. By using a script to extract the two endpoints of each pair of signal lines one by one, without relying on model calculations, the horizontal difference and vertical difference are recorded, and the wiring control module combines the lengths of the two parts to finally generate a compensation length task list. The task list records the number of each pair of differential lines and the path length that needs to be compensated, with the unit accurate to 0.01 millimeters, and is marked to enter the compensation operation queue.

[0155] Step S462: Perform serpentine compensation wiring according to the compensation path length;

[0156] In this embodiment, after the path compensation length task list is generated, the compensation length required for each differential signal pair is assigned to the wiring engine to generate serpentine lines. The wiring process is based on predefined design rules, including line width setting, wiring spacing, turning gap, wiring layer selection, etc. The wiring engine uses the "differential equal-length function module" in the Cadence Allegro PCB Designer system for automatic layout. The compensation method is limited to local serpentine line compensation. The serpentine unit adopts a U-shaped folding structure, and each compensation structure includes a forward wiring section and two U-shaped turns. The compensation wiring area is preferably selected in the blank area after the starting section of the differential pair to avoid overlapping with other network or component wirings. The compensation path is designed with equal spacing and equal length. The length of a single section structure is a fixed value, such as 0.6 millimeters, the line width is uniformly set to 0.15 millimeters, and a minimum spacing of 0.25 millimeters is maintained between serpentine lines to ensure that the electrical isolation distance meets the high-speed design specifications. The wiring tool will automatically push the number of serpentine units in the local space according to the compensation length until the length requirement indicated in the task list is met. The turning point coordinates of each serpentine structure are completely recorded for subsequent compensation verification and simulation analysis.

[0157] Step S463: Compensate the differential signal line path according to the serpentine line layout path to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0158] In this embodiment, after the layout is completed, the total length of the routing paths of all differential signal lines will be recalculated to ensure that the overall routing lengths of the positive and negative lines reach strict consistency after the compensation operation. This verification process is completed by a routing verification tool. Using the routing analysis function within the same platform, each section of the routing is scanned segment by segment and the lengths are accumulated to output the complete path lengths of the positive and negative lines, which are recorded in the differential pair compensation log file. If the error exceeds the allowable threshold (e.g., 0.05 mm), the position or number of serpentine segments will be readjusted until the lengths are consistent. The routed data after compensation is exported in the form of a standard intermediate file format (such as DXF or GDSII) through a routing export tool. The routing trajectory of each pair of signal lines, the number of compensation segments, the coordinate information of each segment, the line width parameter, and the routing layer data will be archived as a structured data table and recorded in CSV format. This compensation data, as a key constraint item in the high-speed differential signal transmission model, is imported into the high-speed signal modeling environment through a data interface. The signal modeling tool uses the Keysight ADS system to model the transmission channel, automatically parses the differential line structure data and the serpentine segment structure, and converts them into an equivalent transmission line model of the channel. This model is then embedded into the differential channel simulation module as the input basis for multiple simulation modules such as electromagnetic field calculation, crosstalk analysis, and impedance distribution analysis, thus completing a round of structural optimization process for the high-speed signal path.

[0159] Preferably, this specification also provides a construction system based on a high-speed differential signal transmission model for performing the construction method of the high-speed differential signal transmission model as described above. The construction system based on the high-speed differential signal transmission model includes:

[0160] A signal transmission simulation module, configured to obtain printed circuit board design data and extract differential signal line data; construct a high-speed differential signal transmission model according to the differential signal line data; perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data;

[0161] An electrical fault identification module, configured to identify the crosstalk source position based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; detect via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the thermal accumulation degree based on the via misalignment data; identify the electrical fault area of the circuit board based on the thermal accumulation degree;

[0162] A pad layout optimization module, configured to extract the stack-up structure information according to the printed circuit board design data; perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; optimize the pad layout according to the interlayer delamination data;

[0163] The differential equal-length compensation module is used to reconstruct signal routing according to the electrical fault area of the circuit board; perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

[0164] Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the application document are intended to be included in the present invention.

[0165] The above are only specific embodiments of the present invention, enabling those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

Claims

1. A method for constructing a high-speed differential signal transmission model, characterized in that, It includes the following steps: Step S1: Obtain the printed circuit board design data and extract the differential signal line data; Construct a high-speed differential signal transmission model based on the differential signal line data; Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; Step S2: Identify the crosstalk source location based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; Detect the via misalignment based on the crosstalk source coordinates to obtain the via misalignment data, and evaluate the thermal accumulation degree based on the via misalignment data; Identify the electrical fault area of the circuit board based on the thermal accumulation degree; Step S3: Extract the stack-up structure information according to the printed circuit board design data; Perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; Optimize the pad layout according to the interlayer delamination data; Step S4: Reconstruct the signal routing according to the electrical fault area of the circuit board; Perform differential equal-length compensation on the pad layout according to the signal routing to obtain the equal-length compensation data, and upload it to the high-speed differential signal transmission model to generate an optimized model.

2. The method for constructing a high-speed differential signal transmission model according to claim 1, wherein Specifically, Step S1 is as follows: Step S11: Obtain the printed circuit board design data and extract the differential signal line data; Restore the signal propagation path based on the differential signal line data; Identify the impedance mutation area according to the signal propagation path; Adjust the differential signal line spacing based on the impedance mutation area; Identify and calculate the trace delay according to the signal propagation path; Adjust the differential signal line length based on the trace delay; Construct a high-speed differential signal transmission model according to the differential signal line spacing and the differential signal line length; Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data.

3. The method for constructing a high-speed differential signal transmission model according to claim 2, wherein Specifically, Step S16 is as follows: Step S161: Import the high-speed differential signal transmission model into the signal simulation software; Step S162: Set the signal frequency range to 100 MHz - 10 GHz, the signal amplitude range to 0.5 V - 3.3 V, and the signal waveform to a sine wave in the simulation software; Step S163: Set the differential impedance range to 80 Ω - 120 Ω and the single-ended impedance range to 40 Ω - 60 Ω in the simulation software; Step S164: Set the signal source type to a differential signal pair, the transmission line type to a microstrip line, the signal transmission line length to 10 mm - 300 mm, and the signal line spacing range to 0.1 mm - 1.0 mm in the simulation software; Step S165: Run the signal transmission simulation program in the simulation software and output the high-speed differential signal transmission data.

4. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that Specifically, the identification of the crosstalk source location in Step S2 is as follows: Extract the low transmission efficiency signal data based on the high-speed differential signal transmission data; Represent the low transmission efficiency circuit board according to the low transmission efficiency signal data, and perform image acquisition on the low transmission efficiency circuit board to obtain the low transmission efficiency circuit board image; Identify the trace path based on the low transmission efficiency circuit board image; Calculate the trace spacing according to the trace path; Calculate the trace angle according to the trace path, and identify the sharp turning area of the trace on the low transmission efficiency circuit board image based on the trace angle; Identify the small spacing area of the trace in the sharp turning area of the trace according to the trace spacing; Perform electromagnetic field simulation based on the small pitch region of the trace to obtain electromagnetic field simulation data; Identify the electromagnetic field enhancement region according to the electromagnetic field simulation data; Map the electromagnetic field enhancement region to the small pitch region of the trace to obtain the crosstalk source region, and record it as the crosstalk source coordinates.

5. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that The specific degree of heat accumulation in step S2 is: Extract the via coordinates based on the crosstalk source coordinates; Perform X-ray scanning according to the via coordinates to obtain via X-ray scanning data; Reconstruct the 3D image of the via based on the via X-ray scanning data; Divide the via penetration amount based on the 3D image of the via to obtain local via penetration data and global via penetration data; Calculate the lateral position offset based on the local via penetration data; Calculate the depth misalignment offset based on the global via penetration data; Integrate the lateral position offset and the depth misalignment offset to obtain via misalignment data; Determine the coefficient of thermal expansion of the via material based on the via misalignment data; perform thermal conduction simulation of the circuit board according to the coefficient of thermal expansion of the via material to obtain circuit board thermal conduction data; Perform thermal stress detection on the via misalignment data according to the circuit board thermal conduction data to obtain via thermal stress data; Evaluate the degree of via tearing based on the via thermal stress data; Identify the heat accumulation region according to the degree of via tearing; Evaluate the degree of heat accumulation based on the heat accumulation region.

6. The method for constructing a high-speed differential signal transmission model according to claim 1, wherein The specific process of step S2 for identifying the electrical fault region of the circuit board is: Evaluate the soldering quality based on the degree of heat accumulation to obtain soldering data; Statistical solder usage based on the soldering data; calculate the solder accumulation volume based on the solder usage; determine the solder filling state according to the solder accumulation volume; evaluate the solder joint firmness according to the solder filling state; Predict the risk of solder joint detachment according to the solder joint firmness; Extract the solder joint detachment position according to the risk of solder joint detachment; obtain the signal trace position of the circuit board; map the solder coverage area to the signal trace position according to the solder joint detachment position to obtain solder coverage area data; Perform resistance conduction test according to the solder coverage area data to obtain resistance conduction data; Determine the electrical fault region of the circuit board according to the resistance conduction data.

7. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that Step S3 is specifically: Step S31: Extract the stack-up structure information according to the printed circuit board design data; Step S32: Determine the milling process based on the stack-up structure information; perform via milling simulation according to the milling process to obtain via milling data; Step S33: Screen the via milling samples according to the via milling data, and irradiate the via milling samples with high-energy electron beam to obtain high-energy electron beam irradiation data; capture the diffraction pattern based on the high-energy electron beam irradiation data; identify the crystal morphology according to the diffraction pattern; Judge the grain deformation according to the crystal morphology to obtain grain deformation data; Evaluate the milling residual stress based on the grain deformation data; Step S34: Perform stack-up crack analysis on the stack-up structure information according to the milling residual stress to obtain stack-up crack data; Step S35: Predict the risk of interlayer delamination according to the stack-up crack data to obtain interlayer delamination data; Step S36: Optimize the pad layout according to the interlayer delamination data.

8. The method for constructing a high-speed differential signal transmission model according to claim 7, wherein Step S36 is specifically: Step S361: Calculate the delamination depth according to the interlayer delamination data; calculate the delamination length according to the interlayer delamination data; calculate the interlayer delamination area according to the delamination depth and the delamination length; Step S362: Mark the interlayer delamination area based on the interlayer delamination area; Perform risk division based on the interlayer delamination area. If the interlayer delamination area is greater than or equal to 30% of the interlayer delamination area, obtain a high-risk interlayer delamination area; If the interlayer delamination area is less than 30% of the interlayer delamination area, obtain a low-risk interlayer delamination area; Step S363: Adjust the pad size based on the low-risk interlayer delamination area to obtain pad size data; Step S364: Adjust the pad material based on the high-risk interlayer delamination area to obtain pad material data; Step S365: Integrate the pad size data and the pad material data and determine them as the optimized pad layout.

9. The method for constructing a high-speed differential signal transmission model according to claim 1, characterized in that Step S4 is specifically as follows: Step S41: Reconstruct the signal routing according to the electrical fault area of the circuit board; Extract the differential signal line routing based on the signal routing; Step S42: Calculate the pad pitch based on the pad layout; Step S43: Identify the differential signal line influence area for the pad pitch according to the differential signal line routing to obtain differential signal line influence area data; Step S44: Identify the starting end of the differential signal line according to the differential signal line influence area data; Step S45: Calculate the starting point offset according to the starting end of the differential signal line; Step S46: Perform differential equal-length compensation based on the starting point offset to obtain equal-length compensation data and upload it to the high-speed differential signal transmission model to generate an optimized model.

10. A construction system based on a high-speed differential signal transmission model, characterized in that, For implementing the method for constructing a high-speed differential signal transmission model as described in claim 1, the system for constructing a high-speed differential signal transmission model based on this includes: A signal transmission simulation module, which is used to obtain printed circuit board design data and extract differential signal line data; Construct a high-speed differential signal transmission model according to the differential signal line data; Perform signal transmission simulation based on the high-speed differential signal transmission model to obtain high-speed differential signal transmission data; An electrical fault identification module, which is used to identify the crosstalk source location based on the high-speed differential signal transmission data to obtain the crosstalk source coordinates; Detect via misalignment based on the crosstalk source coordinates to obtain via misalignment data, and evaluate the thermal accumulation degree based on the via misalignment data; Identify the electrical fault area of the circuit board based on the thermal accumulation degree; A pad layout optimization module, which is used to extract the stack-up structure information according to the printed circuit board design data; Perform interlayer delamination detection based on the stack-up structure information to obtain interlayer delamination data; Optimize the pad layout according to the interlayer delamination data; A differential equal-length compensation module, which is used to reconstruct the signal routing according to the electrical fault area of the circuit board; Perform differential equal-length compensation on the pad layout according to the signal routing to obtain equal-length compensation data and upload it to the high-speed differential signal transmission model to generate an optimized model.

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