Stress simulation method of chip packaging structure

Abstract

The invention provides a stress simulation method for a chip packaging structure, and the method comprises the steps: S1, dividing the chip packaging structure into first modeling regions and second modeling regions, the first modeling regions being located at four corner regions of the chip packaging structure, and the corner regions being arranged at intervals; s2, acquiring physical parameters of the electric lead-out layer in different modeling areas, and simplifying the physical parameters of the electric lead-out layer in the second modeling area to obtain equivalent physical parameters; and S3, constructing a stress simulation model of the chip packaging structure based on the physical parameters of the electric lead-out layer in the first modeling area and the equivalent physical parameters of the electric lead-out layer in the second modeling area. The invention provides an equivalent simulation modeling method for stress calculation, and effectively solves the problems of difficult modeling, complex simulation, high calculation requirement and the like in the field of stress simulation calculation in the prior art.

Description

Technical Field

[0001] The present invention relates to the field of chip packaging, and particularly to a method for stress simulation of a chip packaging structure. Background Art

[0002] With the rapid development of advanced packaging technologies, the internal interconnection structure of the package has become increasingly complex, and the number of interconnection structures has also increased rapidly, especially in the field of 2.5D packaging technologies. The bumps in the interconnection structure play a key role in connecting the chip and the interposer, and are also the parts most prone to failure. To avoid failure, through one-to-one simulation modeling, the stress magnitude received by the bumps can be accurately calculated, thereby evaluating their failure risks.

[0003] However, currently, in the existing technologies, the related research mainly focuses on simulating and equivalenting warpage, and there is no simulation technology for accurately equivalenting and calculating the stress of such a large number of bumps. If only relying on one-to-one simulation modeling for stress calculation, due to the small size of the bumps, generally only dozens of micrometers, the number of bumps in the simulation model will be as high as five or six hundred thousand, and there are large differences in the arrangement density and size, making it difficult to simulate or the simulation is relatively complex and not easy to calculate quickly. At the same time, it is also very difficult to accurately measure it through direct experiments.

[0004] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0005] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a method for stress simulation of a chip packaging structure, which is used to solve the problems that it is difficult to simulate or the simulation is relatively complex and not easy to calculate quickly in directly simulating the stress distribution in chip packaging in the prior art.

[0006] To achieve the above object and other related objects, the present invention provides a method for stress simulation of a chip packaging structure. The chip packaging structure includes an electrical lead-out layer, and the electrical lead-out layer includes a plurality of electrical connection parts and a plurality of buffer parts, and each of the buffer parts is arranged between each of the electrical connection parts. The stress simulation method at least includes:

[0007] Step S1: Divide the chip packaging structure into a first modeling area and a second modeling area, wherein the first modeling area is located in the four corner areas of the chip packaging structure and the corner areas are separated from each other;

[0008] Step S2: Obtain the physical parameters of the electrical lead-out layer in different modeling regions, and simplify the physical parameters of the electrical lead-out layer in the second modeling region to obtain equivalent physical parameters;

[0009] Step S3: Based on the physical parameters of the electrical lead-out layer in the first modeling region and the equivalent physical parameters of the electrical lead-out layer in the second modeling region, construct a stress simulation model of the chip package structure.

[0010] Optionally, the electrical connection part includes a first metal, a second metal, and a third metal arranged from top to bottom; in step S2, the physical parameters of the electrical lead-out layer include electrical connection part parameters and buffer part parameters, where the electrical connection part parameters include the material parameters and structural parameters of the first metal, the material parameters and structural parameters of the second metal, and the material parameters and structural parameters of the third metal, and the buffer part parameters include the material parameters and structural parameters of the filler layer.

[0011] Optionally, the material parameters include elastic modulus, Poisson's ratio, shear modulus, and coefficient of thermal expansion.

[0012] Optionally, in step S2, the method for simplifying the physical parameters of the electrical lead-out layer in the second modeling region includes:

[0013] Perform a mixed equivalent treatment on each electrical connection part and each buffer part of the electrical lead-out layer in the second modeling region to obtain the equivalent physical parameters of the electrical lead-out layer in the second modeling region.

[0014] Optionally, when the electrical connection part includes a first metal, a second metal, and a third metal arranged from top to bottom, the method for simplifying the physical parameters in the second modeling region includes:

[0015] Perform a mixed equivalent treatment on the material parameters and structural parameters of the first metal, the material parameters and structural parameters of the second metal, and the material parameters and structural parameters of the third metal respectively with the material parameters and structural parameters of the buffer part to respectively obtain the material parameters and structural parameters of the first composite material, the material parameters and structural parameters of the second composite material, and the material parameters and structural parameters of the third composite material.

[0016] Optionally, each corner region includes M×N electrical connection parts, where both M and N are integers greater than or equal to 2 and less than or equal to 10.

[0017] Optionally, the value of M is equal to the value of N.

[0018] Optionally, step S3 includes: step S31, establishing a geometric model of the package structure based on each physical parameter and the equivalent physical parameter; step S32, setting the range of the solution domain, applying loads and boundary conditions, and solving the geometric model of the package structure based on finite element analysis to obtain a stress simulation model of the chip package structure.

[0019] Optionally, the stress simulation method for the chip package structure further includes a step of correcting the stress simulation model, including:

[0020] Step S4, constructing an actual simulation model of the chip package structure based on the physical parameters of the electrical lead-out layer, and selecting any electrical connection part in the actual simulation model as a measurement point;

[0021] Step S5, reading out the first simulation stress of the measurement point in the actual simulation model, and reading out the second simulation stress of the measurement point in the stress simulation model;

[0022] Step S6, comparing the first simulation stress and the second simulation stress, and when the second simulation stress does not meet the preset error condition, performing a correction operation on the stress simulation model and outputting the corrected stress simulation model;

[0023] Step S7, repeatedly executing step S5 and step S6 until the measurement point meets the preset error condition.

[0024] Optionally, when each of the corner regions contains M×N electrical connection parts, the method for performing a correction operation on the stress simulation model includes increasing the values of M and N to re-divide the first modeling region.

[0025] As described above, the stress simulation method for the chip package structure of the present invention has the following beneficial effects:

[0026] 1. The present invention proposes an equivalent simulation modeling method for stress calculation, effectively solving the problems in the prior art such as difficult modeling, complex simulation, and high computing power requirements in the field of stress simulation calculation. The present invention successfully overcomes the problem of difficult stress calculation due to a large number of bumps and complex arrangements, not only significantly improving the calculation efficiency but also ensuring high accuracy of the calculation results.

[0027] 2. The method of the present invention is simple, can be well applied to the field of stress calculation for chip packaging, and has a broad market prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It shows a schematic structural diagram of the chip package structure of the present invention.

[0029] Figure 2It shows a schematic diagram of the steps of the stress simulation method for the chip packaging structure of the present invention.

[0030] Figure 3 It shows a top view of the chip packaging structure of the present invention.

[0031] Figure 4 It shows the equivalent top view after cutting along the Figure 1 O-line position after step S2 of the present invention.

[0032] Figure 5 It shows the equivalent top view after cutting along the Figure 1 P-line position after step S2 of the present invention.

[0033] Figure 6 It shows the equivalent top view after cutting along the Figure 1 Q-line position after step S2 of the present invention.

[0034] Figure 7 It shows the equivalent structure diagram of the chip packaging structure after step S2 of the present invention.

[0035] Figure 8 It shows the flow chart for verifying and correcting the stress simulation model of the present invention.

[0036] Figure 9 It shows a schematic diagram of the position for selecting the electrical connection part.

[0037] Figure 10 It shows the stress result contour map of the electrical connection part at the Figure 9 position after constructing the actual simulation model for the 6mm×6mm chip packaging structure.

[0038] Figure 11 It shows the stress result contour map of the electrical connection part at the Figure 9 position after constructing the stress simulation model for the 6mm×6mm chip packaging structure.

[0039] Figure 12 It shows the stress result contour map of the electrical connection part at the Figure 9 position after constructing the actual simulation model for the 10mm×10mm chip packaging structure.

[0040] Figure 13 It shows the stress result contour map of the electrical connection part at the Figure 9 position after constructing the stress simulation model for the 10mm×10mm chip packaging structure.

[0041] Description of component labels

[0042] 1 Chip packaging structure

[0043] 10 Chip

[0044] 11 Electrical lead-out layer

[0045] 111 Electrical connection part

[0046] 111a First modeling area

[0047] 111b Second modeling area

[0048] 1111 First metal

[0049] 1112 Second metal

[0050] 1113 Third metal

[0051] 112 Buffer part

[0052] 12 Electrical connection layer

[0053] 13 First composite material

[0054] 14 Second composite material

[0055] 15 Third composite material Detailed implementation manners

[0056] The following illustrates the implementation manners of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please refer to Figures 1 to 13 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0058] Figure 1 There is shown a chip packaging structure 1 for packaging a chip 10. Among them, the chip packaging structure 1 includes an electrical lead-out layer 11, and the electrical lead-out layer 11 includes a plurality of electrical connection parts 111 and a plurality of buffer parts 112. Each buffer part 112 is arranged between each electrical connection part 111.

[0059] Specifically, a plurality of electrical connection parts 111 are arranged in an array.

[0060] As an example, the electrical connection part 111 includes a first metal 1111, a second metal 1112, and a third metal 1113 arranged from top to bottom.

[0061] In the present embodiment, the first metal is copper (CU), the second metal is nickel (NI), and the third metal is silver arsenic (SnAg), which together constitute the electrical connection portion 111. In the present embodiment, the buffer portion 112 includes a filler layer manufactured based on a bottom filling process. It should be noted that the materials and quantities of the above structure are only for the convenience of understanding the method of stress simulation in the subsequent chip packaging structure. The actual amount of metal, the corresponding materials used, and the actual filling materials of the buffer portion 112 are not limited to the present embodiment. In addition, the structural shape of the electrical connection portion 111 includes various shapes such as spherical, columnar, and block, and is not limited to the present embodiment.

[0062] It should be noted that, in this embodiment, the chip 10 is packaged based on the 2.5D packaging technology. After the chip 10 is packaged by the chip packaging structure 1, it will be connected to the subsequent electrical connection layer 12 to achieve chip packaging and electrical lead-out, thereby obtaining the chip packaging structure 1. Figure 1 Only one chip 10 is shown in the figure, but the number of chips 10 actually connected is not limited to this embodiment. Under the 2.5D packaging technology, the electrical connection portion 111 (set as the bump in the 2.5D packaging technology in this embodiment) is subjected to stress caused by factors such as the mismatch of the coefficient of thermal expansion (CTE), the curing process of the packaging material, and temperature changes. These stresses are unevenly distributed, and when the stress exceeds a certain limit, it is easy to cause the bump to crack, delaminate, and fail the electrical connection.

[0063] However, since the 2.5D package is a stacked package with a high degree of integration, multiple chips are usually integrated inside. There is a bump array at the bottom of each chip, and the size of each bump is usually only 20-30μm. The actual number of electrical connections 111 is 100,000-600,000, or even more.

[0064] Based on this, this embodiment provides a stress simulation method for a chip packaging structure, which is used to solve the problem that a large number of Bump arrays are difficult to simulate directly or the simulation is relatively complex and difficult to calculate quickly. It should be noted that the stress simulation method for a chip packaging structure of this embodiment can also be applied to a Bump array with a small number of Bumps, and is not limited to this embodiment.

[0065] like Figure 2 As shown, this embodiment provides a stress simulation method for a chip packaging structure 1, comprising the following steps; wherein the chip packaging structure 1 is implemented using the structure described above.

[0066] like Figure 2 and Figure 3As shown, in step S1, the chip packaging structure 1 is divided into a first modeling area 111a and a second modeling area 111b. Among them, the first modeling area 111a is located in the four corner areas of the chip packaging structure 1, and the corner areas are separated from each other (that is: the corner areas do not touch or intersect with each other).

[0067] As Figure 2 and Figure 3 shown, in step S2, the physical parameters of the electrical lead layer 11 in different modeling areas are obtained, and the physical parameters of the electrical lead layer 11 in the second modeling area 111b are simplified to obtain equivalent physical parameters;

[0068] Specifically, the electrical connection part 111 includes a first metal 1111, a second metal 1112, and a third metal 1113 arranged from top to bottom; in step S2, the physical parameters of the chip packaging structure 1 include electrical connection part parameters and buffer part parameters. Among them, the electrical connection part parameters include the material parameters and structural parameters of the first metal 1111, the material parameters and structural parameters of the second metal 1112, and the material parameters and structural parameters of the third metal 1113, and the buffer part parameters include the material parameters and structural parameters of the filler layer.

[0069] As an example, each material parameter includes, but is not limited to, elastic modulus, Poisson's ratio, shear modulus, and coefficient of thermal expansion. Each structural parameter includes, but is not limited to, shape characteristics, size characteristics, position characteristics, and volume characteristics.

[0070] Specifically, in step S2, the method for simplifying the physical parameters in the second modeling area 111b includes: performing a hybrid equivalent process on each electrical connection part 111 and each buffer part 112 of the electrical lead layer 11 in the second modeling area 111b to obtain the equivalent physical parameters of the electrical lead layer 111 in the second modeling area 111b. That is, the different structures in the second modeling area 111b are mixed to directly simplify the second modeling area 111b.

[0071] As an example, in this embodiment, when the electrical connection part 111 includes a first metal 1111, a second metal 1112, and a third metal 1113 arranged from top to bottom, the method for simplifying the physical parameters in the second modeling area 111b includes:

[0072] As Figures 4 to 6 shown, the material parameters and structural parameters of the first metal 1111, the material parameters and structural parameters of the second metal 1112, and the material parameters and structural parameters of the third metal 1113 are respectively subjected to a hybrid equivalent process with the material parameters and structural parameters of the filler layer to respectively obtain the material parameters and structural parameters of the first composite material 13, the material parameters and structural parameters of the second composite material 14, and the material parameters and structure of the third composite material 15.

[0073] As Figure 4 shown, the first equivalent physical parameters of the first composite material 13 are obtained by equivalently mixing the first metal 1111 and the filler layer; as Figure 5 shown, the second equivalent physical parameters of the second composite material 14 are obtained by equivalently mixing the material parameters and structural parameters of the second metal 1112 and the material parameters and structural parameters of the filler layer; as Figure 6 shown, the third equivalent physical parameters of the third composite material 15 are obtained by equivalently mixing the material parameters and structural parameters of the third metal 1113 and the material parameters and structural parameters of the filler layer.

[0074] In this embodiment, the equivalent physical parameters include but are not limited to elastic modulus, Poisson's ratio, shear modulus, and coefficient of thermal expansion.

[0075] In this embodiment, the elastic modulus requirements are satisfied as follows:

[0076] Ez = VdEd + VrEr (1)

[0077] Ex = Ey = EdEr / (VrEd + VdEr) (2)

[0078] where Ex, Ey, and Ez are the elastic moduli in the x, y, and z directions; the Z direction is the direction from the chip package structure 1 to the chip 10; X and Y are two perpendicular directions in the plane where the array is arranged in the chip package structure 1; V is the volume ratio; the subscript d represents metals such as Cu, Ni, SnAg, etc., and r represents the underfill layer. When calculating the first equivalent physical parameters, d is set to Cu; when calculating the second equivalent physical parameters, d is set to Ni; when calculating the third equivalent physical parameters, d is set to SnAg. That is, it is required that each layer mixes the metal and underfill to obtain the corresponding physical parameters.

[0079] In this embodiment, Poisson's ratio satisfies:

[0080] μxz = μyz = Ex(Vd / μd + Vrμr) / Ez (3)

[0081] μxy = Vrμr + Vdμd[1 + μd - (Ed / Ez)μxz] / [1 - (μd)^2 + μd(Ed / Ez)μxz] (4)

[0082] where μxz, μyz, and μxy are the Poisson's ratios in the xz, yz, and xy planes, respectively.

[0083] In this embodiment, the shear modulus satisfies:

[0084] Gxz = Gyz = GdGr / (VrGd + VdGr) (5)

[0085] Gxy = Ex / [2 * (1 + μxy)] (6)

[0086] Wherein, Gxz, Gyz, and Gxy are the shear moduli in the xz, yz, and xy directions respectively.

[0087] In this embodiment, the coefficient of thermal expansion satisfies:

[0088] αz = [VdαdEd + VrαrEr] / Ez (7)

[0089] αx = αy = αdVd(1 + μd) + αrVr(1 + μr) - αzμxz (8)

[0090] Wherein, αx, αy, and αz are the coefficients of thermal expansion in the x, y, and z directions respectively.

[0091] Based on the above formulas (1) - (8), the physical parameters of the simplified second modeling region 111b are obtained, which is convenient for subsequent stress modeling.

[0092] It should be noted that the actual equivalent method is not limited to that provided in this embodiment. At the same time, the actual equivalent number of layers and materials should be determined according to the number of layers and materials required for actual modeling, and is not limited to this embodiment.

[0093] Specifically, each corner region contains M × N electrical connection parts 111; both M and N are integers greater than or equal to 2 and less than or equal to 10. That is, each corner region is not simplified, only the second modeling region 111b is simplified. Since stress failure usually occurs at the bottom several bumps at the four corner positions of the chip package structure 1, higher accuracy is required for it.

[0094] As an example, try to ensure that the difference between M and N is small to avoid large deviations in the selected points. Among them, it is preferably set that the value of M is equal to the value of N, and such a setting can ensure that the finally established stress model is more accurate.

[0095] In this embodiment, it is set that the 4 corner regions are all 3 × 3 arrays, and it is required that they are not simplified to ensure more accurate stress at the corner positions.

[0096] As an example, in this embodiment, in order to improve the accuracy of modeling, some additional regions can be appropriately selected and retained without being simplified. For example, in this embodiment, the first modeling region 111a further includes K edge regions (not shown in the figure); each edge region is arranged on the four sides of the array to ensure accurate stress at the most stress - sensitive positions of the edges and corners of the chip package structure 1. Among them, each edge region does not overlap with each corner region.

[0097] It should be noted that in order to simplify the calculation amount as much as possible in this embodiment, it is preferably set that each corner region is small and independent of each other without being tangent or intersecting. Compared with the stress modeling of ball grid arrays such as flip chips, where the ball diameter is usually small (0.25 mm - 0.5 mm) and the number of ball grids is small (no more than 1000 at most), this embodiment has a better optimization effect on 2.5D packaging and even other packages with a large number of bumps. In this embodiment, only 4 3×3 arrays of bumps are finally involved in the calculation, which greatly simplifies the bump array with a quantity of 100,000 - 200,000, and is applicable to the requirements of high-density packaging.

[0098] It should be further noted that for the method provided in this embodiment, considering the different accuracies required for each position in the bump array and the different ambiguities required for the final simulation, different situations are distinguished to ensure both the accuracy of the modeling and simulation and the simplification of the simulation computing power.

[0099] As Figure 2 shown, step S3: Construct a stress simulation model of the chip package structure based on the physical parameters of the electrical lead layer 11 in the first modeling region 111a and the equivalent physical parameters of the electrical lead layer 11 in the second modeling region 111b.

[0100] Specifically, step S3 includes:

[0101] Step S31: Establish a geometric model of the package structure based on the physical parameters and equivalent physical parameters of the electrical lead layer 11.

[0102] Specifically, as Figure 7 shown, the simplified chip package structure 11 includes the simplified and equivalent second modeling region 111b and the unsimplified first modeling region 111a. Based on Figure 7 the physical parameters and equivalent physical parameters, establish a geometric model of the package structure.

[0103] Step S32: Set the solution domain range, applied load, and boundary conditions, and solve the geometric model of the package structure based on finite element analysis to obtain the stress simulation model of the chip package structure.

[0104] Through finite element analysis, the geometric model is discretized into a finite element analysis mesh, and the equations are solved respectively based on the set solution domain range, applied load, and boundary conditions to obtain the stress simulation model. Among them, the solution methods of each equation include direct methods and iterative methods, and it is required to solve under the condition of meeting the preset constraints. It should be noted that the specific settings for constructing the stress simulation model are not limited to this embodiment.

[0105] As Figure 8 shown, the stress simulation method of the chip package structure further includes modifying the stress simulation model, including:

[0106] Step S4: Based on the physical parameters of the electrical lead layer 11, construct an actual simulation model of the chip package structure, and select any electrical connection part in the actual simulation model as the measurement point to be measured;

[0107] Step S5: Read out the first simulation stress of the measurement point to be measured in the actual simulation model, and read out the second simulation stress of the measurement point to be measured in the stress simulation model (the simplified simulation model constructed in this embodiment).

[0108] Step S6: Compare the first simulation stress and the second simulation stress, and when the second simulation stress does not meet the preset error condition, perform a correction operation on the stress simulation model and output the corrected stress simulation model.

[0109] Step S7: Repeat Step S5 and Step S6 until the measurement point meets the preset error condition.

[0110] Specifically, compared with the previously unsimplified simulation model, the simplified simulation model constructed in this embodiment has a certain error. However, generally speaking, if it is considered to be less than the preset error condition, the stress simulation model can be directly used. In this embodiment, the preset error condition is set to 95% - 105% of the first simulation stress (as Figure 5 in which, α is taken as 5%, and the actual value can be determined based on needs). At the same time, when the simplified simulation model constructed in this embodiment is still difficult to meet a certain standard, a correction operation needs to be performed on the stress simulation model until the stress simulation model meets the conditions.

[0111] Among them, in this embodiment, when each corner region contains M×N electrical connection parts, performing a correction operation on the stress simulation model includes increasing the values of M and N to re-divide the first modeling region 111a. By increasing the participation degree of the first modeling region 111a, the accuracy of the stress simulation model can be improved.

[0112] At the same time, in another embodiment, performing a correction operation on the stress simulation model further includes extracting more physical parameters to construct the stress simulation model to improve the accuracy of stress modeling.

[0113] It should be noted that other correction methods can also be set for correction, and it is not limited to this embodiment.

[0114] In this embodiment, as Figure 8As shown, two simulations can be constructed for the Bump arrays of 6mm×6mm and 10mm×10mm respectively. It is possible to first verify the 6mm×6mm one and then the 10mm×10mm one, or verify both the 6mm×6mm and 10mm×10mm simultaneously, without being limited to this embodiment. At the same time, the specific array size for verification is not limited to this embodiment either.

[0115] The Figure 9 stress of the outermost corner 1 Bump ( Figure 9 the R part) shown is read out to obtain the stress simulation results as shown in Figures 10 to 13 . It can be clearly calculated that the maximum pressure values of the actual simulation model of 6mm×6mm and the stress simulation model of this embodiment are 61.147MPa and 61.871MPa respectively, with an error rate of 0.74%; the maximum pressure values of the actual simulation model of 10mm×10mm and the stress simulation model of this embodiment are 62.613MPa and 63.785MPa respectively, with an error rate of 1.87%. Among them, in the verification from 6mm×6mm to 10mm×10mm, the area increased by 64%. If reflected in the number of bumps, assuming that the 6mm×6mm chip packaging structure 1 has 300,000 bumps, then the 10mm×10mm chip packaging structure 1 will have nearly 500,000 bumps. And this embodiment only retains the four corner regions and each corner region only has 3×3 bumps for one-to-one simulation, and the rest of the positions are equivalently simplified, and the final accuracy error is still less than 2%. Therefore, the method of this embodiment is applicable to the case of a large range of Bump numbers and has a wider application scenario. This embodiment effectively takes into account the problem that the computer computing power cannot support processing such a large number of models in the case of a large number of Bumps.

[0116] In summary, the present invention provides a stress simulation method for a chip packaging structure, including: S1, dividing the chip packaging structure into a first modeling region and a second modeling region, where the first modeling region is located in the four corner regions of the chip packaging structure and the corner regions are separated from each other; S2, obtaining the physical parameters of the electrical lead-out layer in different modeling regions, and simplifying the physical parameters of the electrical lead-out layer in the second modeling region to obtain equivalent physical parameters; S3, constructing a stress simulation model of the chip packaging structure based on the physical parameters of the electrical lead-out layer in the first modeling region and the equivalent physical parameters of the electrical lead-out layer in the second modeling region. The present invention proposes an equivalent simulation modeling method for stress calculation, effectively solving the problems in the prior art such as difficult modeling, complex simulation, and high computing power requirements in the field of stress simulation calculation. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0117] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A stress simulation method for a chip packaging structure, characterized in that: The chip packaging structure includes an electrical lead-out layer, the electrical lead-out layer includes a plurality of electrical connection parts and a plurality of buffer parts, each of the buffer parts is arranged between each of the electrical connection parts; The stress simulation method at least comprises: Step S1, dividing the chip packaging structure into a first modeling area and a second modeling area, wherein the first modeling area is located at four corner areas of the chip packaging structure and the corner areas are spaced apart from each other; Step S2, obtaining physical parameters of the electrical extraction layer in different modeling areas, and simplifying the physical parameters of the electrical extraction layer in the second modeling area to obtain equivalent physical parameters; Step S3: constructing a stress simulation model of the chip packaging structure based on the physical parameters of the electrical lead-out layer in the first modeling area and the equivalent physical parameters of the electrical lead-out layer in the second modeling area.

2. The stress simulation method of chip packaging structure according to claim 1, characterized in that: The electrical connection part includes a first metal, a second metal and a third metal arranged from top to bottom; in step S2, the physical parameters of the electrical lead-out layer include electrical connection part parameters and buffer part parameters, wherein the electrical connection part parameters include material parameters and structural parameters of the first metal, material parameters and structural parameters of the second metal, material parameters and structural parameters of the third metal, and the buffer part parameters include material parameters and structural parameters of the filling layer.

3. The stress simulation method of chip packaging structure according to claim 2, characterized in that: The material parameters include elastic modulus, Poisson's ratio, shear modulus and thermal expansion coefficient.

4. The stress simulation method for a chip packaging structure according to any one of claims 1 to 3, characterized in that: In step S2, the method for simplifying the physical parameters of the electrical extraction layer in the second modeling area includes: The electrical connection parts and the buffer parts of the electrical extraction layer in the second modeling area are mixed and equivalently processed to obtain equivalent physical parameters of the electrical extraction layer in the second modeling area.

5. The stress simulation method of chip packaging structure according to claim 4, characterized in that: When the electrical connection portion includes a first metal, a second metal, and a third metal arranged from top to bottom, a method for simplifying the physical parameters in the second modeling area includes: The material parameters and structural parameters of the first metal, the material parameters and structural parameters of the second metal, and the material parameters and structural parameters of the third metal are mixed and equivalently processed with the material parameters and structural parameters of the buffer part to obtain the material parameters and structural parameters of the first composite material, the material parameters and structural parameters of the second composite material, and the material parameters and structural parameters of the third composite material, respectively.

6. The stress simulation method of chip packaging structure according to claim 1, characterized in that: Each of the corner regions includes M×N electrical connection portions, wherein M and N are both integers greater than or equal to 2 and less than or equal to 10.

7. The stress simulation method of chip packaging structure according to claim 6, characterized in that: The value of M is equal to the value of N.

8. The stress simulation method of chip packaging structure according to claim 1, characterized in that: Step S3 comprises, Step S31, establishing a packaging structure geometric model based on various physical parameters and equivalent physical parameters; Step S32, setting a solution domain range, applying loads and boundary conditions, and solving the geometric model of the packaging structure based on finite element analysis to obtain a stress simulation model of the chip packaging structure.

9. The stress simulation method of chip packaging structure according to claim 1, characterized in that: The stress simulation method of the chip packaging structure also includes a step of correcting the stress simulation model, including: Step S4, constructing an actual simulation model of the chip packaging structure based on the physical parameters of the electrical lead-out layer, and selecting any electrical connection part in the actual simulation model as a point to be tested; Step S5, reading out the first simulated stress of the point to be measured in the actual simulation model, and reading out the second simulated stress of the point to be measured in the stress simulation model; Step S6, comparing the first simulated stress and the second simulated stress, and when the second simulated stress does not meet a preset error condition, performing a correction operation on the stress simulation model and outputting the corrected stress simulation model; Step S7, repeating steps S5 and S6 until the point to be measured meets the preset error condition.

10. The stress simulation method of chip packaging structure according to claim 9, characterized in that: When each of the corner regions includes M×N electrical connection portions, the method of performing a correction operation on the stress simulation model includes increasing the values ​​of M and N to re-divide the first modeling region.

Images