Time sequence control system, control method thereof and display device

Abstract

The invention provides a time sequence control system, a control method thereof and a display device, relates to the technical field of display, and is used for solving the problems that in a display product, the time sequence of power-on and power-off work among all driving chips is difficult to control, so that the driving chips are in an uncertain state, a display panel generates charge residues, and the display effect is poor. And therefore, the problem of picture flicker or abnormal display is solved. In the sequential control system, a control circuit provides control information for an enable circuit and provides a basic power supply signal for a power supply management circuit; the enabling circuit outputs a power supply enabling signal to the power supply management circuit and outputs a corresponding controlled enabling signal to the controlled circuit under the control of the control information; the power supply management circuit enters a standby state or a working state under the control of the power supply enable signal, and can generate a target power supply signal according to the basic power supply signal in the working state; and the controlled circuit enters a standby state or a working state under the control of the controlled enable signal and the target power supply signal.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a timing control system, a control method thereof, and a display device. Background Art

[0002] With the continuous development of display technologies, the application fields of display products are becoming more and more extensive, and correspondingly, people's requirements for the display quality of display products are also getting higher and higher. A display product generally includes a display area and a peripheral area. The display area includes a plurality of sub-pixels for display, and the peripheral area includes a driving circuit structure for driving the sub-pixels to implement the display function. The driving circuit structure includes various types of driving chips, and too many driving chips will bring the following problems: it is difficult to control the timing of power-on and power-off operations between the driving chips, and improper power-on and power-off will cause the driving chips to be in an uncertain state, resulting in charge residue on the display panel, thereby causing screen flickering or abnormal display. Summary of the Invention

[0003] The purpose of the present invention is to provide a timing control system, a control method thereof, and a display device, which are used to solve the problem that in a display product, it is difficult to control the timing of power-on and power-off operations between the driving chips, resulting in the driving chips being in an uncertain state, causing charge residue on the display panel, thereby causing screen flickering or abnormal display.

[0004] To achieve the above purpose, the present invention provides the following technical solutions:

[0005] A first aspect of the present invention provides a timing control system, which is characterized by including: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit;

[0006] The control circuit is used to provide control information to the enable circuit and provide a basic power signal to the power management circuit;

[0007] The enable circuit is used to output a power enable signal to the power management circuit and output a corresponding controlled enable signal to the controlled circuit under the control of the control information;

[0008] The power management circuit is used to enter a standby state under the control of the power enable signal; or, enter a working state under the control of the power enable signal, generate a target power signal according to the basic power signal, and transmit the target power signal to the corresponding controlled circuit;

[0009] The controlled circuit is used to enter a standby state or a working state under the control of the controlled enable signal and the target power signal.

[0010] Optionally, when the timing control system transitions from the standby state to the working state:

[0011] The control circuit is specifically configured to provide first control information to the enable circuit, and the first control information indicates outputting a power signal to the enable circuit;

[0012] The enable circuit is specifically configured to output a first power enable signal to the power management circuit after receiving the first control information, and the first power enable signal indicates that the power management circuit enters the working state;

[0013] The power management circuit is specifically configured to generate a target power signal based on the basic power signal after receiving the first power enable signal, and transmit the target power signal to the corresponding controlled circuit;

[0014] The enable circuit is specifically configured to continue to output a corresponding first controlled enable signal to the controlled circuit, and the first controlled enable signal indicates that the controlled circuit enters the working state;

[0015] The controlled circuit is specifically configured to enter the working state after receiving the first controlled enable signal and the target power signal;

[0016] And / or,

[0017] When the timing control system transitions from the working state to the standby state:

[0018] The control circuit is specifically configured to provide second control information to the enable circuit, and the second control information indicates stopping outputting a power signal to the enable circuit;

[0019] The enable circuit is specifically configured to output a corresponding second controlled enable signal to the controlled circuit after receiving the second control information, and the second controlled enable signal indicates that the controlled circuit enters the standby state;

[0020] The enable circuit is specifically configured to continue to output a second power enable signal to the power management circuit, and the second power enable signal indicates that the power management circuit enters the standby state;

[0021] The power management circuit is specifically configured to enter the standby state after receiving the second power enable signal, and the power management circuit stops generating the target power signal.

[0022] Optionally, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0023] When the timing control system transitions from the standby state to the working state, the enabling circuit is specifically configured to: first output a corresponding first controlled enabling signal to the GAMMA chip, and this first controlled enabling signal instructs the GAMMA chip to enter the working state; then output a corresponding first controlled enabling signal to the level conversion chip, and this first controlled enabling signal instructs the level conversion chip to enter the working state;

[0024] and / or,

[0025] When the timing control system transitions from the working state to the standby state, the enabling circuit is specifically configured to: first output a corresponding second controlled enabling signal to the level conversion chip, and this second controlled enabling signal instructs the level conversion chip to enter the standby state; then output a corresponding second controlled enabling signal to the GAMMA chip, and this second controlled enabling signal instructs the GAMMA chip to enter the standby state.

[0026] Optionally, the control circuit is further configured to provide instruction information to the enabling circuit, and the instruction information indicates the timings corresponding to each power enabling signal and each controlled enabling signal;

[0027] The enabling circuit is configured to output a power enabling signal to the power management circuit and output a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

[0028] Optionally, the timing control system further includes a timing control chip; the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0029] The power management circuit is configured to generate a first target power signal, a second target power signal, and a third target power signal according to the basic power signal, and transmit the first target power signal to the timing control chip, transmit the second target power signal to the GAMMA chip, and transmit the third target power signal to the level conversion chip.

[0030] Based on the technical solution of the above timing control system, a second aspect of the present invention provides a display device including the above timing control system.

[0031] Based on the technical solution of the above timing control system, a third aspect of the present invention provides a timing control method applied to a timing control system, and the timing control system includes: a control circuit, an enabling circuit, a power management circuit, and at least one controlled circuit; the timing control method includes:

[0032] The control circuit provides control information to the enabling circuit and provides a basic power signal to the power management circuit;

[0033] Under the control of the control information, the enabling circuit outputs a power enabling signal to the power management circuit and a corresponding controlled enabling signal to the controlled circuit;

[0034] Under the control of the power enabling signal, the power management circuit enters the standby state; or, under the control of the power enabling signal, it enters the working state, generates a target power signal according to the basic power signal, and transmits the target power signal to the corresponding controlled circuit;

[0035] Under the control of the enabling signal and the target power signal, the controlled circuit enters the standby state or the working state.

[0036] Optionally, when the timing control system transitions from the standby state to the working state, the timing control method specifically includes:

[0037] The control circuit provides first control information to the enabling circuit, and the first control information instructs to output a power signal to the enabling circuit;

[0038] After receiving the first control information, the enabling circuit outputs a first power enabling signal to the power management circuit, and the first power enabling signal instructs the power management circuit to enter the working state;

[0039] After receiving the first power enabling signal, the power management circuit generates a target power signal according to the basic power signal and transmits the target power signal to the corresponding controlled circuit;

[0040] The enabling circuit continues to output a corresponding first controlled enabling signal to the controlled circuit, and the first controlled enabling signal instructs the controlled circuit to enter the working state;

[0041] After receiving the first controlled enabling signal and the target power signal, the controlled circuit enters the working state;

[0042] and / or,

[0043] When the timing control system transitions from the working state to the standby state, the timing control method specifically includes:

[0044] The control circuit provides second control information to the enabling circuit, and the second control information instructs to stop outputting a power signal to the enabling circuit;

[0045] After receiving the second control information, the enabling circuit outputs a corresponding second controlled enabling signal to the controlled circuit, and the second controlled enabling signal instructs the controlled circuit to enter the standby state;

[0046] The enabling circuit continues to output a second power enabling signal to the power management circuit, and the second power enabling signal instructs the power management circuit to enter a standby state;

[0047] After receiving the second power enabling signal, the power management circuit enters a standby state, and the power management circuit stops generating the target power signal.

[0048] Optionally, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0049] When the timing control system transitions from the standby state to the working state, the step of the enabling circuit continuing to output the corresponding first controlled enabling signal to the controlled circuit specifically includes:

[0050] The enabling circuit first outputs the corresponding first controlled enabling signal to the GAMMA chip, and the first controlled enabling signal instructs the GAMMA chip to enter the working state; the enabling circuit then outputs the corresponding first controlled enabling signal to the level conversion chip, and the first controlled enabling signal instructs the level conversion chip to enter the working state;

[0051] and / or,

[0052] When the timing control system transitions from the working state to the standby state, the step of the enabling circuit outputting the corresponding second controlled enabling signal to the controlled circuit after receiving the second control information specifically includes:

[0053] The enabling circuit first outputs the corresponding second controlled enabling signal to the level conversion chip, and the second controlled enabling signal instructs the level conversion chip to enter the standby state; the enabling circuit then outputs the corresponding second controlled enabling signal to the GAMMA chip, and the second controlled enabling signal instructs the GAMMA chip to enter the standby state.

[0054] Optionally, the timing control method further includes:

[0055] The control circuit provides instruction information to the enabling circuit, and the instruction information indicates the timings corresponding to the power enabling signals and the controlled enabling signals;

[0056] The enabling circuit outputs the power enabling signal to the power management circuit and outputs the corresponding controlled enabling signal to the controlled circuit according to the instruction information.

[0057] In the technical solution provided by the present invention, an enable circuit is provided in the timing control system. The enable circuit is controlled by the control circuit and can output a power enable signal for controlling the power management circuit and a controlled enable signal for controlling the controlled circuit, so that the power management circuit and each controlled circuit can be independently controlled by the received corresponding enable signal, that is, according to the specific type of the received enable signal, the switching between the standby state and the working state is realized. Therefore, in the technical solution provided by the present invention, by setting the enable circuit, the flexible control of the power-on and power-off working timings of the power management circuit and each controlled circuit is realized, the limitation of only relying on the power signal to control each controlled circuit before is solved, and the problem that the signals for controlling each controlled circuit are too single to realize the independent control between each controlled circuit well is overcome.

[0058] Therefore, in the technical solution provided by the present invention, by setting the enable circuit, the overall control of the power-on and power-off working timings of the power management circuit and each controlled circuit can be realized, so that the power management circuit and each controlled circuit can work according to the ideal timings, ensuring the stability of the system operation. When applying the timing control system to a display product, it can solve the problem that it is difficult to control the power-on and power-off working timings between each driving chip (i.e., the controlled circuit) in the display product, resulting in an uncertain state of the driving chip, causing charge residue on the display panel, and thus causing problems such as screen flicker or abnormal display.

[0059] Moreover, in the technical solution provided by the present invention, the enable circuit is independent of each chip structure and is only controlled by the control circuit and does not need to be powered by the power management circuit. Therefore, when the entire timing control system is in the standby state, the power management circuit can be controlled to be in a completely non-working standby state, that is, the power management circuit does not need to generate any power signal for external supply, minimizing the power consumption of the entire timing control system. Description of the Drawings

[0060] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0061] Figure 1 is a schematic block diagram of the timing control system provided by an embodiment of the present invention;

[0062] Figure 2 is a power-on and power-off schematic diagram of the timing control method provided by an embodiment of the present invention. Detailed Embodiments

[0063] To further illustrate the timing control system, its control method, and the display device provided by the embodiments of the present invention, a detailed description will be given below with reference to the accompanying drawings of the specification.

[0064] Please refer to Figure 1 and Figure 2 , the embodiments of the present invention provide a timing control system, including: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit (such as: a GAMMA chip, a level conversion chip);

[0065] The control circuit is configured to provide control information K1 to the enable circuit and a basic power supply signal PPVCC to the power management circuit;

[0066] The enable circuit is configured to output a power enable signal EN1 to the power management circuit and corresponding controlled enable signals (such as: EN2, EN3) to the controlled circuit under the control of the control information K1;

[0067] The power management circuit is configured to enter a standby state under the control of the power enable signal; or, enter a working state under the control of the power enable signal, generate a target power supply signal according to the basic power supply signal PPVCC, and transmit the target power supply signal to the corresponding controlled circuit;

[0068] The controlled circuit is configured to enter a standby state or a working state under the control of the controlled enable signal and the target power supply signal.

[0069] Exemplarily, the control circuit includes a host system, the enable circuit includes an enable chip (EnableIC), the power management circuit includes a power management chip, and the controlled circuit includes a GAMMA chip (PGAMMA IC) and a level conversion chip (PLS), but is not limited thereto. It should be noted that in addition to the GAMMA chip and the level conversion chip, the controlled circuit may further include a timing control chip, a source driver, a gate driver, etc.

[0070] Exemplarily, the timing control system is applied to a display device. The display device adopts the Gate On Array technology, forms a shift register unit GOA on the array substrate of the display device, and the level conversion chip is used to generate signals required by the shift register unit GOA. The GAMMA chip is used to generate the GAMMA voltage required by the display device.

[0071] Exemplarily, the control information provided by the control circuit to the enable circuit is used to indicate the working state of the enable circuit. For example, the control information includes outputting a power signal to the enable circuit or stopping outputting a power signal to the enable circuit. Based on this control information, the enable circuit controls the type of the output enable signal. For example, it outputs a first set of enable signals or a second set of enable signals. The first set of enable signals includes a first power enable signal EN11 and first controlled enable signals (such as EN21, EN31), and the second set of enable signals includes a second power enable signal EN12 and second controlled enable signals (such as EN22, EN32). It can be set that the first power enable signal EN11 and the first controlled enable signals (such as EN21, EN31) include high-level signals, and the second power enable signal EN12 and the second controlled enable signals (such as EN22, EN32) include low-level signals, but it is not limited thereto.

[0072] Exemplarily, the power management circuit is controlled by two sets of signals, namely a power enable signal EN1 and a basic power signal PPVCC. The basic power signal PPVCC is used to supply power to the power management circuit, and the power management circuit can also generate a target power signal based on the basic power signal PPVCC. The power management circuit is used to enter the standby state under the control of the power enable signal or enter the working state under the control of the power enable signal. When the power management circuit enters the standby state, it stops generating the target power signal, and when the power management circuit enters the working state, it generates the target power signal.

[0073] According to the specific structure of the above timing control system, it can be known that an enable circuit is provided in the timing control system provided by the embodiment of the present invention. This enable circuit is controlled by the control circuit and can output a power enable signal for controlling the power management circuit and a controlled enable signal for controlling the controlled circuit, so that both the power management circuit and each controlled circuit can be independently controlled by the corresponding received enable signal, that is, according to the specific type of the received enable signal, it realizes the switching between the standby state and the working state. Therefore, in the timing control system provided by the embodiment of the present invention, by setting the enable circuit, the power-on and power-off working timings of the power management circuit and each controlled circuit are flexibly controlled, solving the limitation of only controlling each controlled circuit by the power signal before, and overcoming the problem that the signals for controlling each controlled circuit are too single to achieve good independent control between each controlled circuit.

[0074] Therefore, in the timing control system provided by the embodiments of the present invention, by setting the enable circuit, it is possible to overall control the power-on and power-off working timings of the power management circuit and each controlled circuit, enabling the power management circuit and each controlled circuit to work according to the ideal timings, thus ensuring the stability of the system operation. When applying the timing control system to a display product, it can solve the problem that it is difficult to control the power-on and power-off working timings between each driving chip (i.e., the controlled circuit) in the display product, resulting in an uncertain state of the driving chip, causing charge residue on the display panel, and thus causing problems such as screen flickering or abnormal display.

[0075] Moreover, in the timing control system provided by the embodiments of the present invention, the enable circuit is independent of each chip structure and is only controlled by the control circuit, without being powered by the power management circuit. Therefore, when the entire timing control system is in the standby state, it is possible to control the power management circuit to be in a completely non-operating standby state, that is, there is no need for the power management circuit to generate any power signals for external supply, minimizing the power consumption of the entire timing control system.

[0076] As Figure 2 shown, in some embodiments, when the timing control system transitions from the standby state to the working state:

[0077] The control circuit is specifically configured to provide first control information to the enable circuit, and the first control information instructs to output a power signal to the enable circuit;

[0078] The enable circuit is specifically configured to, after receiving the first control information, output a first power enable signal EN11 to the power management circuit, and the first power enable signal EN11 instructs the power management circuit to enter the working state;

[0079] The power management circuit is specifically configured to, after receiving the first power enable signal EN11, generate a target power signal according to the basic power signal PPVCC, and transmit the target power signal to the corresponding controlled circuit;

[0080] The enable circuit is specifically configured to continue to output corresponding first controlled enable signals (such as: EN21, EN31) to the controlled circuit, and the first controlled enable signals (such as: EN21, EN31) instruct the controlled circuit to enter the working state;

[0081] The controlled circuit is specifically configured to, after receiving the first controlled enable signal (such as: EN21, EN31) and the target power signal, enter the working state;

[0082] Exemplarily, when the timing control system transitions from the standby state to the working state, that is, when the timing control system is powered on, the enabling circuit first outputs the first power enabling signal EN11, and then outputs the first controlled enabling signals (such as EN21, EN31). When the timing control system includes at least two controlled circuits, the first controlled enabling signals (such as EN21, EN31) received by each controlled circuit can also have a sequence.

[0083] Exemplarily, when the timing control system is in the standby state and the working state, the control circuit provides the basic power signal PPVCC to the power management circuit.

[0084] In some embodiments, when the timing control system transitions from the working state to the standby state:

[0085] The control circuit is specifically configured to provide second control information to the enabling circuit, and the second control information instructs to stop outputting the power signal to the enabling circuit;

[0086] The enabling circuit is specifically configured to, after receiving the second control information, output corresponding second controlled enabling signals (such as EN22, EN32) to the controlled circuits, and the second controlled enabling signals (such as EN22, EN32) instruct the controlled circuits to enter the standby state;

[0087] The enabling circuit is specifically configured to continue to output the second power enabling signal EN12 to the power management circuit, and the second power enabling signal EN12 instructs the power management circuit to enter the standby state;

[0088] The power management circuit is specifically configured to, after receiving the second power enabling signal EN12, enter the standby state, and the power management circuit stops generating the target power signal.

[0089] Exemplarily, when the timing control system transitions from the working state to the standby state, that is, when the timing control system is powered off, the enabling circuit first outputs corresponding second controlled enabling signals (such as EN22, EN32) to the controlled circuits, and then outputs the second power enabling signal EN12. When the timing control system includes at least two controlled circuits, the second controlled enabling signals (such as EN22, EN32) received by each controlled circuit can also have a sequence.

[0090] In the timing control system provided by the above embodiment, the enabling circuit first outputs corresponding second controlled enabling signals (such as: EN22, EN32) to the controlled circuit, and then outputs the second power enabling signal EN12, so that the controlled circuit is in a standby state first, and then the power management circuit is in a standby state. This way is beneficial to improving the discharge time of the controlled circuit, enabling the controlled circuit to discharge fully. When the timing control system is applied to a display product, it can make the display product discharge more fully.

[0091] In the standby state of the timing control system provided by the above embodiment, the control circuit continues to provide the basic power signal PPVCC to the power management circuit, the enabling circuit outputs the second power enabling signal EN12 and the second controlled enabling signals (such as: EN22, EN32), and both the power management circuit and the controlled circuit are in the standby state. This can not only save power consumption, but also when the timing control system switches from the standby state to the working state, by controlling the enabling circuit to output the first power enabling signal EN11 and the first controlled enabling signals (such as: EN21, EN31), the power management circuit and the controlled circuit can be quickly switched to the working state, achieving a high response speed.

[0092] In some embodiments, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0093] When the timing control system switches from the standby state to the working state, the enabling circuit is specifically configured to: first output a corresponding first controlled enabling signal (such as: EN21) to the GAMMA chip, and this first controlled enabling signal (such as: EN21) instructs the GAMMA chip to enter the working state; then output a corresponding first controlled enabling signal (such as: EN31) to the level conversion chip, and this first controlled enabling signal (such as: EN31) instructs the level conversion chip to enter the working state;

[0094] and / or,

[0095] When the timing control system switches from the working state to the standby state, the enabling circuit is specifically configured to: first output a corresponding second controlled enabling signal (such as: EN32) to the level conversion chip, and this second controlled enabling signal (such as: EN32) instructs the level conversion chip to enter the standby state; then output a corresponding second controlled enabling signal (such as: EN22) to the GAMMA chip, and this second controlled enabling signal (such as: EN22) instructs the GAMMA chip to enter the standby state.

[0096] Exemplarily, the timing control system further includes a timing control chip TCON IC; the at least one controlled circuit includes a GAMMA chip and a level conversion chip; the power management circuit is configured to generate a first target power signal Power1, a second target power signal Power2, and a third target power signal Power3 according to the basic power signal PPVCC, and transmit the first target power signal Power1 to the timing control chip TCON IC, transmit the second target power signal Power2 to the GAMMA chip, and transmit the third target power signal Power3 to the level conversion chip.

[0097] Exemplarily, the timing control system further includes a driver chip Driver IC, and the power management circuit is further configured to transmit the second target power signal Power2 to the driver chip Driver IC.

[0098] Exemplarily, when the timing control system transitions from the standby state to the working state, the power management circuit starts to work after receiving the first power enable signal EN11, generates the first target power signal Power1 and transmits it to the timing control chip, generates the second target power signal Power2 and transmits it to the GAMMA chip, and generates the third target power signal Power3 and transmits it to the level conversion chip. At this time, both the GAMMA chip and the level conversion chip are waiting for the corresponding first controlled enable signals (such as: EN21, EN31). When the GAMMA chip receives the corresponding first controlled enable signal (such as: EN21, EN31), the GAMMA chip starts to work. When the level conversion chip receives the corresponding first controlled enable signal (such as: EN21, EN31), the level conversion chip starts to work.

[0099] Exemplarily, when the timing control system transitions from the working state to the standby state, the enable circuit first outputs the corresponding second controlled enable signals (such as: EN22, EN32) to the level conversion chip to make the level conversion chip enter the standby state, realizing the discharge of the level conversion chip, and making the display panel enter the discharge state according to the setting; then the enable circuit outputs the corresponding second controlled enable signals (such as: EN22, EN32) to the GAMMA chip, and the GAMMA chip enters the standby state, realizing the discharge of the GAMMA chip; finally, the enable circuit outputs the second power enable signal EN12 to the power management circuit, and the power management circuit enters the standby state, realizing the discharge of the power management circuit and stopping generating each target power signal.

[0100] In the timing control system provided by the above embodiments, by setting the enable circuit, it is possible to overall control the power-on and power-off working timings of the power management circuit and each controlled circuit, enabling the power management circuit and each controlled circuit to work according to the ideal timings, thus ensuring the stability of the system operation. Meanwhile, during power-on, it ensures that each chip powers on in sequence, reducing the display product's startup screen anomalies and flashing screen phenomena; during power-off, it enables the level conversion chip that controls the discharge of the display panel to enter the standby state first. After ensuring that the display panel is fully discharged, other ICs then enter the standby state one after another, avoiding problems such as display product's shutdown afterimages, flashing screens, and charge accumulation.

[0101] In some embodiments, the control circuit is further configured to provide instruction information to the enable circuit, and the instruction information indicates the timings corresponding to each power enable signal and each controlled enable signal;

[0102] The enable circuit is configured to output a power enable signal to the power management circuit and output corresponding controlled enable signals to the controlled circuits according to the instruction information.

[0103] Exemplarily, a register is included in the enable circuit, and the instruction information is stored in the register, but is not limited thereto.

[0104] Exemplarily, the timings corresponding to each power enable signal and each controlled enable signal can be adjusted according to actual needs, so as to realize the adjustment of the power-on and power-off sequences among the chips. For example: specifically refer to Figure 2 , Figure 2 In, t1 represents the time interval between the first power enable signal EN11 and the first controlled enable signal EN21 during power-on, t2 represents the time interval between the first controlled enable signal EN21 and the first controlled enable signal EN31, t3 represents the time interval between the second controlled enable signal EN32 and the second controlled enable signal EN22, and t4 represents the time interval between the second controlled enable signal EN22 and the second power enable signal EN12. By changing the instruction information, t1, t2, t3, and t4 can be adjusted.

[0105] Exemplarily, the control circuit can program and modify the internal register of the enable circuit through I2C (Inter-Integrated Circuit, a two-wire bidirectional synchronous serial bus), that is, adjust t1, t2, t3, and t4 to obtain different power-on and power-off timings.

[0106] In the timing control system provided by the above embodiments, the timings of each enable signal can be adjusted by the control circuit, with higher controllability and stronger flexibility.

[0107] An embodiment of the present invention further provides a display device, including the timing control system provided by the above embodiments.

[0108] Exemplarily, the display device includes a liquid crystal display device, an organic light-emitting diode display device, etc., but is not limited thereto.

[0109] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc. Among them, the display device further includes a flexible circuit board, a printed circuit board, a backplane, etc.

[0110] When the display device provided by the embodiment of the present invention includes the above-mentioned timing control system, it can solve the problem that it is difficult to control the power-on and power-off timing between each driving chip (i.e., the controlled circuit) in the display device, resulting in an uncertain state of the driving chip, causing charge residue on the display panel in the display device, thereby causing screen flicker or abnormal display. When the display device provided by the embodiment of the present invention includes the above-mentioned timing control system, it is beneficial to reduce the overall power consumption of the display device.

[0111] The embodiment of the present invention also provides a timing control method, which is applied to a timing control system. The timing control system includes: a control circuit, an enable circuit, a power management circuit, and at least one controlled circuit; the timing control method includes:

[0112] The control circuit provides control information to the enable circuit and provides a basic power supply signal PPVCC to the power management circuit;

[0113] The enable circuit outputs a power enable signal to the power management circuit and outputs a corresponding controlled enable signal to the controlled circuit under the control of the control information;

[0114] The power management circuit enters the standby state under the control of the power enable signal; or, enters the working state under the control of the power enable signal, generates a target power supply signal according to the basic power supply signal PPVCC, and transmits the target power supply signal to the corresponding controlled circuit;

[0115] The controlled circuit enters the standby state or the working state under the control of the enable signal and the target power supply signal.

[0116] In the timing control method provided by the embodiment of the present invention, the enabling circuit is controlled by the control circuit and can output a power enabling signal for controlling the power management circuit and a controlled enabling signal for controlling the controlled circuit, so that the power management circuit and each controlled circuit can be independently controlled by the received corresponding enabling signal, that is, according to the specific type of the received enabling signal, the switching between the standby state and the working state is realized. Therefore, in the timing control method provided by the embodiment of the present invention, by setting the enabling circuit, the flexible control of the power-on and power-off working timings of the power management circuit and each controlled circuit is realized, the limitation of only relying on the power signal to control each controlled circuit before is solved, and the problem that the signals for controlling each controlled circuit are too single to realize the independent control between each controlled circuit well is overcome.

[0117] Therefore, in the timing control method provided by the embodiment of the present invention, by setting the enabling circuit, the overall control of the power-on and power-off working timings of the power management circuit and each controlled circuit can be realized, so that the power management circuit and each controlled circuit work according to the ideal timings, ensuring the stability of the system operation. When applying the timing control system to a display product, it can solve the problem that it is difficult to control the power-on and power-off working timings between each driving chip (i.e., the controlled circuit) in the display product, resulting in the driving chip being in an uncertain state, causing charge residue on the display panel, and thus causing problems such as screen flicker or abnormal display.

[0118] Moreover, in the timing control method provided by the embodiment of the present invention, the enabling circuit is independent of each chip structure and is only controlled by the control circuit and does not need to be powered by the power management circuit. Therefore, when the entire timing control system is in the standby state, the power management circuit can be controlled to be in a completely non-working standby state, that is, the power management circuit does not need to generate any power signal for external supply, minimizing the power consumption of the entire timing control system.

[0119] In some embodiments, when the timing control system transitions from the standby state to the working state, the timing control method specifically includes:

[0120] The control circuit provides first control information to the enabling circuit, and the first control information instructs to output a power signal to the enabling circuit;

[0121] After receiving the first control information, the enabling circuit outputs a first power enabling signal EN11 to the power management circuit, and the first power enabling signal EN11 instructs the power management circuit to enter the working state;

[0122] After receiving the first power enable signal EN11, the power management circuit generates a target power signal based on the basic power signal PPVCC and transmits the target power signal to the corresponding controlled circuit;

[0123] The enable circuit continues to output corresponding first controlled enable signals (such as EN21, EN31) to the controlled circuit, and the first controlled enable signals (such as EN21, EN31) instruct the controlled circuit to enter the working state;

[0124] After receiving the first controlled enable signal (such as EN21, EN31) and the target power signal, the controlled circuit enters the working state;

[0125] And / or, when the timing control system transitions from the working state to the standby state, the timing control method specifically includes:

[0126] The control circuit provides second control information to the enable circuit, and the second control information instructs to stop outputting the power signal to the enable circuit;

[0127] After receiving the second control information, the enable circuit outputs corresponding second controlled enable signals (such as EN22, EN32) to the controlled circuit, and the second controlled enable signals (such as EN22, EN32) instruct the controlled circuit to enter the standby state;

[0128] The enable circuit continues to output the second power enable signal EN12 to the power management circuit, and the second power enable signal EN12 instructs the power management circuit to enter the standby state;

[0129] After receiving the second power enable signal EN12, the power management circuit enters the standby state, and the power management circuit stops generating the target power signal.

[0130] In the timing control method provided in the above embodiment, the enable circuit first outputs corresponding second controlled enable signals (such as EN22, EN32) to the controlled circuit, and then outputs the second power enable signal EN12, so that the controlled circuit is first in the standby state, and then the power management circuit is in the standby state. This method is beneficial to improving the discharge time of the controlled circuit, enabling the controlled circuit to discharge fully. When applying the timing control system to a display product, it can make the display product discharge more fully.

[0131] In the timing control method provided by the above embodiments, in the standby state, the control circuit continues to provide the basic power supply signal PPVCC to the power management circuit, and the enabling circuit outputs the second power supply enabling signal EN12 and the second controlled enabling signals (such as: EN22, EN32). Both the power management circuit and the controlled circuit are in the standby state. This can not only save power consumption, but also, when the timing control system switches from the standby state to the working state, by controlling the enabling circuit to output the first power supply enabling signal EN11 and the first controlled enabling signals (such as: EN21, EN31), the power management circuit and the controlled circuit can be quickly switched to the working state, achieving a high response speed.

[0132] In some embodiments, the at least one controlled circuit includes a GAMMA chip and a level conversion chip;

[0133] When the timing control system switches from the standby state to the working state, the step of the enabling circuit continuing to output the corresponding first controlled enabling signal to the controlled circuit specifically includes:

[0134] The enabling circuit first outputs the corresponding first controlled enabling signal to the GAMMA chip, and this first controlled enabling signal instructs the GAMMA chip to enter the working state; the enabling circuit then outputs the corresponding first controlled enabling signal to the level conversion chip, and this first controlled enabling signal instructs the level conversion chip to enter the working state;

[0135] and / or,

[0136] When the timing control system switches from the working state to the standby state, the step of the enabling circuit outputting the corresponding second controlled enabling signal to the controlled circuit after receiving the second control information specifically includes:

[0137] The enabling circuit first outputs the corresponding second controlled enabling signal to the level conversion chip, and this second controlled enabling signal instructs the level conversion chip to enter the standby state; the enabling circuit then outputs the corresponding second controlled enabling signal to the GAMMA chip, and this second controlled enabling signal instructs the GAMMA chip to enter the standby state.

[0138] In the timing control method provided by the above embodiments, by setting the enable circuit, it is possible to achieve overall control of the power-on and power-off working timings of the power management circuit and each controlled circuit, enabling the power management circuit and each controlled circuit to work according to the ideal timings, thus ensuring the stability of the system operation. At the same time, during power-on, it is ensured that each chip is powered on in sequence, reducing the phenomenon of abnormal startup screens and screen flashing of the display product; during power-off, the level conversion chip that controls the discharge of the display panel first enters the standby state. After ensuring that the display panel is completely discharged, other ICs then enter the standby state one after another, avoiding problems such as shutdown afterimages, screen flashing, and charge accumulation in the display product.

[0139] In some embodiments, the timing control method further includes:

[0140] The control circuit provides instruction information to the enable circuit, and the instruction information indicates the timings corresponding to each power enable signal and each controlled enable signal;

[0141] The enable circuit outputs a power enable signal to the power management circuit and corresponding controlled enable signals to the controlled circuits according to the instruction information.

[0142] In the timing control method provided by the above embodiments, the timings of the enable signals can be adjusted by the control circuit, with higher controllability and stronger flexibility.

[0143] In the method embodiments of the present invention, the sequence numbers of the steps cannot be used to limit the sequence of the steps. For those of ordinary skill in the art, without creative efforts, the changes in the sequence of the steps are also within the protection scope of the present invention.

[0144] It should be noted that the embodiments in this specification are all described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the product embodiments, they are described relatively simply, and the relevant parts can refer to the partial description of the product embodiments.

[0145] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this invention belongs. The "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected", "coupled" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0146] It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element can be "directly" on or under the other element, or intervening elements may be present.

[0147] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner.

[0148] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A timing control system, characterized in that, it includes: a control circuit, an enable circuit, a power management circuit and at least one controlled circuit; the control circuit is configured to provide control information to the enable circuit and a basic power signal to the power management circuit; the enable circuit is configured to output a power enable signal to the power management circuit and a corresponding controlled enable signal to the controlled circuit under the control of the control information; the power management circuit is configured to enter a standby state under the control of the power enable signal; or, enter a working state under the control of the power enable signal, generate a target power signal according to the basic power signal, and transmit the target power signal to the corresponding controlled circuit; the controlled circuit is configured to enter a standby state or a working state under the control of the controlled enable signal and the target power signal.

2. The timing control system according to claim 1, characterized in that, when the timing control system transitions from the standby state to the working state: the control circuit is specifically configured to provide first control information to the enable circuit, and the first control information indicates to output a power signal to the enable circuit; the enable circuit is specifically configured to output a first power enable signal to the power management circuit after receiving the first control information, and the first power enable signal indicates that the power management circuit enters the working state; the power management circuit is specifically configured to generate a target power signal according to the basic power signal and transmit the target power signal to the corresponding controlled circuit after receiving the first power enable signal; the enable circuit is specifically configured to continue to output a corresponding first controlled enable signal to the controlled circuit, and the first controlled enable signal indicates that the controlled circuit enters the working state; the controlled circuit is specifically configured to enter the working state after receiving the first controlled enable signal and the target power signal; and / or, when the timing control system transitions from the working state to the standby state: the control circuit is specifically configured to provide second control information to the enable circuit, and the second control information indicates to stop outputting a power signal to the enable circuit; the enable circuit is specifically configured to output a corresponding second controlled enable signal to the controlled circuit after receiving the second control information, and the second controlled enable signal indicates that the controlled circuit enters the standby state; the enable circuit is specifically configured to continue to output a second power enable signal to the power management circuit, and the second power enable signal indicates that the power management circuit enters the standby state; the power management circuit is specifically configured to enter the standby state after receiving the second power enable signal, and the power management circuit stops generating the target power signal.

3. The timing control system according to claim 2, characterized in that, the at least one controlled circuit includes a GAMMA chip and a level conversion chip; When the timing control system transitions from the standby state to the working state, the enabling circuit is specifically configured to: first output a corresponding first controlled enabling signal to the GAMMA chip, and this first controlled enabling signal instructs the GAMMA chip to enter the working state; then output a corresponding first controlled enabling signal to the level conversion chip, and this first controlled enabling signal instructs the level conversion chip to enter the working state; and / or, When the timing control system transitions from the working state to the standby state, the enabling circuit is specifically configured to: first output a corresponding second controlled enabling signal to the level conversion chip, and this second controlled enabling signal instructs the level conversion chip to enter the standby state; then output a corresponding second controlled enabling signal to the GAMMA chip, and this second controlled enabling signal instructs the GAMMA chip to enter the standby state.

4. The timing control system according to claim 1, wherein, the control circuit is further configured to provide instruction information to the enabling circuit, and the instruction information indicates the timings corresponding to each power enabling signal and each controlled enabling signal; the enabling circuit is configured to output a power enabling signal to the power management circuit and output a corresponding controlled enabling signal to the controlled circuit according to the instruction information.

5. The timing control system according to claim 1, wherein, the timing control system further includes a timing control chip; the at least one controlled circuit includes a GAMMA chip and a level conversion chip; the power management circuit is configured to generate a first target power signal, a second target power signal, and a third target power signal according to the basic power signal, and transmit the first target power signal to the timing control chip, transmit the second target power signal to the GAMMA chip, and transmit the third target power signal to the level conversion chip.

6. A display device, wherein, it includes the timing control system according to any one of claims 1 to 5.

7. A timing control method, wherein, it is applied to a timing control system, and the timing control system includes: a control circuit, an enabling circuit, a power management circuit, and at least one controlled circuit; the timing control method includes: the control circuit provides control information to the enabling circuit and provides a basic power signal to the power management circuit; the enabling circuit outputs a power enabling signal to the power management circuit and outputs a corresponding controlled enabling signal to the controlled circuit under the control of the control information; the power management circuit enters the standby state under the control of the power enabling signal; or enters the working state under the control of the power enabling signal, generates a target power signal according to the basic power signal, and transmits the target power signal to the corresponding controlled circuit; the controlled circuit enters the standby state or the working state under the control of the enabling signal and the target power signal.

8. The timing control method according to claim 7, wherein, when the timing control system transitions from the standby state to the working state, the timing control method specifically includes: The control circuit provides first control information to the enable circuit, and the first control information indicates to output a power signal to the enable circuit; After receiving the first control information, the enable circuit outputs a first power enable signal to the power management circuit, and the first power enable signal indicates that the power management circuit enters a working state; After receiving the first power enable signal, the power management circuit generates a target power signal according to the basic power signal and transmits the target power signal to the corresponding controlled circuit; The enable circuit continues to output a corresponding first controlled enable signal to the controlled circuit, and the first controlled enable signal indicates that the controlled circuit enters a working state; After receiving the first controlled enable signal and the target power signal, the controlled circuit enters a working state; and / or When the timing control system transitions from a working state to a standby state, the timing control method specifically includes: The control circuit provides second control information to the enable circuit, and the second control information indicates to stop outputting a power signal to the enable circuit; After receiving the second control information, the enable circuit outputs a corresponding second controlled enable signal to the controlled circuit, and the second controlled enable signal indicates that the controlled circuit enters a standby state; The enable circuit continues to output a second power enable signal to the power management circuit, and the second power enable signal indicates that the power management circuit enters a standby state; After receiving the second power enable signal, the power management circuit enters a standby state, and the power management circuit stops generating the target power signal.

9. The timing control method according to claim 8, wherein the at least one controlled circuit includes a GAMMA chip and a level conversion chip; When the timing control system transitions from a standby state to a working state, the step that the enable circuit continues to output a corresponding first controlled enable signal to the controlled circuit specifically includes: The enable circuit first outputs a corresponding first controlled enable signal to the GAMMA chip, and the first controlled enable signal indicates that the GAMMA chip enters a working state; the enable circuit then outputs a corresponding first controlled enable signal to the level conversion chip, and the first controlled enable signal indicates that the level conversion chip enters a working state; and / or When the timing control system transitions from a working state to a standby state, the step that the enable circuit outputs a corresponding second controlled enable signal to the controlled circuit after receiving the second control information specifically includes: The enable circuit first outputs a corresponding second controlled enable signal to the level conversion chip, and the second controlled enable signal indicates that the level conversion chip enters a standby state; the enable circuit then outputs a corresponding second controlled enable signal to the GAMMA chip, and the second controlled enable signal indicates that the GAMMA chip enters a standby state.

10. The timing control method according to claim 7, wherein the timing control method further includes: The control circuit provides instruction information to the enable circuit, and the instruction information indicates the timings corresponding to the respective power enable signals and the respective controlled enable signals; The enable circuit outputs a power enable signal to the power management circuit and outputs a corresponding controlled enable signal to the controlled circuit according to the instruction information.

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