An intelligent control system and method for the quality of semiconductor production process

Abstract

The present invention relates to the technical field of semiconductor device testing, and specifically to an intelligent control system and method for the quality of semiconductor production processes, which obtains the target application scenario information of the semiconductor device to be tested; uses the first intelligent test model to generate a baseline test severity configuration that matches the target application scenario according to the target application scenario information, and the baseline test severity configuration includes the test limit values of multiple test parameters, test item selection, and test conditions; during the test process, it obtains and analyzes the quality feedback data and upstream process data related to the semiconductor device to be tested in real time to obtain semiconductor real-time data; uses the semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjusts the baseline test severity configuration, and generates a final test severity configuration; generates a control instruction based on the final test severity configuration to test the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device testing, and particularly to an intelligent control system and method for the quality of semiconductor production process. Background Art

[0002] In the semiconductor manufacturing process, performing effective tests or measurements is a core quality control link to ensure the performance and reliability of the final integrated circuit. Semiconductor adaptive testing technology uses historical data, process control monitoring data obtained during the manufacturing process, or real-time test results to dynamically adjust the content and limits of semiconductor testing. Although such technologies have been applied in some links such as wafer sorting and final testing, aiming to improve test coverage or reduce test time. However, the existing technologies still have significant limitations in real-time data integration and dynamic optimization, especially in the ability to use the information during the manufacturing process for immediate test strategy adjustment, which restricts their comprehensive support for quality control in the entire semiconductor manufacturing process.

[0003] For the quality testing in the semiconductor manufacturing process, the adaptive testing technology shows different strategies in different application scenarios. For automotive-grade chips, the testing needs to focus on reliability, and may adopt more stringent test limits and screening methods to identify potential outliers caused by process deviations, ensuring the stability of the device in a harsh environment. In contrast, the testing of consumer-grade chips focuses more on efficiency, and optimizes the process through technologies such as reducing test time. Process control monitoring data, as a key information source for monitoring process consistency and predicting potential quality problems, is crucial for identifying process deviations. However, most of the current technologies use process control monitoring data for post-mortem analysis and lack effective real-time adjustment ability, so that the potential of process control monitoring data to guide dynamic optimization of test strategies during the manufacturing process has not been fully exploited.

[0004] Therefore, an intelligent control system and method for the quality of semiconductor production process are proposed. Summary of the Invention

[0005] The object of the present invention is to provide an intelligent control system and method for the quality of semiconductor production process. By obtaining the target application scenario information of the semiconductor device to be tested; using the first intelligent test model, according to the target application scenario information, generating a baseline test severity configuration that matches the target application scenario, the baseline test severity configuration includes the test limit values of multiple test parameters, test item selection and test conditions; during the test process, obtaining and analyzing in real time the quality feedback data and upstream process data related to the semiconductor device to be tested to obtain semiconductor real-time data; using the semiconductor quality adjustment model, comprehensively analyzing the semiconductor real-time data and the baseline test severity configuration, dynamically adjusting the baseline test severity configuration, and generating a final test severity configuration; generating a control instruction based on the final test severity configuration to test the semiconductor device.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] An intelligent control system for the quality of semiconductor production process, the semiconductor test stage includes:

[0008] An information acquisition module, configured to obtain the target application scenario information of the semiconductor device to be tested, the target application scenario information includes preset reliability requirements, working condition parameters and risk levels;

[0009] A baseline configuration generation module, configured to use the first intelligent test model to generate a baseline test severity configuration that matches the target application scenario according to the target application scenario information, the baseline test severity configuration includes the test limit values of multiple test parameters, test item selection and test conditions;

[0010] A real-time data monitoring module, configured to obtain and analyze in real time the quality feedback data and upstream process data related to the semiconductor device to be tested during the test process to obtain semiconductor real-time data;

[0011] A dynamic adjustment module, configured to use the semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjust the baseline test severity configuration, and generate a final test severity configuration;

[0012] A test control module, configured to generate a control instruction based on the final test severity configuration to test the semiconductor device.

[0013] Preferably, the quality feedback data includes at least one of the pass rate of early test items during the test process, the real-time measurement values of key test parameters, statistical distribution information, spatial failure modes on the wafer map, and failure mode classification results;

[0014] The upstream process data includes the monitored values of key process step parameters from the manufacturing execution system, equipment status information, and fault detection and classification alarms from the upstream process.

[0015] Preferably, the first intelligent test model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer, and an optimization decision layer;

[0016] The target scenario selection layer selects a scenario from the preset automotive safety integrity level, industrial control level, and consumer electronics level based on the target application scenario information, and obtains the working temperature range, allowable failure rate index, and mission profile data based on the scenario;

[0017] The data analysis layer analyzes and quantifies the working temperature range, allowable failure rate index, and stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the working temperature range and the stress test conditions, and generates scenario characteristic parameters;

[0018] The knowledge fusion layer performs multi-modal fusion on the historical test plan library, process design rule library, and the scenario characteristic parameters, and establishes a constraint relationship matrix between test parameters;

[0019] The optimization decision layer performs multi-objective optimization on the constraint relationship matrix, balances the test coverage rate and cost constraints, and generates a baseline test severity configuration; the baseline test severity configuration includes: a gradient configuration plan for test temperature points and heat preservation time, and a dynamic sensitivity parameter configuration for statistical specification limits.

[0020] Preferably, the semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer, and an optimized adjustment parameter output layer;

[0021] The data input layer receives the semiconductor real-time data and the baseline test severity configuration as inputs;

[0022] The data processing layer uses signal processing algorithms and statistical methods to clean and normalize the input data; uses feature extraction algorithms to extract key feature indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional and heterogeneous input data; the key feature indicators include the drift amount of key parameters, volatility indicators, clustering failure mode indices on the wafer map, and the degree of deviation of upstream process parameters from specifications;

[0023] The risk assessment layer includes an anomaly detection unit, an association analysis unit, and a risk quantification unit; the anomaly detection unit obtains the feature index anomaly coefficient through the feature indexes extracted by the isolation forest analysis; the association analysis unit uses association rule mining to analyze key feature indexes to obtain potential feature associations; the risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the feature index anomaly coefficient and the potential feature associations; compares the quality risk level with the baseline test severity configuration to obtain an adjustment strategy;

[0024] The optimization and adjustment parameter output layer outputs an adjustment strategy instruction.

[0025] Preferably, the specific steps for dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include:

[0026] Receive the quality risk level and the adjustment strategy instruction output from the semiconductor quality adjustment model;

[0027] Judge whether the preset adjustment trigger condition is satisfied or there is significant process fluctuation according to the quality risk level and the adjustment strategy instruction; if it is judged that the adjustment trigger condition is satisfied, modify the baseline test severity configuration according to the adjustment strategy instruction to generate the final test severity configuration; if it is judged that the adjustment trigger condition is not satisfied, that is, the model evaluation believes that the current quality is stable and the risk is within the acceptable range, the final test severity configuration remains the same as the baseline test severity configuration.

[0028] An intelligent control method for the quality of the semiconductor production process, semiconductor testing stage:

[0029] S1. Obtain the target application scenario information of the semiconductor device to be tested, where the target application scenario information includes preset reliability requirements, working condition parameters, and risk levels;

[0030] S2. Use the first intelligent test model to generate a baseline test severity configuration that matches the target application scenario according to the target application scenario information, where the baseline test severity configuration includes the test limit values, test item selections, and test conditions of multiple test parameters;

[0031] S3. During the testing process, obtain and analyze the quality feedback data and upstream process data related to the semiconductor device to be tested in real time to obtain semiconductor real-time data;

[0032] S4. Use the semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjust the baseline test severity configuration, and generate the final test severity configuration;

[0033] S5. Generate control instructions based on the generated final test severity configuration and test the semiconductor device.

[0034] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0035] 1. By integrating the first intelligent test model with the target application scenario information, the present invention generates a baseline test severity configuration that meets the preset reliability requirements, working condition parameters, and risk levels, ensuring a high degree of matching between the test plan and the actual usage environment of the device. Using data analysis and knowledge fusion methods, quantitative analysis is performed on temperature range, failure rate, and stress data, the construction of a constraint relationship matrix between test parameters is realized, and the coverage rate and cost are balanced in multi-objective optimization, effectively improving the test accuracy and production efficiency of semiconductor products, while reducing the risks caused by unreasonable test configurations and comprehensively testing the product quality level.

[0036] 2. The present invention proposes a semiconductor quality adjustment model, which realizes the intelligent comprehensive analysis of real-time data and baseline configuration through a four-layer structure of a data input layer, a data processing layer, a risk assessment layer, and an optimized adjustment parameter output layer. Using isolation forest, association rule mining, and statistical methods to accurately extract key feature indicators, quantitatively evaluate process drift and failure risks, and timely identify abnormal situations. By dynamically adjusting the test severity configuration and triggering early warnings based on risk levels and process fluctuations, the test strategy is ensured to be updated in real time, effectively reducing the production defect rate.

[0037] 3. The present invention introduces a real-time data monitoring module in the test stage, effectively integrating quality feedback data and upstream process data to achieve full-scale dynamic monitoring and fault warning. By collecting the passing rates of early test items, measured values of key parameters, and wafer space failure modes, while obtaining manufacturing execution system monitoring parameters, equipment status, and fault alarm information. Using efficient signal processing algorithms and statistical methods to extract key indicators of process drift and quality fluctuations, thereby dynamically adjusting the test strategy, achieving rapid response and risk control for abnormal conditions during the production process, and improving the overall reliability of product testing. Description of the Drawings

[0038] Figure 1 It is a schematic structural diagram of an intelligent control system for semiconductor production process quality provided by the present invention;

[0039] Figure 2 It is a schematic flow diagram of an intelligent control method for semiconductor production process quality provided by the present invention;

[0040] Figure 3 It is a schematic structural diagram of the first intelligent test model provided by an embodiment of the present invention;

[0041] Figure 4Schematic diagram of the semiconductor quality adjustment model provided by the embodiment of the present invention. Detailed implementation manners

[0042] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0043] Based on an intelligent control method for the quality of semiconductor production process, the present invention provides an intelligent control system for the quality of semiconductor production process. For the specific system structure diagram and method flow chart, please refer to Figures 1 to 2 ;

[0044] Embodiment 1

[0045] As an implementation manner of the present invention, referring to Figure 2 S1 in, S1 is applied to the information acquisition module of an intelligent control system for the quality of semiconductor production process. The information acquisition module is used to acquire the target application scenario information of the semiconductor device to be tested, and the target application scenario information includes preset reliability requirements, working condition parameters and risk levels.

[0046] As an implementation manner of the present invention, referring to Figure 2 S2 in, S2 is applied to the baseline configuration generation module of an intelligent control system for the quality of semiconductor production process. The baseline configuration generation module is used to generate a baseline test severity configuration matching the target application scenario based on the first intelligent test model according to the target application scenario information. The baseline test severity configuration includes test limit values of multiple test parameters, test item selection and test conditions.

[0047] Further, the first intelligent test model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer and an optimization decision layer. For details, please refer to Figure 3 ;

[0048] The target scenario selection layer selects a scenario from the preset automotive safety integrity level, industrial control level, and consumer electronics level based on the target application scenario information, and obtains the working temperature range, allowable failure rate index, and mission profile data based on the scenario;

[0049] The data analysis layer analyzes and quantifies the working temperature range, allowable failure rate index, and stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the working temperature range and the stress test conditions, and generates scenario feature parameters;

[0050] The knowledge fusion layer performs multi-modal fusion on the historical test scenario library, the process design rule library, and the scenario feature parameters to establish a constraint relationship matrix among test parameters;

[0051] The optimization decision layer generates a baseline test severity configuration by performing multi-objective optimization on the constraint relationship matrix to balance the test coverage rate and cost constraints; the baseline test severity configuration includes: a gradient configuration scheme for test temperature points and heat preservation time, and a dynamic sensitivity parameter configuration for statistical specification limits.

[0052] In this embodiment, by constructing a first intelligent test model, in-depth analysis of target application scenario information and intelligent configuration generation are realized. The target scenario selection layer can automatically match various application standards such as automotive safety, industrial control, and consumer electronics, and combine the working temperature range, allowable failure rate, and task data to ensure that the generated test severity configuration highly matches the actual application environment. The data analysis layer performs quantitative analysis on various parameters to extract key features, while the knowledge fusion layer constructs a constraint matrix among test parameters with the help of historical test scenarios and process design rules, providing a reliable basis for multi-objective optimization decision-making, so as to generate a scientific and reasonable baseline configuration on the premise of balancing the test coverage rate and cost constraints. This solution effectively improves the test accuracy and production efficiency, reduces the risks brought by process fluctuations, and ensures the consistency and reliability of the quality of semiconductor devices.

[0053] As an implementation manner of the present invention, referring to Figure 2 S3 in, S3 is applied to the real-time data monitoring module of an intelligent control system for the quality of a semiconductor production process. The real-time data monitoring module is used to obtain and analyze in real time the quality feedback data and upstream process data related to the semiconductor device to be tested during the test process to obtain semiconductor real-time data.

[0054] Furthermore, the quality feedback data includes at least one of the pass rate of early test items during the test process, the real-time measured values of key test parameters, statistical distribution information, spatial failure modes on the wafer map, and failure mode classification results;

[0055] The upstream process data includes the monitored values of key process step parameters from the manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes.

[0056] In this embodiment, the real-time data monitoring module can instantaneously obtain the quality feedback data and upstream process data of semiconductor devices during the testing process, ensuring that the test data presents the current state of the devices in real time and comprehensively. By collecting the pass rate at the initial stage of testing, real-time measured values of key parameters, statistical distributions, spatial failure modes on the wafer map, and the classification results of failure modes, and combining the key process parameters, equipment status, and fault alarms of the manufacturing execution system, the system realizes all-round dynamic monitoring of the production process. Through real-time data collection and analysis, not only can potential risks and process fluctuations be quickly identified, but also solid data support is provided for timely adjustment of test strategies and optimization of process control, thereby significantly improving product quality and reducing the production defect rate.

[0057] As an implementation manner of the present invention, referring to Figure 2 S4 in, S4 is applied to the dynamic adjustment module of an intelligent control system for semiconductor production process quality. The dynamic adjustment module is used to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration by using the semiconductor quality adjustment model, dynamically adjust the baseline test severity configuration, and generate the final test severity configuration.

[0058] Furthermore, the semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer, and an optimization adjustment parameter output layer. For details, refer to Figure 4 ;

[0059] The data input layer receives the semiconductor real-time data and the baseline test severity configuration as inputs;

[0060] The data processing layer uses signal processing algorithms and statistical methods to clean and normalize the input data; uses feature extraction algorithms to extract key feature indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional and heterogeneous input data; the key feature indicators include the drift amount of key parameters, volatility indicators, the clustering failure mode index on the wafer map, and the degree of deviation of upstream process parameters from specifications;

[0061] The risk assessment layer includes an anomaly detection unit, an association analysis unit, and a risk quantification unit; the anomaly detection unit obtains the feature index anomaly coefficient by analyzing the feature indicators extracted by the isolation forest; the association analysis unit uses association rule mining to analyze the key feature indicators to obtain potential feature associations; the risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the feature index anomaly coefficient and the potential feature associations; compares the quality risk level with the baseline test severity configuration to obtain an adjustment strategy;

[0062] The optimization adjustment parameter output layer outputs an adjustment strategy instruction.

[0063] In this embodiment, the dynamic adjustment module comprehensively analyzes real-time data and baseline test severity configurations by using a semiconductor quality adjustment model, realizing real-time identification and quantitative assessment of quality fluctuations, process drifts, and potential failure risks during the production process. The data processing layer cleans, normalizes, and extracts features from the input data to accurately capture key metrics from high-dimensional and heterogeneous data, such as critical parameter drifts, volatility, and wafer map failure mode indices; while the risk assessment layer generates risk assessment results and formulates scientific and reasonable adjustment strategies through isolation forest and association rule mining methods. This module can dynamically generate the final test severity configuration based on the comparison result between the risk level and the baseline configuration, and output the corresponding adjustment strategy instructions to achieve real-time optimization and update of test parameters, thereby effectively reducing production risks, improving product consistency and reliability.

[0064] Further, the specific steps of dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include:

[0065] Receiving the quality risk level and adjustment strategy instructions output from the semiconductor quality adjustment model;

[0066] Judging whether the preset adjustment trigger condition is met or there is significant process fluctuation based on the quality risk level and adjustment strategy instructions; if it is judged that the adjustment trigger condition is met, the baseline test severity configuration is modified according to the adjustment strategy instructions to generate the final test severity configuration; if it is judged that the adjustment trigger condition is not met, that is, the model evaluates that the current quality is stable and the risk is within an acceptable range, the final test severity configuration remains the same as the baseline test severity configuration.

[0067] In this embodiment, by dynamically judging the quality risk level and adjustment strategy instructions, real-time optimization of the test severity configuration is effectively achieved. When the system detects a preset adjustment trigger condition or obvious process fluctuation, the baseline configuration can be scientifically modified according to the output adjustment strategy to generate a final test configuration that better fits the current production status; while when the quality is stable and the risk is within a controllable range, the original configuration remains unchanged to avoid unnecessary adjustments. This mechanism not only ensures a high degree of matching between the test configuration and the actual process status, improves test accuracy and product reliability, but also reduces risks and production costs caused by unreasonable configurations, significantly enhancing the overall production efficiency and process control level, providing a solid technical support for the intelligent management and control of the semiconductor manufacturing process.

[0068] As an implementation manner of the present invention, referring to Figure 2S5 in the intelligent control system for semiconductor production process quality is applied to the test control module. The test control module is used to generate control instructions based on the configured final test severity and test the semiconductor device.

[0069] The intelligent control system for semiconductor production process quality of the present invention realizes intelligent test schemes through the collaborative work of information collection, baseline configuration generation, real-time monitoring, dynamic adjustment and test control modules. The system relies on the preset reliability requirements, working condition parameters and risk levels in the target application scenario, automatically matches safety, industrial, consumer and other standards, and generates scientific baseline configurations. The real-time monitoring module collects key test data and process information, comprehensively reflects the device status, and provides support for anomaly detection. The dynamic adjustment module conducts quantitative analysis on process fluctuations through data cleaning, feature extraction and risk assessment algorithms, and automatically optimizes the test configuration according to the triggering conditions to ensure that the final configuration highly matches the actual process and reduces production risks. The test control module generates instructions according to the optimized configuration to achieve precise testing, improve efficiency and product consistency. For details, refer to Table 1.

[0070] Table 1 Improvement Table of Quality Control Effect

[0071]

[0072] Embodiment 2

[0073] As an implementation manner of the present invention, referring to Figure 2 S1 in the intelligent control system for semiconductor production process quality is applied to the information acquisition module. The information acquisition module is used to acquire the target application scenario information of the semiconductor device to be tested, and the target application scenario information includes preset reliability requirements, working condition parameters and risk levels.

[0074] As an implementation manner of the present invention, referring to Figure 2 S2 in the intelligent control system for semiconductor production process quality is applied to the baseline configuration generation module. The baseline configuration generation module is used to utilize the first intelligent test model to generate a baseline test severity configuration that matches the target application scenario based on the target application scenario information. The baseline test severity configuration includes test limit values, test item selections and test conditions of multiple test parameters.

[0075] Furthermore, the first intelligent test model includes a target scenario selection layer, a data parsing layer, a knowledge fusion layer and an optimization decision layer;

[0076] The target scenario selection layer selects a scenario from the preset automotive safety integrity level, industrial control level, and consumer electronics level based on the target application scenario information, and obtains the working temperature range, allowable failure rate index, and mission profile data based on the scenario; the target application scenario information includes at least the preset reliability requirements, such as automotive safety integrity levels ASIL B, C, or D; industrial control levels and consumer electronics levels; working condition parameters, such as a specific working temperature range from -40°C to 125°C, allowable maximum junction temperature; risk levels, such as allowable failure rate index ppm or FIT rate, and mission profile data;

[0077] The data parsing layer parses and quantifies the working temperature range, allowable failure rate index, and stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the working temperature range and the stress test conditions, and generates scenario feature parameters;

[0078] The knowledge fusion layer performs multimodal fusion on the historical test scheme library, process design rule library, and the scenario feature parameters, and establishes a constraint relationship matrix between test parameters;

[0079] The optimization decision layer performs multi-objective optimization on the constraint relationship matrix, balances the test coverage rate and cost constraints, and generates a baseline test severity configuration; the baseline test severity configuration includes: a gradient configuration scheme for test temperature points and heat preservation time, and a dynamic sensitivity parameter configuration for statistical specification limits;

[0080] This configuration clearly defines the initial test parameter combination that matches the input target application scenario, specifically including but not limited to: the initial upper and lower threshold values of electrical parameters (voltage, current, and timing), the selection of test temperature points (room temperature, high temperature, and low temperature) and the heat preservation time requirements for each temperature point, the initial conditions of stress tests (high and low temperature cycles and voltage stress), whether to enable partial averaging tests and their initial parameters, the initial sensitivity parameters of statistical specification limits, the selected basic test vector set, and the initial branch logic of the test process.

[0081] Table 2 quantitatively shows the ability of the model of the present invention to output baseline configurations with different severity levels according to different application scenarios (such as the high reliability requirements of the automotive grade compared with the cost sensitivity of the consumer grade);

[0082] In multi-objective optimization, it is necessary to maximize the test coverage rate and minimize the test cost:

[0083] Maximizing the test coverage rate (Cov): refers to the degree to which the test configuration can detect potential defects related to the target application scenario;

[0084] Minimizing the test cost (Cost): mainly includes test time, equipment usage, possible yield loss, etc.

[0085] Decision variables At least including:

[0086] Gradient configuration of test temperature points and heat preservation time ; Dynamic sensitivity parameter configuration of statistical specification limits ; Initial upper and lower threshold values of electrical parameters ; Initial conditions of stress test ; Partial average test and its initial parameters ; Selection of basic test vector set ; Initial branch logic of test process ; That is, the decision variables are:

[0087] ;

[0088] The constraint conditions are:

[0089] ;

[0090] The multi-objective optimization formula is:

[0091] ;

[0092] Wherein, is the optimal decision, is the scenario feature parameter, is the industrial grade, is the cost function;

[0093] Table 2 Baseline configuration parameter table output by the first intelligent test model

[0094]

[0095] As an implementation manner of the present invention, referring to Figure 2 S3 in, S3 is applied to the real-time data monitoring module of an intelligent control system for semiconductor production process quality. The real-time data monitoring module is used to obtain and analyze quality feedback data and upstream process data related to the semiconductor device to be tested in real time during the test process, and obtain semiconductor real-time data.

[0096] The specific process of generating the semiconductor real-time data includes:

[0097] Step 1 (Quality feedback data collection): Collect quality feedback data related to the semiconductor devices (batches, wafers, and individual chips) currently being tested in real-time or near real-time from the test equipment. These data include at least the real-time pass rate statistics of early key test items, the real-time measurement value sequences of key electrical performance parameters (leakage current, operating frequency, and power consumption), the statistical distribution information of these parameter measurement values (mean, standard deviation, and Cp / Cpk), the spatial failure modes presented on the wafer map (central failure, edge failure, and cluster failure), and the failure mode classification results generated by the test system or additional analysis software;

[0098] Step 2 (Upstream process data collection): Query the manufacturing execution system, equipment automation system, or dedicated process monitoring database in real-time or periodically through an interface to obtain upstream key manufacturing process information related to the currently tested device. These data include at least the process parameter monitoring values from key process steps (lithography, etching, thin film deposition, and implantation) (exposure dose, etching time, thin film thickness, and implantation energy), the real-time status information of the equipment performing these steps (equipment ID, maintenance records, and operating parameters), and the fault detection and classification system alarms or quality event records generated from upstream processes (wafer manufacturing and front-end packaging);

[0099] Step 3 (Data integration): Pool, align timestamps, and correlate the quality feedback data collected in Step 1 and the upstream process data collected in Step 2 (by batch number, wafer number, and chip location information) to generate semiconductor real-time data.

[0100] Furthermore, the quality feedback data includes at least one of the pass rate of early test items during the test process, the real-time measurement values of key test parameters, statistical distribution information, spatial failure modes on the wafer map, and failure mode classification results;

[0101] The upstream process data includes the process parameter monitoring values of key process steps from the manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes.

[0102] As an implementation manner of the present invention, referring to Figure 2 S4 in, S4 is applied to the dynamic adjustment module of an intelligent control system for semiconductor production process quality. The dynamic adjustment module is used to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration by using the semiconductor quality adjustment model, dynamically adjust the baseline test severity configuration, and generate the final test severity configuration.

[0103] Furthermore, the semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer, and an optimized adjustment parameter output layer;

[0104] The data input layer receives the semiconductor real-time data and the baseline test severity configuration as inputs;

[0105] The data processing layer uses signal processing algorithms (filtering and smoothing) and statistical methods (standardization and normalization) to clean and normalize the input data; uses feature extraction algorithms to extract key feature indicators reflecting quality fluctuations, process drifts, and potential failure risks from high-dimensional and heterogeneous input data; the key feature indicators include the drift amount of key parameters, volatility indicators, clustering failure mode indices on the wafer map, and the degree of deviation of upstream process parameters from specifications; the feature extraction algorithms can be principal component analysis PCA, time series feature extraction, or spatial pattern recognition algorithms;

[0106] The risk assessment layer includes an anomaly detection unit, an association analysis unit, and a risk quantification unit; the anomaly detection unit obtains the anomaly coefficient of the feature indicators by analyzing the feature indicators extracted by the isolation forest; the association analysis unit uses association rule mining to analyze the key feature indicators and obtains the potential associations of the features; the risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the anomaly coefficient of the feature indicators and the potential associations of the features ; compares the quality risk level with the baseline test severity configuration to obtain an adjustment strategy;

[0107] ;

[0108] Among them, is the importance weight of feature , is the anomaly coefficient of feature , is to normalize it to a suitable range, is the risk weight of the combined anomaly of feature and , is the correlation information between feature and , is to evaluate the comprehensive impact degree of the risk when features and are simultaneously abnormal based on association rule analysis, is the benchmark for evaluating the risk assessment.

[0109] The optimization and adjustment parameter output layer outputs adjustment strategy instructions.

[0110] Furthermore, the specific steps for dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include:

[0111] Receiving the quality risk level and adjustment strategy instructions output from the semiconductor quality adjustment model;

[0112] Judge whether the preset adjustment trigger condition is met or there is significant process fluctuation according to the quality risk level and adjustment strategy instruction;

[0113] If it is judged that the adjustment trigger condition is met, then according to the adjustment strategy instruction, modify the baseline test severity configuration to generate the final test severity configuration; the specific modification operation is:

[0114] Increase the severity level: For the aspects where the model indicates risks, increase the severity level of at least one test parameter. For example:

[0115] For electrical parameter risks, tighten the upper and lower limit test thresholds of relevant electrical parameters; for temperature sensitivity risks, add additional test temperature points (add extremely high or low temperature tests) or extend the heat preservation time at specific temperature points; for reliability or potential defect risks, adopt more severe stress test conditions (increase stress voltage, increase stress time or cycle times); for group anomaly risks, enable or tighten the judgment criteria for some average tests, or increase the sensitivity parameter for statistical specification limit judgment (reduce the k-sigma value);

[0116] Or / and add diagnostic tests: Add additional and more diagnostic test items or test vector sets, especially for screening specific potential failure modes identified by the model; modify the branch logic of the test process. For example, for some boundary cases or suspicious chips, guide them into a more detailed diagnostic test sub-process;

[0117] If it is judged that the adjustment trigger condition is not met, that is, the model evaluation believes that the current quality is stable and the risk is within an acceptable range, then the final test severity configuration remains the same as the baseline test severity configuration; the final test severity configuration includes: the upper and lower limit thresholds of electrical parameters, test temperature points and heat preservation time, stress test conditions, some average tests, the sensitivity parameter of statistical specification limits, test vector set selection or test process branch logic.

[0118] As an implementation manner of the present invention, refer to Figure 2 S5 in, S5 is applied to the test control module of an intelligent control system for semiconductor production process quality, and the test control module is used to generate a control instruction based on the final test severity configuration to test the semiconductor device.

[0119] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principle and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An intelligent control system for the quality of semiconductor production processes, characterized in that The semiconductor testing stage includes: An information acquisition module for acquiring target application scenario information of a semiconductor device to be tested, where the target application scenario information includes preset reliability requirements, operating condition parameters, and risk levels; A baseline configuration generation module for using a first intelligent testing model to generate a baseline test severity configuration that matches the target application scenario based on the target application scenario information, where the baseline test severity configuration includes test limit values of multiple test parameters, test item selections, and test conditions; A real-time data monitoring module for, during the testing process, acquiring and analyzing quality feedback data and upstream process data related to the semiconductor device to be tested in real time to obtain semiconductor real-time data; the upstream process data includes key process step parameter monitoring values from a manufacturing execution system, equipment status information, and fault detection and classification alarms from upstream processes; A dynamic adjustment module for using a semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjust the baseline test severity configuration, and generate a final test severity configuration; A test control module for generating a control instruction based on the final test severity configuration to test the semiconductor device.

2. The intelligent control system for semiconductor production process quality according to claim 1, wherein: The quality feedback data includes at least one of the pass rate of early test items during the testing process, real-time measurement values of key test parameters, statistical distribution information, spatial failure modes on a wafer map, and failure mode classification results.

3. The intelligent control system for semiconductor production process quality according to claim 1, wherein: The first intelligent testing model includes a target scenario selection layer, a data analysis layer, a knowledge fusion layer, and an optimization decision layer; The target scenario selection layer selects a scenario from preset automotive safety integrity levels, industrial control levels, and consumer electronics levels based on the target application scenario information, and obtains a working temperature range, an allowable failure rate index, and mission profile data based on the scenario; The data analysis layer analyzes and quantifies the working temperature range, the allowable failure rate index, and stress test data, obtains the correlation analysis between the scenario and the allowable failure rate index, and the mapping relationship between the working temperature range and stress test conditions, and generates scenario feature parameters; The knowledge fusion layer performs multi-modal fusion on a historical test plan library, a process design rule library, and the scenario feature parameters to establish a constraint relationship matrix between test parameters; The optimization decision layer performs multi-objective optimization on the constraint relationship matrix, balances test coverage and cost constraints, and generates a baseline test severity configuration; The baseline test severity configuration includes: a gradient configuration scheme for test temperature points and heat preservation times, and a dynamic sensitivity parameter configuration for statistical specification limits.

4. The intelligent control system for semiconductor production process quality according to claim 1, wherein: The semiconductor quality adjustment model includes a data input layer, a data processing layer, a risk assessment layer, and an optimized adjustment parameter output layer; The data input layer receives the semiconductor real-time data and the baseline test severity configuration as inputs; The data processing layer uses signal processing algorithms and statistical methods to clean and normalize the input data; Feature extraction algorithms are used to extract key feature indicators from high-dimensional and heterogeneous input data that reflect quality fluctuations, process drifts, and potential failure risks; the key feature indicators include the drift amount of key parameters, volatility indicators, clustering failure mode indices on the wafer map, and the degree of deviation of upstream process parameters from specifications; The risk assessment layer includes an anomaly detection unit, an association analysis unit, and a risk quantification unit; the anomaly detection unit obtains the feature indicator anomaly coefficient by analyzing the feature indicators extracted by the isolation forest; the association analysis unit uses association rule mining to analyze the key feature indicators to obtain potential feature associations; The risk quantification unit comprehensively evaluates the quality risk level of the semiconductor device based on the feature indicator anomaly coefficient and the potential feature associations; The quality risk level is compared with the baseline test severity configuration to obtain an adjustment strategy; The optimization and adjustment parameter output layer outputs an adjustment strategy instruction.

5. An intelligent control system for semiconductor production process quality according to claim 4, wherein: The specific steps for dynamically adjusting the baseline test severity configuration and generating the final test severity configuration include: Receiving the quality risk level and the adjustment strategy instruction output from the semiconductor quality adjustment model; Judging whether the preset adjustment trigger condition is satisfied and / or whether there is significant process fluctuation based on the quality risk level and the adjustment strategy instruction; if it is judged that the adjustment trigger condition is satisfied, the baseline test severity configuration is modified according to the adjustment strategy instruction to generate the final test severity configuration; if it is judged that the adjustment trigger condition is not satisfied, that is, the model evaluates that the current quality is stable and the risk is within an acceptable range, then the final test severity configuration remains the same as the baseline test severity configuration.

6. An intelligent control method for the quality of a semiconductor production process, characterized in that, Execute an intelligent control system for semiconductor production process quality as described in claim 1, semiconductor testing stage: S1. Obtain the target application scenario information of the semiconductor device to be tested, where the target application scenario information includes preset reliability requirements, working condition parameters, and risk levels; S2. Use the first intelligent test model to generate a baseline test severity configuration that matches the target application scenario based on the target application scenario information, where the baseline test severity configuration includes the test limit values of multiple test parameters, test item selections, and test conditions; S3. During the testing process, obtain and analyze the quality feedback data and upstream process data related to the semiconductor device to be tested in real time to obtain semiconductor real-time data; S4. Use the semiconductor quality adjustment model to comprehensively analyze the semiconductor real-time data and the baseline test severity configuration, dynamically adjust the baseline test severity configuration, and generate the final test severity configuration; S5. Generate a control instruction based on the final test severity configuration to test the semiconductor device.

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