Through hole structure and manufacturing method thereof, and manufacturing method of through hole interconnection structure

Abstract

The invention relates to a through hole structure and a manufacturing method thereof, and a manufacturing method of a through hole interconnection structure, and the manufacturing method of the through hole structure comprises the steps: forming a blind hole in a substrate; completely oxidizing the residual substrate material at the bottom of the blind hole; and removing the oxide layer to obtain a through hole structure which is provided with a through hole penetrating through the substrate. According to the method, the blind hole is formed in the substrate, a supporting sheet is not used for manufacturing the through hole structure, bonding and de-bonding equipment is not needed, and the production cost is saved. The substrate material with the residual thickness at the bottom of the blind hole is completely oxidized into the oxide layer through oxidation, and then the oxide layer is removed to obtain the through hole penetrating through the substrate, so that the back surface of the substrate does not need to be thinned, the defects of silicon slag and edge breakage caused by thinning are avoided, and the yield and the reliability of the device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and particularly to a via structure, a manufacturing method of a via structure, and a manufacturing method of a via interconnect structure. Background Art

[0002] As semiconductor process nodes become smaller and smaller, traditional packaging such as wire bonding and flip chip technology can no longer meet the requirements of chip products. Through-Silicon Via (TSV) is a high-density lead connection packaging technology and is widely used in 2.5D and 3D (three-dimensional) packaging. Its advantages include: it can provide a shorter vertical interconnect path for chip stacking, thereby reducing circuit delay and power consumption, reducing the limitation on the position of I / O pins, and increasing the I / O channel bandwidth.

[0003] An exemplary method for preparing a through-silicon via is to temporarily bond an interposer and a support wafer together. After forming a through-silicon via in the interposer, debonding is then performed to separate the interposer and the support wafer. This solution requires the use of bonding and debonding equipment, so the equipment investment and production cost are relatively high. The interposer is a silicon wafer with a through-silicon via structure, that is, a through-silicon via interconnect structure. The through-silicon via structure includes a silicon-based substrate and a through-silicon via penetrating the silicon-based substrate. In the structure of a multi-layer chip stack package, an interposer can be used to interconnect multiple chips in different upper and lower layers to achieve the integration of chips with different functions. Exemplarily, assuming that a chip package includes three stacked silicon wafers, the silicon wafer located in the middle position can be used as an interposer to connect the silicon wafer located in the upper layer and the silicon wafer located in the lower layer.

[0004] Another exemplary method for preparing a through-silicon via does not use a support wafer and directly processes a through-silicon via in the interposer. However, the interposer is not completely penetrated, but the bottom of the through-silicon via is exposed by back thinning the interposer. This solution does not require the purchase of new bonding and debonding equipment, but silicon slag, water marks, etc. caused by thinning are likely to remain in the via and are difficult to clean thoroughly. And when the thinning grinding wheel reaches the via, the edge of the via is prone to chipping, and the profile of the bottom of the via is relatively poor. These will all affect the yield and reliability of the device. Summary of the Invention

[0005] Based on this, it is necessary to provide a manufacturing method of a via structure that can balance production cost, yield, and reliability of the device.

[0006] A manufacturing method of a via structure includes: forming a blind hole in a substrate; oxidizing all the remaining substrate material at the bottom of the blind hole; removing the oxide layer to obtain a via structure having a via penetrating the substrate.

[0007] The manufacturing method of the above through-hole structure forms blind holes in the substrate and does not use a support wafer for manufacturing the through-hole structure. Therefore, there is no need for bonding and debonding equipment, saving production costs. By oxidation, all the substrate material with the remaining thickness at the bottom of the blind hole is oxidized into an oxide layer, and then the oxide layer is removed to obtain a through-hole penetrating the substrate. There is no need to thin the back surface of the substrate, avoiding the defects of silicon slag and chipping caused by thinning, which is beneficial to improving the yield and reliability of the device.

[0008] In one embodiment, the thickness of the remaining substrate material at the bottom of the blind hole is less than 10 microns.

[0009] In one embodiment, the removing of the oxide layer is performed by wet etching.

[0010] In one embodiment, the etchant for the wet etching includes hydrofluoric acid.

[0011] In one embodiment, the step of oxidizing all the remaining substrate material at the bottom of the blind hole includes: performing an oxidation treatment on the substrate to form an oxide layer on the surface of the substrate, and oxidizing all the remaining substrate material at the bottom of the blind hole.

[0012] In one embodiment, the step of performing an oxidation treatment on the substrate includes forming the oxide layer by low-pressure chemical vapor deposition.

[0013] In one embodiment, the step of performing an oxidation treatment on the substrate includes forming the oxide layer by using a dry oxidation process or a wet oxidation process.

[0014] In one embodiment, the forming of the blind hole in the substrate is performed by deep reactive ion etching to form the blind hole.

[0015] In one embodiment, the through-hole is a through-silicon via, and the substrate is a silicon substrate.

[0016] It is also necessary to provide a through-hole structure.

[0017] A through-hole structure includes a substrate, and a through-hole is formed in the substrate. The through-hole structure is manufactured by using the manufacturing method of the through-hole structure described in any of the foregoing embodiments.

[0018] It is also necessary to provide a manufacturing method of a through-hole interconnect structure.

[0019] A manufacturing method of a through-hole interconnect structure includes: forming the through-hole structure by using the manufacturing method of the through-hole structure described in any of the foregoing embodiments; and forming a conductive material on the inner wall of the through-hole.

[0020] It is also necessary to provide a through-hole interconnection structure.

[0021] A through-hole interconnection structure includes a substrate in which through-holes are formed. The through-hole interconnection structure further includes a conductive material located on the inner wall of the through-holes. The through-hole structure is manufactured by using the manufacturing method of the through-hole structure described in any of the foregoing embodiments.

[0022] It is also necessary to provide an electronic device.

[0023] An electronic device includes: a first chip, a second chip, and the aforementioned through-silicon via interconnection structure; the first chip, the through-silicon via interconnection structure, and the second chip are stacked in sequence, and the first chip and the second chip are electrically connected through the through-silicon via interconnection structure. Description of the Drawings

[0024] To better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, one or more drawings may be referred to. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, and the currently understood best mode of these inventions.

[0025] Figures 1a to 1c is a schematic diagram of an exemplary through-silicon via preparation;

[0026] Figure 2a and Figure 2b is another schematic diagram of an exemplary through-silicon via preparation;

[0027] Figure 3 is a flowchart of the manufacturing method of the through-hole structure in an embodiment of the present application;

[0028] Figures 4a to 4c is according to an embodiment of the present application Figure 3 a schematic diagram of a silicon wafer during the process of manufacturing a through-hole structure by the method shown;

[0029] Figure 5 is a flowchart of the manufacturing method of the through-hole interconnection structure in an embodiment of the present application;

[0030] Figure 6 is a schematic structural diagram of the through-hole interconnection structure in an embodiment of the present application;

[0031] Figure 7 is a schematic structural diagram of an electronic device in an embodiment of the present application;

[0032] Figure 8 is a micrograph of the edge of the through-hole where chipping is likely to occur. Detailed Description of the Embodiments

[0033] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present invention will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0035] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, a first element, component, region, layer or part discussed below may be denoted as a second element, component, region, layer or part without departing from the teachings of the present invention.

[0036] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the drawings to other elements or features. It should be understood that, in addition to the orientation shown in the drawings, spatial relationship terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawing is flipped, then an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0038] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the invention. As such, variations from the shapes shown, for example due to manufacturing techniques and / or tolerances, are to be expected. Accordingly, embodiments of the present invention should not be limited to the particular shapes of regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an implantation region shown as rectangular will typically have rounded or curved features at its edges and / or an implantation concentration gradient, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device and are not intended to limit the scope of the present invention.

[0039] The semiconductor field vocabulary used herein is the common technical vocabulary of those skilled in the art. For example, for P-type and N-type impurities, to distinguish the doping concentration, simply P+ type represents the P-type with heavy doping concentration, P type represents the P-type with medium doping concentration, P- type represents the P-type with light doping concentration, N+ type represents the N-type with heavy doping concentration, N type represents the N-type with medium doping concentration, and N- type represents the N-type with light doping concentration.

[0040] Figures 1a to 1c is a schematic diagram of an exemplary through-silicon via fabrication. Referring to Figure 1a , first, the interposer 120 and the support wafer 110 are temporarily bonded (wafer bonding) together. Then, deep reactive ion etching (DRIE) is performed on the interposer 120 to form a hole 121, as shown in Figure 1b . Finally, debonding is performed to separate the interposer 120 from the support wafer 110, ultimately forming a through-silicon via structure. As described in the background art, this solution requires the use of bonding and debonding equipment, so the purchase and production costs of the equipment are relatively high.

[0041] Figure 2a and Figure 2b is another schematic diagram of an exemplary through-silicon via fabrication. Referring toFigure 2a First, a deep reactive ion etching is performed on the insert sheet 120 to form a hole 121, and the hole 121 is a blind hole, with a certain thickness of substrate material remaining at the bottom of the blind hole. Then, the back surface of the insert sheet 120 is thinned, that is, the back surface of the hole 121 is exposed by grinding, and finally a through-silicon via structure is formed, as Figure 2b shown. As described in the background art, this solution does not require the purchase of new bonding and debonding equipment, but silicon slag, water marks, etc. caused by thinning are likely to remain in the through holes and are difficult to clean thoroughly. And when the thinning grinding wheel reaches the through hole, chipping is likely to occur at the edge of the through hole, and the profile of the bottom of the through hole is relatively poor. Referring to Figure 8 , it will affect the yield and reliability of the device.

[0042] Figure 3 is a flowchart of a method for manufacturing a through-hole structure in an embodiment of the present application, including the following steps:

[0043] S310, forming a blind hole in the substrate.

[0044] In an embodiment of the present application, a substrate 220 serving as an insert sheet is obtained, and then a blind hole 221a is formed in the substrate 220 by deep reactive ion etching. See Figure 4a . In an embodiment of the present application, a photoresist may be coated on the upper surface of the substrate 220 first, and then the photoresist is exposed using a TSV photomask, and then the desired etching pattern is defined through development. This pattern is the opening position of the etched blind hole 221a. Then, an etching device for deep reactive ion etching may be used to etch downward a preset thickness or for a preset time from the position where the pattern defined by lithography is located to obtain the blind hole 221a.

[0045] S320, oxidizing all the remaining substrate material at the bottom of the blind hole.

[0046] In an embodiment of the present application, the remaining photoresist in step S310 should be removed before step S320. The depth of the blind hole 221a obtained in step S310 should be deep enough so that the remaining substrate material at the bottom of the blind hole 221a is thin enough to ensure that all the remaining substrate material is oxidized into an oxide layer 222 in step S320. See Figure 4b . In an embodiment of the present application, the thickness of the remaining substrate material at the bottom of the blind hole 221a is less than 10 microns to ensure that step S320 can oxidize it all into the oxide layer 222.

[0047] S330, removing the oxide layer to obtain a through-hole structure with through holes.

[0048] In one embodiment of the present application, the oxide layer 222 is completely removed by wet etching. Since the oxide layer 222 at the bottom of the blind via 221a is also completely removed, a through-hole 221b penetrating the substrate 220 is obtained after step S330 is completed, as Figure 4c shown.

[0049] In the manufacturing method of the above through-hole structure, a blind via 221a is formed in the substrate 220, and a support wafer is not used for manufacturing the through-hole structure. Therefore, no bonding and debonding equipment is required, saving production costs. By oxidation, all the substrate material with the remaining thickness at the bottom of the blind via 221a is oxidized into the oxide layer 222, and then the oxide layer 222 is removed to obtain a through-hole 221b penetrating the substrate 222. There is no need to perform back thinning on the substrate 222 to expose the back surface of the blind via 221a, avoiding the defects of silicon slag and chipping caused by thinning, which is beneficial to improving the yield and reliability of the device.

[0050] In Figure 4b the embodiment shown, step S320 is to perform an oxidation treatment on the substrate 220 to form an oxide layer 222 on the surface of the substrate 220, and all the remaining substrate material at the bottom of the blind via 221a is oxidized. Since the material on the inner wall of the blind via 221a is oxidized into the oxide layer 222 during the oxidation process, the roughness of the inner wall caused by the via etching in step S310 will be repaired. Therefore, the inner wall of the through-hole 221b will be relatively smooth and have a good morphology.

[0051] In one embodiment of the present application, the formed through-hole structure is a through-silicon via structure, the through-hole 221b is a TSV, and the substrate 220 is a silicon substrate.

[0052] In one embodiment of the present application, the etchant for wet etching to remove the oxide layer 222 in step S330 includes hydrofluoric acid, such as a hydrofluoric acid solution. In one embodiment of the present application, the etchant for this wet etching may also include a Buffered Oxide Etch (BOE) solution. The BOE solution is a solution formed by mixing hydrofluoric acid and ammonium fluoride in a certain ratio. Among them, hydrofluoric acid is the main etching solution, and ammonium fluoride is used as a buffer.

[0053] In one embodiment of the present application, step S320 forms the oxide layer 222 by low-pressure chemical vapor deposition (LPCVD).

[0054] In one embodiment of the present application, step S320 forms the oxide layer 222 by a dry oxidation process or a wet oxidation process. The oxidation gas used in the wet oxidation process generally includes hydrogen and oxygen, and the oxidation gas used in the dry thermal oxidation process generally only includes oxygen.

[0055] The present application correspondingly provides a via structure, including a substrate 220 in which a via 221b is formed. This via structure is manufactured by using the manufacturing method of the via structure described in any of the foregoing embodiments. In an embodiment of the present application, this via structure is a through-silicon via structure, the via 221b is a TSV, and the substrate 220 is a silicon substrate.

[0056] The present application correspondingly provides a manufacturing method of a via interconnect structure. Figure 5 It is a flowchart of the manufacturing method of the via interconnect structure in an embodiment of the present application, including the following steps:

[0057] S510, forming a blind hole in the substrate.

[0058] In an embodiment of the present application, the substrate 220 as an insert piece is obtained, and then a blind hole 221a is formed in the substrate 220 by deep reactive ion etching. See Figure 4a . In an embodiment of the present application, a photoresist may be coated on the upper surface of the substrate 220 first, and then the photoresist is exposed using a TSV photomask, and then the required etching pattern is defined by development. This pattern is the opening position of the etched blind hole 221a. Then, an etching device for deep reactive ion etching can be used to etch downward a preset thickness or a preset time from the position where the pattern defined by lithography is located to obtain the blind hole 221a.

[0059] S520, performing an oxidation treatment on the substrate to form an oxide layer on the substrate surface.

[0060] In an embodiment of the present application, the remaining photoresist in step S510 should be removed before step S520. The depth of the blind hole 221a obtained in step S510 should be deep enough so that the remaining substrate material at the bottom of the blind hole 221a is thin enough to ensure that all the remaining substrate material is oxidized into the oxide layer 222 in step S520. See Figure 4b . In an embodiment of the present application, the thickness of the remaining substrate material at the bottom of the blind hole 221a is less than 10 microns to ensure that step S520 can oxidize all of it into the oxide layer 222.

[0061] S530, removing the oxide layer to obtain a via structure with a via.

[0062] In an embodiment of the present application, the oxide layer 222 is completely removed by wet etching. Since the oxide layer 222 at the bottom of the blind hole 221a is also completely removed, a via 221b penetrating the substrate 220 is obtained after step S530 is completed, as Figure 4c shown.

[0063] S540, forming a conductive material on the inner wall of the via.

[0064] Methods such as sputtering, electroplating, electroless plating, etc. can be selected to form the conductive material 224, such as Figure 6 shown. In an embodiment of the present application, the conductive material 244 can be a metal or alloy material, such as titanium nitride. The conductive material 244 can be used for electrically connecting the conductive patterns formed on the upper surface and / or lower surface of the substrate 220; or, for electrically connecting the chips disposed on the upper surface and / or lower surface of the substrate 220, that is, realizing the interconnection between different stacked chips.

[0065] In the manufacturing method of the above through-hole interconnection structure, a blind hole 221a is formed in the substrate 220, and a support sheet is not used for manufacturing the through-hole structure. Therefore, no bonding and debonding equipment is required, saving production costs. By oxidation, all the substrate material with the remaining thickness at the bottom of the blind hole 221a is oxidized into an oxide layer 222, and then the oxide layer 222 is removed to obtain a through-hole 221b penetrating the substrate 222. There is no need to perform back thinning on the substrate 222 to expose the back surface of the blind hole 221a, avoiding the defects of silicon slag and chipping caused by thinning, which is beneficial to improving the yield and reliability of the device. And because the material on the inner wall of the blind hole 221a is oxidized into the oxide layer 222 during the oxidation process, the roughness of the inner wall caused by the hole etching in step S510 will be repaired. Therefore, the inner wall of the through-hole 221b will be relatively smooth and have a good morphology, which is beneficial to improving the growth quality of the conductive material 244 on the inner wall of the through-hole 221b. Correspondingly, the reliability of the through-silicon via interconnection structure prepared by this method for interconnecting chips is relatively good.

[0066] In an embodiment of the present application, the through-hole interconnection structure is a through-silicon via interconnection structure, the through-hole 221b is a TSV, and the substrate 220 is a silicon substrate.

[0067] In an embodiment of the present application, the etchant for wet etching to remove the oxide layer 222 in step S530 includes hydrofluoric acid, such as a hydrofluoric acid solution. In an embodiment of the present application, the etchant for this wet etching can also include a Buffered Oxide Etch (BOE) solution. The BOE solution is a solution formed by mixing hydrofluoric acid and ammonium fluoride in a certain ratio. Among them, hydrofluoric acid is the main etching solution, and ammonium fluoride is used as a buffer.

[0068] In an embodiment of the present application, step S520 forms the oxide layer 222 by low-pressure chemical vapor deposition (LPCVD).

[0069] In an embodiment of the present application, step S520 forms the oxide layer 222 by a dry oxidation process or a wet oxidation process. The oxidation gas used in the wet oxidation process generally includes hydrogen and oxygen, and the oxidation gas used in the dry thermal oxidation process generally only includes oxygen.

[0070] The present application correspondingly provides a through-hole interconnection structure, including a substrate 220, in which a through-hole 221b is formed. The through-hole interconnection structure further includes a conductive material 244 located on the inner wall of the through-hole 221b. Refer to Figure 6 . The through-hole interconnection structure is manufactured by using the manufacturing method of the through-hole interconnection structure described in any of the foregoing embodiments. In an embodiment of the present application, the through-hole interconnection structure is a through-silicon via (TSV) interconnection structure, the through-hole 221b is a TSV, and the substrate 220 is a silicon substrate.

[0071] The present application correspondingly provides an electronic device. Refer to Figure 7 . The electronic device includes a first chip 100, a second chip 300, and Figure 6 the through-silicon via interconnection structure shown. The first chip 100, the through-silicon via interconnection structure, and the second chip 300 are stacked in sequence, and the first chip 100 and the second chip 300 are electrically connected through the through-silicon via interconnection structure.

[0072] It should be noted that Figure 7 only a three-layer stacked structure is schematically shown. In other embodiments, the electronic device may further include a larger number of chips stacked in sequence, and the multiple chips can be interconnected through the through-silicon via interconnection structure. The electronic device may include MEMS (micro-electro-mechanical system) devices, such as MEMS gene detection and optical lens devices. The electronic device may also be a personal computer, a laptop computer, a smart phone, a tablet computer, an Internet of Things device, and a portable wearable device, etc. The Internet of Things device may be a smart speaker, a smart TV, a smart air conditioner, a smart vehicle-mounted device, etc. The portable wearable device may be a smart watch, a smart bracelet, TWS (true wireless) earphones, smart glasses, a head-mounted device, etc.

[0073] It should be understood that although the steps in the flowchart of the present application are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0074] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0075] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0076] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for manufacturing a through-hole structure, include: forming a blind hole in a substrate; Oxidize all the remaining substrate material at the bottom of the blind hole; The oxide layer is removed to obtain a through-hole structure, wherein the through-hole structure has a through-hole penetrating the substrate.

2. The method for manufacturing a through-hole structure according to claim 1, It is characterized in that The thickness of the remaining substrate material at the bottom of the blind hole is less than 10 microns.

3. The method for manufacturing a through-hole structure according to claim 1, It is characterized in that The oxide layer is removed by wet etching.

4. The method for manufacturing a through-hole structure according to claim 3, It is characterized in that The wet etching etchant includes hydrofluoric acid.

5. The method for manufacturing a through-hole structure according to claim 1, It is characterized in that The step of completely oxidizing the remaining substrate material at the bottom of the blind hole includes: performing oxidation treatment on the substrate to form an oxide layer on the surface of the substrate, and completely oxidizing the remaining substrate material at the bottom of the blind hole.

6. The method for manufacturing a through-hole structure according to claim 5, It is characterized in that The step of oxidizing the substrate includes forming the oxide layer by low pressure chemical vapor deposition.

7. The method for manufacturing a through-hole structure according to claim 1, It is characterized in that The forming of the blind hole in the substrate is performed by deep reactive ion etching.

8. The method for manufacturing a through-hole structure according to any one of claims 1 to 7, It is characterized in that The through hole is a through silicon via, and the substrate is a silicon substrate.

9. A through-hole structure, comprising a substrate, wherein a through-hole is formed in the substrate, It is characterized in that The through hole structure is manufactured by the manufacturing method of any one of claims 1 to 8.

10. A method for manufacturing a through-hole interconnection structure, It is characterized in that include: The through-hole structure is formed by using the method for manufacturing a through-hole structure according to any one of claims 1 to 8; A conductive material is formed on the inner wall of the through hole.

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