Microsystem isolation layout structure based on three-dimensional stacked packaging

Abstract

The invention belongs to the technical field of chip packaging, and relates to a microsystem isolation layout structure based on three-dimensional stacked packaging. The upper-layer substrate and the lower-layer substrate are connected through vertical stacking, so that the overall size of the packaging structure is remarkably reduced, and the space utilization rate is improved. The upper substrate and the lower substrate are connected through vertical stacking, and through three-dimensional stacking packaging, the overall size of the packaging structure is remarkably reduced, so that equipment with the same function is more compact. Through reasonable layout of the field programmable gate array chip, the two analog-to-digital converter chips and the two groups of isolation chips, reduction of the wiring length of signals is facilitated, and reduction of signal interference is further facilitated. The analog signal bonding pad and the digital signal bonding pad are isolated through the empty bonding pad, signal interference can be reduced, and interference between the digital signal and the analog signal is remarkably reduced while the miniaturization requirement is met.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and relates to a microsystem isolation layout structure based on three-dimensional stacked packaging. Background Art

[0002] In modern electronic systems, the integration of ADC (Analog-to-Digital Converter) chips, Field Programmable Gate Array (FPGA) chips, and isolation chips has become increasingly common, especially in fields such as industrial automation, medical design, automotive electronics, and energy management, which have requirements for high-performance signal processing and electrical isolation. This trend of integration is of great significance for improving the overall performance and reliability of the system.

[0003] However, when designing SiP (System-in-Package) products containing ADC, FPGA, and isolation chips, the packaging structure design has become a major challenge. Since miniaturization design needs to be carried out under the conditions of meeting electrical performance and mechanical strength, new packaging structures need to be considered. In addition, the designed SiP products also need to ensure that they can work together at the system level to avoid mutual interference between digital signals and analog signals.

[0004] However, after miniaturized packaging using existing packaging methods, there is often a certain interference between digital signals and analog signals. This interference not only affects the performance of the system, but also may pose a threat to the reliability, high performance, and functional integration requirements of the packaged module integration. Therefore, how to effectively isolate digital signals and analog signals while meeting the miniaturization requirements has become an urgent problem to be solved. Summary of the Invention

[0005] The purpose of the present invention is to provide a microsystem isolation layout structure based on three-dimensional stacked packaging to solve the technical problem of certain interference between digital signals and analog signals during miniaturized packaging. The present invention significantly reduces the interference between digital signals and analog signals while meeting the miniaturization requirements.

[0006] To achieve the above purpose, the present invention adopts the following technical solutions: The present invention discloses a microsystem isolation layout structure based on three-dimensional stacked packaging, including: An upper substrate, on which two analog-to-digital converter chips and two groups of isolation chips are coplanarly arranged. The two analog-to-digital converter chips are located on one side of the upper substrate, and the two groups of isolation chips are located on the other side of the upper substrate. The isolation chips with the part of analog ground and analog power are placed close to the analog-to-digital converter chips; A lower substrate, on which a field programmable gate array chip is arranged, and the field programmable gate array chip is located between the lower substrate and the upper substrate; A pad, the pad is located on the bottom surface of the lower substrate, the lower substrate is located between the pad and the field programmable gate array chip, the pad includes an analog signal pad, a digital signal pad and an empty pad, the empty pad is located between the analog signal pad and the digital signal pad, the analog signal pad is used to receive analog signals, and the digital signal pad is used to receive digital signals.

[0007] Further, a flash memory chip is also provided on the upper substrate, the flash memory chip is coplanarly arranged with the analog-to-digital converter chip and the isolation chip, and the flash memory chip is located between two analog-to-digital converter chips.

[0008] Further, the intervals on the upper substrate where the flash memory chip, the isolation chip and the analog-to-digital converter chip are located are not wired and copper-clad, and there is no wiring and copper-cladding between the flash memory chip, the isolation chip and the analog-to-digital converter chip; The lower substrate and the upper substrate are provided with a copper-clad area for analog ground and a copper-clad area for analog power, and the distance between the copper-clad area for analog ground and the copper-clad area for analog power is greater than or equal to 1 mm.

[0009] Further, the flash memory chip, the isolation chip and the analog-to-digital converter chip are arranged on the upper substrate by bonding, and the field programmable gate array chip is soldered on the lower substrate.

[0010] Further, the field programmable gate array chip, the flash memory chip, the isolation chip and the analog-to-digital converter chip are all connected to the pad through side interconnect signal lead-out terminals, the side interconnect signal lead-out terminals are located on the side of the digital isolation chip package structure, and the distance between the side interconnect signal lead-out terminals is greater than or equal to 1 mm.

[0011] Further, the side interconnect signal lead-out terminals include digital signal lead-out terminals and analog signal lead-out terminals, the digital isolation chip package structure includes four sides, the digital signal lead-out terminals are located on two opposite sides of the digital isolation chip package structure, and the analog signal lead-out terminals are located on the other two opposite sides of the digital isolation chip package structure.

[0012] Further, an insulating glue is potted between the lower substrate and the upper substrate, and on the upper substrate.

[0013] Further, the isolation chip includes a power isolation chip and two signal isolation chips, the power isolation chip is electrically connected to the two signal isolation chips respectively, the two signal isolation chips are electrically connected to each other, an isolation area is provided on the upper substrate, and the isolation chip is located in the isolation area.

[0014] Furthermore, the dummy pad is located between the analog signal pad and the digital signal pad, specifically as follows: There are multiple dummy pads, which are distributed in a strip shape, dividing the area where the analog signal pad is located from the area where the digital signal pad is located.

[0015] Furthermore, solder balls are connected to both the analog signal pad and the digital signal pad.

[0016] Compared with the prior art, the present invention has the following beneficial effects: 1. On the lower substrate of the present invention, a field programmable gate array chip is arranged. The field programmable gate array chip has high flexibility and reconfigurability, and can be programmed according to different application requirements to implement different logic functions, enabling the entire packaging structure to adapt to various application scenarios and improving the versatility and scalability of the system. The upper substrate and the lower substrate are connected by vertical stacking, significantly reducing the overall size of the packaging structure and improving the space utilization rate. The upper substrate and the lower substrate are connected by vertical stacking, and through three-dimensional stacking packaging, the overall size of the packaging structure is significantly reduced, making the equipment with the same function more compact. By reasonably arranging the field programmable gate array chip, two analog-to-digital converter chips and two groups of isolation chips, it is beneficial to reduce the signal trace length, and thus beneficial to reduce signal interference. Using the dummy pad to isolate the analog signal pad and the digital signal pad is beneficial to reduce signal interference. While meeting the miniaturization requirements, the present invention significantly reduces the interference between digital signals and analog signals.

[0017] 2. The flash memory chip of the present invention is located between two analog-to-digital converter chips, and the two analog-to-digital converter chips are symmetrically arranged with respect to the flash memory chip, which is beneficial to make the heat distribution more uniform among the chips, beneficial to improving the signal integrity and at the same time improving the electrical performance of the module.

[0018] 3. In the present invention, no wiring and copper plating are carried out in the interval on the upper substrate where the flash memory chip, the isolation chip and the analog-to-digital converter chip are located, and no wiring and copper plating are carried out between the flash memory chip, the isolation chip and the analog-to-digital converter chip, which is beneficial to ensuring the isolation requirements and reducing signal interference.

[0019] 4. In the present invention, the distance between the copper plating area of the analog ground and the copper plating area of the analog power is greater than or equal to 1 mm, and the distance between the side interconnect signal lead-out ends is greater than or equal to 1 mm, which is beneficial to ensuring the isolation requirements and reducing signal interference.

[0020] 5. In the present invention, the digital signal lead-out ends are located on two opposite sides of the digital isolation chip packaging structure, and the analog signal lead-out ends are located on the other two opposite sides of the digital isolation chip packaging structure, further reducing the mutual interference between the analog signal and the digital signal.

[0021] 6. An insulating adhesive is potted between the lower substrate and the upper substrate of the present invention, further reducing signal interference.

[0022] 7. Multiple non-soldered pads of the present invention are distributed in strips, dividing the area where the analog signal pads are located from the area where the digital signal pads are located, further reducing signal interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a schematic diagram of the lower substrate of an embodiment of the present invention; Figure 2 It is a schematic diagram of the upper substrate of an embodiment of the present invention; Figure 3 For an embodiment of the present invention Figure 2 A - A sectional view; Figure 4 It is a distribution diagram of the side interconnection lines of an embodiment of the present invention; Figure 5 It is a design diagram of the external BGA (Ball Grid Array) isolation of an embodiment of the present invention.

[0024] Wherein: 1. Lower substrate; 2. Upper substrate; 3. Field Programmable Gate Array (FPGA) chip; 4. Flash memory chip; 5. Isolation chip; 501. Signal isolation chip; 502. Power isolation chip; 6. Analog - to - Digital Converter (ADC) chip; 7. Solder ball; 8. Pad; 9. Analog signal pad; 10. Digital signal pad; 11. Non - soldered pad. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0025] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0026] It should be noted that the terms "first", "second", etc. in the description of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data used can be interchanged under appropriate circumstances, so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or are inherent to these processes, methods, products or devices.

[0027] The following are the explanations of relevant terms of the present invention: BGA (Ball Grid Array) is a ball grid array package, which is a high-density surface mount packaging technology.

[0028] POP side interconnection refers to a technology for electrical connection through the side of a package. This technology allows another package to be stacked on one package, and signal transmission between the two is achieved through the side interconnection structure.

[0029] The following further describes the present invention in detail with reference to the drawings: See Figures 1 to 3 , the present invention discloses a micro-system isolation layout structure based on three-dimensional stacked packaging, including: a lower substrate 1, an upper substrate 2, and a pad 8.

[0030] See Figure 2 , two analog-to-digital converter chips 6 and two groups of isolation chips 5 are coplanarly arranged on the upper substrate 2. The two analog-to-digital converter chips 6 are located on one side of the upper substrate 2, and the two groups of isolation chips 5 are located on the other side of the upper substrate 2, which is beneficial to make the heat distribution more uniform among the chips, and at the same time is beneficial to reducing the signal trace length, thereby reducing signal interference. The isolation chips 5 are placed with the parts of analog ground and analog power close to the analog-to-digital converter chips 6, which is beneficial to reducing the signal trace length, thereby reducing signal interference and loss; See Figure 1 , a field programmable gate array chip 3 is arranged on the lower substrate 1. The field programmable gate array chip 3 has high flexibility and reconfigurability, can be programmed according to different application requirements to implement different logic functions, so that the entire packaging structure can adapt to a variety of application scenarios, and improves the versatility and scalability of the system.

[0031] See Figure 3, the field programmable gate array chip 3 is located between the lower substrate 1 and the upper substrate 2, that is, the upper substrate 2 and the lower substrate 1 are connected by vertical stacking, significantly reducing the overall size of the packaging structure and improving the space utilization rate.

[0032] See Figure 5 , a solder pad 8, the solder pad 8 is located on the bottom surface of the lower substrate 1, the lower substrate 1 is located between the solder pad 8 and the field programmable gate array chip 3, the solder pad 8 includes an analog signal solder pad 9, a digital signal solder pad 10 and an empty solder pad 11, the empty solder pad 11 is located between the analog signal solder pad 9 and the digital signal solder pad 10, using the empty solder pad 11 to isolate the analog signal solder pad 9 and the digital signal solder pad 10, thus ensuring the signal transmission quality and being beneficial to reducing signal interference, the analog signal solder pad 9 is used to receive analog signals, and the digital signal solder pad 10 is used to receive digital signals.

[0033] Through three-dimensional stacked packaging, the present invention significantly reduces the overall size of the packaging structure, making devices with the same functions more compact. By reasonably arranging the field programmable gate array chip 3, two analog-to-digital converter chips 6 and two groups of isolation chips 5, it is beneficial to reduce the signal trace length, and thus beneficial to reducing signal interference. Using the empty solder pad 11 to isolate the analog signal solder pad 9 and the digital signal solder pad 10 is beneficial to reducing signal interference. That is, while meeting the miniaturization requirements, the present invention significantly reduces the interference between digital signals and analog signals.

[0034] Embodiment 1: See Figures 1 to 3 , this embodiment discloses a micro-system isolation layout structure based on three-dimensional stacked packaging, including: a lower substrate 1, an upper substrate 2 and a solder pad 8.

[0035] See Figure 2 , two analog-to-digital converter chips 6 and two groups of isolation chips 5 are coplanarly arranged on the upper substrate 2, the two analog-to-digital converter chips 6 are located on one side of the upper substrate 2, the two groups of isolation chips 5 are located on the other side of the upper substrate 2, and the part of the isolation chip 5 with analog ground and analog power is placed close to the analog-to-digital converter chip 6; See Figure 1 , a field programmable gate array chip 3 is arranged on the lower substrate 1, see Figure 3 , the field programmable gate array chip 3 is located between the lower substrate 1 and the upper substrate 2; See Figure 5, the pad 8 is located on the bottom surface of the lower substrate 1, the lower substrate 1 is located between the pad 8 and the field programmable gate array chip 3, the pad 8 includes an analog signal pad 9, a digital signal pad 10 and an empty pad 11, and the empty pad 11 is located between the analog signal pad 9 and the digital signal pad 10.

[0036] Preferably, referring to Figure 2 , a flash memory chip 4 is further provided on the upper substrate 2, the flash memory chip 4 is coplanarly arranged with the analog-to-digital converter chip 6 and the isolation chip 5, and the flash memory chip 4 is located between two analog-to-digital converter chips 6.

[0037] Preferably, referring to Figure 2 , the two analog-to-digital converter chips 6 are symmetrically arranged with respect to the flash memory chip 4, which is beneficial to make the heat distribution more uniform among the chips, beneficial to improving the signal integrity and at the same time improving the electrical performance of the module.

[0038] Preferably, the area on the upper substrate 2 where the flash memory chip 4, the isolation chip 5 and the analog-to-digital converter chip 6 are located is not wired and copper-clad, and there is no wiring and copper-cladding between the flash memory chip 4, the isolation chip 5 and the analog-to-digital converter chip 6, which is beneficial to ensuring the isolation requirement and reducing signal interference; The lower substrate 1 and the upper substrate 2 are provided with a copper-clad area for analog ground and a copper-clad area for analog power, and the distance between the copper-clad area for analog ground and the copper-clad area for analog power is greater than or equal to 1 mm, which is beneficial to ensuring the isolation requirement and reducing signal interference.

[0039] Preferably, the flash memory chip 4, the isolation chip 5 and the analog-to-digital converter chip 6 are arranged on the upper substrate 2 by bonding, and the field programmable gate array chip 3 is soldered on the lower substrate 1.

[0040] Preferably, the field programmable gate array chip 3, the flash memory chip 4, the isolation chip 5 and the analog-to-digital converter chip 6 are all connected to the pad 8 through side interconnect signal lead-out terminals, the side interconnect signal lead-out terminals are located on the side of the digital isolation chip package structure, and the distance between the side interconnect signal lead-out terminals is greater than or equal to 1 mm, which is beneficial to ensuring the isolation requirement and reducing signal interference. Refer to Figure 4 This is the side interconnect line distribution diagram of the embodiment of the present invention.

[0041] Preferably, the side interconnect signal lead-out terminals include digital signal lead-out terminals and analog signal lead-out terminals. The digital isolation chip package structure has four sides. The digital signal lead-out terminals are located on two opposite sides of the digital isolation chip package structure, and the analog signal lead-out terminals are located on the other two opposite sides of the digital isolation chip package structure, reducing the mutual interference between analog signals and digital signals.

[0042] Preferably, referring to Figure 3 , an insulating adhesive is potted between the lower substrate 1 and the upper substrate 2, and an insulating adhesive is potted on the upper substrate 2, further reducing signal interference.

[0043] Preferably, the isolation chip 5 includes a power isolation chip 502 and two signal isolation chips 501. The power isolation chip 502 is electrically connected to the two signal isolation chips 501 respectively, and the two signal isolation chips 501 are electrically connected to each other. An isolation area is provided on the upper substrate 2, and the isolation chip 501 is located within the isolation area.

[0044] Preferably, the dummy pad 11 is located between the analog signal pad 9 and the digital signal pad 10. Referring to Figure 5 , specifically as follows: There are multiple dummy pads 11, and the multiple dummy pads 11 are distributed in a strip shape, dividing the area where the analog signal pad 9 is located from the area where the digital signal pad 10 is located, further reducing signal interference.

[0045] Preferably, solder balls 7 are connected to both the analog signal pad 9 and the digital signal pad 10.

[0046] The present invention combines various processes of POP in a limited space, and effectively avoids the interference between digital signals and analog signals by adopting certain isolation measures.

[0047] Embodiment 2: In order to avoid the mutual influence between digital signals and analog signals in the system-in-package (SiP) of the analog-to-digital converter chip 6 and the isolation chip 5 during module integration, the present invention discloses a micro-system isolation layout structure based on three-dimensional stacked packaging and a micro-system packaging isolation method based on 3D POP (Package on Package, three-dimensional stacked packaging), which can meet the requirements of system-in-package (SiP) for high reliability, small volume, and functional integration of micro-system modules.

[0048] The designed SiP microsystem internally integrates two analog-to-digital converter (ADC) chips 6, one field programmable gate array (FPGA) chip 3, one flash memory chip 4, and two groups of isolation chips 5. Except for the field programmable gate array chip 3, the rest are bare chips. Each group of isolation chips 5 includes two signal isolation chips 501 and one power isolation chip 502. For miniaturization design, the present invention adopts a two-layer POP stacking method. All the devices on the upper substrate 2 are bare chips and are assembled by bonding, while the devices on the lower substrate 1 are assembled by soldering. The signal interconnection of the devices on the upper and lower substrates is realized through side metal scribing, and finally, the signals of the packaged module are led out from 255 solder balls 7 at the bottom of the lower substrate 1.

[0049] First, when laying out the bare chips, it is necessary to reasonably plan the PCB layout (Printed Circuit Board Layout), reduce the signal trace length, and ensure the integrity of the isolation area to prevent electromagnetic interference from penetrating the isolation layer. For the isolation design of the bare chips, by dividing the isolation areas of the two signal isolation chips 501, no wiring or copper plating is carried out between the bare chips and the lower layer of the bare chip body, thus ensuring the isolation requirements. Second, when routing on the substrate, the copper plating areas of the analog ground and the analog power are respectively divided, and it is ensured that the distance between the analog ground and the analog power is greater than or equal to 1 mm to meet the isolation requirements. When potting between the upper and lower substrates, an isolation design is carried out by filling with insulating glue. In addition, when designing the side interconnection signal lead-out terminals, the positions of the digital signals and the analog signals are also considered. The analog signals are placed on two sides, and the digital signals are placed on the other two sides. The digital signals include the digital ground and the digital power, and the analog signals include the analog ground and the analog power. It is ensured that the distance between the digital ground and the analog ground is greater than or equal to 1 mm, and the distance between the digital power and the analog power is greater than or equal to 1 mm to meet the isolation requirements. Finally, there is the isolation design of the external BGA ball grid array of the lower substrate 1. There are 255 pads 8 on the lower substrate 1. The 255 pads 8 not only lead out most of the IO digital signals and some control signals of the field programmable gate array chip (FPGA) externally, but also lead out the analog signals of the analog-to-digital converter chip 6 through the PAD points. The center distance between adjacent PAD points is only 1.27 mm. Therefore, the distance between adjacent PAD points is relatively close, and there is a certain risk. The present invention classifies and counts the signal lead-out terminals of the external BGA ball grid array, and further ensures the system reliability by separating the analog signals of the analog-to-digital converter chip 6 from the surrounding digital signals through the empty pads 11 in space.

[0050] Innovative points of the present invention: By adopting an all-round, multi-type, and multi-angle isolation concept, potential signal interference hazards in the PCB design and packaging of traditional non-hermetic three-dimensional multi-chip system-in-package (SiP) modules are avoided. The main isolation avoidance methods are mainly reflected in the following aspects: 1. Isolation design for the PCB layout of bare chips; 2. Isolation design for the wiring area of the substrate; 3. Potting isolation design; 4. Isolation design for side interconnections; 5. Isolation design for BGA ball grid arrays.

[0051] The lead-out ends of the two-layer substrate are led out from the four sides of the substrate, and a system-in-package (SiP) module is fabricated by 3D stacking, sidewall metallization, and sidewall scribing for the two interconnected substrates, increasing the space utilization rate.

[0052] Based on miniaturization, the present invention can further achieve partition isolation through various isolation methods, thereby further ensuring the signal transmission quality and signal integrity of the system-in-package (SiP) module. The present invention can be applied to a large number of system-in-package (SiP) products based on three-dimensional stacked (3D Package on Package, 3D POP) microsystem packaging, with a certain degree of generality. In addition, the isolation design concept of this module runs through the entire POP packaging design process, and the interference avoidance method is more perfect. By adopting simple methods, the purpose of corresponding functional system integration is achieved, and certain support and guarantee are provided for the reliability of the module.

[0053] Embodiment 3: This embodiment provides a chip package structure for 16-channel digital isolation signal processing based on 3D POP. The layouts of the upper and lower two-layer substrates are as Figure 1 and Figure 2 shown. Among them, Figure 1 is the lower-layer substrate 1, which is a finished FPGA device packaged in a BGA ball grid array, Figure 2This is the upper substrate 2, which contains two analog-to-digital converter chips 6, one flash memory chip 4, and two groups of isolation chips 5. Each group of isolation chips 5 contains two signal isolation chips 501 and one power isolation chip 502. All the chips on the upper substrate 2 are bare chips. In terms of layout, on the one hand, in order to improve signal integrity and at the same time enhance the electrical performance of the module, and on the other hand, to make the heat distribution more uniform among the chips, we adopted a symmetric bare die structure layout. In addition, considering the isolation PCB layout of the bare chips, we placed the analog-to-digital converter chips 6 and the isolation chips 5 in separate areas, and at the same time placed the parts of the isolation chips 5 with analog ground and analog power close to the analog-to-digital converter chips 6. The layout of the remaining isolation chips 5 was placed with reference to the internal bonding diagram of the finished device.

[0054] Figure 2 This is the structural cross-sectional view of the B-side assembly process of the present invention. In terms of structure, the traditional POP side interconnection method is adopted, and the signals to be led out from the upper and lower substrates are led out through the substrate edge, and the upper and lower interconnections are carried out by means of sidewall interconnection.

[0055] Figure 3 This is the signal distribution diagram of the side interconnection lines of the upper and lower substrates after the PCB layout and wiring design are completed according to the signal isolation requirements. It can be seen from the figure that we place the analog signals on the lower side of the B side and the upper side of the D side of the substrate by means of zoning, and the remaining signals are distributed on both sides. Although there are also digital signals and analog signals on both sides, we also separated them by leaving a certain number of flying lead legs, ensuring that the interval between the digital signals and the analog signals is greater than or equal to 1 mm, guaranteeing the partition isolation of the analog signals and digital signals on each layer of the substrate of the module.

[0056] In the process flow of 3D POP, after each layer of the substrate is assembled, stacking and potting will be carried out, that is, the two substrates are stacked vertically, with a spacer placed in the middle, and the potting glue is injected into it. In order to ensure the signal quality of the upper and lower substrates, an insulating potting glue is used for signal isolation between the substrate layers. The potted body exposes the analog signal lead-out ends around the substrate on the side of the module through die cutting. The die-cut body realizes the attachment of the conductor on the surface of the module through surface metallization, and then connects the lead-out ends required for interconnection of the two substrates through sidewall scribing, and finally leads out from the BGA pads at the bottom.

[0057] Figure 4 This is the isolation design diagram of the BGA ball grid array for the module to the outside. Among them, the pads within the red frame are the dummy pads 11, the pads within the blue frame are the analog signal pads 9, and the pads within the middle yellow area are the digital signal pads 10. It can be clearly seen from the figure that we separate the digital signals and the analog signals by setting the dummy pads 11, thus ensuring the signal transmission quality and the reliability of the module.

[0058] The above content is only to illustrate the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any modification made on the basis of the technical solution in accordance with the technical idea proposed by the present invention falls within the protection scope of the present invention.

Claims

1. A microsystem isolation layout structure based on three-dimensional stacked packaging, characterized in that: include: An upper substrate (2), wherein two analog-to-digital converter chips (6) and two groups of isolation chips (5) are coplanarly arranged on the upper substrate (2), the two analog-to-digital converter chips (6) are located on one side of the upper substrate (2), the two groups of isolation chips (5) are located on the other side of the upper substrate (2), and the isolation chip (5) with an analog ground and an analog electrical portion is placed close to the analog-to-digital converter chip (6); A lower substrate (1), a field programmable gate array chip (3) being arranged on the lower substrate (1), and the field programmable gate array chip (3) being located between the lower substrate (1) and the upper substrate (2); A pad (8), the pad (8) being located on the bottom surface of a lower substrate (1), the lower substrate (1) being located between the pad (8) and the field programmable gate array chip (3), the pad (8) comprising an analog signal pad (9), a digital signal pad (10) and an empty pad (11), the empty pad (11) being located between the analog signal pad (9) and the digital signal pad (10), the analog signal pad (9) being used to receive an analog signal, and the digital signal pad (10) being used to receive a digital signal.

2. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 1, characterized in that: A flash memory chip (4) is also provided on the upper substrate (2); the flash memory chip (4) is arranged coplanarly with the analog-to-digital converter chip (6) and the isolation chip (5); and the flash memory chip (4) is located between the two analog-to-digital converter chips (6).

3. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 2, characterized in that: No wiring or copper cladding is performed in the area where the flash memory chip (4), the isolation chip (5) and the analog-to-digital converter chip (6) are located on the upper substrate (2), and no wiring or copper cladding is performed between the flash memory chip (4), the isolation chip (5) and the analog-to-digital converter chip (6); The lower substrate (1) and the upper substrate (2) are provided with a simulated ground copper-clad area and a simulated electrical copper-clad area, and the distance between the simulated ground copper-clad area and the simulated electrical copper-clad area is greater than or equal to 1 mm.

4. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 2, characterized in that: The flash memory chip (4), the isolation chip (5) and the analog-to-digital converter chip (6) are arranged on the upper substrate (2) by bonding, and the field programmable gate array chip (3) is welded on the lower substrate (1).

5. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 2, characterized in that: The field programmable gate array chip (3), the flash memory chip (4), the isolation chip (5) and the analog-to-digital converter chip (6) are all connected to the pad (8) via side interconnection signal lead-out terminals, the side interconnection signal lead-out terminals are located on the side of the digital isolation chip packaging structure, and the distance between the side interconnection signal lead-out terminals is greater than or equal to 1 mm.

6. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 5, characterized in that: The side interconnect signal lead-out terminal includes a digital signal lead-out terminal and an analog signal lead-out terminal. The digital isolation chip packaging structure includes four side surfaces. The digital signal lead-out terminal is located on two opposite side surfaces of the digital isolation chip packaging structure, and the analog signal lead-out terminal is located on the other two opposite side surfaces of the digital isolation chip packaging structure.

7. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 1, characterized in that: Insulating glue is encapsulated between the lower substrate (1) and the upper substrate (2), and on the upper substrate (2).

8. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 1, characterized in that: The isolation chip (5) comprises a power isolation chip (502) and two signal isolation chips (501); the power isolation chip (502) is electrically connected to the two signal isolation chips (501) respectively, and the two signal isolation chips (501) are electrically connected to each other; an isolation area is provided on the upper substrate (2), and the isolation chip (501) is located in the isolation area.

9. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 1, characterized in that: The empty pad (11) is located between the analog signal pad (9) and the digital signal pad (10), specifically as follows: There are a plurality of empty pads (11), and the plurality of empty pads (11) are distributed in strips, dividing the area where the analog signal pads (9) are located from the area where the digital signal pads (10) are located.

10. The microsystem isolation layout structure based on three-dimensional stacked packaging according to claim 1, characterized in that: The analog signal pad (9) and the digital signal pad (10) are both connected to solder balls (7).

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