Electronic device and method of manufacturing same

Abstract

An electronic device and a method of manufacturing the electronic device. In one example, an electronic device may include an electronic component, a component passivation layer coupled to the electronic component, and a component interconnect extending from the electronic component through the component passivation layer. A substrate may be coupled to the component passivation layer and the component interconnect. The substrate may include a substrate passivation layer coupled to the device passivation layer along a bonding boundary, and the substrate passivation layer may include an inorganic material. A substrate inward terminal extends through the substrate passivation layer and may be coupled to the component interconnect along the bonding boundary. A seed crystal is located between the substrate passivation layer and the substrate inward terminal. A dielectric structure may be coupled to the substrate passivation layer. A conductive structure extends through the dielectric structure and is coupled to the substrate inward terminal. Other examples and related methods are also disclosed herein.

Description

Technical Field

[0001] The present disclosure relates generally to electronic devices, and more particularly, to electronic devices and methods for making electronic devices. Background Art

[0002] Previous electronic packages and methods for forming electronic packages are inadequate, for example, resulting in excessive cost, reduced reliability, relatively low performance, or excessive package size. Other limitations and disadvantages of the known and conventional methods will become apparent to those of ordinary skill in the art by comparing these methods with the present disclosure and referring to the drawings. Summary of the invention

[0003] One aspect of the present invention is an electronic device comprising: an electronic component; a component passivation layer coupled to the electronic component; a component interconnect extending from the electronic component through the component passivation layer; a substrate coupled to the component passivation layer and the component interconnect, the substrate comprising: a substrate passivation layer coupled to the component passivation layer along a bonding boundary, wherein the substrate passivation layer comprises an inorganic material; a substrate inward terminal extending through the substrate passivation layer and coupled to the component interconnect along the bonding boundary; a seed crystal located between the substrate passivation layer and the substrate inward terminal; a dielectric structure coupled to the substrate passivation layer; and a conductive structure extending through the dielectric structure and coupled to the substrate inward terminal. In the electronic device, the substrate inward terminal comprises a gold-copper alloy. In the electronic device, the substrate passivation layer is bonded to the component passivation layer along the bonding boundary by covalent bonding. In the electronic device, the component interconnect is bonded to the substrate inward terminal in response to metal migration from the substrate inward terminal across the bonding boundary. In the electronic device, the metal from the substrate inward terminal comprises gold. In the electronic device, an end of the seed is spaced apart from the bonding boundary by a thickness of the seed. In the electronic device, the dielectric structure comprises an organic material. The electronic device further comprises a base substrate coupled to the substrate, the base substrate comprising: a base substrate dielectric structure coupled to the dielectric structure of the substrate; and a base substrate conductive structure interleaved with the base substrate dielectric structure and coupled to the conductive structure of the substrate.

[0004] Another aspect of the present invention is a method of manufacturing an electronic device, comprising: providing a substrate passivation layer defining a pore and comprising an inorganic material; providing a seed crystal over the substrate passivation layer and in the pore; providing a conductive structure over the seed crystal and in the pore, the conductive structure comprising a substrate inward terminal; providing a dielectric structure over the seed crystal and the substrate passivation layer; removing a portion of the seed crystal to expose a side of the substrate inward terminal, wherein the side of the substrate inward terminal is recessed from a side of the substrate passivation layer by a recessed height; providing an electronic component including a component passivation layer over the substrate passivation layer, wherein the electronic component defines a gap between the exposed side of the substrate inward terminal and a component interconnect of the electronic component; coupling the substrate passivation layer to the component passivation layer along a bonding boundary; and bonding the substrate inward terminal to the component interconnect along the bonding boundary by applying a bonding temperature. In the method, the metal of the component interconnect diffuses across the bonding boundary in response to applying the bonding temperature. In the method, the bonding temperature is between 250° C. and 400° C. In the method, the recess height is equal to the thickness of the removed portion of the seed crystal. In the method, the dielectric structure comprises an organic material. In the method, the substrate-inward terminal further comprises: a barrier layer coupled to the conductive structure; and an interface layer coupled to the barrier layer, the interface layer comprising a gold portion and a copper portion. The method further comprises forming a gold-copper alloy from the gold portion and the copper portion by applying an alloying temperature.

[0005] Another aspect of the present invention is an electronic device, comprising: an electronic component, comprising: a component passivation layer coupled to the electronic component; and a component interconnect extending from the electronic component through the component passivation layer, wherein one side of the component passivation layer and one side of the component interconnect are positioned along a bonding boundary; and a substrate coupled to the electronic component, the substrate comprising: a substrate passivation layer coupled to the component passivation layer along the bonding boundary, wherein the substrate passivation layer includes an inner wall defining a pore; a seed coupled to the inner wall of the substrate passivation layer; an interface layer coupled to the component interconnect along the bonding boundary and coupled to the seed; a barrier layer coupled to the interface layer, wherein the interface layer is located between the seed and the barrier layer; a dielectric structure coupled to the substrate passivation layer; and a conductive structure extending through the dielectric structure and into the pore, wherein the conductive structure is coupled to the barrier layer. In the electronic device, the interface layer comprises a gold-copper alloy. In the electronic device, gold from the gold-copper alloy diffuses across the bonding boundary. In the electronic device, an end of the seed crystal is spaced apart from the bonding boundary. In the electronic device, the substrate passivation layer and the device passivation layer comprise an inorganic material, and wherein the dielectric structure of the substrate comprises an organic material. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A cross-sectional view of an exemplary electronic device is shown.

[0007] Figure 1A exhibit Figure 1 Detailed view of an exemplary electronic device.

[0008] FIG. 2A to FIG. 2H A cross-sectional view of an exemplary method for fabricating an exemplary electronic device is shown.

[0009] Figure 3 A cross-sectional view of an exemplary electronic device is shown.

[0010] FIG. 4A to FIG. 4C A cross-sectional view of an exemplary electronic device is shown.

[0011] Figure 5 A cross-sectional view of an exemplary electronic device is shown.

[0012] Figure 5A exhibit Figure 5 Detailed view of an exemplary electronic device.

[0013] 6A to 6H An example method for fabricating an exemplary electronic device is shown using cross-sectional views. DETAILED DESCRIPTION

[0014] The following discussion provides various examples of electronic devices and methods of making electronic devices. These examples are non-limiting, and the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the terms "example" and "for example" are non-limiting.

[0015] The drawings illustrate the general manner of construction, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. In addition, the elements in the drawings are not necessarily drawn to scale. For example, the size of some elements in the drawings may be enlarged relative to other elements to help improve the understanding of the examples discussed in the present disclosure. The same element symbols in different drawings represent the same elements.

[0016] The term "or" means any one or more of the items in the list joined by "or". As an example, "x or y" means any element in the three-element set {(x), (y), (x, y)}. As another example, "x, y or z" means any element in the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0017] The terms “comprises,” “comprising,” “includes,” and “including” are “open” terms and specify the presence of stated features but do not preclude the presence or addition of one or more other features.

[0018] The terms "first," "second," etc. may be used herein to describe various elements, but the elements described should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, for example, a first element discussed in the present disclosure may be referred to as a second element without departing from the teachings of the present disclosure.

[0019] Unless otherwise specified, the term "coupled" may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly coupled via one or more other elements. For example, if element A is coupled to element B, element A may be in direct contact with element B or indirectly coupled to element B via an intervening element C. Similarly, the terms "above" or "on..." may be used to describe two elements that are in direct contact with each other or to describe two elements that are indirectly coupled via one or more other elements. As used herein, the term "coupled" may refer to electrical coupling or mechanical coupling.

[0020] An exemplary electronic device may include an electronic component, a component passivation layer coupled to the electronic component, and a component interconnect extending from the electronic component through the component passivation layer. A substrate may be coupled to the component passivation layer and the component interconnect. The substrate may include a substrate passivation layer coupled to the component passivation layer along a bonding boundary, and the substrate passivation layer may include an inorganic material. A substrate inward terminal extends through the substrate passivation layer and may be coupled to the component interconnect along the bonding boundary. A seed is located between the substrate passivation layer and the substrate inward terminal. A dielectric structure may be coupled to the substrate passivation layer. A conductive structure extends through the dielectric structure and is coupled to the substrate inward terminal.

[0021] An exemplary method of manufacturing an electronic device includes the following steps: providing a substrate passivation layer that defines a pore and includes an inorganic material; providing a seed crystal over the substrate passivation layer and in the pore; and providing a conductive structure over the seed crystal and in the pore. The conductive structure may include a substrate inward terminal. The dielectric structure may be provided over the seed crystal layer and the substrate passivation layer. A portion of the seed crystal may be removed to expose a side of the substrate inward terminal. The side of the substrate inward terminal may be recessed from a side of the substrate passivation layer by a recess height. The electronic component may include a component passivation layer located over the substrate passivation layer. The electronic component defines a gap between the exposed side of the substrate inward terminal and a component interconnect of the electronic component. The substrate passivation layer may be coupled to the component passivation layer along a bonding boundary. The substrate inward terminal may be bonded to the component interconnect along the bonding boundary by applying a bonding temperature.

[0022] An exemplary electronic device may include an electronic component including a component passivation layer coupled to the electronic component and a component interconnect extending from the electronic component through the component passivation layer. One side of the component passivation layer and one side of the component interconnect may be positioned along a bonding boundary. A substrate may be coupled to the electronic component. The substrate includes a substrate passivation layer coupled to the component passivation layer along a bonding boundary. The substrate passivation layer includes an inner wall defining a pore. A seed may be coupled to the inner wall of the substrate passivation layer. An interface layer is coupled to the component interconnect along the bonding boundary and to the seed. A barrier layer may be coupled to the interface layer, wherein the interface layer is located between the seed and the barrier layer. A dielectric structure may be coupled to the substrate passivation layer. A conductive structure extends through the dielectric structure and into the pore. The conductive structure is coupled to the barrier layer.

[0023] Other examples are included in the present disclosure. These examples can be found in the drawings, the claims, or in the detailed description of the present disclosure.

[0024] Various examples use bonding techniques that strictly control material thickness or height along the bonding surface to compensate for mismatched coefficients of thermal expansion (CTE) between adjacent materials. In some examples, the metal bonding surface can be recessed from the inorganic insulating surface to a predetermined recess height. The recess height can be strictly controlled using titanium (Ti) etching or other etching techniques to control the recess height. Etching tends to leave a smoother surface compared to chemical mechanical polishing (CMP) processes that can leave particles or surface defects. Some examples may include gold (Au) and copper (Cu) alloy bonding interfaces. Various examples also include hybrid redistribution structures (e.g., having both inorganic and organic layers) with hybrid bonding interfaces. The hybrid bonding interface can be liner-free to improve (e.g., reduce) the pitch.

[0025] Figure 1 A cross-sectional view of an exemplary electronic device 100 is shown. Figure 1A For Figure 1 An enlarged view of the electronic device 100 in area A of FIG. Figure 1 and 1A In the example shown in , the electronic device 100 may include one or more electronic components 110 , a substrate 120 , a substrate interconnect 130 , and an encapsulation body 140 .

[0026] Electronic component 110 may include component interconnect 111 and component passivation layer 113. Substrate 120 may include dielectric structure 121, conductive structure 122 and substrate passivation layer 123. Conductive structure 122 may include substrate inward terminal 122a, seed 122s, inner conductive structure 122i and substrate outward terminal 122b.

[0027] FIG. 2A to FIG. 2H A cross-sectional view of an exemplary method for manufacturing an exemplary electronic device such as electronic device 100 is shown.

[0028] Figure 2A A cross-sectional view of the electronic device 100 is shown at an early stage of manufacture. Figure 2AIn the example shown in , the substrate passivation layer 123 may be disposed on the surface of the carrier 10. The substrate passivation layer 123 may be disposed by deposition or coating to cover the entire surface of the carrier 10. For example, the substrate passivation layer 123 may be disposed by deposition such as physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). For example, the substrate passivation layer 123 may be disposed by coating, such as spin coating, spray coating, dip coating, or rod coating.

[0029] In some examples, the substrate passivation layer 123 may include an inorganic material. For example, the substrate passivation layer 123 may be silicon oxide (SiO2), silicon carbon nitride (SiCN), or silicon nitride (SiN). In some examples, the thickness of the substrate passivation layer 123 may be in the range of about 0.1 micrometers (μm) to 20 μm. As used herein to describe a measurement of displacement, distance, or length, the term approximately may mean + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%.

[0030] The carrier 10 may be a substantially flat plate. In some examples, the carrier 10 may include or be referred to as a plate, a board, a wafer, a panel, or a strip. The carrier 10 may be made of metal, ceramic, or a semiconductor material. In some examples, the carrier 10 may be made of glass (e.g., soda-lime glass). The thickness of the carrier 10 may be in the range of about 300 μm to about 2000 μm, and the width of the carrier 10 may be in the range of about 100 millimeters (mm) to about 300 mm. The carrier 10 may enable handling and manufacturing of multiple devices during the process of setting the substrate 120.

[0031] After the mask pattern is formed on the top side of the substrate passivation layer 123, the pores 123a can be provided in the substrate passivation layer 123 by removing the portion of the substrate passivation layer 123 exposed from the mask pattern through etching. The pores 123a can be defined by the inner wall of the substrate passivation layer 123. The top side of the carrier 10 can be exposed through the pores 123a. In some examples, the mask pattern can include a photoresist. The mask pattern can be removed after the substrate passivation layer 123 is patterned.

[0032] Figure 2B A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2B In the example shown in FIG. 1 , the seed crystal 122 s may be disposed to cover the substrate passivation layer 123 and the carrier 10 .

[0033] The seed 122s may contact the top side of the substrate passivation layer 123, the sidewalls of the pores 123a, and the top side of the carrier 10. In some examples, the seed 122s may be disposed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. In some examples, the seed 122s may be referred to as or include a conductive layer, a seed layer, or a buffer layer. In some examples, the seed 122s may include Ti, TiW, W, Cr, Al, Ni, Au, Ag, or Cu. In some examples, the thickness of the seed 122s may be in the range of about 0.01 μm to 0.1 μm, 0.01 μm to 0.05 μm, or 0.01 μm to 0.03 μm.

[0034] Figure 2C A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2C In the example shown in , the inner conductive structure 122i may be disposed above the seed crystal 122s.

[0035] The inner conductive structure 122i may be provided in a pattern, and the pattern may be in contact with and electrically coupled to the seed 122s. The inner conductive structure 122i may include one or more layers defining signal distribution elements. The inner conductive structure 122i may include or be referred to as a conductive path, a conductive layer, a trace, a pad, a via, a redistribution layer (RDL), a wiring pattern, an under bump metallization (UBM), or a circuit pattern. In some examples, the inner conductive structure 122i may include copper (Cu), aluminum (Al), nickel (Ni), palladium (Pd), titanium (Ti), tungsten (W), titanium / tungsten, gold (Au), silver (Ag), an alloy, or other suitable conductive materials known to those of ordinary skill in the art. The inner conductive structure 122i may be provided by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. In some examples, the inner conductive structure 122i may be provided by forming a mask pattern (eg, photoresist) covering a portion of an upper side of the seed 122s and then electroplating the inner conductive structure 122i using the seed 122s as a seed layer. After forming the inner conductive structure 122i, the mask pattern may be removed.

[0036] According to various examples, after forming the inner conductive structure 122i, the portion of the seed 122s not covered by the inner conductive structure 122i may be removed. In some examples, the portion of the seed 122s exposed from the inner conductive structure 122i may be removed by etching. As the seed 122s is removed, the substrate passivation layer 123 may be exposed. The seed 122s may have a plurality of patterns, such as the conductive structure 122, and may be included in the inner conductive structure 122i. According to various examples, the inner conductive structure 122i may include a substrate-inward terminal 122a and a substrate-inward terminal 122a along the top side of the substrate passivation layer 123 (e.g., at Figure 1 The inner conductive structure 122i may be a trace extending along a side of the substrate passivation layer 123 opposite to the electronic component 110. The substrate inner terminal 122a may fill the interior of the void 123a. The thickness of the inner conductive structure 122i may be in the range of about 0.5 μm to about 50 μm.

[0037] Figure 2D A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2D In the example shown in , the dielectric structure 121 and the conductive structure 122 may be disposed in alternating layers over the inner conductive structure 122 i and the substrate passivation layer 123 .

[0038] According to various examples, the dielectric structure 121 may include or be referred to as one or more dielectrics, dielectric materials, dielectric layers, passivation layers, insulating layers, or protective layers. In some examples, the dielectric structure 121 may include an organic dielectric material. For example, the dielectric structure 121 may include an electrically insulating material such as a polymer, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), Ajinomoto Buildup Film (ABF), a molding material, a phenolic resin, an epoxy resin, a polysilicone, or an acrylate polymer. In some examples, the dielectric structure 121 may be disposed by spin coating, spray coating, dip coating, rod coating, printing, oxidation, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other processes known to those of ordinary skill in the art. The dielectric structure 121 can maintain the shape of the substrate 120 and can also structurally support the conductive structure 122 and the electronic component 110 ( Figure 1 ). The dielectric structure 121 may be in contact with the conductive structure 122. The dielectric structure 121 may expose a portion of the conductive structure 122. For example, the substrate-outward terminal 122b may be exposed from a far side of the dielectric structure 121 (e.g., from a side opposite to or away from the substrate passivation layer 123). In some examples, the thickness of individual layers of the dielectric structure 121 may be in a range of about 3 μm to about 100 μm.

[0039] According to various specific examples, the conductive structure 122 may include or be referred to as one or more conductors, conductive materials, conductive paths, conductive layers, RDLs, routing layers, signal distribution elements, traces, vias, pads, or UBMs. In some examples, one or more of the conductive layers may be interlaced with the dielectric layers of the dielectric structure 121. In some examples, the conductive structure 122 may include Cu, Al, Ni, Pd, Ti, W, Ti / W, Au, Ag, alloys, or other suitable conductive materials known to those of ordinary skill in the art. In some examples, the conductive structure 122 may be disposed by sputtering, electroless plating, electrolytic plating, PVD, CVD, MOCVD, ALD, LPCVD, PECVD, or other processes known to those of ordinary skill in the art.

[0040] According to an example, the conductive structure 122 may include a substrate-inward terminal 122a, an inner conductive structure 122i, and a substrate-outward terminal 122b. In some examples, the substrate-inward terminal 122a may be exposed from the proximal side of the substrate 120, and the substrate-outward terminal 122b may be exposed from the distal side of the substrate 120. In some examples, the thickness of the conductive structure 122 may be in the range of about 1 μm to about 50 μm. The thickness of the conductive structure 122 may refer to the individual layers of the conductive structure 122. The conductive structure 122 may transmit a signal, current, or voltage within the substrate 120.

[0041] The substrate 120 may include alternating layers of dielectric structures 121 and conductive structures 122. Some specific examples may include a single layer of a substrate passivation layer 123 located between the carrier 10 and the dielectric structures 121. Although the substrate 120 is depicted as having four layers of dielectric structures 121 alternating with four layers of conductive structures 122, the number of layers may be greater or less than four. The substrate inward terminals 122a may include portions of the conductive structures 122 located in the pores 123a of the substrate passivation layer 123 on the proximal or inner side of the substrate 120 (e.g., portions of the inner conductive structures 122i). The substrate outward terminals 122b may include portions of the conductive structures 122 exposed through the dielectric structures 121 on the distal or outer side of the substrate 120.

[0042] According to various specific examples, the substrate 120 may include an RDL substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers, and may (a) be formed layer by layer over an electronic device to be electrically coupled to the RDL substrate, or (b) may be formed layer by layer over a carrier that may be completely or at least partially removed after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process, and / or may be manufactured layer by layer as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed in an additive buildup process, and may include one or more dielectric layers alternately stacked with one or more conductive layers, and define respective conductive redistribution patterns or traces configured to collectively (a) fan out electrical traces outside the footprint of the electronic device and / or (b) fan in electrical traces within the footprint of the electronic device. The conductive pattern may be formed using an electroplating process such as, for example, an electroplating process or an electroless plating process. The conductive pattern may include a conductive material such as, for example, copper or other electroplatable metals. The location of the conductive pattern may be manufactured using a photopatterning process such as, for example, a photolithography process and a photoresist material to form a lithography mask. The dielectric layer of the RDL substrate may be patterned using a photopatterning process and may include a lithography mask through which light is exposed to desired features of the photopattern such as through holes in the dielectric layer. The dielectric layer may be made of a photodefinable organic dielectric material such as, for example, polyimide (PI), BCB, or PBO. These dielectric materials may be spin-coated or otherwise applied in liquid form rather than attached as a preformed film. In order to allow the desired photodefinable features to be properly formed, these photodefinable dielectric materials may omit structural reinforcements or may be filler-free, without strands, braids, or other particles, and may interfere with light from the photopatterning process. In some examples, these filler-free properties of filler-free dielectric materials may allow the thickness of the resulting dielectric layer to be reduced. Although the photodefinable dielectric materials described above may be organic materials, in some examples, the dielectric material of the RDL substrate may include one or more inorganic dielectric layers. Some examples of one or more inorganic dielectric layers may include silicon nitride (Si3N4), silicon oxide (SiO2), or silicon oxynitride (SiON). One or more inorganic dielectric layers may be formed by growing inorganic dielectric layers using an oxidation or nitridation process rather than using photodefinable organic dielectric materials. These inorganic dielectric layers may be filler-free, without strands, braids, or other dissimilar inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as, for example, a dielectric material comprising bismaleimide triazine (BT) or FR4, and these types of RDL substrates may be referred to as coreless substrates. Other substrates in the present disclosure may also include RDL substrates.

[0043] Although the substrate 120 is Figure 2D1 is depicted as an RDL substrate, but it is contemplated and understood that in some examples, substrate 120 may be a preformed substrate. The preformed substrate may be manufactured before attachment to an electronic device and may include a dielectric layer between individual conductive layers. The conductive layer may include copper and may be formed using an electroplating process. The dielectric layer may be a relatively thick non-photodefinable layer and may be attached as a preformed film rather than a liquid, and may include a resin with a filler such as a strand, a braid, and / or other inorganic particles for rigidity and / or structural support. Since the dielectric layer is non-photodefinable, features such as through holes or openings may be formed by using a drill or laser. In some examples, the dielectric layer may include a prepreg material or ABF. The preformed substrate may include a permanent core structure or carrier, such as, for example, a dielectric material including bismaleimide triazine (BT) or FR4, and the dielectric layer and the conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate omitting a permanent core structure, and the dielectric and conductive layers may be formed on a sacrificial carrier and removed after the dielectric and conductive layers are formed and before being attached to an electronic device. The preformed substrate may be re-named a printed circuit board (PCB) or a laminate substrate. This preformed substrate may be formed by a semi-build-up or modified semi-build-up process. Other substrates in the present disclosure may also include a preformed substrate.

[0044] Figure 2E A cross-sectional view of the electronic device 100 is shown at a late manufacturing stage. Figure 2EA For Figure 2E An enlarged view of the electronic device 100 in area A of FIG. Figure 2E , the carrier 20 is attached to the outside of the substrate 120, the carrier 10 is removed from the inside of the substrate 120, and the substrate 120 is turned over, so the substrate passivation layer 123 and the inside of the substrate 120 are positioned at the upper side of the substrate 120. After turning over the substrate 120, the substrate-outward terminals 122b may be positioned at the bottom side of the substrate 120, and the substrate-inward terminals 122a may be positioned at the top side of the substrate 120.

[0045] The carrier 20 may include a temporary bonding layer 21 disposed on the surface of the carrier 20. The temporary bonding layer 21 of the carrier 20 may be attached to the substrate-outward terminal 122b and the dielectric structure 121 located at the bottom (or outer) side of the substrate 120. The temporary bonding layer 21 may be disposed on the surface of the carrier 20 by a coating method (such as spin coating, blade coating, casting, brushing, spraying, slot die coating, curtain coating, slide coating, or knife over edge coating), a printing method (such as screen printing, pad printing, gravure printing, elastic relief printing, or lithography) or an inkjet printing method (an intermediate technology between coating and printing), or may be disposed by directly attaching a bonding film or a bonding tape. In some examples, the temporary bonding layer 21 may be referred to as a temporary bonding film, a temporary bonding tape, or a temporary adhesive coating. For example, the temporary bonding layer may be a thermal release tape (film) or an optical release tape (film), wherein the adhesive strength is weakened or removed by heat or light, respectively. The temporary bonding layer 21 may allow the carrier 20 to be separated from the substrate 120 before providing the substrate interconnection 130 , as will be described later.

[0046] exist Figure 2E and Figure 2EA In the example shown in , the portion of seed 122s covering substrate inward terminal 122a may be removed. In some examples, seed 122s covering substrate inward terminal 122a may be removed via etching to expose the top side of substrate inward terminal 122a. Prior to removal, the top side of substrate passivation layer 123 may protrude upwardly from the top side of substrate inward terminal 122a by a height approximately equal to the height of seed layer 122s above substrate inward terminal 122a. Substrate inward terminal 122a may be recessed or concave relative to substrate passivation layer 123 by a height approximately equal to the thickness of seed layer 122s. In some examples, the thickness of seed layer 122s and / or the recess depth or recess distance D of the top side of substrate inward terminal 122a may be between about 0.01 μm to 0.1 μm, 0.01 μm to 0.05 μm, or 0.01 μm to 0.03 μm. In other words, the distance D between the top side of substrate passivation layer 123 and the top side of substrate inward terminal 122a may be about 0.01 μm to 0.1 μm, 0.01 μm to 0.05 μm, or 0.01 μm to 0.03 μm.

[0047] Figure 2F A cross-sectional view of the electronic device 100 is shown at a late manufacturing stage. Figure 2FA Before mixing Figure 2F An enlarged view of the electronic device 100 at area A of FIG. 1 , and Figure 2FB Shown after mixed joining Figure 2F The electronic device 100 at area A. Figure 2F ( Figure 2FA and Figure 2FB), the electronic component 110 may be disposed on the top side of the substrate 120.

[0048] In some examples, the pick-and-place equipment may pick up the electronic component 110 and place the electronic component to allow the component interconnect 111 of the electronic component 110 to be positioned at the top side of the substrate-inward terminal 122a of the substrate 120. The component passivation layer 113 of the electronic component 110 may contact the substrate passivation layer 123 of the substrate 120. The component interconnect 111 of the electronic component 110 may be spaced apart from the substrate-inward terminal 122a of the substrate 120 by a gap 124. The height of the gap 124 may be approximately equal to the recessed height or concave height of the top surface of the inner terminal 122a below the top surface of the substrate passivation layer 123.

[0049] In some examples, the passivation bond between the device passivation layer 113 and the substrate passivation layer 123 may initially start as a Van der Waals bond that develops into a covalent bond over time or temperature. In the case of a fixed passivation bond, the device interconnect 111 and the substrate inward terminal 122a may be urged toward each other by applying a bonding temperature until the gap 124 is closed. A direct bond may be established between the device interconnect 111 and the substrate inward terminal 122a. Bonding between the passivation layer 113 and the substrate passivation layer 123 may be achieved via a thermal treatment process. For example, prior to bonding, bonding between the passivation layer 113 and the substrate passivation layer 123 may be achieved at low temperature via surface activation. For example, by performing surface activation on the passivation layer 113 and the substrate passivation layer 123, hydrogen (H) may be generated on the surfaces of the passivation layer 113 and the substrate passivation layer 123 through plasma treatment, oxygen (O) particles separated from water or air during the plasma treatment may be bonded to the hydrogen (H) on the surfaces of the passivation layer 113 and the substrate passivation layer 123, and hydroxyl (OH) groups may be induced on the surfaces of the passivation layer 113 and the substrate passivation layer 123, respectively. The bonding between the passivation layer 113 and the substrate passivation layer 123 may be easily bonded at low temperatures. In some examples, the passivation layer 113 and the substrate passivation layer 123 may be bonded to each other at a temperature ranging from about 25° C. to about 400° C. As used herein to describe temperature, the term about may mean + / -5%, + / -10%, + / -15%, + / -20%, or + / -25%.

[0050] After the passivation layer 113 of the electronic component 110 and the substrate passivation layer 123 of the substrate 120 are initially bonded, the component interconnect 111 of the electronic component 110 and the substrate inward terminal 122a of the substrate 120 may be spaced apart from each other by a gap 124, such as Figure 2FA As shown in .

[0051] The component interconnect 111 and the substrate inward terminal 122a may be joined at a temperature that is higher than the temperature at which the passivation layer 113 and the substrate passivation layer 123 are joined. For example, the component interconnect 111 of the electronic component 110 and the substrate inward terminal 122a of the substrate 120 may be joined by a thermal compression process. In some examples, the component interconnect 111 and the substrate inward terminal 122a may be joined in response to a joining temperature in the range of about 150° C. to about 400° C. In some examples, the direct joining between the component interconnect 111 and the substrate inward terminal 122a may include or may be referred to as a fusion bond or a solderless bond. In some examples, the direct joining may include grain growth of materials of the component interconnect 111 and the substrate inward terminal 122a into each other. In some examples, direct bonding may be established by pressure from component interconnect 111 and substrate inward terminal 122 a expanding toward each other due to heat while being secured by bonding between passivation layer 113 and substrate passivation layer 123 .

[0052] Due to the temperature increase, component interconnect 111 and substrate inward terminal 122a may expand to fill void 124, thereby contacting and bonding with each other. Component interconnect 111 and substrate inward terminal 122a may have a greater thermal expansion coefficient than passivation layer 113 and substrate passivation layer 123. The separation distance between component interconnect 111 and substrate inward terminal 122a (e.g., the height of void 124) may compensate for the expansion due to temperature when bonding component interconnect 111 and substrate inward terminal 122a. Component interconnect 111 and substrate inward terminal 122a may be bonded together by a thermal compression process because their respective surfaces are in contact with each other and metal diffuses from component interconnect 111 and / or substrate inward terminal 122a across bonding boundary 125.

[0053] The substrate 120 may define a void 124 in the space left after the seed 122s is removed. The end of the seed 122s may be spaced from the bonding boundary 125 by the thickness of the removed portion of the seed 122s. Removing the seed 122s may control the recess depth by stripping off a material equal to the thickness or height of the seed 122s above the substrate inward terminal 122a. Etching the seed 122s may produce a recess depth without applying a separate CMP process or other recess adjustments to achieve the appropriate height of the void 124. By avoiding additional recess adjustments, the exposed side of the substrate inward terminal 122a may be substantially smooth. As used herein, the term substantially smooth may describe a surface that is free of burrs, grooves, or other defects that are typically left after a CMP process. Using the thickness of the seed 122s to adjust the recess depth may also allow greater control and / or a more precise recess depth.

[0054] In some examples, controlling the height of the void 124 (e.g., controlling the thickness of the seed 122s removed to form the void 124) can compensate for the difference in thermal expansion between the passivation layers 113 and 123, the device interconnect 111, and the conductive structure 122. The electronic component 110 and the substrate 120 can achieve low-temperature hybrid bonding by bonding the passivation layer 113 and the substrate passivation layer 123, which allows the device interconnect 111 and the substrate inward terminal 122a to expand into contact with each other and bond to each other at a suitable temperature (e.g., about 150° C. to about 400° C.).

[0055] Figure 2G A cross-sectional view of the electronic device 100 is shown at a later stage of manufacture. Figure 2G In the example shown in , the encapsulation body 140 can be disposed over the top (or inner) side of the substrate 120 and around the lateral sides of the electronic component 110. The encapsulation body 140 can be in contact with the top side of the substrate 120 and the top side and sidewalls of the electronic component 110. Thereafter, the upper portion of the encapsulation body 140 can be removed to expose the top side of the electronic component 110. The encapsulation body 140 can be coupled to the substrate passivation layer 123 outside of the footprint of the bonding boundary 125.

[0056] In some examples, the encapsulation body 140 may include or be referred to as a body or a molding. For example, the encapsulation body 140 may include an epoxy molding compound, a resin, a resin-reinforced polymer, a B-staged press film, or a gel. For example, the encapsulation body 140 may be provided by compression molding, transfer molding, liquid body molding, vacuum lamination, paste printing, or film-assisted molding.

[0057] In some examples, the upper portion of encapsulation body 140 may be removed by grinding. In some examples, the top side of encapsulation body 140 may be coplanar with the top side of electronic component 110. In some examples, the thickness of encapsulation body 140 may be in a range of about 10 μm to about 500 μm.

[0058] Figure 2H A cross-sectional view of the electronic device 100 is shown in a later stage of manufacturing. Figure 2H In the example shown in , the substrate interconnect 130 may be disposed on the substrate-outward terminal 122 b of the substrate 120 .

[0059] Before providing the substrate interconnection 130, the carrier 20 ( Figure 2G ) may be separated from the bottom side of the substrate 120. In some examples, after the adhesive force of the temporary bonding layer 21 inserted between the carrier 20 and the substrate 120 is removed or reduced by applying heat, light, a chemical solution, or a physical external force, the carrier 20 may be separated from the bottom side of the substrate 120. When the carrier 20 is removed, the substrate-outward terminals 122b may be exposed at the bottom (or outer) side of the substrate 120.

[0060] In some examples, carrier 30 may be attached to the top side of encapsulation body 140 and the top side of electronic component 110 before carrier 20 is removed. Carrier 30 may include elements, features, materials, or formation processes similar to those of carrier 20.

[0061] The substrate interconnect 130 may contact and couple to the substrate-outward terminal 122 b of the substrate 120 . In some examples, the substrate interconnect 130 may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. For example, after a conductive material containing solder is formed on the substrate-outward terminal 122 b using a ball drop method, the substrate interconnect 130 may be disposed via a reflow process. The substrate interconnect 130 may include or be referred to as a conductive ball, such as a solder ball, a conductive pillar (e.g., a kappa pillar), or a conductive pillar with a solder cap. In some examples, the substrate interconnect 130 may be a ball grid array or a land grid array outside the substrate 120 . In some examples, the size of substrate interconnect 130 may be in a range of about 10 μm to about 500 μm. Substrate interconnect 130 may be electrically connected to electronic component 110 through substrate 120 .

[0062] In some examples, a plurality of electronic devices 100 may be manufactured simultaneously, for example, on a panel or carrier. The electronic devices 100 may be separated into individual electronic devices 100 by a singulation process. For example, individual electronic devices 100 may be provided by singulation (e.g., cutting, sawing, dicing, etc.) through the encapsulation body 140 and the substrate 120. In some examples, the lateral sides of the encapsulation body 140 and the substrate 120 may be coplanar in response to the singulation.

[0063] Figure 3 An exemplary electronic device 101 is shown. According to various examples, the electronic device 101 may include the electronic device 100, a base substrate 150, an external interconnect 160, an adhesive layer 180, and a cover 190. In some examples, the electronic device 101 may include an underfill 170.

[0064] The base substrate 150 may include a base substrate dielectric structure 151 and a base substrate conductive structure 152. The base substrate conductive structure 152 may include a base substrate inward terminal 152a and a base substrate outward terminal 152b. The substrate interconnect 130 may couple the electronic device 100 to the conductive structure 152 of the base substrate 150. For example, the substrate interconnect 130 may be coupled between the outward terminal 122b of the substrate 120 and the base substrate inward terminal 152a.

[0065] Figure 4A A cross-sectional view of electronic device 101 is shown during manufacture. Figure 4A In the example shown in , the electronic device 100 can be placed over the substrate 150 using, for example, pick-and-place equipment. The substrate interconnects 130 can be placed on the base substrate-inward terminals 152a.

[0066] The base substrate 150 may include a base substrate dielectric structure 151 and a base substrate conductive structure 152. In some examples, the base substrate dielectric structure 151 may include or be referred to as one or more dielectric layers. For example, the one or more dielectric layers may include a core layer, a polymer layer, a prepreg layer, or a solder mask layer stacked one above the other. One or more layers or elements of the base substrate conductive structure 152 may be inserted or embedded between one or more layers of the base substrate dielectric structure 151. The upper side and the lower side of the base substrate dielectric structure 151 may include portions of the inner side and the outer side of the base substrate 150, respectively. In some examples, the base substrate dielectric structure 151 may include a polymer, PI, BCB, PBO, BT, ABF, or a resin. In some examples, the thickness of the base substrate dielectric structure 151 may be in the range of about 10 μm to 500 μm.

[0067] The base substrate conductive structure 152 may include one or more conductive layers that define conductive paths with elements such as, for example, traces, pads, vias, and wiring patterns. The base substrate conductive structure 152 may include a base substrate inward terminal 152a on the inner side of the base substrate 150 and a base substrate outward terminal 152b on the outer side of the base substrate 150.

[0068] The base substrate inward terminal 152a and the base substrate outward terminal 152b may have a matrix or array of columns or rows disposed on the inner side and the outer side of the base substrate 150, respectively. In some examples, the base substrate inward terminal 152a or the base substrate outward terminal 152b may include or be referred to as a conductor, a conductive material, a base pad, a conductive pad, a base pad, a wiring pad, a connection pad, a micro pad, or a UBM. The thickness of the base substrate inward terminal 152a or the base substrate outward terminal 152b may be in the range of about 1 μm to 50 μm. The base substrate inward terminal 152a may contact and couple to the substrate interconnect 130. The substrate interconnect 130 may be bonded to the base substrate inward terminal 152a using a reflow or thermal compression process. The base substrate conductive structure 152 of the base substrate 150 may be electrically connected to the component interconnect 111 of the electronic component 110 via the substrate interconnect 130 and the conductive structure 122 of the substrate 120.

[0069] In some examples, the base substrate 150 may include or be referred to as a rigid substrate, a flexible laminate substrate, a ceramic substrate, a glass substrate, a silicon substrate, a printed circuit board, a multilayer substrate, a laminate substrate, or a molded lead frame. In some examples, the base substrate 150 may include or be referred to as an RDL substrate, a build-up substrate, or a coreless substrate. In some examples, the base substrate 150 may have an area that varies according to the area of ​​the electronic device 100. In some examples, the base substrate 150 may have an area of ​​about 3 mm×3 mm to about 150 mm×150 mm. In some examples, the base substrate 150 may have a thickness in the range of about 0.1 mm to about 7 mm. In some examples, the base substrate 150 may include elements, features, materials, or formation processes similar to those of the substrate 120.

[0070] In some examples, the bottom filler 170 may be positioned between the substrate 120 and the base substrate 150. The bottom filler 170 may be in contact with the bottom side of the substrate 120 and the inner side or upper side of the base substrate 150. The bottom filler 170 may be in contact with the substrate interconnection 130. The bottom filler 170 may include or be referred to as a dielectric layer or a non-conductive paste. The bottom filler 170 may not contain an inorganic filler. In some examples, the bottom filler 170 may include or be referred to as CUF, NCP, NCF, ACF, or ACP. In some examples, after being inserted between the substrate 120 and the base substrate 150, the bottom filler 170 may be hardened. In some examples, after the bottom filler 170 is set to cover the inside of the base substrate 150, the substrate interconnection 130 coupled to the substrate outward terminal 122b of the substrate 120 may penetrate the bottom filler 170 and be connected to the base substrate inward terminal 152a of the base substrate 150. The underfill 170 may prevent the substrate interconnection 130 between the substrate 120 and the base substrate 150 from being separated due to physical and chemical impacts.

[0071] Figure 4B A cross-sectional view of the electronic device 101 is shown in a later stage of manufacturing. Figure 4BIn the example shown in , the cover 190 may be disposed above the base substrate 150. The cover 190 may be coupled to the inner side of the base substrate 150 to surround the electronic device 100 (for example, surround the electronic component 110 and the substrate 120). The cover 190 may include a substantially square top plate and side walls extending downward from the edge of the top plate. The lower surface of the side wall of the cover 190 may be attached and fixed to the inside of the base substrate 150 via an adhesive layer 180. The lower side of the cover 190 and the upper side of the electronic component 110 may be attached and fixed via the adhesive layer 180. For example, the adhesive layer 180 may include or be referred to as an adhesive, a thermal interface material (TIM), or a solder. In some examples, the adhesive layer 180 between the upper side of the cover 190 and the upper side of the electronic component 110 may include or be referred to as a thermal interface material (TIM). Adhesive layer 180 may include a thermally conductive material and may contact the top side of electronic component 110 and the bottom side of the upper plate of cover 190. In some examples, adhesive layer 180 may include a polymer-type thermal interface material such as polysilicone, epoxy, or urethane with a high thermal conductivity filler such as graphite, boron nitride, silver, aluminum, or aluminum oxide. Since the thermal interface material includes a thermally conductive material, heat generated by electronic component 110 can be easily transferred to cover 190.

[0072] The cover 190 may be made of a metal with high thermal conductivity and radiation. In some examples, the cover 190 may include aluminum or copper. In some examples, the cover 190 may be referred to as or include a heat sink, a heat plate, a cap, a cover, a shield, or a body. In some examples, trenches, protrusions, or fins may be provided on the upper side of the cover 190 to improve heat dissipation efficiency. The thickness of the cover 190 may be in the range of about 300 μm to about 2000 μm.

[0073] Figure 4C A cross-sectional view of the electronic device 101 is shown in a later stage of manufacturing. Figure 4C In the example shown in FIG. 1 , the external interconnect 160 may be disposed on the base substrate-outward terminal 152 b of the base substrate 150 . The external interconnect 160 may include elements, features, materials, or formation processes similar to or the same as those of the base interconnect 130 .

[0074] The external interconnect 160 may be electrically connected to the electronic component 110 via the base substrate conductive structure 152 of the base substrate 150, the substrate interconnect 130, the conductive structure 122 of the substrate 120, and the component interconnect 111. In some examples, the size of the external interconnect 160 may be in the range of about 1 μm to about 1000 μm. In some examples, the external interconnect 160 may be referred to as an external input / output terminal of the electronic device 100.

[0075] Figure 5A cross-sectional view of an exemplary electronic device 200 is shown. Figure 5A for Figure 5 A detailed view of the electronic device 200 in area A. Figure 5 and Figure 5A In the example shown in , the electronic device 200 may include an electronic component 110, a substrate 220, a substrate interconnect 130, an encapsulation body 140, a base substrate 150, an external interconnect 160, an adhesive layer 180, and a cover 190. In some examples, the electronic device 200 may include an underfill 170.

[0076] The electronic device 200 may be similar to Figure 3 For example, the electronic device 200 may be similar to the electronic device 101 in terms of the electronic component 110, the substrate interconnect 130, the encapsulation body 140, the base substrate 150, the external interconnect 160, the bottom fill 170, the adhesive layer 180, and the cover 190.

[0077] According to various examples, substrate 220 may include dielectric structure 121, conductive structure 122, and substrate passivation layer 123. Conductive structure 122 may include substrate inward terminal 122a, seed 122s, inner conductive structure 122i, interface layer 222i, barrier layer 222x, and substrate outward terminal 122b.

[0078] Figures 6A to 6H A cross-sectional view of an exemplary method for manufacturing an exemplary electronic device 200 is shown. Figure 2A and Figure 2B The method of the electronic device 100 shown in FIG. Fig. 6A The electronic device 200 shown in FIG.

[0079] Fig. 6A A cross-sectional view of an electronic device 200 is shown at a late manufacturing stage. Figure 6AA for Fig. 6A Detailed view of Zone A in the Fig. 6A and Figure 6AA In the example shown in FIG. 2 , the interface layer 222i, the barrier layer 222x, and the inner conductive structure 122i may be disposed above the seed crystal 122s.

[0080] According to various specific examples, the interface layer 222i may be disposed above the seed crystal 122s on the upper side of the seed crystal 122s. The interface layer 222i may be disposed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. In various examples, the interface layer 222i may include Au or Ag. In some examples, the interface layer 222i may be at least initially a multi-layer metal layer in which Cu and Au or Cu and Ag are stacked in sequence. For example, the interface layer 222i may include: a first interface portion 222i-1, which includes a first metal (e.g., Cu) and is located on the seed crystal 122s; and a second interface portion 222i-2, which includes a second metal (e.g., Au or Ag) and is located on the first interface portion 222i-1. In some examples, the thickness of the interface layer 222i may be in the range of about 0.05 μm to about 10 μm.

[0081] According to various examples, barrier layer 222x may be disposed on the upper side of interface layer 222i above interface layer 222i. Barrier layer 222x may be disposed by electroless plating, electrolytic plating, sputtering, PVD, CVD, MOCVD, ALD, LPCVD, or PECVD. Barrier layer 222x may include or be referred to as an isolation layer. In some examples, barrier layer 222x may include Ni, Co, Fe, Ti, TiW, W, Cr, or Al. In some examples, the thickness of barrier layer 222x may be in the range of about 0.05 μm to about 10 μm.

[0082] The interface layer 222i and the barrier layer 222x may be configured to have a plurality of patterns, and each pattern may be coupled to the seed crystal 122s. In some examples, the first interface portion 222i-1 may be formed using, for example, PVD, and may completely cover the seed crystal 122s and the substrate passivation layer 123 (similar to Figure 2B1. The seed 122s in the first interface portion 222i-1 may be formed by placing a seed 122s and a first interface portion 222i-1. After the seed 122s and the first interface portion 222i-1 are disposed, a patterned mask (e.g., a photoresist) may be disposed over the first interface portion 222i-1 and the seed 122s. The patterned mask may include an opening that exposes an area of ​​the first interface portion 222i-1. The second interface portion 222i-2, the barrier layer 222x, and the inner conductive structure 122i may be formed (e.g., electroplated) in the patterned mask opening over the first interface portion 222i-1. After the second interface portion 222i-2, the barrier layer 222x, and the inner conductive structure 122i are formed, the patterned mask may be removed. Removing the patterned mask exposes a section of the first interface portion 222i-1 that is not located below (e.g., not vertically aligned with) the second interface portion 222i-2, the barrier layer 222x, and the inner conductive structure 122i. These exposed sections of the first interface portion 222i-1 and the seed crystal 122s located thereunder may then be removed using, for example, etching, thereby exposing portions of the substrate passivation layer 123. After removing the first interface portion 222i-1 and the sections of the seed crystal 122s that are not covered by the second interface portion 222i-2, the barrier layer 222x, and the inner conductive structure 122i, the seed crystal 122s, the interface layer 222i, the barrier layer 222x, and the inner conductive structure 122i, may have the same pattern.

[0083] The inner conductive structure 122i may include elements, features, materials, or formation processes similar to those of the inner conductive structure 122i of the electronic device 100. The substrate-inward terminal 122a may include a portion of the inner conductive structure 122i positioned in the aperture 123a ( Figure 2A ).

[0084] Figure 6B A cross-sectional view of an electronic device 200 is shown at a late manufacturing stage. Figure 6BA for Figure 6B Detailed view of Zone A in the Figure 6B and Figure 6BA In the example shown in FIG. 1 , the substrate 220 may be configured by sequentially alternating or interleaving dielectric structures 121 and conductive structures 122 to cover inner conductive structures 122i. The substrate 220 may include elements, features, materials, or formation processes similar to or the same as those of the substrate 120 of the electronic device 100.

[0085] After the dielectric structure 121 is provided and in response to the application of the alloying temperature, the interface layer 222i can be converted from a stacked (or dissimilar) metal layer structure to an alloy. For example, before the application of the alloying temperature, the interface layer 222i can include dissimilar regions of different metals (e.g., the first interface portion 222i-1 ( Figure 6AA) and a second interface portion 222i-2) comprising Au, which in response to applying an alloying temperature can form an alloy (e.g., an AuCu alloy) when heated due to the diffusion characteristics of Au. The AuCu alloy can be formed by applying an alloying temperature in the range of about 200°C to about 400°C, which is below the melting point of the individual metals (about 1,064°C for Au and about 1,085°C for Cu). The barrier layer 222x can prevent the gold (Au) in the interface layer 222i from diffusing toward the inner conductive structure 122i. The interface layer 222i can be interposed between the seed crystal 122s and the barrier layer 222x. The barrier layer 222x can be interposed between the interface layer 222i and the inner conductive structure 122i. According to various examples, the substrate-inward terminals 122a may include the interface layer 222i, the barrier layer 222x, the seed 122s, and the portion of the inner conductive structure 122i bounded by the lateral sidewalls of the substrate passivation layer 123 (i.e., the interface layer 222i, the barrier layer 222x, the seed 122s, and the inner conductive structure 122i located at Figure 2A In some examples, the alloying temperature may be applied during the curing of one or more of the dielectric layers of the dielectric structure 121. For example, the curing temperature of the dielectric structure 121 may be equal to or greater than the alloying temperature, so that the interface layer 222i changes from the stacked metal layers to an alloy during the curing process.

[0086] Figure 6C A cross-sectional view of an electronic device 200 is shown at a late manufacturing stage. Figure 6CA for Figure 6C Detailed view of Zone A in the Figure 6C and Figure 6CA In the example shown in , the seed crystal 122s covering the interface layer 222i can be removed to expose the interface layer 222i. In some examples, the seed crystal 122s covering the interface layer 222i can be removed by etching to expose the top side of the interface layer 222i. The top side of the substrate passivation layer 123 can protrude above the top side of the interface layer 222i. The top side of the interface layer 222i can be recessed or depressed relative to the top side of the substrate passivation layer 123. The distance that the top side of the interface layer 222i is recessed relative to the top side of the substrate passivation layer 123 can be referred to as a recess height or recess depth, and can be, for example, about 0.01 μm to 0.1 μm, 0.01 μm to 0.05 μm, or 0.01 μm to 0.03 μm. The technique for removing the seed crystal 122 s from the substrate 220 may be similar to or the same as the technique for removing the seed crystal 122 s from the substrate 120 of the electronic device 100 .

[0087] Fig.6D A cross-sectional view of an electronic device 200 is shown at a late manufacturing stage. Figure 6DA During mixed bonding Fig.6D A detailed view of area A. And Figure 6DB Shown after hybrid joining Figure 6DA Zone A. Fig.6D , Figure 6DA and Figure 6DB In the example shown in , the electronic component 110 can be disposed at the top side of the substrate 220. The electronic component 110 of the electronic device 200 can include elements, features, materials, or formation techniques similar to those of the electronic component 110 of the electronic device 100. For example, similar to the reference Figure 2F , Figure 2FA and Figure 2FB The depicted and described techniques can be used to Fig.6D , Figure 6DA and Figure 6DB on the electronic device 200.

[0088] In some examples, a pick-and-place device may pick up an electronic component 110 and place the electronic component, wherein a component interconnect 111 of the electronic component 110 is positioned above a top side of an interface layer 222i of a substrate-inward terminal 122a. The passivation layer 113 of the electronic component 110 may be in contact with a substrate passivation layer 123 of the substrate 220. The component interconnect 111 may be spaced apart from the interface layer 222i of the substrate-inward terminal 122a by a gap 124. The passivation layer 113 and the substrate passivation layer 123 may be bonded to each other by heat treatment. After the passivation layer 113 of the electronic component 110 and the substrate passivation layer 123 of the substrate 220 are bonded to each other, the component interconnect 111 of the electronic component 110 and the interface layer 222i of the substrate 220 may be spaced apart from each other by a gap 124, as shown in FIG. Figure 6DA As shown in .

[0089] Figure 6DB Depicts the component interconnect 111 of the electronic component 110 and the interface layer 222i of the substrate 120 bonded to each other. A thermal compression process may be applied so that the interface layer 222i extends across the gap 124 and contacts the component interconnect 111. The component interconnect 111 and the interface layer 222i may be bonded together by the thermal compression process because the metals diffuse into each other across the bonding boundary 125. Due to the diffusion properties of the alloy of the interface layer 222i, the interface layer 222i may bond to the component interconnect 111 of the electronic component 110 more easily or quickly. For example, the diffusion properties Au may allow the interface layer 222i comprising an AuCu alloy to bond more easily and / or quickly than Cu alone.

[0090] Fig. 6E A cross-sectional view of an electronic device 200 is shown at a later stage of manufacturing. Fig. 6EIn the example shown in FIG. , the encapsulation body 140 may be disposed over the substrate 220 and the top side of the electronic component 110 . The encapsulation body 140 may include elements, features, materials, or formation processes similar to those of the encapsulation body 140 of the electronic device 100 .

[0091] Fig. 6F A cross-sectional view of an electronic device 200 is shown at a later stage of manufacturing. Fig. 6F In the example shown in , the substrate interconnect 130 may be provided to the substrate-outward terminal 122b of the substrate 220. The substrate interconnect 130 may include elements, features, materials, or formation processes similar to those of the substrate interconnect 130 of the electronic device 100. In some examples, a plurality of electronic devices 200 (e.g., a plurality of substrates 220 to which the electronic components 110 are coupled and on which the encapsulation body 140 is deposited) may be manufactured simultaneously, for example, on a panel or a carrier. The electronic devices may be separated into individual electronic devices 200 (e.g., individual substrates 220 to which one or more electronic components 110 are coupled and on which the encapsulation body 140 is deposited) by a singulation process. For example, individual electronic devices may be provided by singulation (e.g., cutting, sawing, dicing, etc.) through the encapsulation body 140 and the substrate 220. In some examples, the lateral sides of the encapsulation body 140 and the substrate 220 may be coplanar in response to the singulation.

[0092] Figure 6G A cross-sectional view of an electronic device 200 is shown at a later stage of manufacturing. Figure 6G , the substrate interconnect 130 may be disposed on the base substrate 150. In some examples, the underfill 170 may be positioned between the substrate 220 and the base substrate 150. The base substrate 150 and the underfill 170 may include elements, features, materials, or formation processes similar to those of the base substrate 150 and the underfill 170 of the electronic device 101.

[0093] Figure 6H A cross-sectional view of an electronic device 200 is shown at a later stage of manufacturing. Figure 6H , the cover 190 may be disposed on the inside of the base substrate 150, and the external interconnect 160 may be disposed on the base substrate-outward terminal 152 b of the base substrate 150. The cover 190 may be attached and fixed to the base substrate 150 and the electronic component 110 via the adhesive layer 180. The cover 190, the external interconnect 160, and the adhesive layer 180 may include elements, features, materials, or formation processes similar to those of the cover 190, the external interconnect 160, and the adhesive layer 180 of the electronic device 101.

[0094] The devices and methods described herein tend to improve pitch and bonding performance in electronic devices. The recess depth can be tightly controlled by removing the seed layer above the conductive structure to leave a void. The recess depth is typically equal to the height of the removed seed layer, and the recess depth can be selected to compensate for the thermal expansion coefficients of the recessed conductive structure and the adjacent passivation layer. Some examples may include alloying the conductive structure to further increase the bonding speed due to the diffusion properties of the alloying metal.

[0095] This disclosure includes reference to certain examples; however, it will be understood by those of ordinary skill in the art that various changes may be made and equivalents may be substituted without departing from the scope of this disclosure. In addition, modifications may be made to the disclosed examples without departing from the scope of this disclosure. Therefore, it is intended that this disclosure is not limited to the disclosed examples, but will include all examples that fall within the scope of the appended claims.

Claims

1. An electronic device, characterized in that: Include: Electronic components; a component passivation layer coupled to the electronic component; a component interconnect extending from the electronic component through the component passivation layer; a substrate coupled to the device passivation layer and the device interconnect, the substrate comprising: a substrate passivation layer coupled to the device passivation layer along a bonding boundary, wherein the substrate passivation layer comprises an inorganic material; a substrate inboard terminal extending through the substrate passivation layer and coupled to the component interconnect along the bonding boundary; a seed crystal located between the substrate passivation layer and the substrate inward terminal; a dielectric structure coupled to the substrate passivation layer; and A conductive structure extends through the dielectric structure and is coupled to the substrate inward terminal.

2. The electronic device according to claim 1, wherein: The substrate inward termination comprises a gold-copper alloy.

3. The electronic device according to claim 1, wherein: The substrate passivation layer is bonded to the device passivation layer along the bonding boundary by covalent bonding.

4. The electronic device as claimed in claim 3, characterized in that: The component interconnect is bonded to the substrate inward terminal in response to metal migration from the substrate inward terminal across the bonding boundary.

5. The electronic device as claimed in claim 4, characterized in that: The metal from the substrate inward terminals comprises gold.

6. The electronic device as claimed in claim 1, wherein: An end of the seed is spaced apart from the bonding boundary by a thickness of the seed.

7. The electronic device according to claim 1, wherein: The dielectric structure includes an organic material.

8. The electronic device of claim 1, further comprising a base substrate coupled to the substrate, the base substrate comprising: a base substrate dielectric structure coupled to the dielectric structure of the substrate; and A base substrate conductive structure is interleaved with the base substrate dielectric structure and coupled to the conductive structure of the substrate.

9. A method for manufacturing an electronic device, characterized in that: Include: providing a substrate passivation layer defining pores and comprising an inorganic material; Disposing a seed crystal above the substrate passivation layer and in the pores; disposing a conductive structure above the seed and in the aperture, the conductive structure comprising a substrate-inward terminal; Disposing a dielectric structure above the seed crystal and the substrate passivation layer; removing a portion of the seed crystal to expose a side of the substrate inward terminal, wherein the side of the substrate inward terminal is recessed from a side of the substrate passivation layer by a recessed height; disposing an electronic component including a component passivation layer over the substrate passivation layer, wherein the electronic component defines a gap between an exposed side of the substrate inward terminal and a component interconnect of the electronic component; coupling the substrate passivation layer to the device passivation layer along a bonding boundary; and The substrate inward terminals are bonded to the component interconnect along the bonding boundary by applying a bonding temperature.

10. The method according to claim 9, characterized in that Metal of the component interconnect diffuses across the bonding boundary in response to application of the bonding temperature.

11. The method according to claim 9, characterized in that The joining temperature is between 250°C and 400°C.

12. The method according to claim 9, characterized in that The recess height is equal to the thickness of the removed portion of the seed crystal.

13. The method according to claim 9, characterized in that The dielectric structure includes an organic material.

14. The method according to claim 9, characterized in that The substrate inward terminal further comprises: a barrier layer coupled to the conductive structure; and An interface layer is coupled to the barrier layer, wherein the interface layer includes a gold portion and a copper portion.

15. The method according to claim 14, characterized in that It further includes forming a gold-copper alloy from the gold portion and the copper portion by applying an alloying temperature.

16. An electronic device, characterized in that: It contains: An electronic assembly comprising: a component passivation layer coupled to the electronic component; and a component interconnect extending from the electronic component through the component passivation layer, wherein a side of the component passivation layer and a side of the component interconnect are positioned along a bonding boundary; and A substrate coupled to the electronic component, the substrate comprising: a substrate passivation layer coupled to the device passivation layer along the bonding boundary, wherein the substrate passivation layer includes inner walls defining an aperture; a seed crystal coupled to the inner wall of the substrate passivation layer; an interface layer coupled to the component interconnect along the bonding boundary and to the seed; a barrier layer coupled to the interface layer, wherein the interface layer is located between the seed crystal and the barrier layer; a dielectric structure coupled to the substrate passivation layer; and A conductive structure extends through the dielectric structure and into the aperture, wherein the conductive structure is coupled to the barrier layer.

17. The electronic device according to claim 16, wherein: The interface layer includes a gold-copper alloy.

18. The electronic device as claimed in claim 17, wherein: Gold from the gold-copper alloy diffuses across the bond boundary.

19. The electronic device according to claim 16, wherein: An end of the seed is spaced apart from the bonding boundary.

20. The electronic device as claimed in claim 16, wherein: The substrate passivation layer and the device passivation layer include inorganic materials, and wherein the dielectric structure of the substrate includes organic materials.

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