Low-frequency double-frequency control light-load high-ITHD digital control method, device and system and readable storage medium

Abstract

The invention relates to a low-frequency double-frequency control light-load high-ITHD digital control method. The method comprises the following steps: S100, acquiring an FPC switching frequency after frequency reduction; s200, setting the sampling frequency and the loop operation frequency of the inductive current IL of the ADC to be twice of the switching frequency of the FPC, and setting the sampling point and the loop operation point of the inductive current IL of the ADC at the positive integer multiple of 1 / 2 of the switching period T; s300, according to the collected sampling current Itrg and a loop operation formula, the driving duty ratio D2 of the next switching period T is obtained through calculation; s400, setting the midpoint of the obtained driving duty ratio D2 of the next period at the midpoint of the next switching period T; s500, the step S300 and the step S400 are executed in a circulating mode; the problem of poor ITHD caused by serious distortion of inductive current IL in a DCM working mode can be greatly improved, so that the ITHD and PF are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of AC / DC power conversion, and particularly to a low-frequency double-frequency control light-load high-ITHD digital control method, device, system, and readable storage medium. Background Art

[0002] With the continuous development of the power electronics industry, the requirements for the power supply industry are getting higher and higher. In order to better meet the OCPv3 specification of 97.5% efficiency required by customers and balance the requirements of PF value and ITHD value. Therefore, it is particularly important to provide an efficient, simple, and low-cost PFC control scheme. At present, the PFC level of switching power supplies generally operates at a frequency of 60Khz to 70Khz. A higher switching frequency will cause greater losses in the inductor, making it difficult to improve the efficiency. Reducing the switching frequency is an effective way to improve the efficiency.

[0003] Currently, most PFCs use the average current control method (such as Figure 3 , Figure 4 ), and its control flowchart (such as Figure 9 ) requires collecting the average value of the input current. A common method is to use 1 / 2 of the drive required by the switching transistor to trigger the ADC to sample the inductor current I L and perform loop operations at this frequency. If the switching frequency is reduced, the sampling frequency of the inductor current I L of the ADC and the loop operation frequency will also decrease, which will result in a reduction in the number of samples within a power frequency cycle, a deterioration in the sampling accuracy of the inductor current I L , and a slowdown in the response speed of the loop. Moreover, the current PFC drive control method will cause the sampling point of the inductor current I L of the ADC to always follow the drive change (such as Figure 3 , Figure 4 ). When the load is light and the drive is small, the midpoint position of the inductor current I L cannot be accurately collected, which will further affect the sampling accuracy, resulting in a worse waveform of the controlled input current IAC and the ITHD and PF values not meeting the specification requirements. Summary of the Invention

[0004] In view of this, in view of the deficiencies of the existing technology, the main purpose of the present invention is to provide a low-frequency double-frequency control light-load high-ITHD digital control method, which can significantly improve the problem of serious distortion of the inductor current in the DCM working mode, resulting in poor ITHD and PF values, and meet the ITHD and PF value specification requirements.

[0005] To achieve the above object, the present invention adopts the following technical solutions: A low-frequency double-frequency control light-load high-ITHD digital control method, including the following steps: S100. Obtain the FPC switching frequency after frequency reduction; S200. Set the sampling frequency of the inductor current I of the ADC and the loop operation frequency to twice the FPC switching frequency, and set both the sampling point and the loop operation point of the inductor current I of the ADC at positive integer multiples of 1 / 2 of the switching period T; L L S300. Calculate the drive duty cycle D2 of the next switching period T according to the sampled current I collected and the loop operation formula; trg S400. Set the midpoint of the obtained drive duty cycle D2 of the next period at the midpoint of the next switching period T; S500. Loop and execute steps S300 and S400.

[0006] As a preferred solution, in step S300, the following steps are further included: S310. Trigger current sampling at the sampling point of the inductor current I of the ADC; L S320. Input the sampled current I collected by the current sampling into the loop operation formula for loop operation; trg S330. Obtain the drive duty cycle D1 and the completion time t according to the loop operation, and save them; S340. Perform loop integration operation on the obtained drive duty cycle D1, input the obtained result into the loop operation of the next switching period T, and then obtain the drive duty cycle D2 of the next switching period T according to the loop operation; S350. Judge the size relationship between the completion time t and the switching period T: If the completion time t is greater than or equal to the switching period T, return to continue to judge the current sampling trigger point in the next round; If the completion time t is less than or equal to the period T, update the PWM register at the switching period T.

[0007] As a preferred solution, in the DCM mode, loop integration processing is performed on the drive duty cycle D1 obtained through loop operation to improve the versatility of this digital control method in both the CCM mode and the DCM mode. According to the anti-saturation formula of PI control: Where: is the proportionality factor; is the integral factor; is the anti-saturation factor, and ; ​​​​​The calculated result is the drive duty ratio D2 for the next cycle.

[0008] The present application also provides a low-frequency double-frequency control light-load high-ITHD digital control device, including: a processor, and a memory connected to the processor, the memory having instructions stored therein, the instructions causing the control device to execute the above method when executed by the processor.

[0009] The present application also provides a low-frequency double-frequency control light-load high-ITHD digital control system, including: a PFC control circuit, and the above control device.

[0010] The present application also provides a readable storage medium, having computer program code stored thereon, the computer program code executing the above method when run.

[0011] The above-mentioned low-frequency double-frequency control light-load high-ITHD digital control method has obvious advantages and beneficial effects compared with the prior art. Specifically, as can be seen from the above technical solution, it mainly doubles the sampling frequency, loop operation frequency, and loop control frequency of the inductor current I L . Within the sampling frequency supported by the DSP, doubling the frequency control can effectively improve the current control accuracy of the PFC operating in the DCM mode, and it can greatly improve the problem of serious distortion of the inductor current in the DCM operating mode, resulting in a large difference in ITHD and PF values; this low-frequency double-frequency control light-load high-ITHD digital control method is not limited to PFC with a rectifier bridge, half-bridge PFC, totem-pole PFC, single-channel PFC, two-channel interleaved PFC, three-phase interleaved PFC, etc., and can all be used. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a schematic diagram of the circuit structure of an embodiment of the present invention; Figure 2 is a PFC digital control logic diagram of an embodiment of the present invention; Figure 3 is a schematic diagram of the non-double-frequency control method in the CCM mode; Figure 4 is a schematic diagram of the non-double-frequency control method in the DCM mode; Figure 5 is a schematic diagram of the double-frequency control method in the CCM mode of an embodiment of the present invention; Figure 6 is a schematic diagram of the double-frequency control method in the DCM mode of an embodiment of the present invention; Figure 7 is an input current waveform diagram of the non-double-frequency control method; Figure 8 is an input current waveform diagram of the double-frequency control method of an embodiment of the present invention; Figure 9 is the duty cycle update logic of the general method; Figure 10 is the double-frequency duty cycle update logic of the embodiment of the present invention; Figure 11 is the PF value specification of the embodiment of the present invention; Figure 12 is the ITHD value specification of the embodiment of the present invention; Figure 13 is the PF value and ITHD test data before and after using double frequency in the embodiment of the present invention.

[0013] Abbreviation and Terminology Definition PFC: Power Factor Correction, power factor correction OCPv3: Open Compute Project 3.0, open computing project 3.0 CCM: Continuous Conduction Mode, continuous conduction mode DCM: Discontinuous Conduction Mode, discontinuous conduction mode PF: Power Factor, power factor ITHD: I Total Harmonic Distortion, total harmonic distortion Detailed Implementation Manner

[0014] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments; based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0015] It should be noted that when an element is referred to as being "fixed to" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0016] Please refer to Figures 1 to 13 , which shows a low-frequency double-frequency control light-load high-ITHD digital control method provided by the embodiment of the present invention, including the following steps: S100. Obtain the FPC switching frequency after frequency reduction; S200. Set the sampling frequency of the inductor current I of the ADC and the loop operation frequency to twice the FPC switching frequency, and set the sampling point of the inductor current I of the ADC and the loop operation points (at Trg1, Trg2, Trg3....) to positive integer multiples of 1 / 2 of the switching period T (i.e., at T / 2, T, 3T / 2, 2T, 5T / 2...); L S200. Set the sampling frequency of the inductor current I of the ADC and the loop operation frequency to twice the FPC switching frequency, and set the sampling point of the inductor current I of the ADC and the loop operation points (at Trg1, Trg2, Trg3....) to positive integer multiples of 1 / 2 of the switching period T (i.e., at T / 2, T, 3T / 2, 2T, 5T / 2...); L S200. Set the sampling frequency of the inductor current I of the ADC and the loop operation frequency to twice the FPC switching frequency, and set the sampling point of the inductor current I of the ADC and the loop operation points (at Trg1, Trg2, Trg3....) to positive integer multiples of 1 / 2 of the switching period T (i.e., at T / 2, T, 3T / 2, 2T, 5T / 2...); S300. Calculate the driving duty cycle D of the next switching period T according to the sampled current I collected and the loop operation formula; trg S300. Calculate the driving duty cycle D of the next switching period T according to the sampled current I collected and the loop operation formula; S400. Set the midpoint of the obtained driving duty cycle D2 of the next period to the midpoint of the next switching period T (i.e., at T / 2, 3T / 2, 5T / 2...); S500. Loop through steps S300 and S400, thereby significantly improving the sampling accuracy of the inductor current IL of the ADC and the loop response speed.

[0017] Furthermore, in step S300, the following steps are also included: S310. Trigger current sampling at the sampling point of the inductor current I of the ADC, that is, perform current sampling at positive integer multiples of 1 / 2 of the switching period T (i.e., at T / 2, T, 3T / 2, 2T, 5T / 2...); L S310. Trigger current sampling at the sampling point of the inductor current I of the ADC, that is, perform current sampling at positive integer multiples of 1 / 2 of the switching period T (i.e., at T / 2, T, 3T / 2, 2T, 5T / 2...); S320. Input the sampled current I collected by the current sampling into the loop operation formula for loop operation; trg S320. Input the sampled current I collected by the current sampling into the loop operation formula for loop operation; S330. Obtain the driving duty cycle D1 and the completion time t according to the loop operation, and save them; S340. Perform loop integral operation on the obtained driving duty cycle D1, input the obtained result into the loop operation of the next switching period T, and then obtain the driving duty cycle D2 of the next switching period T according to the loop operation; S350. Judge the magnitude relationship between the completion time t and the switching period T: If the completion time t is greater than or equal to the switching period T (t≥T), then return to continue the judgment of the current sampling trigger point for the next round; If the completion time t is less than or equal to the period T (t<T), then update the PWM register at the switching period T.

[0018] Furthermore, in the DCM mode, by performing loop integral processing on the driving duty cycle D1 obtained through the loop operation to improve the generality of this digital control method in both the CCM mode and the DCM mode, according to the anti-saturation formula of PI control:

[0019] Where: is the scale factor; is the integrating factor; is the anti-saturation factor, and ; The calculated result is the driving duty cycle D2 of the next cycle.

[0020] In DCM mode, the reference current I REF and sampling current I AC_sample The error is large (such as Figure 6 ), if the loop parameters here are used, the loop control will overshoot significantly; while in CCM mode (such as Figure 5 ), when the switching cycle T is at (Trg2 / Trg4…), the reference current I REF and sampling current I AC_sample The error is very small, which is different from the DCM mode. Therefore, the driving duty ratio D2 obtained at the switching cycle T needs to be further processed to improve the versatility of this digital control method in the two working modes. According to the anti-saturation formula of PI control, each operation will use the previous result for integration. After using the low-frequency double power control method, the driving duty ratio D1 will be updated at 1 / 2 switching cycle T (Trg1 / Trg3...) and switching cycle T (Trg2 / Trg4...). However, due to the operation delay, the driving duty ratio D1 calculated at the switching cycle T (Trg2 / Trg4...) cannot be loaded when the PWM register is updated. Therefore, the driving duty ratio D1 at the switching cycle T will not be directly used for the output of the switch tube drive, but will be accumulated as an integral term in the PI operation at the next 1 / 2 switching cycle T (Trg1 / Trg3...). At this time, the calculated driving duty ratio D2 will not have a large overshoot due to excessive error, nor will it cause control hysteresis current distortion due to too low error change rate. Therefore, the update logic of the driving duty cycle is the same in DCM mode and CCM mode, so the low-frequency double-frequency control light-load high ITHD digital control method can be perfectly suitable for current control in DCM mode and CCM mode. The optimized input current I AC Effects such as Figure 8 As shown in the figure, in the DC-DC converter, according to the error between the reference value of the output voltage or the inductor current and the actual sampling value, the PI control anti-saturation formula is used to adjust the driving duty cycle of the power switch tube to ensure that the converter can stably output the required voltage and current, while avoiding integral saturation caused by load mutations, resulting in excessive output voltage ripple, slow response speed and other undesirable phenomena, thereby improving the power conversion efficiency and power supply quality of the power supply.

[0021] Specifically, error(t) is usually the reference current I REF With the sampling current I AC_sampleThe error value between etc., with Kp as the proportionality factor, and the proportional link outputs the corresponding control action in real time according to the magnitude of this error; for example, in the DCM mode, when the reference current I REF and the sampled current I AC_sample have a large error (such as a large error at the periods Trg2 / Trg4...), when the value of Kp is appropriate, the proportional link will quickly output a relatively large control adjustment amount according to this large error, so that the error can be reduced as soon as possible, prompting the inductor current of the power supply, etc. to change towards the desired state, which plays a key role in the rapid response of the system. Similarly, in the CCM mode, although the error is relatively small, the proportional link will also output a corresponding and smaller control amount based on this small error for fine-tuning; the integral link under the action of the integral factor Ki is the accumulation of the error error(t) over time. For the control of the power switch tube, it is mainly used to eliminate the steady-state error. During the continuous operation of the power switch tube, even if the proportional link has reduced the error to a certain extent, there may still be subtle and continuous errors. The integral link will continuously accumulate these errors and continuously change the control amount u(t), so that the power switch tube can finally reach a more accurate control state, such as making the inductor current more stably track the reference current, realizing the high-precision stability of output voltage and other indicators. Especially when dealing with some small disturbances and small deviations during the long-term operation of the power supply, this cumulative adjustment effect of the integral link can ensure the steady-state performance of the system; the anti-saturation factor Kcr, and the anti-saturation part is mainly designed for the problem of integral saturation. In the control of the power switch tube, especially in some complex working conditions, such as when the power supply load suddenly changes, etc., it may occur that the control amount u(t) output by the controller is at a large value for a long time (for example, the power switch tube is continuously in the limit conduction or cut-off state), which will cause the integral term to continuously accumulate and the integral saturation phenomenon to occur, and then cause adverse effects such as excessive overshoot and longer adjustment time in the loop control, damaging the control performance of the power switch tube. The anti-saturation part adjusts the integral of the control amount u(t) by feedback, and dynamically adjusts the control amount according to the accumulation of u(t), avoiding the occurrence of integral saturation, ensuring that the output of the control amount is always reasonable in different working modes (such as the DCM mode where overshoot is likely to occur, and the CCM mode where it is relatively stable but may also face special working conditions), so as to maintain the stability and reliability of the control loop of the power switch tube. The u(t) calculated by this PI control anti-saturation formula comprehensively considers various factors such as the real-time proportional adjustment of the error, the integral elimination of the steady-state error, and the prevention of integral saturation. The output control amount aims to optimize the control effect of the power supply in different working modes such as DCM and CCM, and improve the control accuracy and working stability of the power switch tube.

[0022] An embodiment of the present application further provides a low-frequency double-frequency control light-load high-ITHD digital control device, including: a processor, and a memory connected to the processor, the memory having instructions stored therein, and the instructions, when executed by the processor, cause the control device to execute the above method.

[0023] An embodiment of the present application further provides a low-frequency double-frequency control light-load high-ITHD digital control system, including: a PFC control circuit, and the above control device.

[0024] An embodiment of the present application further provides a readable storage medium, on which computer program code is stored, and the computer program code, when run, executes the above method.

[0025] As Figures 11 - 13 shown, a 800W switching power supply (output full load 65A) is used to conduct a comparative test according to the PF value specification ( Figure 11 ), and the ITHD specification ( Figure 12 ), and the comparison data before and after using the double-frequency control method (as Figure 13 shown) can clearly show that the PF value and ITHD using the double-frequency control method are greatly optimized.

[0026] The above-mentioned low-frequency double-frequency control light-load high-ITHD digital control method mainly performs frequency doubling processing on the sampling frequency, loop operation frequency, and loop control frequency of the inductor current I L . Within the sampling frequency supported by the DSP, performing frequency doubling control can effectively improve the current control accuracy of the PFC operating in the DCM mode, and it can greatly improve the problem of serious distortion of the inductor current in the DCM operating mode, resulting in poor ITHD and PF values; this low-frequency double-frequency control light-load high-ITHD digital control method is not limited to rectifier bridge PFC, half-bridge-less PFC, totem pole PFC, single-channel PFC, two-channel interleaved PFC, three-phase interleaved PFC, etc., and can all be used.

[0027] It should be noted that the present invention is not limited to the above embodiments. According to the creative spirit of the present invention, those skilled in the art can also make other changes, and these changes made according to the creative spirit of the present invention should all be included within the scope of protection required by the present invention.

Claims

1. A low-frequency double-frequency control light-load high ITHD digital control method, characterized in that: The steps include: S100, obtaining the FPC switching frequency after frequency reduction; S200, the inductor current I L The sampling frequency and loop operation frequency are set to twice the FPC switching frequency, and the ADC inductor current I L The sampling points and loop operation points are both set at positive integer multiples of 1 / 2 of the switching period T; S300, based on the collected sampling current I trg The driving duty cycle D2 of the next switching cycle T is calculated by the loop operation formula; S400, setting the midpoint of the obtained driving duty cycle D2 of the next cycle at the midpoint of the next switching cycle T; S500: Execute steps S300 and S400 in a loop.

2. The low frequency double frequency control light load high ITHD digital control method as claimed in claim 1, characterized in that: In step S300, the following steps are also included: S310, inductor current I at ADC L The sampling point triggers current sampling; S320, sampling the current I trg Input loop operation formula to perform loop operation; S330, obtaining the driving duty cycle D1 and the completion time t according to the loop operation, and saving them; S340, performing loop integration operation on the obtained driving duty cycle D1, and inputting the obtained result into the loop operation of the next switching cycle T, and then obtaining the driving duty cycle D2 of the next switching cycle T according to the loop operation; S350, determine the relationship between the completion time t and the switching period T: if the completion time t is greater than or equal to the switching period T, return to continue the next round of current sampling trigger point determination; if the completion time t is less than the period T, update the PWM register at the switching period T.

3. The low frequency double frequency control light load high ITHD digital control method as claimed in claim 2, characterized in that: In DCM mode, the driving duty cycle D1 obtained by loop operation is processed by loop integration to improve the versatility of this digital control method in both CCM mode and DCM mode. According to the anti-saturation formula of PI control: in: is the scale factor; is the integrating factor; is the anti-saturation factor, and ; The calculated result is the driving duty cycle D2 of the next cycle.

4. A low-frequency double-frequency control light-load high ITHD digital control device, comprising: A processor, and a memory connected to the processor, the memory having instructions stored therein, which, when executed by the processor, cause the control device to perform the method according to any one of claims 1 to 3.

5. A low-frequency double-frequency control light-load high ITHD digital control system, comprising: A PFC control circuit, and a control device according to claim 4.

6. A computer-readable storage medium having a computer program code stored thereon, wherein the computer program code executes the method according to any one of claims 1 to 3 when executed.

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