A low-frequency double-frequency control light-load high-ITHD digital control method, device, system and readable storage medium

Abstract

The application relates to a low-frequency double-frequency control light-load high-ITHD digital control method, which comprises the following steps: S100, obtaining a PFC switching frequency after frequency reduction; S200, setting a sampling frequency of an inductor current IL of an ADC and a loop operation frequency as twice the PFC switching frequency, and setting an inductor current IL sampling point of the ADC and a loop operation point at positive integer multiples of 1 / 2 of a switching period T; S300, calculating a driving duty ratio D2 of a next switching period T according to a collected sampling current Itrg and a loop operation formula; S400, setting a midpoint of the obtained driving duty ratio D2 of the next period at a midpoint of the next switching period T; and S500, cyclically executing the steps of S300 and S400; the method can greatly improve the problem that an inductor current IL is seriously distorted in a DCM working mode, thereby improving ITHD and PF.

Description

Technical Field

[0001] This invention relates to the field of AC / DC power conversion technology, specifically to a low-frequency double-frequency control light-load high ITHD digital control method, device, system, and readable storage medium. Background Technology

[0002] With the continuous development of the power electronics industry, the requirements for power supplies are becoming increasingly stringent. To better meet customers' demands for the 97.5% efficiency of the OCPv3 specification and balance the requirements for power factor (PF) and internal temperature and heat dissipation (ITHD) values, providing a high-efficiency, simple, and low-cost PFC control solution is particularly important. Currently, the operating frequency of the PFC stage in switching power supplies is generally between 60kHz and 70kHz. Higher switching frequencies lead to significant inductor losses, making it difficult to improve efficiency. Therefore, reducing the switching frequency is an effective method to improve efficiency.

[0003] Currently, most PFCs use average current control (such as...). Figure 3 , Figure 4 ), its control flow diagram (such as Figure 9 To obtain the average value of the input current, a common practice is to use half the drive frequency required for the switching transistor to trigger the ADC to sample the inductor current IL and perform loop operations at this frequency. Down-clocking the switching frequency will also reduce the ADC's inductor current IL sampling frequency and loop operation frequency, leading to a decrease in the number of samples per power frequency cycle, reduced inductor current IL sampling accuracy, and slower loop response. Furthermore, the current PFC drive control method causes the ADC's inductor current IL sampling point to constantly follow the drive changes (e.g., ...). Figure 3 , Figure 4 When the load is light and the drive is small, the midpoint of the inductor current IL cannot be accurately sampled, which will further affect the sampling accuracy, resulting in a worse waveform of the control input current IAC, and the ITHD and PF values ​​cannot meet the specifications. Summary of the Invention

[0004] In view of this, the present invention addresses the deficiencies of the existing technology, and its main objective is to provide a low-frequency double-frequency control method for light-load high ITHD digital control, which can significantly improve the problem of poor ITHD and PF values ​​caused by severe inductor current distortion under DCM operating mode, and meet the ITHD and PF value specifications.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A low-frequency double-frequency control method for light-load high ITHD digital control includes the following steps:

[0007] S100: Obtain the PFC switching frequency after frequency reduction;

[0008] S200. Set the sampling frequency and loop operation frequency of the ADC inductor current IL to twice the PFC switching frequency, and set the sampling point and loop operation point of the ADC inductor current IL at positive integer multiples of 1 / 2 of the switching period T.

[0009] S300. Calculate the drive duty cycle D2 for the next switching cycle T based on the collected sampling current Itrg and the loop operation formula.

[0010] S400, Set the midpoint of the obtained drive duty cycle D2 for the next cycle at the midpoint of the next switching cycle T;

[0011] S500, repeat steps S300 and S400.

[0012] As a preferred embodiment, step S300 also includes the following steps:

[0013] S310, Trigger current sampling at the inductor current IL sampling point of the ADC;

[0014] S320. Input the sampled current Itrg collected by the current sampling into the loop calculation formula to perform loop calculation;

[0015] S330. Obtain the drive duty cycle D1 and completion time t based on the loop operation, and save them;

[0016] S340. Perform loop integration on the obtained drive duty cycle D1, and input the result into the loop operation of the next switching cycle T. Then, obtain the drive duty cycle D2 of the next switching cycle T based on the loop operation.

[0017] S350. Determine the relationship between the completion time t and the switching period T: If the completion time t is greater than or equal to the switching period T, return to continue the current sampling trigger point determination for the next round; if the completion time t is less than or equal to the period T, update the PWM register at the switching period T.

[0018] As a preferred approach, in DCM mode, the drive duty cycle D1 obtained from loop calculation is integrated through loop processing to improve the versatility of this digital control method in both CCM and DCM modes, based on the anti-saturation formula of PI control:

[0019] u(t)=Kp*error(t)+Ki*∫error(t)+Kcr*∫u(t)

[0020] Where: Kp is the scaling factor; Ki is the integral factor; Kcr is the anti-saturation factor, and Kcr = Ki / Kp;

[0021] The calculation result yields the drive duty cycle D2 for the next cycle.

[0022] This application also provides a low-frequency double-frequency control light-load high ITHD digital control device, comprising: a processor, and a memory connected to the processor, the memory having instructions stored therein, the instructions causing the control device to perform the above-described method when executed by the processor.

[0023] This application also provides a low-frequency double-frequency control light-load high ITHD digital control and control system, including: a PFC control circuit, and the aforementioned control device.

[0024] This application also provides a readable storage medium having computer program code stored thereon, which executes the above-described method when run.

[0025] The aforementioned low-frequency double-frequency control method for high ITHD under light load has significant advantages and beneficial effects compared with existing technologies. Specifically, as can be seen from the above technical solution, it mainly involves frequency doubling of the sampling frequency, loop operation frequency, and loop control frequency of the inductor current IL. Within the sampling frequency supported by the DSP, frequency doubling control can effectively improve the current control accuracy of PFC operating in DCM mode. It can significantly improve the problem of severe inductor current distortion leading to poor ITHD and PF values ​​under DCM operating mode. This low-frequency double-frequency control method for high ITHD under light load is not limited to PFC with rectifier bridge; it can also be used for semi-bridgeless PFC, totem pole PFC, single-channel PFC, two-channel interleaved PFC, three-phase interleaved PFC, etc. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the circuit structure of an embodiment of the present invention;

[0027] Figure 2 This is a PFC digital control logic diagram according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the CCM mode without double frequency control.

[0029] Figure 4 This is a schematic diagram of the DCM mode without double frequency control.

[0030] Figure 5 This is a schematic diagram of the CCM mode double frequency control method according to an embodiment of the present invention;

[0031] Figure 6 This is a schematic diagram of the DCM mode double frequency control method according to an embodiment of the present invention;

[0032] Figure 7This is the input current waveform diagram without double frequency control.

[0033] Figure 8 This is an input current waveform diagram of the double frequency control method according to an embodiment of the present invention;

[0034] Figure 9 It is a general duty cycle update logic;

[0035] Figure 10 This is the double-frequency duty cycle update logic of an embodiment of the present invention;

[0036] Figure 11 This refers to the PF value specification of an embodiment of the present invention;

[0037] Figure 12 This is an embodiment of the ITHD value specification of the present invention;

[0038] Figure 13 These are the PF values ​​and ITHD test data before and after using double frequency in an embodiment of the present invention.

[0039] Abbreviations and Terminology Definitions

[0040] PFC: Power Factor Correction

[0041] OCPv3: OpenComputeProject 3.0

[0042] CCM: Continuous Conduction Mode

[0043] DCM: Discontinuous Conduction Mode

[0044] PF: Power Factor

[0045] ITHD: Total Harmonic Distortion Detailed Implementation

[0046] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0047] It should be noted that when a component is said to be "fixed to" another component, it can be directly attached to the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0048] Please see Figures 1 to 13 This illustration shows an embodiment of the present invention providing a low-frequency double-frequency control method for light-load high ITHD digital control, comprising the following steps:

[0049] S100: Obtain the PFC switching frequency after frequency reduction;

[0050] S200. Set the sampling frequency and loop operation frequency of the ADC inductor current IL to twice the PFC switching frequency, and set the sampling points and loop operation points (Trg1, Trg2, Trg3...) of the ADC inductor current IL at positive integer multiples of 1 / 2 of the switching period T (i.e., T / 2, T, 3T / 2, 2T, 5T / 2...).

[0051] S300. The drive duty cycle D of the next switching cycle T is calculated based on the collected sampling current Itrg and the loop operation formula.

[0052] S400, Set the midpoint of the obtained drive duty cycle D2 for the next cycle at the midpoint of the next switching cycle T (i.e., T / 2, 3T / 2, 5T / 2...).

[0053] S500, by repeatedly executing steps S300 and S400, can significantly improve the sampling accuracy of the ADC's inductor current IL and the loop response speed.

[0054] Furthermore, step S300 also includes the following steps:

[0055] S310. Trigger current sampling at the inductor current IL sampling point of the ADC, that is, perform current sampling at positive integer multiples of 1 / 2 of the switching period T (i.e., T / 2, T, 3T / 2, 2T, 5T / 2...).

[0056] S320. Input the sampled current Itrg collected by the current sampling into the loop calculation formula to perform loop calculation;

[0057] S330. Obtain the drive duty cycle D1 and completion time t based on the loop operation, and save them;

[0058] S340. Perform a loop integration operation on the obtained drive duty ratio D1, input the obtained result into the loop operation of the next switching period T, and then obtain the drive duty ratio D2 of the next switching period T according to the loop operation;

[0059] S350. Judge the magnitude relationship between the completion time t and the switching period T: If the completion time t is greater than or equal to the switching period T (t≥T), then return to continue the judgment of the current sampling trigger point for the next round; If the completion time t is less than or equal to the period T (t<T), then update the PWM register at the switching period T.

[0060] Further, in the DCM mode, perform a loop integration process on the drive duty ratio D1 obtained through loop operation to improve the generality of this digital control method in both the CCM mode and the DCM mode. According to the anti-saturation formula of PI control:

[0061] u(t)=Kp*error(t)+Ki*∫error(t)+Kcr*∫u(t)

[0062] Where: Kp is the proportionality factor; Ki is the integral factor; Kcr is the anti-saturation factor, and Kcr = Ki / Kp;

[0063] The calculated result is the drive duty ratio D2 of the next period.

[0064] In the DCM mode, at the switching period T (Trg2 / Trg4…), the reference current I REF and the sampled current I AC_sample have a large error (such as Figure 6 ). If the loop parameters here are used, it will cause a large overshoot in the loop control; while in the CCM mode (such as Figure 5 ), at the switching period T (Trg2 / Trg4…), the reference current I REF and the sampled current I AC_sampleThe error is very small, which is different from the DCM mode. Therefore, the drive duty cycle D2 obtained at the switching cycle T needs to be further processed to improve the versatility of this digital control method in the two working modes. According to the anti-saturation formula of PI control, each calculation will use the result of the previous one for integration. After using the low-frequency double power control method, the drive duty cycle D1 will be updated at 1 / 2 switching cycle T (Trg1 / Trg3...) and at the switching cycle T (Trg2 / Trg4...). However, due to the calculation delay, the drive duty cycle D1 calculated at the switching cycle T (Trg2 / Trg4...) cannot be loaded when the PWM register is updated. Therefore, the drive duty cycle D1 at the switching cycle T will not be directly used for the output of the switching transistor drive. Instead, it will be accumulated as an integral term in the PI calculation at the next 1 / 2 switching cycle T (Trg1 / Trg3...). At this time, the calculated drive duty cycle D2 will not have a large overshoot due to the large error, nor will it cause control hysteresis current distortion due to the low error change rate. Therefore, the update logic for the drive duty cycle is the same in DCM mode and CCM mode. Thus, this low-frequency double-frequency control, light-load, high-ITHD digital control method is perfectly applicable to current control in both DCM and CCM modes, and the optimized input current I... AC The effect is as follows Figure 8 As shown, in a DC-DC converter, based on the error between the reference value and the actual sampled value of the output voltage or inductor current, the PI control anti-saturation formula is used to adjust the drive duty cycle of the power switching transistor. This ensures that the converter can stably output the required voltage and current, while avoiding integral saturation caused by sudden load changes, which can lead to excessive output voltage ripple, slow response speed, and other adverse phenomena, thereby improving the power conversion efficiency and power supply quality of the power supply.

[0065] Specifically, error(t) is usually the error value between the reference current IREF and the sampled current IAC_sample, etc. Kp is a proportional factor, and the proportional circuit outputs the corresponding control action in real time according to the magnitude of this error. For example, in DCM mode, when there is a large error between the reference current IREF and the sampled current IAC_sample (such as when the error is large at the period Trg2 / Trg4...), if the value of Kp is appropriate, the proportional circuit will quickly output a relatively large control adjustment amount according to this large error, so that the error can be reduced as soon as possible, and the inductor current of the power supply should change towards the desired state, which plays a key role in the rapid response of the system. Similarly, in CCM mode, although the error is relatively small, the proportional circuit will still output a corresponding, small control quantity for fine-tuning based on this small error. The integral circuit under the action of the integral factor Ki accumulates the error error(t) over time. For the control of the power switch, it is mainly used to eliminate steady-state error. During the continuous operation of the power switch, even if the proportional circuit has reduced the error to a certain extent, there may still be slight and continuous errors. The integral circuit will continuously accumulate these errors and continuously change the control quantity u(t), so that the power switch can eventually achieve a more precise control state, such as making the inductor current more stably track the reference current and achieve output... The high precision and stability of voltage and other indicators, especially when dealing with small disturbances and deviations during long-term power supply operation, ensure the steady-state performance of the system through the cumulative regulation of the integral term. The anti-saturation factor Kcr is designed to address integral saturation. In power switch control, especially under complex conditions such as sudden changes in power load, the controller output u(t) may remain at a large value for an extended period (e.g., the power switch is continuously in its extreme on or off state). This leads to the continuous accumulation of the integral term, resulting in integral saturation. This, in turn, causes excessive overshoot and longer settling time in the loop control, compromising the control performance of the power switch. The anti-saturation component dynamically adjusts the control quantity based on the cumulative value of u(t) through feedback regulation, preventing integral saturation and ensuring that the output of the control quantity remains reasonable under different operating modes (such as DCM mode, which is prone to overshoot, and CCM mode, which is relatively stable but may also face special conditions). This maintains the stability and reliability of the power switch control loop. The u(t) calculated by the PI control anti-saturation formula takes into account multiple factors such as real-time proportional adjustment of error, integral elimination of steady-state error, and prevention of integral saturation. The output control quantity aims to optimize the control effect of the power supply in different operating modes such as DCM and CCM, and improve the control accuracy and operating stability of the power switching transistor.

[0066] Embodiments of this application also provide a low-frequency double-frequency control light-load high ITHD digital control device, comprising: a processor, and a memory connected to the processor, the memory having instructions stored therein, the instructions causing the control device to perform the above-described method when executed by the processor.

[0067] Embodiments of this application also provide a low-frequency double-frequency control light-load high ITHD digital control system, including: a PFC control circuit, and the control device described above.

[0068] Embodiments of this application also provide a readable storage medium having computer program code stored thereon, which executes the above-described method when run.

[0069] like Figures 11-13 As shown, an 800W switching power supply (output 65A at full load) is used according to the PF value specification ( Figure 11 ) and ITHD specifications ( Figure 12 Comparative tests were conducted, and data before and after using the double-frequency control method were compared (e.g.) Figure 13 As shown in the figure, it is clear that the PF value and ITHD are significantly optimized when using the double frequency control method.

[0070] The aforementioned low-frequency double-frequency control method for high ITHD under light load mainly involves frequency multiplication of the sampling frequency, loop operation frequency, and loop control frequency of the inductor current IL. Within the sampling frequency supported by the DSP, frequency multiplication control can effectively improve the current control accuracy of PFC operating in DCM mode. It can significantly improve the problem of severe inductor current distortion leading to poor ITHD and PF values ​​under DCM operating mode. This low-frequency double-frequency control method for high ITHD under light load is not limited to PFC with rectifier bridge, semi-bridgeless PFC, totem pole PFC, single-channel PFC, two-channel interleaved PFC, three-phase interleaved PFC, etc., and can also be used.

[0071] It should be noted that the present invention is not limited to the above-described embodiments. Based on the inventive spirit of the present invention, those skilled in the art can make other changes, and these changes made in accordance with the inventive spirit of the present invention should be included within the scope of protection claimed by the present invention.

Claims

1. A low frequency double frequency control light load high ITHD digital control method, characterized in that, The method comprises the following steps: S100, obtaining a PFC switching frequency after frequency reduction; S200, setting a sampling frequency of an inductor current IL of an ADC and a loop operation frequency to twice the PFC switching frequency, and setting an inductor current IL sampling point of the ADC and a loop operation point at an integer multiple of 1 / 2 of a switching period T; S300, calculating a driving duty ratio D2 of a next switching period T according to a collected sampling current Itrg and a loop operation formula; S400, setting a midpoint of the obtained driving duty ratio D2 of the next period at a midpoint of the next switching period T; S500, cyclically executing the steps of S300 and S400; In the step S300, the method further comprises the following steps: S310, triggering current sampling at the inductor current IL sampling point of the ADC; S320, inputting a sampling current Itrg collected by the current sampling into a loop operation formula for loop operation; S330, obtaining a driving duty ratio D1 and a completion time t according to the loop operation, and saving them; S340, performing loop integral operation on the obtained driving duty ratio D1, inputting a result obtained by the loop integral operation into loop operation of a next switching period T, and obtaining a driving duty ratio D2 of the next switching period T according to the loop operation; S350, judging a size relationship between the completion time t and the switching period T: if the completion time t is greater than or equal to the switching period T, returning to continue current sampling triggering point judgment of a next round; if the completion time t is less than the period T, updating a PWM register at the switching period T.

2. A low frequency double frequency control light load high ITHD digital control device, comprising: A processor, and a memory connected with the processor, the memory having instructions stored therein, which when executed by the processor, cause the control device to perform the method according to claim 1.

3. A low frequency double frequency control light load high ITHD digital control system comprising: A PFC control circuit, and the control device according to claim 2.

4. A computer readable storage medium having stored thereon computer program code which, when executed, performs the method of claim 1.

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