Off-chip programmable dead time generation circuit

Abstract

The invention belongs to the technical field of analog integrated circuit power management, and provides an adjustable dead time generating circuit for half-bridge driving topology. The circuit specifically comprises a voltage-to-current circuit (V-to-I), a transient enhancement circuit (TEC) and a dead time generation circuit. Different charging currents are obtained by adjusting the size of an off-chip resistor, the capacitor at the input end of the comparator is charged, and when the voltage on the capacitor reaches the reference voltage of the comparator, the output of the comparator is reversed, so that a short pulse is obtained. And adding the obtained short pulse and the input signal to obtain a control signal containing the dead time. Compared with a traditional structure, the half-bridge circuit has the advantages that the dead time in linear relation with the size of the off-chip resistance can be generated, high accuracy is achieved, the half-bridge circuit can have flexible dead time in different application scenes, and the reliability and efficiency of a system are ensured while performance requirements are met.

Description

Technical Field

[0001] The present invention belongs to the technical field of analog integrated circuit power management, and particularly relates to an off-chip programmable dead time generation circuit. Background Art

[0002] In a power management system, especially in a switching power supply (such as a DC-DC converter), the dead time (DT) is a crucial parameter, which refers to the time interval between the turn-off and turn-on of two switching elements (such as MOSFET or IGBT). The setting of the dead time is mainly used to avoid the simultaneous conduction of two switching devices. Too short dead time may cause the bridge arm to short-circuit during the switching transition, generating a DC short-circuit current and burning out the devices and chips; while too long dead time will greatly reduce the efficiency of the switching power supply.

[0003] In high-performance power management design, the precise adjustment of the dead time is crucial for improving power efficiency, extending the device life, and ensuring the stability of the system. Since the switching power supply has different dead time requirements under different application scenarios and external load conditions. Therefore, designing a circuit that can adapt to different working conditions and flexibly adjust the dead time has become an important research direction in the modern power management field. Reasonably set and optimize the dead time in the power management system to ensure the reliability and efficiency of the system while meeting the performance requirements. Summary of the Invention

[0004] The object of the present invention: to solve the different dead time requirements of the switching power supply under different application scenarios, and ensure the reliability and efficiency of the system while meeting the performance requirements.

[0005] The technical solution of the present invention is as follows:

[0006] An off-chip programmable dead time generation circuit, as Figure 3 shown, includes an operational amplifier, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, a first resistor, a second resistor, a first capacitor, a second capacitor, a comparator, and a NOR gate;

[0007] The positive input terminal of the amplifier is connected to the reference voltage (VREF), the negative input terminal is connected to one end of the first resistor and the source of the first NMOS transistor, and the output is connected to the gate of the first NMOS transistor; the other end of the first resistor is grounded; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor and the gates of the second and third PMOS transistors;

[0008] The gates of the first PMOS and the fourth PMOS are connected to the bias voltage (VBias). The source of the first PMOS is connected to the drain of the second PMOS. The source of the second PMOS is connected to the power supply voltage. The source of the third PMOS is connected to the power supply voltage, and the drain is connected to the source of the fourth PMOS. The drain of the fourth PMOS is connected to the source of the fifth PMOS.

[0009] The drain of the fifth PMOS is connected to the negative input terminal of the comparator, and the gate is connected to the input (PWM). One end of the first capacitor is connected to the negative input terminal of the comparator, and the other end is grounded. The source of the second NMOS is grounded, the drain is connected to the negative input terminal of the comparator, and the gate is connected to the input (PWM). The source of the third NMOS is grounded, the gate is connected to the input (PWM), and the drain is connected to the output of the comparator. The positive input terminal of the comparator is connected to the reference voltage (VREF). One input terminal of the NOR gate is connected to the input (PWM), and the other input terminal is connected to the output of the comparator. The output of the NOR gate is connected to OUT.

[0010] One end of the second capacitor is connected to the input (PWM), and the other end is connected to one end of the second resistor and the gate of the seventh PMOS. The other end of the second resistor is connected to the power supply voltage. The source of the seventh PMOS is connected to the power supply voltage, and the drain is connected to the output of the comparator. The gate of the sixth PMOS is connected to the input (PWM), the source is connected to the power supply voltage, and the drain is connected to the power supply voltage of the comparator (INTVDD).

[0011] The beneficial effects of the present invention are as follows: Compared with the traditional structure, the present invention can generate a dead time that is linearly related to the size of the external resistor, with high precision, enabling the switching power supply circuit to have a flexible dead time in different application scenarios, while meeting the performance requirements and ensuring the reliability and efficiency of the system. Description of the Drawings

[0012] Figure 1 It is a schematic diagram of a dual-channel isolation drive system.

[0013] Figure 2 It is a schematic diagram of the dead time.

[0014] Figure 3 It is the schematic diagram of the off-chip programmable dead time generation circuit proposed by the present invention.

[0015] Figure 4 It is the simulation waveform of the off-chip programmable dead time generation circuit proposed by the present invention. Detailed Embodiments

[0016] The technical solution of the present invention will be described in detail below in conjunction with the drawings:

[0017] Figure 3This is the schematic diagram of the off-chip programmable dead time generation circuit proposed by the present invention. Among them, VDD is the power supply voltage; GND is the ground; VREF is the reference voltage generated inside the chip; VBias is the fixed bias voltage generated inside the chip; VC is the voltage of the first capacitor C1; V1 is the output voltage of the comparator; OUT is the output of the NOR gate, which is also the output of the system. Figure 3 The shown schematic diagram of the off-chip programmable dead time generation circuit includes a V-to-I circuit; a transient enhancement circuit (TEC); and a dead time generation circuit.

[0018] The V-to-I circuit includes an operational amplifier EA, a first resistor R1, a first NMOS transistor MN1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4. Among them, the first resistor R1 is an off-chip resistor. The negative feedback structure formed by the operational amplifier and the first NMOS transistor MN1 is the core of the V-to-I circuit. Through the clamping action of the operational amplifier, the voltage on the first resistor R1 is VREF, so that a current I is generated on the first resistor R1. DT , expressed as:

[0019]

[0020] The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 form a current mirror structure to copy and output the current on the first resistor R1. The output currents of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are of magnitude K*I. DT , where the constant K is the size ratio factor of the current mirror.

[0021] The TEC circuit includes a second resistor R2, a second capacitor C2, a sixth PMOS transistor MP6, and a seventh PMOS transistor MP7; the dead time generation circuit includes a fifth PMOS transistor MP5, a second NMOS transistor MN2, a third NMOS transistor MN3, a first capacitor C1, a comparator COMP, and a NOR gate NOR.

[0022] When the input PWM changes from low to high, the fifth PMOS transistor MP5 turns off, the first capacitor C1 has no charging current, the second NMOS transistor MN2 turns on, the first capacitor C1 discharges rapidly, and VC is rapidly pulled down; the sixth PMOS transistor MP6 turns off, disconnecting the power supply voltage INTVDD of the comparator from the system power supply voltage VDD; the seventh PMOS transistor MP7 turns off; the third NMOS transistor MN3 turns on, so the output V1 of the comparator is low. The input PWM and the output V1 of the comparator are operated by the NOR gate, and the output changes from high to low.

[0023] When the input PWM changes from high to low, the fifth PMOS transistor MP5 turns on, the second NMOS transistor MN2 turns off, and the charging current of the first capacitor C1 is K*I DT , and VC rises linearly with time; the third NMOS transistor MN3 turns off; the sixth PMOS transistor MP6 turns on, and the comparator COMP resumes power supply. Since the voltage VREF at the positive input terminal of the comparator is higher than the voltage VC at the negative input terminal at this time, the output voltage V1 of the comparator starts to rise; at the same time, the high-pass filter composed of the second capacitor C2 and the second resistor R2 turns on the seventh PMOS transistor MP7 at the falling edge of the input PWM. The seventh PMOS transistor MP7 quickly pulls up the input voltage V1 of the comparator. Under the combined action of the comparator, V1 quickly rises to a high level, avoiding the glitch phenomenon caused by the simultaneous transition of the two inputs of the NOR gate NOR at the output OUT; when the PWM is at a low level, the seventh PMOS transistor MP7 turns off, and the comparator output V1 maintains a high level under the action of the comparator; when the voltage VC of the first capacitor C1 is charged to be equal to VREF, ignoring the offset of the comparator and the parasitic capacitance at the negative input terminal of the comparator, the output of the comparator changes from high to low. Therefore, the output V1 of the comparator shows a short pulse that changes from low to high when the falling edge of the output PWM arrives, and then changes from high to low after a certain delay time. The high-level maintenance time of the short pulse is the dead time t DT The size of is expressed as:

[0024]

[0025] Substituting I DT The expression of can obtain the relationship between the dead time and the first resistor R1, which is expressed as:

[0026]

[0027] where the value of the first resistor C1 and the proportionality coefficient K are constants. Therefore, the dead time t DT and the size of the first resistor R1 are linearly related. After the PWM and V1 are operated by the NOR gate, the output OUT becomes a signal with a dead time to control the subsequent circuit. Figure 4 This is the simulation result of the off-chip programmable dead time generation circuit proposed by the present invention. It can be seen that the simulation result is the same as the principle described above, and the final output OUT has an obvious dead time.

[0028] In summary, the present invention proposes a circuit that can adjust the dead time by the size of an off-chip resistor, adds a dead time at the falling edge of the input signal, and the size of the dead time is linearly related to the size of the off-chip resistor. It is simple and flexible and is suitable for switching power supply circuits in different application scenarios.

Claims

1. An off-chip programmable dead time generating circuit, characterized in that: It includes an operational amplifier, a first NMOS tube, a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a first resistor, a second resistor, a first capacitor, a second capacitor, and a comparator; The positive input terminal of the amplifier is connected to the reference voltage, the negative input terminal is connected to one end of the first resistor and the source of the first NMOS, and the output terminal is connected to the gate of the first NMOS; the other end of the first resistor is grounded; the drain of the first NMOS is connected to the drain of the first PMOS and the gate of the second PMOS tube and the gate of the third PMOS; The gate of the first PMOS and the gate of the fourth PMOS are connected to a bias voltage, and the source of the first PMOS is connected to the drain of the second PMOS; The source of the second PMOS is connected to the power supply voltage; the source of the third PMOS is connected to the power supply voltage, and the drain is connected to the source of the fourth PMOS; the drain of the fourth PMOS is connected to the source of the fifth PMOS; The drain of the fifth PMOS is connected to the negative input terminal of the comparator, and the gate is connected to the input PWM signal; one end of the first capacitor is connected to the negative input terminal of the comparator, and the other end is grounded; the source of the second NMOS is grounded, the drain is connected to the negative input terminal of the comparator, and the gate is connected to the input PWM signal; the source of the third NMOS is grounded, the gate is connected to the input PWM signal, and the drain is connected to the output of the comparator; the positive input terminal of the comparator is connected to the reference voltage; one input terminal of the NOR gate is connected to the input PWM signal, and the other input terminal is connected to the output of the comparator, and the output terminal of the NOR gate is the output terminal of the dead time generating circuit; One end of the second capacitor is connected to the input PWM signal, and the other end is connected to one end of the second resistor and the gate of the seventh PMOS; the other end of the second resistor is connected to the power supply voltage; the source of the seventh PMOS is connected to the power supply voltage, and the drain is connected to the output of the comparator; the gate of the sixth PMOS is connected to the input PWM signal, the source is connected to the power supply voltage, and the drain is connected to the power supply voltage end of the comparator.

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